Display device

Abstract

A display device is provided. The display device includes a substrate including a display area and a non-display area; a plurality of signal wirings extending on the substrate in a first direction from the non-display area so as to be arranged in the display area; a connection wiring extending on the substrate from the non-display area and electrically connected to the signal wiring via the display area; and an initialization voltage line extending on the substrate in a second direction intersecting the first direction, the connection wiring overlapping the initialization voltage line in a thickness direction.

Description

Technical Field

[0001] This invention relates to display devices. Background Technology

[0002] The importance of display devices is increasing alongside the development of multimedia. Correspondingly, various display devices are being used, such as Liquid Crystal Displays (LCDs) and Organic Light Emitting Displays (OLEDs). Among them, OLEDs, as self-emissive elements, offer excellent viewing angles and are therefore attracting considerable attention as the next generation of display devices.

[0003] An organic light-emitting display device includes pixel circuits and a driving unit that drives the pixel circuits. The driving unit may include a scan driving unit that provides scan signals to the pixel circuits, a data driving unit that provides data signals to the pixel circuits, etc. The driving circuits of the scan driving unit and the data driving unit can be configured in a non-display area adjacent to the display area. From the perspective of the display device's function, the non-display area is considered a dead space. Summary of the Invention

[0004] The problem to be solved by the present invention is to provide a display device that can minimize the non-display area of ​​the display device while preventing the degradation of display quality.

[0005] The subject matter of this invention is not limited to the subject matter mentioned above, and those skilled in the art should understand from the following description other technical subject matter not mentioned.

[0006] An embodiment of a display device for solving the aforementioned problem includes: a substrate including a display area and a non-display area; a plurality of signal wirings extending on the substrate from the non-display area in a first direction and disposed in the display area; a connection wiring extending on the substrate from the non-display area and electrically connected to the signal wirings in the non-display area via the display area; and an initialization voltage line extending on the substrate in a second direction intersecting the first direction, the connection wirings overlapping the initialization voltage line in a thickness direction.

[0007] Alternatively, the initialization voltage line may be formed by a second conductive layer, the signal wiring may be formed by a third conductive layer disposed on the second conductive layer, and the connection wiring may be formed by a fourth conductive layer disposed on the third conductive layer.

[0008] Alternatively, the display device may further include a first power supply voltage line disposed between the initialization voltage line and the connection wiring, the first power supply voltage line overlapping the connection wiring in the thickness direction.

[0009] Alternatively, the display device may further include a scan line disposed between the substrate and the initialization voltage line, wherein the first power supply voltage line overlaps with the scan line in the thickness direction.

[0010] Alternatively, the first power supply voltage line may be formed by the third conductive layer, and the scan line may be formed by the first conductive layer disposed between the substrate and the second conductive layer.

[0011] Alternatively, the connection wiring may include a lateral portion extending in the second direction, and the initialization voltage line may be disposed on a plane between the lateral portion and the scan line.

[0012] Alternatively, the lateral portion may overlap with the first power supply voltage line in the thickness direction.

[0013] Alternatively, the display device may further include a positive electrode disposed on the connection wiring, wherein the lateral portion does not overlap with the positive electrode in the thickness direction.

[0014] Alternatively, the display device may further include a coupling blocking layer disposed between the initialization voltage line and the connection wiring, the coupling blocking layer overlapping the connection wiring in the thickness direction.

[0015] Alternatively, the display device may further include a first power supply voltage line disposed between the initialization voltage line and the connection wiring, wherein the coupling blocking layer is electrically connected to the first power supply voltage line.

[0016] Other embodiments for solving the aforementioned problem include a display device comprising: a substrate including a display area and a non-display area; an initialization voltage line disposed on the substrate; a plurality of signal wirings disposed via the display area and the non-display area; a plurality of connection wirings disposed in the display area and respectively connected to the signal wirings; and a positive electrode disposed on the connection wirings, the connection wirings including a lateral portion extending in a second direction, the lateral portion overlapping the initialization voltage line in the thickness direction but not overlapping the positive electrode.

[0017] The lateral portion may include: a first lateral portion disposed on one side of the anode in a plane; and a second lateral portion disposed on the other side of the anode in a plane, the second lateral portion including a bent portion bent along the edge of the anode.

[0018] The first transverse portion may include: a first branch pattern that protrudes from the first transverse portion toward one side of a first direction that intersects with the second direction; and a second branch pattern that protrudes toward the other side of the first direction. The second transverse portion may include: a third branch pattern that protrudes from the second transverse portion toward one side of the first direction; and a fourth branch pattern that protrudes toward the other side of the first direction.

[0019] Alternatively, a gap may be defined between adjacent second and third branch patterns, the gap overlapping the anode.

[0020] The first to fourth branch patterns may not overlap with the anode.

[0021] Alternatively, the initialization voltage line may be formed by a second conductive layer, the signal wiring may be formed by a third conductive layer disposed on the second conductive layer, and the connection wiring may be formed by a fourth conductive layer disposed on the third conductive layer.

[0022] Alternatively, the display device may further include a scan line disposed between the substrate and the initialization voltage line, wherein the scan line does not overlap with the lateral portion in the thickness direction.

[0023] Alternatively, the display device may further include a first power supply voltage line disposed between the initialization voltage line and the connection wiring, the first power supply voltage line overlapping the connection wiring in the thickness direction.

[0024] Alternatively, the scan line may be formed by a first conductive layer disposed between the substrate and the second conductive layer, and the first power supply voltage line may be formed by the third conductive layer.

[0025] Specific details of other embodiments are included in the detailed description and accompanying drawings.

[0026] (Invention Effects)

[0027] According to one embodiment, a display device includes connection wiring that transmits data signals to signal wiring disposed in a display area, thereby reducing the unused space of the display device.

[0028] Furthermore, preventing the formation of parasitic capacitance between the scan lines and the connecting wiring minimizes coupling between the two wirings. This minimizes or prevents speckling caused by data signal distortion, thereby improving display quality.

[0029] The effects of the various embodiments are not limited to those illustrated above, and more effects are included in this specification. Attached Figure Description

[0030] Figure 1 This is a plan view of a display device according to an embodiment.

[0031] Figure 2 This is a cross-sectional view of a display device according to an embodiment.

[0032] Figure 3 This is a plan view illustrating the signal wiring and connection wiring of a display device according to an embodiment.

[0033] Figure 4 yes Figure 3 An enlarged plan view of region A.

[0034] Figure 5 Therefore Figure 4 The sectional view is taken with line I-I′ as the reference.

[0035] Figure 6 This is a plan view illustrating the configuration of connection wiring and pixels according to one embodiment.

[0036] Figures 7 to 9 This is a plan view showing the configuration of connection wiring and pixels involved in each embodiment.

[0037] Figure 10 It is a planar diagram representing an example of a pixel.

[0038] Figure 11 Therefore Figure 10 The sectional view is taken with the Ⅱ-Ⅱ′ line as the reference.

[0039] Figure 12 This is a plan view representing an example of pixels involved in other embodiments.

[0040] Figure 13 Therefore Figure 12 The sectional view is taken with the Ⅱ-Ⅱ′ line as the reference.

[0041] Figure 14 This is a plan view representing an example of pixels in yet another embodiment.

[0042] Figure 15 Therefore Figure 14 The sectional view is taken with the Ⅱ-Ⅱ′ line as the reference.

[0043] Figure 16 This is a plan view representing an example of pixels in yet another embodiment.

[0044] Figure 17 Therefore Figure 16 The sectional view is taken with the Ⅱ-Ⅱ′ line as the reference.

[0045] Figure 18This is a plan view representing an example of pixels in yet another embodiment.

[0046] Figure 19 Therefore Figure 18 The sectional view is taken with the Ⅱ-Ⅱ′ line as the reference.

[0047] Figure 20 This is a plan view representing an example of pixels in yet another embodiment.

[0048] Figure 21 Therefore Figure 20 The sectional view is taken with the Ⅱ-Ⅱ′ line as the reference.

[0049] Figure 22 This is a plan view representing an example of pixels in yet another embodiment.

[0050] Figure 23 Therefore Figure 22 The sectional view is taken with the Ⅱ-Ⅱ′ line as the reference.

[0051] Figure 24 This is a plan view illustrating the connection wiring involved in yet another embodiment.

[0052] Figure 25 This is a plan view illustrating the connection wiring involved in yet another embodiment.

[0053] Figure 26 This is a plan view illustrating the connection wiring involved in yet another embodiment.

[0054] Figure 27 This is a perspective view of a display device according to yet another embodiment.

[0055] Figure 28 yes Figure 27 An unfolded diagram of the display device.

[0056] Figure 29 It means Figure 27 A plan view of the signal wiring and connection wiring of the display device.

[0057] [Symbol Explanation]

[0058] 1: Display device; 10: Display panel; 20: Driver chip; 30: Display driver substrate; MR: Main area; BR: Bending area; SR: Sub-area; DL: Signal wiring; DM: Connection wiring; VIL: Initialization voltage line; VDL: First power supply voltage line; GI: First scan line; GW: Second scan line. Detailed Implementation

[0059] References and Appendix Figure 1The advantages, features, and methods of achieving these advantages and features of the invention will become more apparent from the detailed embodiments described below. However, the invention is not limited to the embodiments disclosed below and can be implemented in different ways. The embodiments in this specification are provided only to complete the disclosure of the invention and to fully inform those skilled in the art of the scope of the invention. The invention is defined only by the scope of the claims.

[0060] The term "elements" or "layers" being "on" other elements or layers includes cases where they are directly above other elements and cases where other layers or elements exist between them. Throughout the specification, the same symbol refers to the same constituent element.

[0061] Hereinafter, various embodiments will be described with reference to the accompanying drawings. The display device will be described using an organic light-emitting display device as an example.

[0062] Figure 1 This is a plan view of a display device according to an embodiment. Figure 2 This is a cross-sectional view of a display device according to an embodiment.

[0063] Reference Figure 1 as well as Figure 2 The display device 1 is a device for displaying dynamic or static images. In addition to portable electronic devices such as mobile phones, smartphones, desktop PCs (Personal Computers), smartwatches, watch phones, mobile communication terminals, electronic manuals, e-books, PMPs (Portable Multimedia Players), navigators, and UMPCs (Ultra Mobile PCs), the display device 1 can also be used as a display screen for various products such as televisions, laptops, monitors, advertising boards, and the Internet of Things.

[0064] The display device 1 may include a display panel 10. The display panel 10 may be a flexible substrate comprising a flexible polymer material such as polyimide. Therefore, the display panel 10 may be bent, folded, folded, or rolled.

[0065] The display panel 10 may include a main region MR and a curved region BR connected to one side of the main region MR. The display panel 10 may also include a sub-region SR connected to the curved region BR and overlapping the main region MR in the thickness direction.

[0066] The display panel 10 may include a display area DA, which is part of the display screen, and a non-display area NDA other than the display area DA. The display area DA may include multiple pixels. Each pixel may include a light-emitting layer and a circuit layer that controls the amount of light emitted by the light-emitting layer. The circuit layer may include display wiring, display electrodes, and at least one transistor. The light-emitting layer may include an organic light-emitting material. The light-emitting layer may be sealed with an encapsulation film. The detailed structure of the pixels will be described later. The display area DA may have a rectangular shape or a rectangular shape with rounded corners. However, it is not limited to this; the display area DA may have a square or other polygonal shape, or various shapes such as a circle or ellipse.

[0067] The display area DA is configured within the main area MR. Within the main area MR, the peripheral edge portion of the display area DA, the curved area BR, and the sub-area SR can be non-display areas NDA. However, this is not a limitation; the curved area BR and the sub-area SR may also include the display area DA.

[0068] The main region MR may have a shape similar to the outline of the display device 1 on a plane. The main region MR may be a flat area located on one side. However, it is not limited to this. In the main region MR, at least one of the remaining edges other than the edge (edge) connected to the curved region BR may be bent to form a curved surface or may be bent in the vertical direction.

[0069] In the main region MR, if at least one of the remaining edges, excluding the edge connected to the curved region BR, forms a curved surface or is bent, a display region DA can also be configured at the corresponding edge. However, it is not limited to this; a non-display region NDA that does not display an image can also be configured at the curved or bent edge, or both the display region DA and the non-display region NDA can be configured together.

[0070] In the main region MR, the non-display region NDA can be located around the display region DA. The non-display region NDA of the main region MR can extend from the outer boundary of the display region DA to the edge of the display panel 10. Signal wiring DL, connection wiring DM, or drive circuitry for applying signals to the display region DA can be configured in the non-display region NDA of the main region MR. In addition, an outermost black matrix can be configured in the non-display region NDA of the main region MR, but it is not limited to this.

[0071] The curved region BR is connected to the main region MR. For example, the curved region BR can be connected to the main region MR via a short side of the main region MR. The width of the curved region BR in the second direction DR2 can be smaller than the width of the main region MR in the second direction DR2. The connection between the main region MR and the curved region BR can have an L-shaped cut.

[0072] In the bending region BR, the display panel 10 can be bent with a certain curvature in the opposite direction to the third direction DR3, that is, in the opposite direction to the display surface. The bending region BR can have a certain radius of curvature, but is not limited to this, and can have different radii of curvature in each interval. As the display panel 10 is bent in the bending region BR, the surface of the display panel 10 can be reversed. That is, the side of the display panel 10 facing upwards turns outwards through the bending region BR and then faces downwards again, thus changing direction.

[0073] The sub-region SR extends from the curved region BR. The sub-region SR can begin extending in a direction parallel to the main region MR after the curvature is complete. The sub-region SR can overlap with the main region MR in the third direction DR3, i.e., the thickness direction, of the display panel 10. The sub-region SR can overlap with the non-display area NDA at the edge of the main region MR, and further overlap with the display area DA of the main region MR.

[0074] The width of the sub-region SR in the second direction DR2 can be the same as the width of the curved region BR in the second direction DR2, but is not limited to this.

[0075] A driver chip 20 may be configured on a sub-region SR of the display panel 10. The driver chip 20 may include an integrated circuit that drives the display panel 10. In one embodiment, the integrated circuit may be a data driver integrated circuit that generates and provides data signals, but is not limited thereto. The driver chip 20 may be mounted on the display panel 10 in the sub-region SR. The driver chip 20 may be mounted on a side of the display panel 10 that is the same side as the display surface, but as the curved region BR is bent and reversed as described above, it may be mounted on a side of the display panel 10 facing the opposite direction to the third direction DR3, so that the upper surface of the driver chip 20 may face the opposite direction to the third direction DR3.

[0076] The driver chip 20 can be attached to the display panel 10 via an anisotropic conductive thin film or by ultrasonic bonding. The width of the driver chip 20 in the second direction DR2 can be smaller than the width of the display panel 10 in the second direction DR2. The driver chip 20 can be disposed in the center of the sub-region SR in the second direction DR2, with its left and right edges respectively located away from the left and right edges of the sub-region SR.

[0077] A display driving substrate 30 may be connected to the end of a sub-region SR of the display panel 10. A pad portion may be provided at the end of the sub-region SR, and the display driving substrate 30 may be connected to the pad portion. The display driving substrate 30 may be a flexible printed circuit board or a thin film.

[0078] Multiple signal cabling (DL) and connection cabling (DM) can be configured in the sub-region SR, the curved region BR, and the main region MR. The signal cabling (DL) and connection cabling (DM) can extend from the sub-region SR through the curved region BR to the main region MR. That is, the signal cabling (DL) and connection cabling (DM) can extend from the non-display region NDA and be configured in the display region DA.

[0079] The following details the signal cabling (DL) and connection cabling (DM).

[0080] Figure 3 This is a plan view illustrating the signal wiring and connection wiring of a display device according to an embodiment. Figure 4 yes Figure 3 An enlarged plan view of region A. Figure 5 Therefore Figure 4 The sectional view is taken with line I-I′ as the reference.

[0081] Reference Figures 3 to 5 The display device 1 may include signal wiring DL and connection wiring DM. Furthermore, the configuration of the signal wiring DL and connection wiring DM can be symmetrical about a reference axis (not shown) extending in the first direction DR1 and passing through the center of the area of ​​the display device 1. Hereinafter, the description will focus on the signal wiring DL and connection wiring DM configured on the right side of the display device 1.

[0082] Multiple signal traces (DLs) extend along a first direction DR1 and are arranged sequentially along a second direction DR2 at specific intervals. The second direction DR2 intersects the first direction DR1 and may be perpendicular to it. The signal traces (DLs) may be, for example, data lines that transmit data signals.

[0083] Each signal cable DL can extend across the display area DA in the first direction DR1. One end of the signal cable DL can be located in the non-display area NDA. One end of the signal cable DL can be electrically connected to the connection cable DM.

[0084] Multiple connection wires (DMs) can be electrically connected to each of multiple signal wires (DLs). The connection wires (DMs) are configured on a different layer than the layers containing the signal wires (DLs), and the connection wires (DMs) can be insulated from the signal wires (DLs) by an insulating layer. For this, refer to... Figure 5 To be continued later.

[0085] Connecting wires (DMs) can extend from the non-display area (NDA) through the display area (DA) to the non-display area (NDA). Connecting wires (DMs) can be configured to be separated from each other at specific intervals. The intervals between connecting wires (DMs) can be substantially the same as the intervals between signal wires (DLs).

[0086] Additionally, the connection wiring DM can extend from the non-display area NDA in a first direction DR1 (e.g., the upper side), and then change direction within the display area DA to extend in a second direction DR2 (e.g., the left side), extending to one end of the corresponding signal wiring DL in an area adjacent to or intersecting with the corresponding signal wiring DL. That is, the connection wiring DM can extend to the non-display area NDA where the signal wiring DL is located.

[0087] Each connection cabling DM may include a lateral portion DMA configured along the second direction DR2 and a longitudinal portion DMB configured along the first direction DR1. The longitudinal portion DMB of the connection cabling DM may include a first longitudinal portion DMB1 and a second longitudinal portion DMB2 configured along the first direction DR1. The lateral portion DMA of the connection cabling DM extends from one end of the first longitudinal portion DMB1 in the second direction DR2, and the second longitudinal portion DMB2 extends from one end of the lateral portion DMA in the opposite direction to the first direction DR1.

[0088] like Figure 4 As shown, the vertical portion DMB of the connecting cable DM is located within the display area DA and may overlap with the signal cable DL on the plane. However, this is only an example and is not limited to this. For example, the vertical portion DMB of the connecting cable DM may not overlap with the signal cable DL on the plane within the display area DA. That is, the vertical portion DMB of the connecting cable DM can be configured in a separate space between multiple signal cables DL.

[0089] On the other hand, Figure 3 as well as Figure 4 The image shows a case where the connecting cable DM is bent at a right angle, but it is not limited to this.

[0090] The connector DMs do not intersect each other on the plane, allowing them to be configured by circling adjacent connector DMs. Therefore, the connector DMs can have different lengths; that is, the length of the connector DM located on the outer edge can be longer than the length of the connector DM located on the inner edge.

[0091] Multiple connection cables DM can be directly connected one-to-one with signal cables DL through the first contact hole CNT1 located in the non-display area NDA. For example, as Figure 5 As shown, the signal wiring DL can be formed by a third conductive layer 130, and the connection wiring DM can be formed by a fourth conductive layer 140. The signal wiring DL and the connection wiring DM are insulated by a fourth insulating layer IL4. The connection wiring DM extends to one end of the signal wiring DL, and the first contact hole CNT1 exposed at one end of the signal wiring DL is electrically connected to the signal wiring DL by penetrating the fourth insulating layer IL4.

[0092] As described above, the display device 1 includes a connection cable DM configured via a display area DA, through which image signals can be provided to signal cables DL. Therefore, the additional unused space required to connect the signal cables DL to the driver chip 20 is eliminated. That is, unused space can be minimized.

[0093] The following details the relationship between the connection wiring DM and the pixel P.

[0094] Figure 6 This is a plan view illustrating the configuration of connection wiring and pixels in one embodiment. Figures 7 to 9 This is a plan view showing the configuration of connection wiring and pixels involved in each embodiment.

[0095] Reference Figures 6 to 11 Each pixel P may include multiple sub-pixels. These sub-pixels may include a first sub-pixel R emitting light of a first color, a second sub-pixel G emitting light of a second color, and a third sub-pixel B emitting light of a third color (when no distinction is needed, they are also referred to as sub-pixels R, G, and B). This specification illustrates the case where the first sub-pixel R is a red sub-pixel, the second sub-pixel G is a green sub-pixel, and the third sub-pixel B is a blue sub-pixel, but it is not limited to this. One first sub-pixel R, two second sub-pixels G, and one third sub-pixel B can be defined as one pixel P.

[0096] A pixel P refers to a group of sub-pixels that can represent grayscale. Figure 6 The example illustrates a configuration along the second direction DR2 in the order of second sub-pixel G, first sub-pixel R, second sub-pixel G, and third sub-pixel B, but the configuration of each sub-pixel R, G, and B is not limited to this.

[0097] Subpixels R, G, and B can have different shapes and sizes. Figure 6 The example illustrates the case where the third sub-pixel B has the largest size and the second sub-pixel G has the smallest size, but the sizes of sub-pixels R, G, and B are not limited to this.

[0098] Each sub-pixel R, G, and B can be arranged in a plane between the lateral portions DMA of the connecting wiring DM. The lateral portions DMA may include a first lateral portion DM1 and a second lateral portion DM2. The first lateral portion DM1 and the second lateral portion DM2 are parts of the connecting wiring DM connected to mutually different signal wiring DL, and can be configured to not intersect and be separate from each other. The first lateral portion DM1 and the second lateral portion DM2 can extend in the second direction DR and are arranged sequentially along the first direction DR1 at specific intervals.

[0099] The first horizontal portion DM1 can be configured on one side of sub-pixels R, G, and B, and the second horizontal portion DM2 can be configured on the other side of sub-pixels R, G, and B. That is, the first horizontal portion DM1 can be configured adjacent to one side of the first direction DR1 of sub-pixels R, G, and B, and the second horizontal portion DM2 can be configured adjacent to the other side of the first direction DR1 of sub-pixels R, G, and B. The first horizontal portion DM1 and the second horizontal portion DM2 can be configured not to overlap with sub-pixels R, G, and B.

[0100] For each pixel P, anodes ANO1, ANO2, and ANO3 can be configured. Anodes ANO1, ANO2, and ANO3 can be configured on a plane between the lateral portions DMA of the connecting wiring DM. That is, anodes ANO1, ANO2, and ANO3 can be configured on a plane between the first lateral portion DM1 and the second lateral portion DM. Anodes ANO1, ANO2, and ANO3 can be configured not to overlap with the first lateral portion DM1 and the second lateral portion DM2.

[0101] The anode may include a first anode ANO1 to a third anode ANO3 corresponding to sub-pixels R, G, and B. Specifically, the first anode ANO1 may be configured corresponding to the second sub-pixel G, the second anode ANO2 to the first sub-pixel R, and the third anode ANO3 to the third sub-pixel B. Detailed explanations of the anodes ANO1, ANO2, and ANO3 will be provided later.

[0102] On the other hand, such as Figure 6 As shown, the lateral portion DMA of the connecting wiring DM can be formed by a straight line extending in the second direction DR2, but the portion may be deformed or bent.

[0103] Specifically, such as Figures 7 to 9 As shown, the lateral portion DMA may include a partially bent portion BP. For example, as Figure 7As shown, the first lateral portion DM1 is formed by a straight line extending along the second direction DR2, and the second lateral portion DM2′ may include a bent portion BP that is partially bent from the second direction DR2. The bent portion BP may be a region bent along the edge positions of the anodes ANO1, ANO2, and ANO3. That is, the bent portion BP may be arranged parallel to the edge positions of the anodes ANO1, ANO2, and ANO3 at a specific interval. The bent portion BP of the second lateral portion DM2′ may be bent along the edge position of the first anode ANO1 of the second sub-pixel G. For example, if the first anode ANO1 includes a concave-convex portion, the bent portion BP of the second lateral portion DM2′ may be bent along the concave-convex portion of the first anode ANO1 from the second direction DR2 toward one side and then to the other side, and then back to the second direction DR2. As the second lateral portion DM2′ includes the bent portion BP, the distance between the second lateral portion DM2′ and the anodes ANO1, ANO2, and ANO3 can be reduced. That is, the distance from the first horizontal portion DM1 to the second sub-pixel G can be greater than the distance from the second horizontal portion DM2′ to the second sub-pixel G.

[0104] In addition, such as Figure 8 As shown, the second horizontal portion DM2 can be configured as a straight line, but the first horizontal portion DM1' may include a bent portion BP. The bent portion BP of the first horizontal portion DM1' may be bent along the edge of the second anode ANO2 of the first sub-pixel R. Additionally, the bent portion BP of the first horizontal portion DM1' may be bent along the edge of the third anode ANO3 of the third sub-pixel B. With the first horizontal portion DM1' including the bent portion BP, the distance between the first horizontal portion DM1' and the anodes ANO1, ANO2, and ANO3 can be reduced. That is, the distance from the first horizontal portion DM1' to the first sub-pixel R can be less than the distance from the second horizontal portion DM2 to the first sub-pixel R. Furthermore, the distance from the first horizontal portion DM1' to the third sub-pixel B can be less than the distance from the second horizontal portion DM2 to the third sub-pixel B. However, this is not a limitation. Figures 7 to 8 The illustrated embodiments, such as Figure 9 As shown, both the first transverse portion DM1′ and the second transverse portion DM2′ may include the bent portion BP.

[0105] The structure of pixel P will be explained in more detail below.

[0106] Figure 10 It is a planar diagram representing an example of a pixel.

[0107] Reference Figure 10 Pixel P also includes a first scan line GI, a second scan line GW, an emission control line EM, an initialization voltage line VIL, and a first power supply voltage line VDL.

[0108] The first scan line GI transmits the first scan signal, the second scan line GW transmits the second scan signal, and the light emission control line EM transmits the light emission control signal. The first scan line GI, the second scan line GW, and the light emission control line EM can be arranged in a plane along the second direction DR2. The second scan line GW can be arranged in a plane between the first scan line GI and the light emission control line EM.

[0109] The initialization voltage line VIL transmits the initialization voltage. The initialization voltage line VIL can be configured in the plane along the second direction DR2. The initialization voltage line VIL can be configured in the plane on one side of the first scan line GI, but is not limited to this.

[0110] The signal routing DL transmits data signals and can be configured along the first direction DR1 on the plane, thereby intersecting with the first scan line GI, the second scan line GW, the light emission control line EM, and the initialization voltage line VIL.

[0111] The first power supply voltage line VDL transmits the driving voltage and can be configured on one side of the signal routing line DL. The first power supply voltage line VDL can be configured on a plane along the first direction DR1, so that it can intersect with the first scan line GI, the second scan line GW, the light emission control line EM, and the initialization voltage line VIL.

[0112] The connection routing DM can be configured along either the first direction DR1 or the second direction DR2, and can be configured to partially overlap with the initialization voltage line VIL. Specifically, the lateral portion DMA of the connection routing DM can be configured along the second direction DR2 and overlap with the initialization voltage line VIL. This prevents coupling between the connection routing DM and other routing, which will be explained in detail later.

[0113] Each pixel P may include multiple transistors DT, ST1 to ST6 and capacitor C connected to the first scan line GI, the second scan line GW, the light emission control line EM, the signal wiring DL, the initialization voltage line VIL, and the first power supply voltage line VDL.

[0114] exist Figure 10 The example shown illustrates a pixel P comprising seven transistors DT, ST1 to ST6, and a capacitor C, but this specification is not limited to this.

[0115] The driving transistor DT may include a driving channel region DT_ACT, a driving gate electrode DT_G, a driving source region DT_S, and a driving drain region DT_D. The driving channel region DT_ACT may overlap with the driving gate electrode DT_G. The driving gate electrode DT_G may include a first driving gate electrode DT_G1 and a second driving gate electrode DT_G2. The second driving gate electrode DT_G2 may be disposed on the first driving gate electrode DT_G1, and the first driving gate electrode DT_G1 and the second driving gate electrode DT_G2 may be connected through a second contact hole CNT2. The first driving gate electrode DT_G1 may overlap with the driving channel region DT_ACT, and the second driving gate electrode DT_G2 may be connected to the drain region D2 of the second switching transistor ST2 through a third contact hole CNT3. The driving source region DT_S may be connected to the drain region D1 of the first switching transistor ST1. The driving drain region DT_D may be connected to the source region S2 of the second switching transistor ST2 and the source region S6 of the sixth switching transistor ST6.

[0116] The first switching transistor ST1 may include a first channel region ACT1, a first gate electrode G1, a first source region S1, and a first drain region D1. The first gate electrode G1 may be part of the second scan line GW, and is the overlapping area of ​​the first channel region ACT1 and the second scan line GW. The first source region S1 may be connected to the signal wiring DL through the fourth contact hole CNT4. The first drain region D1 may be connected to the source region DT_S of the driving transistor DT.

[0117] The second switching transistor ST2 may include a second channel region ACT2, a second gate electrode G2, a second source region S2, and a second drain region D2. The second switching transistor ST2 is turned on according to a second scan signal received through the second scan line GW, thereby realizing the diode connection of the driving transistor DT. The second gate electrode G2 may be a part of the second scan line GW, and is the overlapping region of the second channel region ACT2 and the second scan line GW. The second source region S2 may be connected to the drain region DT_D of the driving transistor DT. The second drain region D2 may be connected to the gate electrode DT_G of the driving transistor DT.

[0118] On the other hand, the second switching transistor ST2 can be formed by two transistors. In this case, the second switching transistor ST2 is as follows: Figure 10 As shown, it may include two second channel regions ACT2 and two second gate electrodes G2.

[0119] The third switching transistor ST3 may include a third channel region ACT3, a third gate electrode G3, a third source region S3, and a third drain region D3. The third switching transistor ST3 can be turned on according to a first scan signal received through the first scan line GI, thereby transmitting an initialization voltage to the gate electrode DT_G of the driving transistor DT, and performing an initialization operation to initialize the gate voltage of the driving transistor DT. The third gate electrode G3 may be a part of the first scan line GI, and is the overlapping area of ​​the third channel region ACT3 and the first scan line GI. The third source region S3 may be connected to the gate electrode DT_G of the driving transistor DT and the drain region D2 of the second switching transistor ST2. The third drain region D3 may be connected to the initialization voltage line VIL through the fifth contact hole CNT5.

[0120] On the other hand, the third switching transistor ST3 can be formed from two transistors. In this case, the third switching transistor ST3 can be as follows: Figure 10 As shown, it includes two third channel regions ACT3 and two third gate electrodes G3.

[0121] The fourth switching transistor ST4 may include a fourth channel region ACT4, a fourth gate electrode G4, a fourth source region S4, and a fourth drain region D4. The fourth gate electrode G4 may be part of the first scan line GI, and is the overlapping region of the fourth channel region ACT4 and the first scan line GI. The fourth source region S4 may be connected to the anode (not shown) of the organic light-emitting element. The fourth drain region D4 may be connected to the initialization voltage line VIL through the fifth contact hole CNT5.

[0122] Specifically, the initialization voltage line VIL can be connected to the initialization connection electrode VIE through the sixth contact hole CNT6, and the initialization connection electrode VIE can be connected to the drain region D3 of the third switching transistor ST3 through the fifth contact hole CNT5. The initialization connection electrode VIE can be configured to intersect with the first scan line GI. In addition, the anode (not shown) can be connected to the anode connection electrode ANDE through the anode contact hole ANO_CNT, and the anode connection electrode ANDE can be connected to the source region S4 of the fourth switching transistor ST4 through the seventh contact hole CNT7.

[0123] The fifth switching transistor ST5 may include a fifth channel region ACT5, a fifth gate electrode G5, a fifth source region S5, and a fifth drain region D5. The fifth gate electrode G5 may be part of the light-emitting control line EM, and is the overlapping area of ​​the fifth channel region ACT5 and the light-emitting control line EM. The fifth source region S5 may be connected to the source region DT_S of the driving transistor DT and the drain region D1 of the first switching transistor ST1. The fifth drain region D5 may be connected to the first power supply voltage line VDL through the eighth contact hole CNT8.

[0124] The sixth switching transistor ST6 may include a sixth channel region ACT6, a sixth gate electrode G6, a sixth source region S6, and a sixth drain region D6. The sixth gate electrode G6 may be part of the light-emitting control line EM, and is the overlapping area of ​​the sixth channel region ACT6 and the light-emitting control line EM. The sixth source region S6 may be connected to the drain region DT_D of the driving transistor DT and the source region S2 of the second switching transistor ST2. The sixth drain region D6 may be connected to the anode (not shown) of the organic light-emitting element. The fifth switching transistor ST5 and the sixth switching transistor ST6 are simultaneously turned on according to the light-emitting control signal received through the light-emitting control line EM, thereby allowing current to flow through the organic light-emitting element.

[0125] It is possible that the first electrode CE1 of capacitor C is substantially the same as the gate electrode DT_G of driving transistor DT, the second electrode CE2 overlaps with the gate electrode DT_G of driving transistor DT, and is connected to the first power supply voltage line VDL through the ninth contact hole CNT9.

[0126] The cross-sectional structure of pixel P is described in detail below.

[0127] Figure 11 Therefore Figure 10 The sectional view is taken with the Ⅱ-Ⅱ′ line as the reference.

[0128] exist Figure 11 In this context, for some constituent elements, if they are the same structure as the aforementioned constituent elements, new symbols are added to clarify the interlayer composition, and these symbols are recorded at all times.

[0129] Reference Figure 11 Each pixel P may include a substrate 101, a buffer layer BF, a semiconductor layer, a first insulating layer IL1, a first conductive layer 110, a second insulating layer IL2, a second conductive layer 120, a third insulating layer IL3, a third conductive layer 130, a fourth insulating layer IL4, a fourth conductive layer 140, a fifth insulating layer IL5, a first electrode layer 171, a pixel definition film 180 having an opening that exposes the first electrode layer 171, an organic layer 172 disposed in the opening of the pixel definition film 180, and a second electrode layer 173 disposed on the organic layer 172 and the pixel definition film 180.

[0130] Each of the above layers can be formed from a single membrane, or from a stack of membranes comprising multiple membranes. Other layers may also be disposed between the layers.

[0131] The substrate 101 supports the layers disposed thereon. The substrate 101 may be formed of an insulating material such as a polymer resin. Examples of such insulating materials include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or combinations thereof. The substrate 101 may be a flexible substrate 101 capable of bending, folding, rolling, etc. Examples of materials used to form flexible substrates include polyimide (PI), but are not limited to this. Substrate 101 may also be a rigid substrate formed of glass, quartz, etc.

[0132] A buffer layer BF is disposed on the substrate 101. The buffer layer BF prevents the diffusion of impurity ions and the penetration of moisture or external gases, and performs a surface planarization function. The buffer layer BF may include silicon nitride, silicon oxide, or silicon oxide nitride, etc.

[0133] A semiconductor layer is disposed on the buffer layer BF. The semiconductor layer forms the channel for the driving transistor DT of pixel P and the first switching transistors ST1 to the sixth switching transistors ST6. The semiconductor layer may include polycrystalline silicon. The polycrystalline silicon may be formed by crystallizing amorphous silicon.

[0134] When the semiconductor layer is formed of polycrystalline silicon, the ion-doped semiconductor layer can become conductive when ions are doped into it. Therefore, the semiconductor layer includes not only the channel regions of the driving transistor DT and the first switching transistors ST1 to ST6, but also source and drain regions. Specifically, the semiconductor layer may include the driving channel region DT_ACT of the driving transistor DT, and the first channel regions ACT1 to ACT6 of the first switching transistors ST1 to ST6. Furthermore, the semiconductor layer may include the driving source region DT_S, the driving drain region DT_D, the first source regions S1 to S6, and the first drain regions D1 to D6, respectively, located on either side of the driving channel region DT_ACT.

[0135] Each source region DT_S, S1 to S6 and each drain region DT_D, D1 to D6 are connected to both sides of each channel region DT_ACT, ACT1 to ACT6 in the plane.

[0136] In other embodiments, the semiconductor layer may include monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or oxide semiconductor. The oxide semiconductor may, for example, include binary compounds AB containing indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. x ternary compound AB x Cy, quaternary compound AB x C y D z In one embodiment, the semiconductor layer may include ITZO (an oxide of indium, tin, and titanium) or IGZO (an oxide of indium, gallium, and tin).

[0137] A first insulating layer IL1 is disposed on the semiconductor layer. The first insulating layer IL1 can be disposed approximately across the entire surface of the substrate 101. The first insulating layer IL1 can be a gate insulating film with gate insulation function. The first insulating layer IL1 may include silicon compounds, metal oxides, etc. For example, the first insulating layer IL1 may include silicon oxide, silicon nitride, silicon nitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. The first insulating layer IL1 can be a single film or a multilayer film formed by stacking films of different materials.

[0138] A first conductive layer 110 is disposed on the first insulating layer IL1. The first conductive layer 110 may comprise one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer 110 may be a single film or a multilayer film.

[0139] The first scan line GI, the second scan line GW, and the light emission control line EM can be formed by the first conductive layer 110. In addition, the first driving gate electrode DT_G1 of the driving transistor DT and the first gate electrodes G1 to the sixth gate electrodes G6 of the first switching transistor ST1 to the sixth switching transistor ST6 can be respectively part of the first scan line GI or the second scan line GW, and are formed by the first conductive layer 110.

[0140] A second insulating layer IL2 is disposed on the first conductive layer 110. The second insulating layer IL2 can be disposed across approximately the entire surface of the substrate 101. The second insulating layer IL2 serves to insulate the first conductive layer 110 and the second conductive layer 120.

[0141] The second insulating layer IL2 may be an interlayer insulating film. The second insulating layer IL2 may include the same material as the first insulating layer IL1 described above, or one or more materials selected from those exemplified as constituent materials of the first insulating layer IL1.

[0142] A second conductive layer 120 is disposed on the second insulating layer IL2. The initialization voltage line VIL and the second gate electrode DT_G2 of the driving transistor DT can be formed by the second conductive layer 120.

[0143] The second conductive layer 120 may comprise one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The second conductive layer 120 may be formed of the same material as the first conductive layer 110, but is not limited thereto. The second conductive layer 120 may be a single film or a multilayer film.

[0144] The third insulating layer IL3 covers the second conductive layer 120. The third insulating layer IL3 insulates the second conductive layer 120 and the third conductive layer 130. The third insulating layer IL3 may include the same material as the first insulating layer IL1 described above, or one or more materials selected from those exemplified as constituent materials of the first insulating layer IL1.

[0145] A third conductive layer 130 is disposed on the third insulating layer IL3. The third conductive layer 130 may comprise one or more metals selected from aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The third conductive layer 130 may be a single film or a multilayer film. For example, the third conductive layer 130 may be formed from a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Ti / Cu, etc.

[0146] The third conductive layer 130 may include signal wiring DL and a first power supply voltage line VDL.

[0147] The fourth insulating layer IL4 covers the third conductive layer 130. The fourth insulating layer IL4 can be a through-hole layer. The fourth insulating layer IL4 may include organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB).

[0148] A fourth conductive layer 140 is disposed on the fourth insulating layer IL4. The fourth conductive layer 140 may include the same material as the third conductive layer 130 described above, or one or more materials selected from those exemplified as constituent materials of the third conductive layer 130.

[0149] The fourth conductive layer 140 may include interconnect wiring DM. The lateral portion DMA of the interconnect wiring DM may be configured not to overlap with the first scan line GI. Alternatively, the lateral portion DMA may be configured to overlap with the initialization voltage line VIL. The lateral portion DMA may completely overlap with the initialization voltage line VIL in the thickness direction.

[0150] Specifically, when the lateral portion DMA of the connection wiring DM overlaps with the first scan line GI, data signal distortion may occur due to the coupling between the connection wiring DM and the first scan line GI.

[0151] When the same scan signal is supplied to the first scan line GI of one pixel and the second scan line GW of another pixel, and the connection wiring DM of one pixel is connected to the signal wiring DL of the other pixel, data signal distortion may occur due to the coupling between the lateral portion DMA of the connection wiring DM of one pixel and the first scan line GI. That is, a distorted data signal may be input to the signal wiring DL of the other pixel. As a result, a brightness difference may occur between one pixel and another, which may lead to spots caused by the brightness difference.

[0152] To address this, the display device 1 of this embodiment is configured such that the lateral portion DMA of the connecting wiring DM does not overlap with the first scan line GI, thereby preventing the formation of parasitic capacitance between the lateral portion DMA of the connecting wiring DM and the first scan line GI. Furthermore, the initialization voltage line VIL disposed between the connecting wiring DM and the first scan line GI overlaps with the connecting wiring DM, thereby minimizing or preventing coupling between the two wirings. In other words, it prevents data signal distortion and the appearance of speckles, thus improving display quality.

[0153] The fifth insulating layer IL5 covers the fourth conductive layer 140. The fifth insulating layer IL5 may be a via layer. The fifth insulating layer IL5 may include the same material as the fourth insulating layer IL4 described above, or one or more materials selected from those exemplified as constituent materials of the fourth insulating layer IL4.

[0154] A first electrode layer 171 is disposed on the fifth insulating layer IL5. While not limited to the following, the first electrode layer 171 can have a laminated film structure comprising layers of materials with high work functions, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium oxide (In2O3), and reflective materials such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or mixtures thereof. The layer with the high work function can be disposed above the reflective material layer, making it close to the organic layer 172. The first electrode layer 171 can have multiple layer structures such as ITO / Mg, ITO / MgF, ITO / Ag, and ITO / Ag / ITO, but is not limited to these.

[0155] The anodes ANO1, ANO2, and ANO3 of pixel P can be formed by the first electrode layer 171. The anodes ANO1, ANO2, and ANO3 can be configured to not overlap with the lateral portion DMA of the connecting wiring DM. This prevents spots caused by coupling.

[0156] A pixel defining film 180 may be disposed on the first electrode layer 171. The pixel defining film 180 may include an opening that exposes the first electrode layer 171. The pixel defining film 180 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon nitride oxide, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, and zinc oxide, or organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or baenzocyclobutene (BCB). The pixel defining film 180 may be a single film or a multilayer film formed by stacking films of different materials.

[0157] An organic layer 172 is disposed within the opening of the pixel defining film 180. The organic layer 172 may include an organic light-emitting layer, a hole injection / transport layer, and an electron injection / transport layer.

[0158] The second electrode layer 173 is disposed on the organic layer 172 and the pixel defining film 180. A cathode CAT may be formed from the second electrode layer 173. The cathode CAT may be disposed across the entire display area. The second electrode layer 173 may include a layer of material with a low work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, or compounds or mixtures thereof (e.g., mixtures of Ag and Mg). The second electrode layer 173 may also include a transparent metal oxide layer disposed on the material layer with the low work function.

[0159] As described above, the display device 1 is configured such that the lateral portion DMA of the connecting wiring DM does not overlap with the first scan line GI, thereby preventing the formation of parasitic capacitance between the lateral portion DMA of the connecting wiring DM and the first scan line GI. Furthermore, it is configured such that the initialization voltage line VIL disposed between the connecting wiring DM and the first scan line GI overlaps with the connecting wiring DM, thereby minimizing or preventing coupling between the two wirings. That is, it prevents data signal distortion and the appearance of speckles, thus improving display quality.

[0160] Other embodiments are described below.

[0161] Figure 12 This is a plan view representing an example of pixels involved in other embodiments. Figure 13 Therefore Figure 12 The sectional view is taken with the Ⅱ-Ⅱ′ line as the reference.

[0162] Reference Figure 12 as well as Figure 13 The display device involved in this embodiment and Figure 10 as well as Figure 11 The difference in the embodiment is that the first power supply voltage line VDL′ extends and overlaps with the lateral portion DMA of the connection wiring DM.

[0163] Specifically, the first power supply voltage line VDL′ can be configured between the connecting wiring DM and the first scan line GI, and can be configured to overlap with the lateral portion DMA of the connecting wiring DM and the first scan line GI. That is, the first power supply voltage line VDL′ can overlap with the lateral portion DMA of the connecting wiring DM in the thickness direction. Furthermore, the first power supply voltage line VDL′ can be configured to overlap with the first scan line GI in the thickness direction. In other words, the first power supply voltage line VDL′ can also be configured between the lateral portion DMA of the connecting wiring DM and the first scan line GI. This more effectively prevents coupling between the lateral portion DMA of the connecting wiring DM and the first scan line GI.

[0164] Figure 14 This is a plan view representing an example of pixels in yet another embodiment. Figure 15 Therefore Figure 14 The sectional view is taken with the Ⅱ-Ⅱ′ line as the reference.

[0165] Reference Figure 14 as well as Figure 15 The display device involved in this embodiment and Figure 10 as well as Figure 11 The difference in the embodiment is that, on the plane, the initialization voltage line VIL′ is configured between the lateral portion DMA of the connection wiring DM and the first scan line GI.

[0166] Specifically, the lateral portion (DMA) of the connecting wiring DM and the first scan line GI can be configured to be separate from each other, and the initialization voltage line VIL′ is disposed in the space where the lateral portion (DMA) of the connecting wiring DM and the first scan line GI are separated. That is, the lateral portion (DMA) of the connecting wiring DM can be disposed on one side of the initialization voltage line VIL′ so that the lateral portion (DMA) of the connecting wiring DM and the first scan line GI do not overlap, and the first scan line GI is disposed on the other side of the initialization voltage line VIL′. Thus, as described above, coupling between the lateral portion (DMA) of the connecting wiring DM and the first scan line GI can be prevented to improve display quality.

[0167] On the other hand, Figure 14 as well as Figure 15 The example illustrates a case where the lateral portion (DMA) of the connection wiring DM and the initialization voltage line (VIL′) are configured not to overlap in the thickness direction, but it is not limited to this. That is, the lateral portion (DMA) of the connection wiring DM can be configured to partially overlap with the initialization voltage line (VIL′).

[0168] Figure 16 This is a plan view representing an example of pixels in yet another embodiment. Figure 17 Therefore Figure 16 The sectional view is taken with the Ⅱ-Ⅱ′ line as the reference.

[0169] Reference Figure 16 as well as Figure 17 The display device involved in this embodiment and Figure 14 as well as Figure 15 The difference in the embodiment is that the first power supply voltage line VDL′ extends and overlaps with the lateral portion DMA of the connection wiring DM.

[0170] Specifically, the first power supply voltage line VDL′ can be configured between the connection wiring DM and the first scan line GI, thereby overlapping with the lateral portion DMA of the connection wiring DM and the first scan line GI. That is, the first power supply voltage line VDL′ can overlap with the lateral portion DMA of the connection wiring DM in the thickness direction. Furthermore, the first power supply voltage line VDL′ can be configured to overlap with the first scan line GI in the thickness direction. That is, the first power supply voltage line VDL′ can also be configured between the lateral portion DMA of the connection wiring DM and the first scan line GI. Therefore, as described above, coupling between the lateral portion DMA of the connection wiring DM and the first scan line GI can be prevented more effectively.

[0171] Figure 18 This is a plan view representing an example of pixels in yet another embodiment. Figure 19 Therefore Figure 18 The sectional view is taken with the Ⅱ-Ⅱ′ line as the reference.

[0172] Reference Figure 18 as well as Figure 19 The display device involved in this embodiment and Figure 10 as well as Figure 11 The difference in the embodiment is that the initialization voltage line VIL″ includes an extension VIL_EP.

[0173] Specifically, the initialization voltage line VIL″ may include an extension VIL_EP extending to one side. The extension VIL_EP may extend from the initialization voltage line VIL″ configured on the second direction DR2 in the opposite direction to the first direction DR1. The extension VIL_EP may be configured to overlap with the first scan line GI. The width of the extension VIL_EP on the first direction DR1 may be greater than the width of the first scan line GI on the first direction DR1. With the extension VIL_EP of the initialization voltage line VIL″ overlapping with the first scan line GI, coupling between the lateral portion DMA of the connection wiring DM and the first scan line GI can be more effectively prevented.

[0174] Figure 20 This is a plan view representing an example of pixels in yet another embodiment. Figure 21 Therefore Figure 20 The sectional view is taken with the Ⅱ-Ⅱ′ line as the reference.

[0175] Reference Figure 20 as well as Figure 21 The display device involved in this embodiment and Figure 18 as well as Figure 19 The difference in the embodiment is that the first power supply voltage line VDL′ extends and overlaps with the lateral portion DMA of the connection wiring DM.

[0176] Specifically, the first power supply voltage line VDL′ can be configured between the connecting wiring DM and the first scan line GI, and can be configured to overlap with the lateral portion DMA of the connecting wiring DM and the first scan line GI. That is, the first power supply voltage line VDL′ can overlap with the lateral portion DMA of the connecting wiring DM in the thickness direction. Furthermore, the first power supply voltage line VDL′ can be configured to overlap with the first scan line GI in the thickness direction. That is, the first power supply voltage line VDL′ can also be configured between the lateral portion DMA of the connecting wiring DM and the first scan line GI. Therefore, as described above, coupling between the lateral portion DMA of the connecting wiring DM and the first scan line GI can be prevented more effectively.

[0177] Figure 22 This is a plan view representing an example of pixels in yet another embodiment. Figure 23 Therefore Figure 22 The sectional view is taken with the Ⅱ-Ⅱ′ line as the reference.

[0178] Reference Figure 22 as well as Figure 23 The display device involved in this embodiment and Figure 10 as well as Figure 11 The difference in the embodiment is that it also includes a coupling blocking layer CSL disposed between the connection wiring DM′ and the first scan line GI.

[0179] Specifically, the coupling blocking layer CSL can be configured to extend along the second direction DR2 in the plane and completely overlap with the connection routing DM′. Additionally, the coupling blocking layer CSL can be configured to completely overlap with the first scan line GI in the plane. Configuring the coupling blocking layer CSL to overlap with both the connection routing DM′ and the first scan line GI more effectively reduces coupling between the two routing lines.

[0180] Additionally, the coupling blocking layer CSL can be configured to extend along the first direction DR1 and overlap with the first power supply voltage line VDL. The coupling blocking layer CSL can be electrically connected to the first power supply voltage line VDL through the tenth contact hole CNT10. This reduces the resistance of the first power supply voltage line VDL.

[0181] The coupling blocking layer CSL is disposed on the fourth insulating layer IL4. The coupling blocking layer CSL may be formed from the fourth conductive layer 140. The fourth conductive layer 140 has been described above, so the details are omitted.

[0182] A fifth insulating layer IL5 is disposed on the fourth conductive layer 140, and a connection wiring DM' is disposed on the fifth insulating layer IL5. The connection wiring DM' may be formed by the fifth conductive layer 150. The fifth conductive layer 150 may include the same material as the fourth conductive layer 140 described above, or one or more materials selected from those exemplified as constituent materials of the fourth conductive layer 140.

[0183] A sixth insulating layer IL6 is disposed on the fifth conductive layer 150. The sixth insulating layer IL6 may be a via layer. The sixth insulating layer IL6 may include the same material as the fifth insulating layer IL5 described above, or one or more materials selected from those exemplified as constituent materials of the fifth insulating layer IL5.

[0184] A first electrode layer 171 is disposed on the sixth insulating layer IL6. The first electrode layer 171 has been described above, so the details are omitted.

[0185] Figure 24 This is a plan view illustrating the connection wiring involved in yet another embodiment.

[0186] Reference Figure 24 The display device involved in this embodiment and Figure 6 The difference in the embodiments is that they include multiple branch patterns DMP1, DMP2, DMP3, and DMP4.

[0187] Specifically, the first lateral portion DM1 of the connecting cabling DM may include a first branch pattern DMP1 and a second branch pattern DMP2, and the second lateral portion DM2′ of the connecting cabling DM may include a third branch pattern DMP3 and a fourth branch pattern DMP4.

[0188] It is possible that the first branch pattern DMP1 protrudes from one side of the first horizontal portion DM1 toward the first direction DR1, and the second branch pattern DMP2 protrudes from the other side of the first horizontal portion DM1 toward the opposite direction of the first direction DR1.

[0189] It is possible that the third branch pattern DMP3 protrudes from one side of the second horizontal portion DM2′ toward the first direction DR1, and the fourth branch pattern DMP4 protrudes from the other side of the second horizontal portion DM2′ toward the opposite direction of the first direction DR1.

[0190] The first branch patterns DMP1 to the fourth branch patterns DMP4 can be configured to be parallel to each other. Additionally, the first branch patterns DMP1 to the fourth branch patterns DMP4 configured in the same column can be aligned with each other.

[0191] The first branch patterns DMP1 to the fourth branch patterns DMP4 can have the same spacing and be arranged along the second direction DR2. The spacing between the first branch patterns DMP1 to the fourth branch patterns DMP4 in the second direction DR2 can be the same as the spacing between the vertical portions DMB of the connecting wiring DM in the second direction DR2. Therefore, the first branch patterns DMP1 to the fourth branch patterns DMP4, together with the horizontal portion DMA, can achieve a grid pattern shape in the display area DA. That is, irregular patterns in the vertical and horizontal portions of the connecting wiring DM can be minimized, thus preventing the pattern from being recognized.

[0192] One end of the second branch pattern DMP2 and one end of the third branch pattern DMP3 can be configured to be separate from each other. Therefore, a gap GAP can be defined between one end of the second branch pattern DMP2 and one end of the third branch pattern DMP3. The gap GAP can be configured not to overlap with the anodes ANO1, ANO2, and ANO3. That is, the gap GAP can be positioned in the space where the first anode ANO1 to the third anode ANO3 are separated. In other words, one end of the second branch pattern DMP2 and one end of the third branch pattern DMP3 can be configured not to overlap with the anodes ANO1, ANO2, and ANO3.

[0193] Figure 25 This is a plan view illustrating the connection wiring involved in yet another embodiment.

[0194] Reference Figure 25 The display device involved in this embodiment and Figure 24The difference in the embodiments is that the gap GAP is configured to overlap with the anodes ANO1, ANO2, and ANO3.

[0195] Specifically, the gap is configured to overlap with the first anode ANO1 to the third anode ANO3. The size of the gap overlapping with each anode ANO1, ANO2, and ANO3 can vary depending on the size of the anodes ANO1, ANO2, and ANO3. For example, the gap overlapping with the first anode ANO1 can be smaller than the gap overlapping with the second anode ANO2. Furthermore, the gap overlapping with the first anode ANO1 can be smaller than the gap overlapping with the third anode ANO3.

[0196] As described above, the display device according to this embodiment can be configured such that the first anode ANO1 to the third anode ANO3 overlap with the gap GAP, thereby blocking the gap GAP disposed in the display area DA. This prevents the reflection of external light caused by the gap GAP and the identification of spots, thereby further improving display quality.

[0197] Figure 26 This is a plan view illustrating the connection wiring involved in yet another embodiment.

[0198] Reference Figure 26 The display device involved in this embodiment and Figure 24 The difference in the embodiments is that the multiple branch patterns DMP1, DMP2, DMP3, DMP4 are configured to not overlap with the anodes ANO1, ANO2, ANO3.

[0199] Specifically, the anodes ANO1, ANO2, and ANO3 are configured to not overlap with the second branch pattern DMP2 and the third branch pattern DMP3 on the plane. That is, the anodes ANO1, ANO2, and ANO3 can be configured between the opposing second branch pattern DMP2 and the third branch pattern DMP3. Specifically, the anodes ANO1, ANO2, and ANO3 can be configured within the gap GAP defined between one end of the second branch pattern DMP2 and one end of the third branch pattern DMP3.

[0200] Figure 27 This is a perspective view of a display device according to yet another embodiment. Figure 28 yes Figure 27 An unfolded diagram of the display device. Figure 29 It means Figure 27 A plan view of the signal wiring and connection wiring of the display device.

[0201] Reference Figure 27 as well as Figure 29In this embodiment, the display device 1_2, as the display area DA, may include the main display area DA0 and the first sub-display area DA1 to the fourth sub-display area DA4.

[0202] The main display area DA0 may be located on a plane of the display device 1_2, and has the widest area (or size) among the main display area DA0 and the first to fourth sub-display areas DA1 to DA4. For example, the main display area DA0 may be located on the upper surface of the display device 1_2. The main display area DA0 may have a polygonal shape such as a rectangle, or a planar shape such as a circle or an ellipse.

[0203] The first sub-display areas DA1 to DA4 can be located on planes different from the plane of the main display area DA0. Each of the first sub-display areas DA1 to DA4 has an area smaller than the main display area DA0, and they can be located on different planes. The first sub-display areas DA1 to DA4 can extend from each side of the main display area DA0.

[0204] The main display area DA0 and the first sub-display areas DA1 to the fourth sub-display areas DA4 can be configured within the main area MR.

[0205] The non-display area NDA can be configured on the unfolded view of the display device 1_2 along the outermost edge of the main display area DA0 and the first sub-display area DA1 to the fourth sub-display area DA4.

[0206] The non-display area NDA may include a first corner portion 21 to a fourth corner portion 24. The first corner portion 21 to the fourth corner portion 24 may be configured adjacent to the corner portion (i.e., the part where the two sides intersect) of the main display area DA0.

[0207] The first corner portion 21 to the fourth corner portion 24 are substantially identical to each other except for their respective positions. Hereinafter, based on the first corner portion 21, the common features of the first corner portion 21 to the fourth corner portion 24 will be explained, thereby omitting repeated explanations.

[0208] The first corner portion 21 may have a shape that protrudes outward from the corner of the main display area DA0. The first corner portion 21 may be located between the first sub-display area DA1 and the fourth sub-display area DA4, and the intersection angle between the first sub-display area DA1 and the fourth sub-display area DA4 may be mitigated by an obtuse angle. One end of the first corner portion 21 may be located in the first sub-display area DA1, and the other end may be located in the fourth display area DA4.

[0209] The first corner portion 21 provides space for configuring signal wiring DL or for the signal wiring DL to pass through. When the first sub-display area DA1 and the fourth sub-display area DA4 of the display panel 10 are bent or folded, the first corner portion 21 can be folded inwards (i.e., towards the internal space of the display device 1 or the center of weight). In this case, the first corner portion 21 is bent, and one end of the first corner portion 21 (i.e., the first portion adjacent to the first sub-display area DA1) and the other end of the first corner portion 21 (i.e., the second portion adjacent to the fourth sub-display area DA4) can be opposite each other. One end and the other end of the first corner portion 21 can be joined together or bonded through a bonding layer or the like.

[0210] Since the first corner portion 21 is bent inward when the first sub-display area DA1 and the fourth sub-display area DA4 are bent, the first corner portion 21 does not need to be exposed to the outside. Therefore, the first corner portion 21 to the fourth corner portion 24 can be included in the non-display area NDA.

[0211] The non-display area NDA also includes a curved area BR and a sub-area SR. The curved area BR can be connected to at least one of the first sub-display areas DA1 to the fourth sub-display area DA4. For example, the curved area BR can be connected to one side of the fourth sub-display area DA4 (e.g., the lower side of the fourth sub-display area DA4 in the unfolded view of the display device 1_2).

[0212] like Figure 28 As shown, when the fourth sub-display area DA4 is bent or flexed vertically relative to the main display area DA0, the flexed area BR can be bent or flexed again vertically relative to the fourth sub-display area DA4 (i.e., bent or flexed at an angle of 180° relative to the main display area DA0). The sub-area SR located on one side of the flexed area BR can be configured at the lower part of the main display area DA0 in the thickness direction of the main display area DA0. The sub-area SR can overlap with and be configured parallel to the main display area DA0.

[0213] A driver chip IC can be configured in the sub-region SR. As described above, as the sub-region SR is bent and reversed starting from the main display area DA0, the upper surface of the driver chip IC can face the opposite direction to the third direction DR3. On the other hand, the driver chip IC in this embodiment can be compared with the reference... Figures 1 to 3 The driver chip ICs described are essentially the same, so detailed descriptions of them are omitted.

[0214] The connecting cable DM extends from the non-display area NDA on the lower side of the fourth sub-display area DA4 along the first direction DR1, and then extends in the opposite direction of the second direction DR2 within the display area DA. In areas adjacent to or intersecting with the corresponding signal cables DL connected to each connecting cable DM, it extends to one end of the corresponding signal cable DL. That is, the connecting cable DM can extend to the non-display area NDA on the lower side of the first sub-display area DA1 and to the first corner 21. The connecting cable DM can be directly connected one-to-one with the corresponding signal cable DL through the first contact hole CNT1 located in the non-display area NDA on the lower side of the first sub-display area DA1 and the first corner 21.

[0215] As described above, the display device 1_2 includes connection wiring DM configured via the display area DA, thereby eliminating the need for additional unused space required to connect the signal wiring DL configured in the first sub-display area DA1 to the driver chip 20. That is, unused space can be minimized.

[0216] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, those skilled in the art should understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the invention. Therefore, the embodiments described above are illustrative in all respects and should not be construed as limiting.

Claims

1. A display device, comprising: The substrate includes a display area and a non-display area; Multiple signal wirings extend in a first direction from the non-display area on the substrate, thereby being configured in the display area; Connecting wiring extends on the substrate from the non-display area and passes through the display area, and is electrically connected to the signal wiring in the non-display area; as well as An initialization voltage line extends on the substrate in a second direction intersecting the first direction. The initialization voltage line is located in the display area. In the display area, the connection wiring overlaps with the initialization voltage line in the thickness direction, and The connection wiring is arranged on a different layer than the signal wiring.

2. The display device according to claim 1, wherein, The initialization voltage line is formed by a second conductive layer. The signal wiring is formed by a third conductive layer disposed on the second conductive layer. The connection wiring is formed by a fourth conductive layer disposed on the third conductive layer.

3. The display device according to claim 2, wherein, The display device further includes a first power supply voltage line disposed between the initialization voltage line and the connection wiring. The first power supply voltage line overlaps with the connection wiring in the thickness direction.

4. The display device according to claim 3, wherein, The display device further includes scan lines disposed between the substrate and the initialization voltage line. The first power supply voltage line overlaps with the scan line in the thickness direction.

5. The display device according to claim 4, wherein, The first power supply voltage line is formed by the third conductive layer. The scan line is formed by a first conductive layer disposed between the substrate and the second conductive layer.

6. The display device according to claim 1, wherein, The connection wiring is configured to transmit data signals generated by the driver to the signal wiring.

7. The display device according to claim 1, wherein, The connection wiring starts from the non-display area and extends in the first direction, and then changes direction to extend in the second direction within the display area, extending to the non-display area at one end of the corresponding signal wiring in an area adjacent to or intersecting with the corresponding signal wiring.

8. The display device according to claim 7, wherein, The connecting wiring includes a lateral portion extending in the second direction.

9. The display device according to claim 8, wherein, The lateral portion is configured to overlap with the initialization voltage line in the thickness direction.

10. The display device according to claim 8, wherein, The initialization voltage line is arranged on the plane between the horizontal portion and the scan line.

11. The display device according to claim 8, wherein, The display device further includes a first power supply voltage line disposed between the initialization voltage line and the connection wiring. The lateral portion overlaps with the first power supply voltage line in the thickness direction.

12. The display device according to claim 8, wherein, The display device further includes scan lines disposed between the substrate and the initialization voltage line. The lateral portion is configured not to overlap with the scan line.

13. The display device according to claim 12, wherein, The initialization voltage line includes an extension that extends to one side and overlaps with the scan line.

14. The display device according to claim 8, wherein, The display device further includes a positive electrode disposed on the connection wiring. The lateral portion does not overlap with the anode in the thickness direction.

15. The display device according to claim 14, wherein, The lateral portion includes multiple branch patterns, and the multiple branch patterns overlap with the anode.

16. The display device according to claim 2, wherein, The display device further includes a coupling blocking layer disposed between the initialization voltage line and the connection wiring. The coupling blocking layer overlaps with the connection wiring in the thickness direction.

17. The display device according to claim 16, wherein, The display device further includes a first power supply voltage line disposed between the initialization voltage line and the connection wiring. The coupling blocking layer is electrically connected to the first power supply voltage line.

Images