Gate driver, display device, and electronic device

Abstract

The invention relates to a gate driver, a display device and an electronic device. The gate driver includes: an input circuit transmitting an input signal to a control circuit based on a first clock signal; a control circuit that controls a voltage of a control node based on an input signal, a first clock signal, a second clock signal, and a voltage control signal; and an output circuit outputting a gate signal based on the voltage of the control node. The control circuit transmits one of the first power supply voltage and the second power supply voltage to a control node, and the output circuit outputs one of the first power supply voltage and the third power supply voltage as a gate signal.

Description

Technical Field

[0001] The embodiments supported by this disclosure relate to gate drivers, display devices including gate drivers, and electronic devices including display devices. Background Technology

[0002] The display device may include a display panel and a display panel driver. The display panel may include multiple gate lines, multiple emitter lines, multiple data lines, and multiple pixels. The display panel driver may include a gate driver that provides gate signals to the gate lines, an emitter driver that provides emitter signals to the emitter lines, a data driver that provides data voltages to the data lines, and a drive controller that controls the gate driver, emitter driver, and data driver.

[0003] In some cases, as the size of the transistors included in the gate driver increases, the capacitance of the parasitic capacitors associated with the gate driver may increase, and the power consumption of the display device may increase due to the charging and discharging of the parasitic capacitors. Summary of the Invention

[0004] The embodiments supported by this disclosure provide gate drivers that reduce power consumption of display devices and have improved stability.

[0005] The embodiments supported by this disclosure provide a display device including a gate driver.

[0006] The embodiments supported by this disclosure provide electronic devices including a display device.

[0007] In a gate driver according to an embodiment of the present disclosure, the gate driver includes: an input circuit that sends an input signal to a control circuit based on a first clock signal; a control circuit that controls the voltage of a control node based on the input signal, the first clock signal, a second clock signal, and a voltage control signal; and an output circuit that outputs a gate signal based on the voltage of the control node. The control circuit includes: a fifth transistor including a control electrode connected to a second node, a first electrode receiving a first power supply voltage, and a second electrode connected to the control node; a sixth transistor including a control electrode connected to a fourth node, a first electrode connected to the control node, and a second electrode receiving a second power supply voltage; and a ninth transistor including a control electrode receiving a voltage control signal, a first electrode connected to a third node, and a second electrode connected to the fourth node. The control circuit sends one of the first power supply voltage and the second power supply voltage to the control node, and the output circuit outputs one of the first power supply voltage and the third power supply voltage as a gate signal.

[0008] In one embodiment, the input circuit may include a first transistor, which includes a control electrode for receiving a first clock signal, a first electrode for receiving an input signal, and a second electrode connected to a first node. The control circuit may further include: a second transistor, including a control electrode for receiving a third power supply voltage, a first electrode connected to a first node, and a second electrode connected to a third node; a third transistor, including a control electrode connected to a third node, a first electrode for receiving a second clock signal, and a second electrode connected to a second node; a fourth transistor, including a control electrode for receiving the first clock signal, a first electrode for receiving the first power supply voltage, and a second electrode connected to a second node; a first capacitor, including a first electrode connected to a second node and a second electrode connected to a third node; a second capacitor, including a first electrode for receiving the first power supply voltage and a second electrode connected to a second node; and a third capacitor, including a first electrode connected to a second node and a second electrode connected to a fourth node.

[0009] In one embodiment, the output circuit may include: a seventh transistor, including a control electrode connected to the control node, a first electrode receiving a first power supply voltage, and a second electrode connected to the output node; and an eighth transistor, including a control electrode connected to the control node, a first electrode connected to the output node, and a second electrode receiving a third power supply voltage.

[0010] In an implementation, the level of the first power supply voltage may be higher than the level of the third power supply voltage, and the level of the third power supply voltage may be higher than the level of the second power supply voltage.

[0011] In the implementation, the sixth, eighth, and ninth transistors can be implemented as transistors of a first type, and the first to fifth transistors and the seventh transistor can be implemented as transistors of a second type, different from the transistors of the first type.

[0012] In the implementation, the sixth, eighth, and ninth transistors can be implemented as N-type transistors.

[0013] In an implementation, the first to fifth transistors and the seventh transistor can be implemented as P-type transistors.

[0014] In an embodiment, the sixth transistor may further include a second control electrode connected to the control electrode of the sixth transistor, the eighth transistor may further include a second control electrode connected to the control electrode of the eighth transistor, and the ninth transistor may further include a second control electrode connected to the control electrode of the ninth transistor.

[0015] In a display device according to an embodiment of the present disclosure, the display device includes: a display panel including pixels; a gate driver that outputs a gate signal to the pixels; and a data driver that outputs a data voltage to the pixels. The gate driver includes: an input circuit that sends an input signal to a control circuit based on a first clock signal; a control circuit that controls the voltage of a control node based on the input signal, the first clock signal, a second clock signal, and a voltage control signal; and an output circuit that outputs a gate signal based on the voltage of the control node. The control circuit includes: a fifth transistor including a control electrode connected to a second node, a first electrode receiving a first power supply voltage, and a second electrode connected to the control node; a sixth transistor including a control electrode connected to a fourth node, a first electrode connected to the control node, and a second electrode receiving a second power supply voltage; and a ninth transistor including a control electrode receiving a voltage control signal, a first electrode connected to a third node, and a second electrode connected to the fourth node. The control circuit sends one of the first power supply voltage and the second power supply voltage to the control node, and the output circuit outputs one of the first power supply voltage and the third power supply voltage as a gate signal.

[0016] In an embodiment, the input circuit may include a first transistor, which includes a control electrode for receiving a first clock signal, a first electrode for receiving an input signal, and a second electrode connected to a first node. The control circuit may further include: a second transistor, which includes a control electrode for receiving a third power supply voltage, a first electrode connected to a first node, and a second electrode connected to a third node; a third transistor, which includes a control electrode connected to a third node, a first electrode for receiving a second clock signal, and a second electrode connected to a second node; a fourth transistor, which includes a control electrode for receiving a first clock signal, a first electrode for receiving a first power supply voltage, and a second electrode connected to a second node; a first capacitor, which includes a first electrode connected to a second node and a second electrode connected to a third node; a second capacitor, which includes a first electrode for receiving a first power supply voltage and a second electrode connected to a second node; and a third capacitor, which includes a first electrode connected to a second node and a second electrode connected to a fourth node.

[0017] In one embodiment, the output circuit may include: a seventh transistor, including a control electrode connected to the control node, a first electrode receiving a first power supply voltage, and a second electrode connected to the output node; and an eighth transistor, including a control electrode connected to the control node, a first electrode connected to the output node, and a second electrode receiving a third power supply voltage.

[0018] In an implementation, the level of the first power supply voltage may be higher than the level of the third power supply voltage, and the level of the third power supply voltage may be higher than the level of the second power supply voltage.

[0019] In the implementation, the sixth, eighth, and ninth transistors can be implemented as transistors of a first type, and the first to fifth transistors and the seventh transistor can be implemented as transistors of a second type, different from the transistors of the first type.

[0020] In the implementation, the sixth, eighth, and ninth transistors can be implemented as N-type transistors.

[0021] In an implementation, the first to fifth transistors and the seventh transistor can be implemented as P-type transistors.

[0022] In an embodiment, the sixth transistor may further include a second control electrode connected to the control electrode of the sixth transistor, the eighth transistor may further include a second control electrode connected to the control electrode of the eighth transistor, and the ninth transistor may further include a second control electrode connected to the control electrode of the ninth transistor.

[0023] In an electronic device according to an embodiment of the present disclosure, the electronic device includes: a processor that outputs input control signals and inputs image data; a display panel including pixels; a gate driver that outputs gate signals to the pixels; a data driver that outputs data voltages to the pixels; and a drive controller that controls the gate driver and the data driver based on the input control signals and the input image data. The gate driver includes: an input circuit that sends an input signal to a control circuit based on a first clock signal; a control circuit that controls the voltage of a control node based on the input signal, the first clock signal, a second clock signal, and a voltage control signal; and an output circuit that outputs a gate signal based on the voltage of the control node. The control circuit includes: a fifth transistor including a control electrode connected to a second node, a first electrode receiving a first power supply voltage, and a second electrode connected to the control node; a sixth transistor including a control electrode connected to a fourth node, a first electrode connected to the control node, and a second electrode receiving a second power supply voltage; and a ninth transistor including a control electrode receiving a voltage control signal, a first electrode connected to a third node, and a second electrode connected to the fourth node. The control circuit sends one of the first power supply voltage and the second power supply voltage to the control node, and the output circuit outputs one of the first power supply voltage and the third power supply voltage as a gate signal.

[0024] In an embodiment, the input circuit may include a first transistor, which includes a control electrode for receiving a first clock signal, a first electrode for receiving an input signal, and a second electrode connected to a first node. The control circuit may further include: a second transistor, which includes a control electrode for receiving a third power supply voltage, a first electrode connected to a first node, and a second electrode connected to a third node; a third transistor, which includes a control electrode connected to a third node, a first electrode for receiving a second clock signal, and a second electrode connected to a second node; a fourth transistor, which includes a control electrode for receiving the first clock signal, a first electrode for receiving the first power supply voltage, and a second electrode connected to a second node; a first capacitor, which includes a first electrode connected to a second node and a second electrode connected to a third node; a second capacitor, which includes a first electrode for receiving the first power supply voltage and a second electrode connected to a second node; and a third capacitor, which includes a first electrode connected to a second node and a second electrode connected to a fourth node.

[0025] In one embodiment, the output circuit may include: a seventh transistor, including a control electrode connected to the control node, a first electrode receiving a first power supply voltage, and a second electrode connected to the output node; and an eighth transistor, including a control electrode connected to the control node, a first electrode connected to the output node, and a second electrode receiving a third power supply voltage.

[0026] In an implementation, the level of the first power supply voltage may be higher than the level of the third power supply voltage, and the level of the third power supply voltage may be higher than the level of the second power supply voltage.

[0027] According to embodiments of this disclosure, the gate driver may include a first transistor to a ninth transistor and a first capacitor to a third capacitor. The sixth, eighth, and ninth transistors may be implemented as N-type transistors, and the first to fifth transistors and the seventh transistor may be implemented as P-type transistors.

[0028] In an example where the sixth, eighth, and ninth transistors are implemented as N-type transistors (e.g., N-type metal-oxide-slim transistors), the cutoff characteristics of the sixth, eighth, and ninth transistors can be improved. Therefore, the leakage current of each of the sixth, eighth, and ninth transistors can be reduced. Consequently, the gate driver can stably output a carry signal or a gate signal. Therefore, the stability of the gate driver can be improved, and the stability of the display device including the gate driver can be improved. In some aspects, as the leakage current of each of the sixth, eighth, and ninth transistors decreases, the power consumption of the display device can be reduced.

[0029] Compared to conventional gate drivers, in examples where the sixth, eighth, and ninth transistors are implemented as N-type transistors (e.g., N-type metal-oxide-slim transistors), the number of transistors included in the gate driver can be reduced. Therefore, the dead time of the display device including the gate driver can be reduced, and the power consumption of the display device can be lowered. In some respects, the integration density of the display device can be increased.

[0030] The clock signal line connected to the gate driver can be connected to a P-type transistor, which is smaller than the size of an N-type transistor. Therefore, the capacitance of each of the parasitic capacitors formed by the clock signal line and the P-type transistor can be reduced. Consequently, the power consumption of the display device due to the charging and discharging of parasitic capacitors can be reduced, and the overall power consumption of the display device can be lowered.

[0031] In some aspects, in examples where the first to fifth and seventh transistors are implemented as P-type transistors (e.g., P-type LTPS thin-film transistors), the current flowing through each of the first to fifth and seventh transistors can be relatively large. Therefore, the stability of the gate driver can be improved, and the stability of the display device including the gate driver can be improved. Attached Figure Description

[0032] The above and other features and advantages of the present invention will become more apparent from the detailed description of embodiments of the present invention with reference to the accompanying drawings, in which: Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure; Figure 2 It is shown that it includes Figure 1 A block diagram illustrating an implementation of a stage in a gate driver; Figure 3 It is shown Figure 2 Circuit diagram of the implementation method of the stage; Figure 4 It is shown Figure 3 A timing diagram of the implementation method for the level operation; Figure 5 It is shown Figure 3 The level at Figure 4 The circuit diagram of the operation in the first cycle of the timing diagram; Figure 6 It is shown Figure 3 The level at Figure 4 The circuit diagram of the operation in the second cycle of the timing diagram; Figure 7 It is shown Figure 3 The level at Figure 4 The circuit diagram of the operation in the third cycle of the timing diagram; Figure 8 It is shown Figure 3 The level at Figure 4 The circuit diagram of the operation in the fourth cycle of the timing diagram; Figure 9 It is shown Figure 2 Circuit diagram of the implementation method of the stage; Figure 10 It is shown that it includes Figure 1 A block diagram illustrating an implementation of a stage in a gate driver; Figure 11 It is shown Figure 10 Circuit diagram of the implementation method of the stage; Figure 12 It is shown Figure 11 A timing diagram of the implementation method for the level operation; Figure 13 It is shown Figure 10 Circuit diagram of the implementation method of the stage; Figure 14 It is shown that it includes Figure 1 A circuit diagram illustrating the implementation of pixels in a display panel; Figure 15 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure; and Figure 16 It is shown Figure 15 The diagram illustrates an implementation of an electronic device as a smartphone. Detailed Implementation

[0033] In the following description, the display device according to the embodiment will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same parts in the drawings, and redundant descriptions of the same parts will be omitted.

[0034] However, the aspects supported by this disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary aspects of the invention to those skilled in the art.

[0035] Terms such as "first," "second," etc., can be used to describe various components, but these components should not be limited by these terms. Terms used herein can distinguish one component from others and are not limited by these terms. For example, without departing from the scope of this disclosure, a first component can be referred to as a second component, and similarly, a second component can be referred to as a first component. Unless otherwise stated, singular terms may include plural forms.

[0036] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, “a,” “an,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. For example, “one element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as a limiting “a” or “one.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms “comprising” and / or “including” or “including” and / or “comprising” specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0037] Given the measurements discussed and the errors associated with the measurement of a particular quantity, the terms “about” or “approximately” as used herein include the value and include a suitable range of deviations from the particular value as determined by one of ordinary skill in the art. For example, the term “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value.

[0038] The term "substantially" as used in this document means approximately or actually. The term "substantially equal" means approximately or actually equal. The term "substantially identical" means approximately or actually identical. The term "substantially equal" means approximately or actually equal. The term "substantially perpendicular" means approximately or actually perpendicular.

[0039] Spatial relative terms, such as “below,” “under,” “lower,” “above,” “upper,” etc., may be used herein for ease of description to describe the relationship between one element or feature and another (additional) element or feature as shown in the figures. It will be understood that, in addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the figures is flipped, the element described as “below” or “under” other elements or features will subsequently be oriented “above” other elements or features. Thus, the term “below” can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0040] Embodiments are described herein with reference to schematic cross-sectional views as exemplary embodiments. Thus, variations in shape as a result of, for example, manufacturing techniques and / or tolerances, are to be expected. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the areas shown herein, but are to include, for example, deviations in shape due to manufacturing processes. For example, areas shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, acute angles shown may be rounded. Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to illustrate precise shapes of the areas, nor are they intended to limit the scope of the claims.

[0041] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in common dictionaries, shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and shall not be interpreted in an idealized or overly formalized sense unless expressly so defined herein.

[0042] It should be understood that the various embodiments of this disclosure and the terminology used therein are not intended to limit the technical features set forth herein to the specific embodiments, but rather to include various changes, equivalents, or substitutions for the respective embodiments. In the description of the drawings, similar reference numerals may be used to refer to similar or related elements. It will be understood that the singular forms of nouns corresponding to terms may include one or more things unless the relevant context clearly indicates otherwise. As used herein, each of the phrases such as “A or B,” “at least one of A and B,” “A, B, or C,” and “at least one of A, B, and C” may include any one or all possible combinations of the items listed together with the corresponding phrase among the plurality of phrases.

[0043] It will be understood that, whether the terms “operably” or “communically” are used or not, if an element (e.g., a first element) is referred to as “connected to another element (e.g., a second element),” “linked to another element (e.g., a second element),” “connected to another element (e.g., a second element),” or “attached to another element (e.g., a second element)”, it means that the element can be directly (e.g., wiredly) connected to the other element, wirelessly connected to the other element, or connected to the other element via a third element.

[0044] Figure 1 This is a block diagram showing a display device 1 according to an embodiment of the present disclosure.

[0045] refer to Figure 1 The display device 1 includes a display panel 100 and a display panel driver 700. The display panel driver 700 may include a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and a transmit driver 600.

[0046] The display panel 100 may include a display area for displaying images and a peripheral area adjacent to the display area.

[0047] The display panel 100 includes multiple gate lines GL, multiple data lines DL, multiple emission lines EL, and multiple pixels PX electrically connected to each of the gate lines GL, data lines DL, and emission lines EL. The gate lines GL may extend along a first direction D1, the data lines DL may extend along a second direction D2 intersecting the first direction D1, and the emission lines EL may extend along the first direction D1.

[0048] The drive controller 200 can receive input image data IMG and input control signal CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. In some embodiments, the input image data IMG may also include white image data. In another example, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0049] The drive controller 200 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0050] The drive controller 200 can generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and can output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0051] The drive controller 200 can generate a second control signal CONT2 based on the input control signal CONT for controlling the operation of the data driver 500, and can output the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0052] The drive controller 200 can generate a data signal DATA based on the input image data IMG. The drive controller 200 can output the data signal DATA to the data driver 500.

[0053] The drive controller 200 can generate a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and can output the third control signal CONT3 to the gamma reference voltage generator 400.

[0054] The drive controller 200 can generate a fourth control signal CONT4 for controlling the operation of the transmitter driver 600 based on the input control signal CONT, and can output the fourth control signal CONT4 to the transmitter driver 600.

[0055] The gate driver 300 can generate a gate signal for driving the gate line GL in response to a first control signal CONT1 received from the drive controller 200. The gate driver 300 can output the gate signal to the gate line GL. For example, the gate signal may include a write gate signal, a compensated gate signal, and an initialized gate signal.

[0056] In one embodiment, the gate driver 300 may be integrated on the display panel 100 in the peripheral region. Alternatively, the gate driver 300 may be mounted on the display panel 100 in the peripheral region.

[0057] The gamma reference voltage generator 400 can generate a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 can output the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF can correspond to the data signal DATA.

[0058] In an implementation, the gamma reference voltage generator 400 may be located in the drive controller 200 or in the data driver 500.

[0059] The data driver 500 can receive a second control signal CONT2 and a data signal DATA from the drive controller 200, and can receive a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 can use the gamma reference voltage VGREF to convert the digital data signal DATA into an analog data voltage. The data driver 500 can output a data voltage to the data line DL.

[0060] In one embodiment, the data driver 500 may be integrated into the display panel 100 in the peripheral area. Alternatively, the data driver 500 may be mounted on the display panel 100 in the peripheral area.

[0061] The transmitter driver 600 can generate a transmit signal for driving the transmitter line EL in response to a fourth control signal CONT4 received from the drive controller 200. The transmitter driver 600 can output the transmit signal to the transmitter line EL.

[0062] In one embodiment, the transmitter driver 600 may be integrated into the display panel 100 in the peripheral region. Alternatively, the transmitter driver 600 may be mounted on the display panel 100 in the peripheral region.

[0063] Figure 2 It is shown that it includes Figure 1 A block diagram illustrating an implementation of a stage in the gate driver 300.

[0064] refer to Figure 2 The gate driver 300 may include stages. For example, the gate driver 300 may include a first stage ST[1] and a second stage ST[2]. In some aspects, the gate driver 300 may include an nth stage ST[n], where n is an integer greater than or equal to 2.

[0065] Each of the stages can receive a first power supply voltage VGH, a second power supply voltage VGL2, and a third power supply voltage VGL1. In some respects, each of the stages can receive a first clock signal CLK1 and a second clock signal CLK2.

[0066] The level of the first power supply voltage VGH can be higher than the level of the third power supply voltage VGL1. The level of the third power supply voltage VGL1 can be higher than the level of the second power supply voltage VGL2. In other words, the first power supply voltage VGH can be higher than the third power supply voltage VGL1, and the third power supply voltage VGL1 can be higher than the second power supply voltage VGL2.

[0067] Each stage can receive an input signal and a voltage control signal. The input signal can be a start signal FLM or a gate signal from the previous stage. In some respects, the voltage control signal can be a start carry signal CR[0] or a carry signal from the previous stage. For example, the carry signal from the previous stage applied to the second stage ST[2] can be the first carry signal CR[1].

[0068] The first stage ST[1] can receive a first power supply voltage VGH, a second power supply voltage VGL2, a third power supply voltage VGL1, a first clock signal CLK1, and a second clock signal CLK2. In some aspects, the first stage ST[1] can receive a start signal FLM and a start carry signal CR[0]. The first stage ST[1] can output a first carry signal CR[1] at the first control node Q[1]. In some aspects, the first stage ST[1] can output a first gate signal GW[1] at the first output node NO[1].

[0069] The second stage ST[2] can receive a first power supply voltage VGH, a second power supply voltage VGL2, a third power supply voltage VGL1, a first clock signal CLK1, and a second clock signal CLK2. In some aspects, the second stage ST[2] can receive a first gate signal GW[1] and a voltage control signal. The voltage control signal applied to the second stage ST[2] can be a first carry signal CR[1]. The second stage ST[2] can output a second carry signal CR[2] at the second control node Q[2]. In some aspects, the second stage ST[2] can output a second gate signal GW[2] at the second output node NO[2].

[0070] In this way, the nth stage ST[n] can receive the first power supply voltage VGH, the second power supply voltage VGL2, the third power supply voltage VGL1, the first clock signal CLK1, and the second clock signal CLK2. In some aspects, the nth stage ST[n] can receive the (n-1)th gate signal GW[n-1] and a voltage control signal. The voltage control signal applied to the nth stage ST[n] can be the (n-1)th carry signal CR[n-1]. The nth stage ST[n] can output the nth carry signal CR[n] at the nth control node Q[n]. In some aspects, the nth stage ST[n] can output the nth gate signal GW[n] at the nth output node NO[n].

[0071] Figure 3 It is shown Figure 2 The circuit diagram of the implementation of the stage.

[0072] For ease of explanation, in this embodiment, the stage is the nth stage ST[n] that receives the (n-1)th carry signal CR[n-1] and the (n-1)th gate signal GW[n-1].

[0073] refer to Figure 3 The nth level ST[n] may include input circuit 10, control circuit 20 and output circuit 30.

[0074] Input circuit 10 can send the (n-1)th gate signal GW[n-1] to the first node N1 based on the first clock signal CLK1.

[0075] The input circuit 10 may include a first transistor T1.

[0076] The first transistor T1 may include a control electrode that receives the first clock signal CLK1, a first electrode that receives the (n-1)th gate signal GW[n-1], and a second electrode connected to the first node N1.

[0077] The control circuit 20 can control the voltage of the nth control node Q[n] based on the (n-1)th gate signal GW[n-1], the first clock signal CLK1, the second clock signal CLK2, and the (n-1)th carry signal CR[n-1]. In some aspects, the control circuit 20 can output the voltage of the nth control node Q[n] as the nth carry signal CR[n].

[0078] The control circuit 20 may include the second transistor T2 to the sixth transistor T6, the ninth transistor T9, and the first capacitor C1 to the third capacitor C3.

[0079] The second transistor T2 may include a control electrode that receives a third power supply voltage VGL1, a first electrode connected to a first node N1, and a second electrode connected to a third node N3.

[0080] The third transistor T3 may include a control electrode connected to the third node N3, a first electrode that receives the second clock signal CLK2, and a second electrode connected to the second node N2.

[0081] The fourth transistor T4 may include a control electrode that receives the first clock signal CLK1, a first electrode that receives the first power supply voltage VGH, and a second electrode that is connected to the second node N2.

[0082] The fifth transistor T5 may include a control electrode connected to the second node N2, a first electrode receiving a first power supply voltage VGH, and a second electrode connected to the nth control node Q[n].

[0083] The sixth transistor T6 may include a control electrode connected to the fourth node N4, a first electrode connected to the nth control node Q[n], and a second electrode that receives the second power supply voltage VGL2.

[0084] The ninth transistor T9 may include a control electrode that receives the (n-1)th carry signal CR[n-1], a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4.

[0085] The first capacitor C1 may include a first electrode connected to the second node N2 and a second electrode connected to the third node N3.

[0086] The second capacitor C2 may include a first electrode that receives a first power supply voltage VGH and a second electrode connected to a second node N2.

[0087] The third capacitor C3 may include a first electrode connected to the second node N2 and a second electrode connected to the fourth node N4.

[0088] The output circuit 30 can output the nth gate signal GW[n] at the nth output node NO[n] based on the voltage of the nth control node Q[n].

[0089] The output circuit 30 may include a seventh transistor T7 and an eighth transistor T8.

[0090] The seventh transistor T7 may include a control electrode connected to the nth control node Q[n], a first electrode receiving a first power supply voltage VGH, and a second electrode connected to the nth output node NO[n].

[0091] The eighth transistor T8 may include a control electrode connected to the nth control node Q[n], a first electrode connected to the nth output node NO[n], and a second electrode receiving the third power supply voltage VGL1. The control electrodes described with reference to the first transistor T1 to the eighth transistor T8 may be gate electrodes that respectively control the current flow through the first transistor T1 to the eighth transistor T8.

[0092] The level of the first power supply voltage VGH can be higher than the level of the third power supply voltage VGL1. The level of the third power supply voltage VGL1 can be higher than the level of the second power supply voltage VGL2.

[0093] The sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 can be implemented as transistors of the first type. In some embodiments, the first transistors T1 through T5 and the seventh transistor T7 can be implemented as transistors of the second type, which are different from the first type of transistors.

[0094] In some embodiments, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 can be implemented as N-type transistors. In some embodiments, the first transistor T1 through the fifth transistor T5 and the seventh transistor T7 can be implemented as P-type transistors.

[0095] For example, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 can be implemented as N-type metal-oxide-slim thin-film transistors. In some embodiments, the first transistor T1 through the fifth transistor T5 and the seventh transistor T7 can be implemented as P-type low-temperature polycrystalline silicon (LTPS) thin-film transistors.

[0096] In the example where the sixth transistor T6 is implemented as an N-type transistor (e.g., an N-type metal-oxide-slim transistor), the cutoff characteristics of the sixth transistor T6 can be improved, and the leakage current of the sixth transistor T6 can be reduced. Therefore, the voltage of the nth control node Q[n] can stably maintain the level of the first power supply voltage VGH, and the stability of the gate driver 300 can be improved. In some respects, as the leakage current of the sixth transistor T6 decreases, the power consumption of the display device 1 can be reduced.

[0097] In the example where the eighth transistor T8 is implemented as an N-type transistor (e.g., an N-type metal-oxide-slim transistor), the cutoff characteristics of the eighth transistor T8 can be improved, and the leakage current of the eighth transistor T8 can be reduced. Therefore, the nth gate signal GW[n] output at the nth output node NO[n] can stably maintain the level of the first power supply voltage VGH, and the stability of the gate driver 300 can be improved. In some respects, as the leakage current of the eighth transistor T8 decreases, the power consumption of the display device 1 can be reduced.

[0098] In the example where the ninth transistor T9 is implemented as an N-type transistor (e.g., an N-type metal-oxide-slim transistor), the cutoff characteristics of the ninth transistor T9 can be improved, and the leakage current of the ninth transistor T9 can be reduced. Therefore, when the ninth transistor T9 is turned off, the voltages at the third node N3 and the fourth node N4 can be different from each other. In the example where the ninth transistor T9 is turned off, the voltage level at the third node N3 can be the same as the level of the first supply voltage VGH, and the voltage level at the fourth node N4 can have a fourth supply voltage level that is lower than the level of the first supply voltage VGH (see reference). Figure 4 (VC). Since the voltage of the fourth node N4 has a fourth power supply voltage level, the stress applied to the sixth transistor T6 can be reduced, and the characteristic changes of the sixth transistor T6 caused by stress can be reduced. Therefore, the stability of the gate driver 300 can be improved. In some aspects, as the leakage current of the ninth transistor T9 decreases, the power consumption of the display device 1 can be reduced.

[0099] The description of the voltage level of a node in this document can refer to the voltage level at the node. The description of the voltage level of a node having a supply voltage level (e.g., a first supply voltage VGH, a second supply voltage VGL2, a third supply voltage VGL1, or the like) can refer to the voltage level at the node being equal to the supply voltage.

[0100] Compared to conventional gate drivers, since the sixth transistor T6 and the eighth transistor T8 are implemented as N-type transistors (e.g., N-type metal-oxide-slim transistors), the number of transistors included in the gate driver 300 can be reduced. Therefore, the dead time of the display device 1 including the gate driver 300 can be reduced, and the power consumption of the display device 1 can be lowered. In some respects, the integration density of the display device 1 can be increased.

[0101] In some aspects, a first clock signal CLK1 can be applied to the first transistor T1 and the fourth transistor T4 via a first clock signal line, and a second clock signal CLK2 can be applied to the third transistor T3 via a second clock signal line. When the first transistor T1, the third transistor T3, and the fourth transistor T4 are implemented as P-type transistors, the dimensions of the first transistor T1, the third transistor T3, and the fourth transistor T4 can be relatively smaller than the dimensions of the first transistor T1, the third transistor T3, and the fourth transistor T4 when they are implemented as N-type transistors. Therefore, the capacitance of the first parasitic capacitor formed by the first clock signal line and the first transistor T1 can be reduced, and the capacitance of the second parasitic capacitor formed by the first clock signal line and the fourth transistor T4 can be reduced. In some aspects, the capacitance of the third parasitic capacitor formed by the second clock signal line and the third transistor T3 can be reduced. Therefore, the power consumption of the display device 1 caused by the charging and discharging of the first parasitic capacitor to the third parasitic capacitor can be reduced. That is, the power consumption of the display device 1 can be reduced.

[0102] When the first transistor T1 to the fifth transistor T5 and the seventh transistor T7 are implemented as P-type transistors (e.g., P-type LTPS thin film transistors), the current flowing through each of the first transistor T1 to the fifth transistor T5 and the seventh transistor T7 can be larger, and the stability of the gate driver 300 can be improved.

[0103] Figure 4 It is shown Figure 3 A timing diagram illustrating the implementation of the level-based operations. Figure 5 It is shown Figure 3 The level at Figure 4 The circuit diagram for the operation in the first cycle TP1 of the timing diagram. Figure 6 It is shown Figure 3 The level at Figure 4 The circuit diagram for the operation in the second cycle TP2 of the timing diagram. Figure 7 It is shown Figure 3 The level at Figure 4 The circuit diagram of the operation in the third cycle TP3 of the timing diagram, and Figure 8 It is shown Figure 3 The level at Figure 4 The circuit diagram for the operation in the fourth cycle TP4 of the timing diagram.

[0104] refer to Figure 4 The period during which the signal is applied to the nth stage ST[n] may include the first period TP1, the second period TP2, the third period TP3, and the fourth period TP4.

[0105] refer to Figure 4 and Figure 5 The (n-1)th gate signal GW[n-1] and the first clock signal CLK1 can have the level of the first power supply voltage VGH in the first cycle TP1. The second clock signal CLK2 can have the level of the third power supply voltage VGL1 in the first cycle TP1. The (n-1)th carry signal CR[n-1] can have the level of the second power supply voltage VGL2 in the first cycle TP1.

[0106] The voltage at the first node N1 can be at the level of the first power supply voltage VGH, and the voltage at the second node N2 can also be at the level of the first power supply voltage VGH. The voltage at the fourth node N4 can be at the level of the fourth power supply voltage VC. The fourth power supply voltage level VC can be higher than the level of the second power supply voltage VGL2. For example, the fourth power supply voltage level VC can be the same as the level of the third power supply voltage VGL1.

[0107] The first transistor T1 can be turned off in response to the first clock signal CLK1 and the (n-1)th gate signal GW[n-1].

[0108] The second transistor T2 can be turned on in response to the voltage of the first node N1 and the third power supply voltage VGL1. The second transistor T2 can send the voltage of the first node N1 to the third node N3. Therefore, the voltage of the third node N3 can have the level of the first power supply voltage VGH.

[0109] The third transistor T3 can be turned off in response to the second clock signal CLK2 and the voltage of the third node N3.

[0110] The fourth transistor T4 can be turned off in response to the first power supply voltage VGH and the first clock signal CLK1.

[0111] The fifth transistor T5 can be turned off in response to the first power supply voltage VGH and the voltage of the second node N2.

[0112] The sixth transistor T6 can be turned on in response to the voltage of the fourth node N4 and the second power supply voltage VGL2. The difference between the voltage of the fourth node N4 and the second power supply voltage VGL2 can be greater than the threshold voltage of the sixth transistor T6. Therefore, the sixth transistor T6 can be turned on. The sixth transistor T6 can send the second power supply voltage VGL2 to the nth control node Q[n]. Therefore, the nth control node Q[n] can have the level of the second power supply voltage VGL2. The nth control node Q[n] can output the nth carry signal CR[n] with the level of the second power supply voltage VGL2.

[0113] The ninth transistor T9 can be turned off in response to the (n-1)th carry signal CR[n-1] and the voltage of the third node N3. The difference between the (n-1)th carry signal CR[n-1] and the voltage of the third node N3 can be less than the threshold voltage of the ninth transistor T9. Therefore, the ninth transistor T9 can be turned off. In the example where the ninth transistor T9 is implemented as an N-type transistor, the turn-off characteristics of the ninth transistor T9 can be improved, and the leakage current of the ninth transistor T9 can be reduced. Therefore, the voltage of the third node N3 and the voltage of the fourth node N4 can be different from each other. Therefore, since the voltage of the fourth node N4 has a fourth power supply voltage level VC that is lower than the level of the first power supply voltage VGH, the stress applied to the sixth transistor T6 can be reduced, and the characteristic changes of the sixth transistor T6 due to stress can be reduced. Therefore, the stability of the gate driver 300 can be improved. In some aspects, as the leakage current of the ninth transistor T9 decreases, the power consumption of the display device 1 can be reduced.

[0114] The seventh transistor T7 can be turned on in response to the first power supply voltage VGH and the voltage of the nth control node Q[n]. Therefore, the seventh transistor T7 can send the first power supply voltage VGH to the nth output node NO[n]. The nth output node NO[n] can output the nth gate signal GW[n] with the level of the first power supply voltage VGH.

[0115] The eighth transistor T8 can be turned off in response to the third power supply voltage VGL1 and the voltage of the nth control node Q[n]. The difference between the voltage of the nth control node Q[n] and the third power supply voltage VGL1 can be less than the threshold voltage of the eighth transistor T8. Therefore, the eighth transistor T8 can be turned off. In the example where the eighth transistor T8 is implemented as an N-type transistor, the turn-off characteristics of the eighth transistor T8 can be improved, and the leakage current of the eighth transistor T8 can be reduced. Therefore, the nth gate signal GW[n] output at the nth output node NO[n] can stably maintain the level of the first power supply voltage VGH, and the stability of the gate driver 300 can be improved. In some respects, as the leakage current of the eighth transistor T8 decreases, the power consumption of the display device 1 can be reduced.

[0116] The voltage at the second node N2 can be stably maintained by the second capacitor C2. In some respects, when the voltage at the second node N2 is stably maintained, the voltages at the third node N3 and the fourth node N4 can also be stably maintained.

[0117] refer to Figure 4 and Figure 6 The (n-1)th gate signal GW[n-1] and the first clock signal CLK1 can have the level of the third power supply voltage VGL1 in the second cycle TP2. The second clock signal CLK2 can have the level of the first power supply voltage VGH in the second cycle TP2. The (n-1)th carry signal CR[n-1] can have the level of the first power supply voltage VGH in the second cycle TP2.

[0118] The first transistor T1 can be turned on in response to the first clock signal CLK1 and the (n-1)th gate signal GW[n-1]. The first transistor T1 can send the (n-1)th gate signal GW[n-1] to the first node N1. The voltage of the first node N1 can have the level of the third power supply voltage VGL1.

[0119] The second transistor T2 can be turned on in response to the voltage of the first node N1 and the third power supply voltage VGL1. The second transistor T2 can send the voltage of the first node N1 to the third node N3. Therefore, the voltage of the third node N3 can have the level of the third power supply voltage VGL1.

[0120] The third transistor T3 can be turned on in response to the second clock signal CLK2 and the voltage of the third node N3. The third transistor T3 can send the second clock signal CLK2 to the second node N2. The voltage of the second node N2 can have the level of the first power supply voltage VGH.

[0121] The fourth transistor T4 can be turned on in response to the first power supply voltage VGH and the first clock signal CLK1. The fourth transistor T4 can send the first power supply voltage VGH to the second node N2. The voltage of the second node N2 can have the level of the first power supply voltage VGH.

[0122] The fifth transistor T5 can be turned off in response to the first power supply voltage VGH and the voltage of the second node N2.

[0123] The ninth transistor T9 can be turned on in response to the (n-1)th carry signal CR[n-1] and the voltage of the third node N3. The difference between the (n-1)th carry signal CR[n-1] and the voltage of the third node N3 can be greater than the threshold voltage of the ninth transistor T9. Therefore, the ninth transistor T9 can be turned on. The ninth transistor T9 can send the voltage of the third node N3 to the fourth node N4. The voltage of the fourth node N4 can have the level of the third power supply voltage VGL1. The level of the fourth power supply voltage VC can be the same as the level of the third power supply voltage VGL1.

[0124] The sixth transistor T6 can be turned on in response to the voltage of the fourth node N4 and the second power supply voltage VGL2. The difference between the voltage of the fourth node N4 and the second power supply voltage VGL2 can be greater than the threshold voltage of the sixth transistor T6. Therefore, the sixth transistor T6 can be turned on. The sixth transistor T6 can send the second power supply voltage VGL2 to the nth control node Q[n]. Therefore, the nth control node Q[n] can have the level of the second power supply voltage VGL2. The nth control node Q[n] can output the nth carry signal CR[n] with the level of the second power supply voltage VGL2.

[0125] The seventh transistor T7 can be turned on in response to the first power supply voltage VGH and the voltage of the nth control node Q[n]. Therefore, the seventh transistor T7 can send the first power supply voltage VGH to the nth output node NO[n]. The nth output node NO[n] can output the nth gate signal GW[n] with the level of the first power supply voltage VGH.

[0126] The eighth transistor T8 can be turned off in response to the third power supply voltage VGL1 and the voltage of the nth control node Q[n]. The difference between the voltage of the nth control node Q[n] and the third power supply voltage VGL1 can be less than the threshold voltage of the eighth transistor T8. Therefore, the eighth transistor T8 can be turned off. In the example where the eighth transistor T8 is implemented as an N-type transistor, the turn-off characteristics of the eighth transistor T8 can be improved, and the leakage current of the eighth transistor T8 can be reduced. Therefore, the nth gate signal GW[n] output at the nth output node NO[n] can stably maintain the level of the first power supply voltage VGH, and the stability of the gate driver 300 can be improved. In some respects, as the leakage current of the eighth transistor T8 decreases, the power consumption of the display device 1 can be reduced.

[0127] refer to Figure 4 and Figure 7The (n-1)th gate signal GW[n-1] and the first clock signal CLK1 can have the level of the first power supply voltage VGH in the third cycle TP3. The second clock signal CLK2 can have the level of the third power supply voltage VGL1 in the third cycle TP3. The (n-1)th carry signal CR[n-1] can have the level of the second power supply voltage VGL2 in the third cycle TP3.

[0128] The first transistor T1 can be turned off in response to the first clock signal CLK1 and the (n-1)th gate signal GW[n-1].

[0129] The second transistor T2 can be turned off in response to the voltage of the first node N1 and the third power supply voltage VGL1. The voltage of the first node N1 can maintain the level of the third power supply voltage VGL1.

[0130] The third transistor T3 can be turned on in response to the second clock signal CLK2 and the voltage of the third node N3. The third transistor T3 can send the second clock signal CLK2 to the second node N2. The voltage of the second node N2 can have the level of the third power supply voltage VGL1.

[0131] When the voltage level of the second node N2 decreases from the level of the first supply voltage VGH to the level of the third supply voltage VGL1, the voltage level of the third node N3 can be decreased through the coupling of the first capacitor C1. That is, the voltage of the third node N3 is bootstrapped. Therefore, the voltage of the third node N3 can have a fifth supply voltage level VGL3. The fifth supply voltage level VGL3 can be lower than the level of the second supply voltage VGL2. In some aspects, when the voltage level of the second node N2 decreases from the level of the first supply voltage VGH to the level of the third supply voltage VGL1, the voltage level of the fourth node N4 can be decreased through the coupling of the third capacitor C3. That is, the voltage of the fourth node N4 is bootstrapped. Therefore, the fourth node N4 can have a fifth supply voltage level VGL3.

[0132] The fourth transistor T4 can be turned off in response to the first power supply voltage VGH and the first clock signal CLK1.

[0133] The fifth transistor T5 can be turned on in response to the first power supply voltage VGH and the voltage of the second node N2. The fifth transistor T5 can send the first power supply voltage VGH to the nth control node Q[n]. The voltage of the nth control node Q[n] can have the level of the first power supply voltage VGH.

[0134] The ninth transistor T9 can be turned on in response to the (n-1)th carry signal CR[n-1] and the voltage of the third node N3. The difference between the (n-1)th carry signal CR[n-1] and the voltage of the third node N3 can be greater than the threshold voltage of the ninth transistor T9. Therefore, the ninth transistor T9 can be turned on.

[0135] The sixth transistor T6 can be turned off in response to the voltage of the fourth node N4 and the second power supply voltage VGL2. The difference between the voltage of the fourth node N4 and the second power supply voltage VGL2 can be less than the threshold voltage of the sixth transistor T6. Therefore, the sixth transistor T6 can be turned off. In the example where the sixth transistor T6 is implemented as an N-type transistor, the turn-off characteristics of the sixth transistor T6 can be improved, and the leakage current of the sixth transistor T6 can be reduced. Therefore, the nth carry signal CR[n] output at the nth control node Q[n] can stably maintain the level of the first power supply voltage VGH, and the stability of the gate driver 300 can be improved. In some respects, as the leakage current of the sixth transistor T6 decreases, the power consumption of the display device 1 can be reduced.

[0136] The seventh transistor T7 can be turned off in response to the first power supply voltage VGH and the voltage of the nth control node Q[n].

[0137] The eighth transistor T8 can be turned on in response to the third power supply voltage VGL1 and the voltage of the nth control node Q[n]. The difference between the voltage of the nth control node Q[n] and the third power supply voltage VGL1 can be greater than the threshold voltage of the eighth transistor T8. Therefore, the eighth transistor T8 can be turned on. The eighth transistor T8 can send the third power supply voltage VGL1 to the nth output node NO[n]. The nth output node NO[n] can output the nth gate signal GW[n] with the level of the third power supply voltage VGL1.

[0138] refer to Figure 4 and Figure 8 The (n-1)th gate signal GW[n-1] and the second clock signal CLK2 can have the level of the first power supply voltage VGH in the fourth cycle TP4. The first clock signal CLK1 can have the level of the third power supply voltage VGL1 in the fourth cycle TP4. The (n-1)th carry signal CR[n-1] can have the level of the second power supply voltage VGL2.

[0139] The first transistor T1 can be turned on in response to the first clock signal CLK1 and the (n-1)th gate signal GW[n-1]. The first transistor T1 can send the (n-1)th gate signal GW[n-1] to the first node N1. The voltage of the first node N1 can have the level of the first power supply voltage VGH.

[0140] The second transistor T2 can be turned on in response to the voltage of the first node N1 and the third power supply voltage VGL1. The second transistor T2 can send the voltage of the first node N1 to the third node N3. Therefore, the voltage of the third node N3 can have the level of the first power supply voltage VGH.

[0141] The third transistor T3 can be turned off in response to the second clock signal CLK2 and the voltage of the third node N3.

[0142] The fourth transistor T4 can be turned on in response to the first power supply voltage VGH and the first clock signal CLK1. The fourth transistor T4 can send the first power supply voltage VGH to the second node N2. The voltage of the second node N2 can have the level of the first power supply voltage VGH.

[0143] In the example where the voltage level at the second node N2 increases from the level of the third supply voltage VGL1 to the level of the first supply voltage VGH, the voltage level at the third node N3 can be increased through coupling via the third capacitor C3. Therefore, the voltage at the fourth node N4 can have a fourth supply voltage level VC. The fourth supply voltage level VC can be higher than the level of the second supply voltage VGL2. For example, the fourth supply voltage level VC can be the same as the level of the third supply voltage VGL1.

[0144] The fifth transistor T5 can be turned off in response to the first power supply voltage VGH and the voltage of the second node N2.

[0145] The ninth transistor T9 can be turned off in response to the (n-1)th carry signal CR[n-1] and the voltage of the third node N3. The difference between the (n-1)th carry signal CR[n-1] and the voltage of the third node N3 can be less than the threshold voltage of the ninth transistor T9. Therefore, the ninth transistor T9 can be turned off. In the example where the ninth transistor T9 is implemented as an N-type transistor, the turn-off characteristics of the ninth transistor T9 can be improved, and the leakage current of the ninth transistor T9 can be reduced. Therefore, the voltage of the third node N3 and the voltage of the fourth node N4 can be different from each other. Therefore, since the voltage of the fourth node N4 has a fourth power supply voltage level VC that is lower than the level of the first power supply voltage VGH, the stress applied to the sixth transistor T6 can be reduced, and the characteristic changes of the sixth transistor T6 due to stress can be reduced. Therefore, the stability of the gate driver 300 can be improved. In some aspects, as the leakage current of the ninth transistor T9 decreases, the power consumption of the display device 1 can be reduced.

[0146] The sixth transistor T6 can be turned on in response to the voltage of the fourth node N4 and the second power supply voltage VGL2. The difference between the voltage of the fourth node N4 and the second power supply voltage VGL2 can be greater than the threshold voltage of the sixth transistor T6. Therefore, the sixth transistor T6 can be turned on. The sixth transistor T6 can send the second power supply voltage VGL2 to the nth control node Q[n]. Therefore, the nth control node Q[n] can have the level of the second power supply voltage VGL2. The nth control node Q[n] can output the nth carry signal CR[n] with the level of the second power supply voltage VGL2.

[0147] The seventh transistor T7 can be turned on in response to the first power supply voltage VGH and the voltage of the nth control node Q[n]. Therefore, the seventh transistor T7 can send the first power supply voltage VGH to the nth output node NO[n]. The nth output node NO[n] can output the nth gate signal GW[n] with the level of the first power supply voltage VGH.

[0148] The eighth transistor T8 can be turned off in response to the third power supply voltage VGL1 and the voltage of the nth control node Q[n]. The difference between the voltage of the nth control node Q[n] and the third power supply voltage VGL1 can be less than the threshold voltage of the eighth transistor T8. Therefore, the eighth transistor T8 can be turned off. In the example where the eighth transistor T8 is implemented as an N-type transistor, the turn-off characteristics of the eighth transistor T8 can be improved, and the leakage current of the eighth transistor T8 can be reduced. Therefore, the nth gate signal GW[n] output at the nth output node NO[n] can stably maintain the level of the first power supply voltage VGH, and the stability of the gate driver 300 can be improved. In some respects, as the leakage current of the eighth transistor T8 decreases, the power consumption of the display device 1 can be reduced.

[0149] Figure 9 It is shown Figure 2 The circuit diagram of the implementation of the stage.

[0150] refer to Figure 9 The nth stage ST[n]a may include input circuit 10, control circuit 20a, and output circuit 30a. Except that each of the sixth transistor T6a, eighth transistor T8a, and ninth transistor T9a includes a second control electrode, the nth stage ST[n]a is essentially the same as... Figure 3 The nth level ST[n] is the same. Therefore, the same reference numerals will be used to refer to the same level. Figure 3 The components described in the previous embodiments are the same as or similar to those described above, and any repeated explanations of the above elements will be omitted.

[0151] The sixth transistor T6a may include a control electrode connected to the fourth node N4, a first electrode connected to the nth control node Q[n], and a second electrode receiving the second power supply voltage VGL2. In some aspects, the sixth transistor T6a may also include a second control electrode connected to the control electrode of the sixth transistor T6a.

[0152] The eighth transistor T8a may include a control electrode connected to the nth control node Q[n], a first electrode connected to the nth output node NO[n], and a second electrode receiving the third power supply voltage VGL1. In some aspects, the eighth transistor T8a may also include a second control electrode connected to the control electrode of the eighth transistor T8a.

[0153] The ninth transistor T9a may include a control electrode for receiving the (n-1)th carry signal CR[n-1], a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4. In some aspects, the ninth transistor T9a may also include a second control electrode connected to the control electrode of the ninth transistor T9a.

[0154] The characteristics of the sixth transistor T6a, the eighth transistor T8a, and the ninth transistor T9a may change due to stress. For example, the threshold voltage of each of the sixth transistor T6a, the eighth transistor T8a, and the ninth transistor T9a may change due to stress. When each of the sixth transistor T6a, the eighth transistor T8a, and the ninth transistor T9a also includes a second control electrode, the threshold voltage of each of the sixth transistor T6a, the eighth transistor T8a, and the ninth transistor T9a may remain unchanged. Therefore, the stability of the gate driver 300 can be improved.

[0155] The sixth transistor T6a, the eighth transistor T8a, and the ninth transistor T9a can be implemented as transistors of the first type. In some embodiments, the first transistors T1 to the fifth transistor T5 and the seventh transistor T7 can be implemented as transistors of the second type, which are different from the first type of transistors.

[0156] In some embodiments, the sixth transistor T6a, the eighth transistor T8a, and the ninth transistor T9a can be implemented as N-type transistors. In some embodiments, the first transistor T1 through the fifth transistor T5 and the seventh transistor T7 can be implemented as P-type transistors.

[0157] For example, the sixth transistor T6a, the eighth transistor T8a, and the ninth transistor T9a can be implemented as N-type metal-oxide-slim thin-film transistors. In some embodiments, the first transistor T1 through the fifth transistor T5 and the seventh transistor T7 can be implemented as P-type LTPS thin-film transistors.

[0158] In the example where the sixth transistor T6a is implemented as an N-type transistor (e.g., an N-type metal-oxide-slim transistor), the cutoff characteristics of the sixth transistor T6a can be improved, and the leakage current of the sixth transistor T6a can be reduced. Therefore, the voltage of the nth control node Q[n] can stably maintain the level of the first power supply voltage VGH, and the stability of the gate driver 300 can be improved. In some respects, as the leakage current of the sixth transistor T6a decreases, the power consumption of the display device 1 can be reduced.

[0159] In the example where the eighth transistor T8a is implemented as an N-type transistor (e.g., an N-type metal-oxide-slim transistor), the cutoff characteristics of the eighth transistor T8a can be improved, and the leakage current of the eighth transistor T8a can be reduced. Therefore, the nth gate signal GW[n] output at the nth output node NO[n] can stably maintain the level of the first power supply voltage VGH, and the stability of the gate driver 300 can be improved. In some respects, as the leakage current of the eighth transistor T8a decreases, the power consumption of the display device 1 can be reduced.

[0160] In the example where the ninth transistor T9a is implemented as an N-type transistor (e.g., an N-type metal-oxide-slim transistor), the cutoff characteristics of the ninth transistor T9a can be improved, and the leakage current of the ninth transistor T9a can be reduced. Therefore, when the ninth transistor T9a is turned off, the voltages of the third node N3 and the fourth node N4 can be different from each other. In the example where the ninth transistor T9a is turned off, the voltage level of the third node N3 can be the same as the level of the first power supply voltage VGH, and the voltage level of the fourth node N4 can have a fourth power supply voltage level VC that is lower than the level of the first power supply voltage VGH. Since the voltage of the fourth node N4 has the fourth power supply voltage level VC, the stress applied to the sixth transistor T6a can be reduced, and the characteristic changes of the sixth transistor T6a due to stress can be reduced. Therefore, the stability of the gate driver 300 can be improved. In some aspects, as the leakage current of the ninth transistor T9a decreases, the power consumption of the display device 1 can be reduced.

[0161] Compared to conventional gate drivers, since the sixth transistor T6a and the eighth transistor T8a are implemented as N-type transistors (e.g., N-type metal-oxide-slim transistors), the number of transistors included in the gate driver 300 can be reduced. Therefore, the dead time of the display device 1 including the gate driver 300 can be reduced, and the power consumption of the display device 1 can be lowered. In some respects, the integration density of the display device 1 can be increased.

[0162] In some aspects, a first clock signal CLK1 can be applied to the first transistor T1 and the fourth transistor T4 via a first clock signal line, and a second clock signal CLK2 can be applied to the third transistor T3 via a second clock signal line. When the first transistor T1, the third transistor T3, and the fourth transistor T4 are implemented as P-type transistors, the dimensions of the first transistor T1, the third transistor T3, and the fourth transistor T4 can be relatively smaller than the dimensions of the first transistor T1, the third transistor T3, and the fourth transistor T4 when they are implemented as N-type transistors. Therefore, the capacitance of the first parasitic capacitor formed by the first clock signal line and the first transistor T1 can be reduced, and the capacitance of the second parasitic capacitor formed by the first clock signal line and the fourth transistor T4 can be reduced. In some aspects, the capacitance of the third parasitic capacitor formed by the second clock signal line and the third transistor T3 can be reduced. Therefore, the power consumption of the display device 1 caused by the charging and discharging of the first parasitic capacitor to the third parasitic capacitor can be reduced. That is, the power consumption of the display device 1 can be reduced.

[0163] When the first transistor T1 to the fifth transistor T5 and the seventh transistor T7 are implemented as P-type transistors (e.g., P-type LTPS thin film transistors), the current flowing through each of the first transistor T1 to the fifth transistor T5 and the seventh transistor T7 can be larger, and the stability of the gate driver 300 can be improved.

[0164] Figure 10 It is shown that it includes Figure 1 A block diagram illustrating an implementation of a stage in the gate driver 300a.

[0165] refer to Figure 10 The gate driver 300a may include stages. For example, the gate driver 300a may include a first stage ST[1]b and a second stage ST[2]b. In some aspects, the gate driver 300a may include an nth stage ST[n]b. Apart from the signals applied to the stage of the gate driver 300a, the stage is essentially the same as... Figure 2 The levels are the same. Therefore, the same reference numerals will be used to refer to those of the same level. Figure 2 The components described in the previous embodiments are the same as or similar to those described above, and any repeated explanations of the above elements will be omitted.

[0166] Each of the stages can receive a first power supply voltage VGH, a second power supply voltage VGL2, and a third power supply voltage VGL1. In some respects, each of the stages can receive a first clock signal CLK1 and a second clock signal CLK2.

[0167] Each stage can receive an input signal. The input signal can be the start signal FLM or the gate signal of the previous stage.

[0168] The first stage ST[1]b can receive the first power supply voltage VGH, the second power supply voltage VGL2, the third power supply voltage VGL1, the first clock signal CLK1, and the second clock signal CLK2. In some aspects, the first stage ST[1]b can receive the start signal FLM. In some aspects, the first stage ST[1]b can output the first gate signal GW[1] at the first output node NO[1].

[0169] The second stage ST[2]b can receive the first power supply voltage VGH, the second power supply voltage VGL2, the third power supply voltage VGL1, the first clock signal CLK1, and the second clock signal CLK2. In some aspects, the second stage ST[2]b can receive the first gate signal GW[1]. In some aspects, the second stage ST[2]b can output the second gate signal GW[2] at the second output node NO[2].

[0170] In this way, the nth stage ST[n]b can receive the first power supply voltage VGH, the second power supply voltage VGL2, the third power supply voltage VGL1, the first clock signal CLK1, and the second clock signal CLK2. In some aspects, the nth stage ST[n]b can receive the (n-1)th gate signal GW[n-1]. In some aspects, the nth stage ST[n]b can output the nth gate signal GW[n] at the nth output node NO[n].

[0171] Figure 11 It is shown Figure 10 The circuit diagram of the implementation of the stage.

[0172] For ease of explanation, in this embodiment, the level is the nth level ST[n]b that receives the (n-1)th gate signal GW[n-1].

[0173] refer to Figure 11 The nth stage ST[n]b may include input circuit 10, control circuit 20b, and output circuit 30b. Except for control circuit 20b and output circuit 30b, the nth stage ST[n]b is essentially the same as... Figure 3 The nth level ST[n] is the same. Therefore, the same reference numerals will be used to refer to the same level. Figure 3 The components described in the previous embodiments are the same as or similar to those described above, and any repeated explanations of the above elements will be omitted.

[0174] The control circuit 20b may include the second transistor T2 to the sixth transistor T6b and the first capacitor C1 to the third capacitor C3b.

[0175] The second transistor T2 may include a control electrode that receives a third power supply voltage VGL1, a first electrode connected to a first node N1, and a second electrode connected to a third node N3.

[0176] The third transistor T3 may include a control electrode connected to the third node N3, a first electrode that receives the second clock signal CLK2, and a second electrode connected to the second node N2.

[0177] The fourth transistor T4 may include a control electrode that receives the first clock signal CLK1, a first electrode that receives the first power supply voltage VGH, and a second electrode that is connected to the second node N2.

[0178] The fifth transistor T5 may include a control electrode connected to the second node N2, a first electrode receiving a first power supply voltage VGH, and a second electrode connected to the nth control node Q[n].

[0179] The sixth transistor T6b may include a control electrode connected to the third node N3, a first electrode connected to the nth control node Q[n], and a second electrode receiving the second power supply voltage VGL2.

[0180] The first capacitor C1 may include a first electrode connected to the second node N2 and a second electrode connected to the third node N3.

[0181] The second capacitor C2 may include a first electrode that receives a first power supply voltage VGH and a second electrode connected to a second node N2.

[0182] The third capacitor C3b may include a first electrode connected to the second node N2 and a second electrode connected to the third node N3.

[0183] The sixth transistor T6b and the eighth transistor T8 can be implemented as transistors of the first type. In some embodiments, the first transistors T1 through T5 and the seventh transistor T7 can be implemented as transistors of the second type, which are different from the first type of transistors.

[0184] In some embodiments, the sixth transistor T6b and the eighth transistor T8 can be implemented as N-type transistors. In some embodiments, the first transistor T1 through the fifth transistor T5 and the seventh transistor T7 can be implemented as P-type transistors.

[0185] For example, the sixth transistor T6b and the eighth transistor T8 can be implemented as N-type metal-oxide-slim thin-film transistors. In some embodiments, the first transistors T1 through T5 and the seventh transistor T7 can be implemented as P-type LTPS thin-film transistors.

[0186] In the example where the sixth transistor T6b is implemented as an N-type transistor (e.g., an N-type metal-oxide-slim transistor), the cutoff characteristics of the sixth transistor T6b can be improved, and the leakage current of the sixth transistor T6b can be reduced. Therefore, the voltage of the nth control node Q[n] can stably maintain the level of the first power supply voltage VGH, and the stability of the gate driver 300a can be improved. In some respects, as the leakage current of the sixth transistor T6b decreases, the power consumption of the display device 1 can be reduced.

[0187] In the example where the eighth transistor T8 is implemented as an N-type transistor (e.g., an N-type metal-oxide-slim transistor), the cutoff characteristics of the eighth transistor T8 can be improved, and the leakage current of the eighth transistor T8 can be reduced. Therefore, the nth gate signal GW[n] output at the nth output node NO[n] can stably maintain the level of the first power supply voltage VGH, and the stability of the gate driver 300a can be improved. In some respects, as the leakage current of the eighth transistor T8 decreases, the power consumption of the display device 1 can be reduced.

[0188] Compared to conventional gate drivers, since the sixth transistor T6b and the eighth transistor T8 are implemented as N-type transistors (e.g., N-type metal-oxide-slim transistors), the number of transistors included in the gate driver 300a can be reduced. Therefore, the dead time of the display device 1 including the gate driver 300a can be reduced, and the power consumption of the display device 1 can be lowered. In some respects, the integration density of the display device 1 can be increased.

[0189] In some aspects, a first clock signal CLK1 can be applied to the first transistor T1 and the fourth transistor T4 via a first clock signal line, and a second clock signal CLK2 can be applied to the third transistor T3 via a second clock signal line. When the first transistor T1, the third transistor T3, and the fourth transistor T4 are implemented as P-type transistors, the dimensions of the first transistor T1, the third transistor T3, and the fourth transistor T4 can be relatively smaller than the dimensions of the first transistor T1, the third transistor T3, and the fourth transistor T4 when they are implemented as N-type transistors. Therefore, the capacitance of the first parasitic capacitor formed by the first clock signal line and the first transistor T1 can be reduced, and the capacitance of the second parasitic capacitor formed by the first clock signal line and the fourth transistor T4 can be reduced. In some aspects, the capacitance of the third parasitic capacitor formed by the second clock signal line and the third transistor T3 can be reduced. Therefore, the power consumption of the display device 1 caused by the charging and discharging of the first parasitic capacitor to the third parasitic capacitor can be reduced. That is, the power consumption of the display device 1 can be reduced.

[0190] When the first transistor T1 to the fifth transistor T5 and the seventh transistor T7 are implemented as P-type transistors (e.g., P-type LTPS thin film transistors), the current flowing through each of the first transistor T1 to the fifth transistor T5 and the seventh transistor T7 can be larger, and the stability of the gate driver 300a can be improved.

[0191] Figure 12 It is shown Figure 11 A timing diagram of the implementation method of the level operation.

[0192] refer to Figure 12 The period during which the signal is applied to the nth stage ST[n]b can include the first period TP1', the second period TP2', the third period TP3', and the fourth period TP4'. Except for the voltage applied to the control electrode of the sixth transistor T6b during the first period TP1' to the fourth period TP4', this timing diagram is essentially the same as... Figure 4 The timing diagrams are the same. Therefore, the same reference numerals will be used to refer to the same... Figure 4 The components described in the previous embodiments are the same as or similar to those described above, and any repeated explanations of the above elements will be omitted.

[0193] When the control electrode of the sixth transistor T6b is connected to the third node N3, the sixth transistor T6b can be turned on or off based on the voltage of the third node N3 and the level of the second power supply voltage VGL2.

[0194] In the first cycle TP1', the sixth transistor T6b can be turned on in response to the voltage of the third node N3 and the second power supply voltage VGL2. The difference between the voltage of the third node N3 and the second power supply voltage VGL2 can be greater than the threshold voltage of the sixth transistor T6b. The sixth transistor T6b can send the second power supply voltage VGL2 to the nth control node Q[n]. Therefore, the nth control node Q[n] can have the level of the second power supply voltage VGL2.

[0195] The eighth transistor T8 can be turned off in response to the third power supply voltage VGL1 and the voltage of the nth control node Q[n]. The difference between the voltage of the nth control node Q[n] and the third power supply voltage VGL1 can be less than the threshold voltage of the eighth transistor T8. Therefore, the eighth transistor T8 can be turned off. In the example where the eighth transistor T8 is implemented as an N-type transistor, the turn-off characteristics of the eighth transistor T8 can be improved, and the leakage current of the eighth transistor T8 can be reduced. Therefore, the nth gate signal GW[n] output at the nth output node NO[n] can stably maintain the level of the first power supply voltage VGH, and the stability of the gate driver 300a can be improved. In some respects, as the leakage current of the eighth transistor T8 decreases, the power consumption of the display device 1 can be reduced.

[0196] In the second cycle TP2', the sixth transistor T6b can be turned on in response to the voltage of the third node N3 and the second power supply voltage VGL2. The difference between the voltage of the third node N3 and the second power supply voltage VGL2 can be greater than the threshold voltage of the sixth transistor T6b. Therefore, the sixth transistor T6b can be turned on. The sixth transistor T6b can send the second power supply voltage VGL2 to the nth control node Q[n]. Therefore, the nth control node Q[n] can have the level of the second power supply voltage VGL2.

[0197] The eighth transistor T8 can be turned off in response to the third power supply voltage VGL1 and the voltage of the nth control node Q[n]. The difference between the voltage of the nth control node Q[n] and the third power supply voltage VGL1 can be less than the threshold voltage of the eighth transistor T8. Therefore, the eighth transistor T8 can be turned off. In the example where the eighth transistor T8 is implemented as an N-type transistor, the turn-off characteristics of the eighth transistor T8 can be improved, and the leakage current of the eighth transistor T8 can be reduced. Therefore, the nth gate signal GW[n] output at the nth output node NO[n] can stably maintain the level of the first power supply voltage VGH, and the stability of the gate driver 300a can be improved. In some respects, as the leakage current of the eighth transistor T8 decreases, the power consumption of the display device 1 can be reduced.

[0198] In the third cycle TP3', the sixth transistor T6b can be turned off in response to the voltage of the third node N3 and the second power supply voltage VGL2. The difference between the voltage of the third node N3 and the second power supply voltage VGL2 can be less than the threshold voltage of the sixth transistor T6b. Therefore, the sixth transistor T6b can be turned off. In the example where the sixth transistor T6b is implemented as an N-type transistor, the turn-off characteristics of the sixth transistor T6b can be improved, and the leakage current of the sixth transistor T6b can be reduced. Therefore, the voltage of the nth control node Q[n] can be stably maintained at the level of the first power supply voltage VGH, and the stability of the gate driver 300a can be improved. In some respects, as the leakage current of the sixth transistor T6b decreases, the power consumption of the display device 1 can be reduced.

[0199] The eighth transistor T8 can be turned on in response to the third power supply voltage VGL1 and the voltage of the nth control node Q[n]. The difference between the voltage of the nth control node Q[n] and the third power supply voltage VGL1 can be greater than the threshold voltage of the eighth transistor T8. Therefore, the eighth transistor T8 can be turned on. The eighth transistor T8 can send the third power supply voltage VGL1 to the nth output node NO[n]. The nth output node NO[n] can output the nth gate signal GW[n] with the level of the third power supply voltage VGL1.

[0200] In the fourth cycle TP4', the sixth transistor T6b can be turned on in response to the voltage of the third node N3 and the second power supply voltage VGL2. The difference between the voltage of the third node N3 and the second power supply voltage VGL2 can be greater than the threshold voltage of the sixth transistor T6b. Therefore, the sixth transistor T6b can be turned on. The sixth transistor T6b can send the second power supply voltage VGL2 to the nth control node Q[n]. Therefore, the nth control node Q[n] can have the level of the second power supply voltage VGL2.

[0201] The eighth transistor T8 can be turned off in response to the third power supply voltage VGL1 and the voltage of the nth control node Q[n]. The difference between the voltage of the nth control node Q[n] and the third power supply voltage VGL1 can be less than the threshold voltage of the eighth transistor T8. Therefore, the eighth transistor T8 can be turned off. In the example where the eighth transistor T8 is implemented as an N-type transistor, the turn-off characteristics of the eighth transistor T8 can be improved, and the leakage current of the eighth transistor T8 can be reduced. Therefore, the nth gate signal GW[n] output at the nth output node NO[n] can stably maintain the level of the first power supply voltage VGH, and the stability of the gate driver 300a can be improved. In some respects, as the leakage current of the eighth transistor T8 decreases, the power consumption of the display device 1 can be reduced.

[0202] Figure 13 It is shown Figure 10 The circuit diagram of the implementation of the stage.

[0203] For ease of explanation, in this embodiment, the stage is the nth stage ST[n]c that receives the (n-1)th gate signal GW[n-1].

[0204] refer to Figure 13 The nth stage ST[n]c may include input circuit 10, control circuit 20c, and output circuit 30c. Except that each of the sixth transistor T6c and the eighth transistor T8c includes a second control electrode, the nth stage ST[n]c is essentially the same as... Figure 11 The nth level ST[n]b is the same. Therefore, the same reference numerals will be used to refer to the same level. Figure 11 The components described in the previous embodiments are the same as or similar to those described above, and any repeated explanations of the above elements will be omitted.

[0205] The sixth transistor T6c may include a control electrode connected to the third node N3, a first electrode connected to the nth control node Q[n], and a second electrode receiving the second power supply voltage VGL2. In some aspects, the sixth transistor T6c may also include a second control electrode connected to the control electrode of the sixth transistor T6c.

[0206] The eighth transistor T8c may include a control electrode connected to the nth control node Q[n], a first electrode connected to the nth output node NO[n], and a second electrode receiving the third power supply voltage VGL1. In some aspects, the eighth transistor T8c may also include a second control electrode connected to the control electrode of the eighth transistor T8c.

[0207] The characteristics of the sixth transistor T6c and the eighth transistor T8c may change due to stress. For example, the threshold voltage of each of the sixth transistor T6c and the eighth transistor T8c may change due to stress. Therefore, for example, a second control electrode is included in each of the sixth transistor T6c and the eighth transistor T8c to prevent or mitigate any changes in the threshold voltage of each of the sixth transistor T6c, the eighth transistor T8c, and the ninth transistor T9a. This improves the stability of the gate driver 300a.

[0208] The sixth transistor T6c and the eighth transistor T8c can be implemented as transistors of the first type. In some embodiments, the first transistors T1 through T5 and the seventh transistor T7 can be implemented as transistors of the second type, which are different from the first type of transistors.

[0209] In some embodiments, the sixth transistor T6c and the eighth transistor T8c can be implemented as N-type transistors. In some embodiments, the first transistor T1 to the fifth transistor T5 and the seventh transistor T7 can be implemented as P-type transistors.

[0210] For example, the sixth transistor T6c and the eighth transistor T8c can be implemented as N-type metal-oxide-slim thin-film transistors. In some embodiments, the first transistors T1 through T5 and the seventh transistor T7 can be implemented as P-type LTPS thin-film transistors.

[0211] In the example where the sixth transistor T6c is implemented as an N-type transistor (e.g., an N-type metal-oxide-slim transistor), the cutoff characteristics of the sixth transistor T6c can be improved, and the leakage current of the sixth transistor T6c can be reduced. Therefore, the voltage of the nth control node Q[n] can stably maintain the level of the first power supply voltage VGH, and the stability of the gate driver 300a can be improved. In some respects, as the leakage current of the sixth transistor T6c decreases, the power consumption of the display device 1 can be reduced.

[0212] In the example where the eighth transistor T8c is implemented as an N-type transistor (e.g., an N-type metal-oxide-slim transistor), the cutoff characteristics of the eighth transistor T8c can be improved, and the leakage current of the eighth transistor T8c can be reduced. Therefore, the nth gate signal GW[n] output at the nth output node NO[n] can stably maintain the level of the first power supply voltage VGH, and the stability of the gate driver 300a can be improved. In some respects, as the leakage current of the eighth transistor T8c decreases, the power consumption of the display device 1 can be reduced.

[0213] Compared to conventional gate drivers, since the sixth transistor T6c and the eighth transistor T8c are implemented as N-type transistors (e.g., N-type metal-oxide-slim transistors), the number of transistors included in the gate driver 300a can be reduced. Therefore, the dead time of the display device 1 including the gate driver 300a can be reduced, and the power consumption of the display device 1 can be lowered. In some respects, the integration density of the display device 1 can be increased.

[0214] In some aspects, a first clock signal CLK1 can be applied to the first transistor T1 and the fourth transistor T4 via a first clock signal line, and a second clock signal CLK2 can be applied to the third transistor T3 via a second clock signal line. When the first transistor T1, the third transistor T3, and the fourth transistor T4 are implemented as P-type transistors, the dimensions of the first transistor T1, the third transistor T3, and the fourth transistor T4 can be relatively smaller than the dimensions of the first transistor T1, the third transistor T3, and the fourth transistor T4 when they are implemented as N-type transistors. Therefore, the capacitance of the first parasitic capacitor formed by the first clock signal line and the first transistor T1 can be reduced, and the capacitance of the second parasitic capacitor formed by the first clock signal line and the fourth transistor T4 can be reduced. In some aspects, the capacitance of the third parasitic capacitor formed by the second clock signal line and the third transistor T3 can be reduced. Therefore, the power consumption of the display device 1 caused by the charging and discharging of the first parasitic capacitor to the third parasitic capacitor can be reduced. That is, the power consumption of the display device 1 can be reduced.

[0215] When the first transistor T1 to the fifth transistor T5 and the seventh transistor T7 are implemented as P-type transistors (e.g., P-type LTPS thin film transistors), the current flowing through each of the first transistor T1 to the fifth transistor T5 and the seventh transistor T7 can be larger, and the stability of the gate driver 300a can be improved.

[0216] Figure 14 It is shown that it includes Figure 1 A circuit diagram illustrating an implementation of the pixel PX in the display panel 100.

[0217] refer to Figure 14 A pixel PX may include first pixel transistors PT1 to seventh pixel transistors PT7, storage capacitor CST, and light-emitting element EE, but a pixel PX is not limited to these.

[0218] In an implementation, the gate signal output from a stage included in the gate driver 300 may be a write gate signal applied to the second pixel transistor PT2. For example, the nth gate signal GW[n] output from the nth stage ST[n] may be a write gate signal applied to the second pixel transistor PT2, and therefore may also be referred to as the write gate signal GW[n].

[0219] The first pixel transistor PT1 may include a control electrode connected to a first pixel node PN1, a first electrode connected to a second pixel node PN2, and a second electrode connected to a third pixel node PN3. The first pixel transistor PT1 may generate a drive current based on the difference between the voltage of the first pixel node PN1 and the voltage of the second pixel node PN2.

[0220] The second pixel transistor PT2 may include a control electrode for receiving a write gate signal GW[n], a first electrode for receiving a data voltage VDATA, and a second electrode connected to the second pixel node PN2. The second pixel transistor PT2 may send the data voltage VDATA to the second pixel node PN2 in response to the write gate signal GW[n].

[0221] The third pixel transistor PT3 may include a control electrode that receives a compensation gate signal GC[n], a first electrode connected to the third pixel node PN3, and a second electrode connected to the first pixel node PN1. The third pixel transistor PT3 may connect the diode of the first pixel transistor PT1 in response to the compensation gate signal GC[n].

[0222] The fourth pixel transistor PT4 may include a control electrode that receives an initialization gate signal GI[n], a first electrode that receives an initialization voltage VINT, and a second electrode connected to the first pixel node PN1. The fourth pixel transistor PT4 may send an initialization voltage VINT to the first pixel node PN1 in response to the initialization gate signal GI[n].

[0223] The fifth pixel transistor PT5 may include a control electrode that receives the transmission signal EM[n], a first electrode that receives the first pixel power supply voltage ELVDD, and a second electrode that is connected to the second pixel node PN2.

[0224] The sixth pixel transistor PT6 may include a control electrode for receiving the transmitted signal EM[n], a first electrode connected to the third pixel node PN3, and a second electrode connected to the fourth pixel node PN4.

[0225] The fifth pixel transistor PT5 and the sixth pixel transistor PT6 can control the emission of the light-emitting element EE in response to the emission signal EM[n].

[0226] The seventh pixel transistor PT7 may include a control electrode that receives the previous write gate signal GW[n-1], a first electrode that receives the anode initialization voltage VAINT, and a second electrode connected to the fourth pixel node PN4. The seventh pixel transistor PT7 may send the anode initialization voltage VAINT to the fourth pixel node PN4 in response to the previous write gate signal GW[n-1].

[0227] The storage capacitor CST may include a first electrode that receives the first pixel power supply voltage ELVDD and a second electrode connected to the first pixel node PN1. The storage capacitor CST may store the data voltage VDATA.

[0228] The light-emitting element EE may include an anode electrode connected to the fourth pixel node PN4 and a cathode electrode receiving the second pixel power supply voltage ELVSS. The light-emitting element EE may emit light based on the drive current generated by the first pixel transistor PT1.

[0229] Figure 15 This is a block diagram illustrating an electronic device 1000 according to an embodiment of the present disclosure, and Figure 16 It is shown Figure 15 The diagram illustrates an implementation of the electronic device 1000 as a smartphone.

[0230] refer to Figure 15 and Figure 16 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be... Figure 1 The display device 1. In some aspects, the electronic device 1000 may also include ports for communicating with video cards, sound cards, memory cards, universal serial bus (USB) devices, other electronic devices, etc.

[0231] In the implementation method, such as Figure 16As shown, the electronic device 1000 can be implemented as a smartphone. However, the electronic device 1000 is not limited to this. For example, the electronic device 1000 can be implemented as a cellular phone, video phone, smartboard, smartwatch, tablet PC, car navigation system, computer monitor, laptop computer, head-mounted display (HMD) device, etc.

[0232] Processor 1010 can perform various computing functions. Processor 1010 can be a microprocessor, central processing unit (CPU), application processor (AP), etc. Processor 1010 can be connected to other components via address bus, control bus, data bus, etc. In addition, processor 1010 can be connected to an expansion bus (such as, for example, a peripheral component interconnect (PCI) bus).

[0233] Processor 1010 can output input image data IMG and input control signal CONT to Figure 1 The drive controller 200.

[0234] The memory device 1020 can store data for the operation of the electronic device 1000. For example, the memory device 1020 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc.).

[0235] Storage device 1030 may include solid-state drive (SSD) devices, hard disk drive (HDD) devices, CD-ROM devices, etc.

[0236] I / O device 1040 may include input devices (such as keyboards, keypads, mice, touchpads, touchscreens, etc.) and output devices (such as printers, speakers, etc.). According to an embodiment, I / O device 1040 may include display device 1060.

[0237] Power supply 1050 can provide power for the operation of electronic device 1000.

[0238] The display device 1060 can be connected to other components via a bus or other communication link.

[0239] The aspects of this disclosure can be applied to display devices and electronic devices that include display devices. For example, embodiments of this disclosure can be applied to televisions (TV), digital TVs, 3D TVs, mobile phones, smartphones, tablet computers, laptop computers, personal computers (PCs), home electronic devices, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, or the like.

[0240] The foregoing is an example of embodiments of this disclosure and is not intended to limit it. Although exemplary embodiments supported by this disclosure have been described, those skilled in the art will readily understand that many modifications can be made to the embodiments without substantially departing from the novel teachings and benefits of the embodiments of this disclosure. Therefore, all such modifications are intended to be included within the scope of the embodiments of this disclosure as defined in the claims. In the claims, functional terminology is intended to cover structures described herein that perform the functions described, and to cover not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is an example of embodiments of this disclosure and is not intended to be limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. Exemplary embodiments supported by this disclosure are defined by the appended claims, and equivalents of the claims are also included therein.

Claims

1. A gate driver comprising: an input circuit that sends an input signal to a control circuit based on a first clock signal; the control circuit that controls a voltage of a control node based on the input signal, the first clock signal, a second clock signal, and a voltage control signal; and an output circuit that outputs a gate signal based on the voltage of the control node, wherein the control circuit comprises: a fifth transistor that includes a control electrode connected to a second node, a first electrode that receives a first power voltage, and a second electrode connected to the control node; a sixth transistor that includes a control electrode connected to a fourth node, a first electrode connected to the control node, and a second electrode that receives a second power voltage; and a ninth transistor that includes a control electrode that receives the voltage control signal, a first electrode connected to a third node, and a second electrode connected to the fourth node, wherein the control circuit sends one of the first power voltage and the second power voltage to the control node, and the output circuit outputs one of the first power voltage and a third power voltage as the gate signal.

2. The gate driver according to claim 1, wherein the input circuit includes a first transistor that includes a control electrode that receives the first clock signal, a first electrode that receives the input signal, and a second electrode connected to a first node, and the control circuit further comprises: a second transistor that includes a control electrode that receives the third power voltage, a first electrode connected to the first node, and a second electrode connected to the third node; a third transistor that includes a control electrode connected to the third node, a first electrode that receives the second clock signal, and a second electrode connected to the second node; a fourth transistor that includes a control electrode that receives the first clock signal, a first electrode that receives the first power voltage, and a second electrode connected to the second node; a first capacitor that includes a first electrode connected to the second node and a second electrode connected to the third node; a second capacitor that includes a first electrode that receives the first power voltage and a second electrode connected to the second node; and a third capacitor that includes a first electrode connected to the second node and a second electrode connected to the fourth node.

3. The gate driver of claim 2, wherein, the output circuit includes: a seventh transistor that includes a control electrode connected to the control node, a first electrode that receives the first power voltage, and a second electrode connected to an output node; and an eighth transistor that includes a control electrode connected to the control node, a first electrode connected to the output node, and a second electrode that receives the third power voltage.

4. The gate driver according to claim 3, wherein a level of the first power voltage is higher than a level of the third power voltage, and the level of the third power voltage is higher than a level of the second power voltage.

5. The gate driver according to claim 3, wherein the sixth transistor, the eighth transistor, and the ninth transistor are implemented as transistors of a first type, and the seventh transistor is implemented as a transistor of a second type. The first transistor to the fifth transistor and the seventh transistor are implemented as a transistor of a second type different from the transistor of the first type.

6. The gate driver of claim 5, wherein, The sixth transistor, the eighth transistor, and the ninth transistor are implemented as N-type transistors.

7. The gate driver of claim 5, wherein, The first transistor to the fifth transistor and the seventh transistor are implemented as P-type transistors.

8. The gate driver according to claim 3, wherein The sixth transistor further includes a second control electrode connected to the control electrode of the sixth transistor, The eighth transistor further includes a second control electrode connected to the control electrode of the eighth transistor, and The ninth transistor further includes a second control electrode connected to the control electrode of the ninth transistor.

9. A display device comprising: a display panel including a pixel; a gate driver that outputs a gate signal to the pixel; and a data driver that outputs a data voltage to the pixel, wherein the gate driver includes: an input circuit that sends an input signal to a control circuit based on a first clock signal; the control circuit that controls a voltage of a control node based on the input signal, the first clock signal, a second clock signal, and a voltage control signal; and an output circuit that outputs the gate signal based on the voltage of the control node, wherein the control circuit includes: a fifth transistor including a control electrode connected to a second node, a first electrode that receives a first power supply voltage, and a second electrode connected to the control node; a sixth transistor including a control electrode connected to a fourth node, a first electrode connected to the control node, and a second electrode that receives a second power supply voltage; and a ninth transistor including a control electrode that receives the voltage control signal, a first electrode connected to a third node, and a second electrode connected to the fourth node, wherein the control circuit sends one of the first power supply voltage and the second power supply voltage to the control node, and the output circuit outputs one of the first power supply voltage and a third power supply voltage as the gate signal.

10. The display device according to claim 9, wherein the input circuit includes a first transistor including a control electrode that receives the first clock signal, a first electrode that receives the input signal, and a second electrode connected to a first node, and the control circuit further includes: a second transistor including a control electrode that receives the third power supply voltage, a first electrode connected to the first node, and a second electrode connected to the third node; a third transistor including a control electrode connected to the third node, a first electrode that receives the second clock signal, and a second electrode connected to the second node; a fourth transistor including a control electrode that receives the first clock signal, a first electrode that receives the first power supply voltage, and a second electrode connected to the second node; a first capacitor including a first electrode connected to the second node and a second electrode connected to the third node; and a second capacitor including a first electrode connected to the fourth node and a second electrode connected to the third node.

11. The display device according to claim 10, wherein the first transistor includes a first channel region of a first conductivity type, the second transistor includes a second channel region of a second conductivity type different from the first conductivity type, the third transistor includes a third channel region of the first conductivity type, the fourth transistor includes a fourth channel region of the second conductivity type, and the fifth transistor includes a fifth channel region of the second conductivity type.

12. The display device according to claim 11, wherein the first transistor includes a first impurity region of the first conductivity type in the first channel region, the second transistor includes a second impurity region of the second conductivity type in the second channel region, the third transistor includes a third impurity region of the first conductivity type in the third channel region, the fourth transistor includes a fourth impurity region of the second conductivity type in the fourth channel region, and the fifth transistor includes a fifth impurity region of the second conductivity type in the fifth channel region.

13. The display device according to claim 12, wherein the first impurity region is formed in a first portion of the first channel region, the second impurity region is formed in a second portion of the second channel region, the third impurity region is formed in a third portion of the third channel region, the fourth impurity region is formed in a fourth portion of the fourth channel region, and the fifth impurity region is formed in a fifth portion of the fifth channel region.

14. The display device according to claim 13, wherein the first portion is closer to the first electrode than to the second electrode, the second portion is closer to the first electrode than to the second electrode, the third portion is closer to the first electrode than to the second electrode, the fourth portion is closer to the first electrode than to the second electrode, and the fifth portion is closer to the first electrode than to the second electrode.

15. The display device according to claim 14, wherein the first portion is closer to the first electrode than to the second electrode, the second portion is closer to the first electrode than to the second electrode, the third portion is closer to the first electrode than to the second electrode, the fourth portion is closer to the first electrode than to the second electrode, and the fifth portion is closer to the first electrode than to the second electrode. a second capacitor including a first electrode receiving the first power supply voltage and a second electrode connected to the second node; and a third capacitor including a first electrode connected to the second node and a second electrode connected to the fourth node.

11. The display device of claim 10, wherein, the output circuit includes: a seventh transistor including a control electrode connected to the control node, a first electrode receiving the first power supply voltage, and a second electrode connected to an output node; and an eighth transistor including a control electrode connected to the control node, a first electrode connected to the output node, and a second electrode receiving the third power supply voltage.

12. The display device according to claim 11, wherein a level of the first power supply voltage is higher than a level of the third power supply voltage, and the level of the third power supply voltage is higher than a level of the second power supply voltage.

13. The display device according to claim 11, wherein the sixth transistor, the eighth transistor, and the ninth transistor are implemented as transistors of a first type, and the first transistor to the fifth transistor and the seventh transistor are implemented as transistors of a second type different from the transistors of the first type.

14. The display device of claim 13, wherein, the sixth transistor, the eighth transistor, and the ninth transistor are implemented as N-type transistors.

15. The display device of claim 13, wherein, the first transistor to the fifth transistor and the seventh transistor are implemented as P-type transistors.

16. The display device according to claim 11, wherein the sixth transistor further includes a second control electrode connected to the control electrode of the sixth transistor, the eighth transistor further includes a second control electrode connected to the control electrode of the eighth transistor, and the ninth transistor further includes a second control electrode connected to the control electrode of the ninth transistor.

17. An electronic device comprising: a processor outputting an input control signal and input image data; a display panel including pixels; a gate driver outputting a gate signal to the pixels; a data driver outputting a data voltage to the pixels; and a drive controller controlling the gate driver and the data driver based on the input control signal and the input image data, wherein the gate driver includes: an input circuit sending an input signal to a control circuit based on a first clock signal; the control circuit controlling a voltage of a control node based on the input signal, the first clock signal, a second clock signal, and a voltage control signal; and an output circuit outputting the gate signal based on the voltage of the control node, wherein the control circuit includes: a fifth transistor including a control electrode connected to a second node, a first electrode receiving a first power supply voltage, and a second electrode connected to the control node; a sixth transistor including a control electrode connected to a fourth node, a first electrode connected to the control node, and a second electrode receiving a second power supply voltage; and a ninth transistor including a control electrode receiving the voltage control signal, a first electrode connected to a third node, and a second electrode connected to the fourth node, wherein ​ the control circuit sends one of the first power voltage and the second power voltage to the control node, and the output circuit outputs one of the first power voltage and a third power voltage as the gate signal. 18.The electronic device of claim 17, wherein the input circuit includes a first transistor including a control electrode that receives the first clock signal, a first electrode that receives the input signal, and a second electrode connected to a first node, and the control circuit further includes: a second transistor including a control electrode that receives the third power voltage, a first electrode connected to the first node, and a second electrode connected to a third node; a third transistor including a control electrode connected to the third node, a first electrode that receives the second clock signal, and a second electrode connected to the second node; a fourth transistor including a control electrode that receives the first clock signal, a first electrode that receives the first power voltage, and a second electrode connected to the second node; a first capacitor including a first electrode connected to the second node and a second electrode connected to the third node; a second capacitor including a first electrode that receives the first power voltage and a second electrode connected to the second node; and a third capacitor including a first electrode connected to the second node and a second electrode connected to a fourth node. 19.The electronic device of claim 18, wherein, the output circuit includes: a seventh transistor including a control electrode connected to the control node, a first electrode that receives the first power voltage, and a second electrode connected to an output node; and an eighth transistor including a control electrode connected to the control node, a first electrode connected to the output node, and a second electrode that receives the third power voltage. 20.The electronic device of claim 19, wherein a level of the first power voltage is higher than a level of the third power voltage, and the level of the third power voltage is higher than a level of the second power voltage.

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