Three-dimensional memory devices including string select line gate electrodes with silicide layers

Abstract

A three-dimensional memory device is provided. The three-dimensional memory device can include a substrate, a cell stack, a string select line gate electrode, a lower vertical channel structure, an upper vertical channel structure, and a bit line. The string select line gate electrode can include a lower string select line gate electrode and an upper string select line gate electrode formed on an upper surface of the lower string select line gate electrode. The lower string select line gate electrode can include N-doped polysilicon. The upper string select line gate electrode can include a silicide.

Description

Technical Field

[0001] This disclosure relates to a three-dimensional memory device including a string select line gate electrode having a silicide layer. Background Technology

[0002] As the stacking height of memory cells and word lines in 3D memory devices increases, techniques for forming string select lines using additional processes have been proposed. However, because the proposed string select lines formed using these additional processes are made of polysilicon, which has a resistance much higher than that of metal, the resulting 3D memory devices may struggle to achieve low-power and high-speed operation. Summary of the Invention

[0003] Exemplary embodiments of this disclosure provide a three-dimensional memory device including a series select line gate electrode with low resistance and a method for manufacturing the three-dimensional memory device.

[0004] A three-dimensional memory device according to an exemplary embodiment of the present disclosure may include: a substrate; a cell stack disposed on the substrate; a string select line gate electrode disposed on the cell stack; a lower vertical channel structure perpendicularly penetrating the cell stack; an upper vertical channel structure perpendicularly penetrating the string select line gate electrode and connected to the lower vertical channel structure; and a bit line disposed on the upper vertical channel structure. The string select line gate electrode may include a lower string select line gate electrode and an upper string select line gate electrode formed on the upper surface of the lower string select line gate electrode. The lower string select line gate electrode may include N-doped polysilicon. The upper string select line gate electrode may include silicide.

[0005] A three-dimensional memory device according to an exemplary embodiment of the present disclosure may include: a substrate; a common source layer disposed on the substrate; a cell stack disposed on the common source layer; a string select line gate electrode disposed on the cell stack; a lower vertical channel structure that vertically penetrates the cell stack and is connected to the common source layer; an upper vertical channel structure that vertically penetrates the string select line gate electrode and is connected to the lower vertical channel structure; a pad pattern disposed on the upper vertical channel structure; and bit lines disposed on the pad pattern. The pad pattern may include a lower pad pattern and an upper pad pattern formed on the lower pad pattern. The lower pad pattern may include N-doped polysilicon. The upper pad pattern may include silicide.

[0006] A three-dimensional memory device according to an exemplary embodiment of the present disclosure may include: a substrate; a logic circuit layer disposed on the substrate, the logic circuit layer including transistors, metal interconnects, and a lower insulating layer covering the transistors and metal interconnects; a common source layer disposed on the logic circuit layer; a cell stack disposed on the common source layer; a lower vertical channel structure that vertically penetrates the cell stack and connects to the common source layer; a string select line gate electrode disposed on the cell stack and the lower vertical channel structure; an upper vertical channel structure that vertically penetrates the string select line gate electrode and connects to the lower vertical channel structure; a pad pattern disposed on the upper vertical channel structure; and bit lines disposed on the pad pattern. The pad pattern may include a lower pad pattern and an upper pad pattern formed on the lower pad pattern. The string select line gate electrode may include a lower string select line gate electrode and an upper string select line gate electrode formed on the lower string select line gate electrode. The lower pad pattern and the lower string select line gate electrode may include N-doped polysilicon. The upper pad pattern and the upper string select line gate electrode may include silicide.

[0007] A method for forming a three-dimensional memory device according to an exemplary embodiment of the present disclosure may include: forming a molded stack including a molding layer and a sacrificial layer on a substrate; forming a lower vertical channel structure that vertically penetrates the molded stack; forming a string select line gate electrode on the molded stack and the lower vertical channel structure; forming an upper vertical channel structure that vertically penetrates the string select line gate electrode and connects to the lower vertical channel structure; forming a pad pattern on the upper vertical channel structure; and forming a bit line on the pad pattern. The formation of the string select line gate electrode may include forming an initial string select line gate electrode comprising N-doped polysilicon, and silicideting the upper portion of the initial string select line gate electrode to form a lower string select line gate electrode containing N-doped polysilicon and an upper string select line gate electrode containing silicide.

[0008] A method for forming a three-dimensional memory device according to an exemplary embodiment of the present disclosure may include: forming a common source layer on a substrate; forming a molded stack on the common source layer; forming a lower vertical channel structure that vertically penetrates the molded stack and is connected to the common source layer; forming a string select line gate electrode on the molded stack; forming an upper vertical channel structure that vertically penetrates the string select line gate electrode and is connected to the lower vertical channel structure; forming a pad pattern on the upper vertical channel structure; and forming bit lines on the pad pattern. The formation of the string select line gate electrode may include forming an initial string select line gate electrode comprising N-doped polysilicon, and silicideing the upper portion of the initial string select line gate electrode to form a lower string select line gate electrode comprising N-doped polysilicon and an upper string select line gate electrode comprising silicide. The formation of the pad pattern may include forming an initial pad pattern comprising N-doped polysilicon, and silicideing the upper portion of the initial pad pattern to form a lower pad pattern comprising N-doped polysilicon and an upper pad pattern comprising silicide.

[0009] A method of forming a three-dimensional memory device according to an exemplary embodiment of the present disclosure may include: forming a logic circuit layer on a substrate, the logic circuit layer including transistors, metal interconnects, and a lower insulating layer covering the transistors and metal interconnects; forming a common source layer on the logic circuit layer; forming a molded stack on the common source layer; forming a lower vertical channel structure that vertically penetrates the molded stack and is connected to the common source layer; forming a string select line gate electrode on the molded stack and the lower vertical channel structure; forming an upper vertical channel structure that vertically penetrates the string select line gate electrode and is connected to the lower vertical channel structure; forming a pad pattern on the upper vertical channel structure; and forming bit lines on the pad pattern. The formation of the string select line gate electrode may include forming an initial string select line gate electrode comprising N-doped polysilicon, and silicideting the upper portion of the initial string select line gate electrode to form a lower string select line gate electrode comprising N-doped polysilicon and an upper string select line gate electrode comprising silicide. Attached Figure Description

[0010] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0011] Figure 1 This is the layout of a three-dimensional storage device 100 according to an exemplary embodiment of the present disclosure;

[0012] Figures 2A to 2I These are longitudinal sectional views of three-dimensional storage devices 100A-100I, each according to an exemplary embodiment of the present disclosure.

[0013] Figures 3 to 25 This is a diagram illustrating a method for manufacturing a three-dimensional storage device according to an exemplary embodiment of the present disclosure;

[0014] Figures 6 to 21 yes Figure 5 A magnified view of region A;

[0015] Figure 26 and Figure 27 A method for manufacturing a three-dimensional storage device according to an exemplary embodiment of the present disclosure is shown;

[0016] Figure 28 This is a diagram illustrating a method of manufacturing a three-dimensional storage device according to an exemplary embodiment of the present disclosure;

[0017] Figure 29 and Figure 30 These are diagrams illustrating a method for forming a three-dimensional storage device according to an exemplary embodiment of the present disclosure; and

[0018] Figures 31 to 37This is a view illustrating a method for forming a three-dimensional storage device according to an exemplary embodiment of the present disclosure.

[0019] because Figure 1-37 The accompanying drawings are for illustrative purposes, so the elements in the drawings are not necessarily drawn to scale. For example, some elements may be enlarged or exaggerated for clarity. Detailed Implementation

[0020] Figure 1 This is the layout of a three-dimensional storage device 100 according to an exemplary embodiment of the present disclosure.

[0021] Reference Figure 1 A three-dimensional storage device 100 according to an exemplary embodiment of the present disclosure may include a plurality of vertical channel structures VC1 and VC2, a word line separator structure WS, a serial select line SSL, a serial select line separator pattern SSP, and a bit line BL.

[0022] Multiple vertical channel structures VC1 and VC2 may have a circular shape in a top view and may be arranged in a zigzag shape. The multiple vertical channel structures VC1 and VC2 may each include a lower vertical channel structure VC1 and an upper vertical channel structure VC2. The lower vertical channel structure VC1 may have a larger diameter than the upper vertical channel structure VC2. The lower vertical channel structure VC1 and the upper vertical channel structure VC2 may be arranged to completely overlap. For example, in an exemplary embodiment of this disclosure, the upper vertical channel structure VC2 may completely overlap with the lower vertical channel structure VC1, and a portion of the lower vertical channel structure VC1 may not overlap with the upper vertical channel structure VC2. In an exemplary embodiment of this disclosure, the lower vertical channel structure VC1 and the upper vertical channel structure VC2 may overlap and be arranged concentrically. In an exemplary embodiment of this disclosure, the lower vertical channel structure VC1 and the upper vertical channel structure VC2 may overlap and be arranged in an eccentric shape.

[0023] The string select line (SSL) can be electrically and physically separated by the string select line separator pattern (SSP). For example, the string select line SSL can surround an upper vertical channel structure (VC2) arranged in two columns. The string select line separator pattern (SSP) can have a wavy or zigzag shape in a top view. In an exemplary embodiment of this disclosure, the string select line SSL can be formed at one or more levels. For example, the string select line SSL can be formed at one level above the cell stack CS to be described, or at one level and another level directly below said one level, the cell stack CS including multiple word lines located at different levels.

[0024] Bit line BL can extend in a direction perpendicular to the extension direction of serial select line SSL and serial select line separator pattern SSP. For example, bit line BL can extend in the row direction, and serial select line SSL and serial select line separator pattern SSP can extend in the column direction. For example, serial select line separator pattern SSP can extend in the column direction in a wavy or zigzag shape instead of a straight line. Bit line BL can overlap with upper vertical channel structure VC2 arranged on the same line along the row direction. For example, multiple upper vertical channel structures VC2 arranged on the same line as bit line BL can each be electrically connected to the bit line BL above it.

[0025] The word line separator WS can extend in the column direction. The above elements will be described in more detail with reference to other accompanying drawings.

[0026] Figures 2A to 2I These are longitudinal sectional views of three-dimensional storage devices 100A-100I according to an exemplary embodiment of the present disclosure, for example along... Figure 1 The longitudinal sectional view taken by line I-I'.

[0027] Reference Figure 2A A three-dimensional memory device 100A according to an exemplary embodiment of the present disclosure may include a logic circuit layer 11, a common source layer 25, a cell stack CS, a lower vertical channel structure VC1, an upper vertical channel structure VC2, a serial select line gate electrode 50, a serial select line separator pattern SSP, a pad pattern 70, a pad spacer 75, an upper insulating layer 80, a cover insulating layer 87, a pass plug 88, and a bit line BL on a substrate 10. The three-dimensional memory device 100A may also include a lower buffer insulating layer 48 located between the cell stack CS and the serial select line gate electrode 50, a word line separator insulating layer 83 separating the cell stack CS, and a common source plug 85 connected to the common source layer 25.

[0028] Substrate 10 may include a silicon (Si) wafer. In an exemplary embodiment of this disclosure, substrate 10 may include an epitaxially grown material layer, such as, for example, a silicon (Si) layer, a silicon-germanium (SiGe) layer, or a silicon carbide (SiC) layer. In an exemplary embodiment of this disclosure, substrate 10 may include silicon-on-insulator (SOI). In an exemplary embodiment of this disclosure, substrate 10 may include III-V compounds, such as, for example, gallium phosphide (GaP), gallium arsenide (GaAs), gallium antimonide (GaSb), etc.

[0029] The logic circuit layer 11 may include a transistor 12, a metal interconnect 17, and a lower insulating layer 20. For example, the transistor 12 may include source / drain regions and channel regions formed in an active region defined by an isolation region, and may include a gate insulating layer, a gate electrode, a gate cap layer, and gate spacers formed on the substrate 10. The metal interconnect 17 may include vertically extending contact plug patterns and horizontally extending line patterns. The contact plug patterns of the metal interconnect 17 may contact the source / drain regions of the transistor 12.

[0030] The lower insulating layer 20 may cover the transistor 12 and the metal interconnect 17, and may include at least one of, for example, a silicon oxide (SiO2) layer, a silicon nitride (Si3N4) layer, and combinations thereof.

[0031] The common source layer 25 can be formed to extend horizontally over the lower insulating layer 20. For example, the common source layer 25 may comprise N-doped polysilicon (p-Si). In a top view, the common source layer 25 may have a plate shape or a line shape.

[0032] The cell stack CS can be disposed on a common source layer 25 and can include multiple alternately stacked molding layers 31 and multiple word lines 81. The molding layer 31 can include silicon oxide (SiO2). Each of the multiple word lines 81 can include a barrier layer and an electrode layer. The barrier layer can include a barrier insulating layer and a diffusion barrier layer. For example, the barrier insulating layer can include an insulator with a relatively high work function, such as aluminum oxide (Al2O3). The diffusion barrier layer can include a conductive metal compound, such as titanium nitride (TiN). The electrode layer can include a metal, such as tungsten (W).

[0033] The barrier layer and electrode layer will be described again with reference to other accompanying drawings.

[0034] The string select line gate electrode 50 can be disposed on the cell stack CS. The string select line gate electrode 50 may include a lower string select line gate electrode 51 and an upper string select line gate electrode 52. The sidewalls of the lower string select line gate electrode 51 and the sidewalls of the upper string select line gate electrode 52 may be vertically aligned. In this specification, the term "sidewalls" may mean "asidewall" or vice versa. The string select line separator pattern SSP may contact the sidewalls of the lower string select line gate electrode 51 and the upper string select line gate electrode 52. The lower string select line gate electrode 51 may include N-doped polysilicon containing phosphorus (P) and / or arsenic (As). The upper string select line gate electrode 52 may include a metal silicide. For example, the upper string select line gate electrode 52 may be the upper part of the string select line gate electrode 50, and the lower string select line gate electrode 51 may be the lower part of the string select line gate electrode 50. The upper string select gate electrode 52 may include at least one of, for example, nickel silicide (NiSi), titanium silicide (TiSi), cobalt silicide (CoSi), tungsten silicide (WSi), and other metal silicide materials. Because the upper string select gate electrode 52 having a metal silicide is formed on the upper surface of the lower string select gate electrode 51, which includes N-doped polysilicon (p-Si), a sufficiently thick metal silicide electrode can be formed regardless of the distance between it and another adjacent string select gate electrode 50. For example, a thick metal silicide electrode may be formed in the upper portion of each of two adjacent string select gate electrodes 50 having a small separation distance therebetween. Therefore, due to the formation of a metal silicide that is more conductive than N-doped polysilicon (p-Si), the resistance of the string select gate electrode 50 can be reduced. The upper surface of the upper string select gate electrode 52 may include protruding portions and recessed portions. For example, the portion adjacent to the upper vertical channel structure VC2 may protrude, and the portion spaced apart from the upper vertical channel structure VC2 may be recessed. In the top view, the protruding portion of the upper string select line grid electrode 52 may have an optical disc shape surrounding the upper vertical channel structure VC2.

[0035] The lower buffer insulating layer 48 disposed between the cell stack CS and the series select line gate electrode 50 may include silicon oxide (SiO2).

[0036] A series select line separator pattern SSP can be disposed between the series select line gate electrodes 50 to physically and materially separate the series select line gate electrodes 50. Further reference... Figure 1 The string select line separator pattern SSP can extend in a wavy or zigzag shape in the column direction. Therefore, the string select line separator pattern SSP can have a dam shape or a wall shape. The string select line separator pattern SSP can include silicon oxide (SiO2). In an exemplary embodiment of this disclosure, the string select line separator pattern SSP can include the same material as the lower buffer insulating layer 48.

[0037] The lower vertical channel structure VC1 may have a pillar shape that vertically penetrates the cell stack CS (e.g., molding layer 31 and word line 81) to connect to the common source layer 25, and may include a storage layer 41, a lower channel layer 45, and a lower gap fill pattern 47. The lower channel layer 45 may surround the lower gap fill pattern 47, and the storage layer 41 may surround the lower channel layer 45. For example, the lower vertical channel structure VC1 may include: a storage layer 41 conformally formed on the inner wall of a lower vertical channel aperture that vertically penetrates the molding layer 31 and word line 81 to expose the common source layer 25; a lower channel layer 45 conformally formed on the inner wall of the storage layer 41; and a lower gap fill pattern 47 formed on the inner wall of the lower channel layer 45 to fill the lower vertical channel aperture. The storage layer 41 will be described in more detail with reference to other figures.

[0038] The lower channel layer 45 may comprise undoped polysilicon (p-Si). The bottom end of the lower vertical channel structure VC1 may protrude into the common source layer 25. For example, the memory layer 41, the lower channel layer 45, and the lower gap fill pattern 47 may extend into the common source layer 25, and the lower channel layer 45 may be connected to the common source layer 25. The upper portion of the lower gap fill pattern 47 may be located at a lower level than the upper portion of the memory layer 41.

[0039] The upper vertical channel structure VC2 can vertically penetrate the string select grid electrode 50 and the lower buffer insulating layer 48 to connect to the upper portion of the lower vertical channel structure VC1, and may include an insulating pad 61, an upper channel layer 65, and an upper gap fill pattern 67. The upper channel layer 65 may surround the sidewall of the upper gap fill pattern 67, and the insulating pad 61 may surround the sidewall of the upper channel layer 65. The upper vertical channel structure VC2 may include a lower portion having a first width and an upper portion having a second width, wherein the first width is greater than the second width.

[0040] An insulating pad 61 may be disposed between the upper channel layer 65 and the series select line gate electrode 50 to surround the sidewall of the upper channel layer 65. The insulating pad 61 may comprise a silicon oxide (SiO2) or a high-k dielectric layer such as hafnium oxide (HfO2). For example, the series select line gate electrode 50 may be a series select line SSL (see...). Figure 1 Furthermore, the insulating pad 61 may be the gate insulating layer of the series select line gate electrode 50.

[0041] The upper channel layer 65 may include: a first upper channel layer 65a that vertically penetrates the string select gate electrode 50; a second upper channel layer 65b that is conformally formed vertically on the inner wall of the storage layer 41 in the upper part of the lower vertical channel structure VC1; and a third upper channel layer 65c that is conformally formed horizontally on the upper surface of the lower gap filling pattern 47 of the lower vertical channel structure VC1. For example, the first upper channel layer 65a and the second upper channel layer 65b may extend vertically, and the third upper channel layer 65c may extend horizontally. The lower channel layer 45 and the second upper channel layer 65b may be vertically aligned. For example, an insulating pad 61 may surround the sidewall of the first upper channel layer 65a, such that the insulating pad 61 and the first upper channel layer 65a can be in direct contact with each other. The storage layer 41 may surround the sidewall of the second upper channel layer 65b, such that the storage layer 41 and the second upper channel layer 65b can be in direct contact with each other. The third upper channel layer 65c can be disposed between the lower gap filling pattern 47 and the upper gap filling pattern 67, such that the third upper channel layer 65c and the lower gap filling pattern 47 can be in direct contact with each other. Therefore, the lower gap filling pattern 47 and the upper gap filling pattern 67 can be separated by the third upper channel layer 65c. In an exemplary embodiment of this disclosure, the upper portion of the upper channel layer 65 (e.g., the upper portion of the first upper channel layer 65a) may include N-type impurities, such as N-doped polysilicon (p-Si). The lower portion of the first upper channel layer 65a, the second upper channel layer 65b, and the third upper channel layer 65c may include undoped polysilicon (p-Si).

[0042] Storage layer 41 may surround the outer wall of lower channel layer 45 and the outer wall of second upper channel layer 65b. Second upper channel layer 65b may extend horizontally to the lower surface of lower buffer insulation layer 48 to connect to first upper channel layer 65a. For example, second upper channel layer 65b may extend vertically on the inner wall of storage layer 41 above lower vertical channel structure VC1 and may be curved and extend on the lower surface of lower buffer insulation layer 48. Second upper channel layer 65b and / or third upper channel layer 65c may connect to lower channel layer 45. For example, upper channel layer 65 may have a decanter shape or a flaggon shape. Upper gap fill pattern 67 may be surrounded by upper channel layer 65. Upper gap fill pattern 67 may include a lower portion with a relatively wide width (or diameter) and small height, and an upper portion with a relatively narrow width (or diameter) and large height. For example, the upper portion of the upper gap fill pattern 67 may be surrounded by a first upper channel layer 65a, and the lower portion of the upper gap fill pattern 67 may be surrounded by a second upper channel layer 65b. The upper portion of the upper gap fill pattern 67 may have a third width, which is narrower than the fourth width of the lower portion of the upper gap fill pattern 67. For example, the lower portion of the upper gap fill pattern 67 may have a horizontal width (or diameter) similar to the horizontal width (or diameter) of the lower gap fill pattern 47.

[0043] Pad pattern 70 can be disposed on the upper vertical channel structure VC2. For example, pad pattern 70 can be disposed between the upper vertical channel structure VC2 and the bit line BL. Pad pattern 70 can include a lower pad pattern 71 and an upper pad pattern 72. The outer surfaces of the lower pad pattern 71, the upper pad pattern 72, and the first upper channel layer 65a can be vertically aligned. For example, the outer surfaces of the lower pad pattern 71, the upper pad pattern 72, and the first upper channel layer 65a can be vertically coplanar. The lower pad pattern 71 can include N-doped polysilicon (p-Si), and the upper pad pattern 72 can include metal silicide. The lower pad pattern 71 and the upper channel layer 65 can include the same material, such as N-doped polysilicon (p-Si). In an exemplary embodiment of this disclosure, the upper pad pattern 72 can be the upper portion of the pad pattern 70 that is a silicide. For example, the metal silicide of the upper pad pattern 72 can be formed by metal infiltration into the upper part of the preliminary pad pattern to be described, which includes N-doped polycrystalline silicon (p-Si).

[0044] Bit lines (BL) can include metals such as tungsten (W). (See reference...) Figure 1 The bit line BL can extend horizontally in the row direction. A passage plug 88 can be disposed between the bit line BL and the upper vertical channel structure VC2. The passage plug 88 can include a metal, such as tungsten (W). The passage plug 88 can be in direct contact with the upper pad pattern 72 and can have a columnar shape.

[0045] The spacer 75 may be disposed on the protrusion of the upper select line grid electrode 52 to surround the upper sidewall of the upper vertical channel structure VC2. The spacer 75 may also surround the sidewall of the pad pattern 70 and the sidewall of the access plug 88. In a top view, the spacer 75 may have an optical disc shape.

[0046] The upper insulating layer 80 may cover the string select line gate electrode 50 and the pad spacer 75, and may surround the sidewalls of the via plug 88. The upper insulating layer 80 may comprise the same material as the string select line separator pattern SSP. Therefore, the interface between the upper insulating layer 80 and the string select line separator pattern SSP is omitted. For example, in this case, there is no interface between the upper insulating layer 80 and the string select line separator pattern SSP.

[0047] The interface between the upper insulating layer 80 and the string selection line separator pattern SSP will be described with reference to other accompanying drawings.

[0048] The upper insulating layer 80 may comprise the same material as the spacer 75. Therefore, the interface between the upper insulating layer 80 and the spacer 75 is indicated by a dashed line. For example, in this case, there is no physical interface between the upper insulating layer 80 and the spacer 75.

[0049] A word line separator insulating layer 83 may be conformally formed on the sidewall of a word line separator trench that perpendicularly penetrates the cell stack CS to expose the common source layer 25. The word line separator trench will be described with reference to other figures.

[0050] The word line separator insulation layer 83 may include an insulating material, such as, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon nitride oxide (SiON), aluminum oxide (Al2O3), or other insulating materials. (See reference...) Figure 1 The word line separator insulation layer 83 may have a dam shape or wall shape that extends in the column direction along the boundary line of the word line separator structure WS.

[0051] The common source plug 85 may include a conductor surrounded by a word line separating insulation layer 83. For example, the common source plug 85 may include a low-resistance metal, such as, for example, tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), or other metals. Further reference... Figure 1 The common source plug 85 may have a dam shape or wall shape that fills the interior of the word line separator structure WS and extends in the column direction. The common source plug 85 may be electrically connected to the common source layer 25. In an exemplary embodiment of this disclosure, the common source plug 85 may extend in the column direction to separate adjacent word lines in the word lines 81; however, the common source plug 85 may be electrically insulated from the word lines 81 because the sidewalls of the common source plug 85 may be covered by the word line separator insulation layer 83.

[0052] Because the upper part of the series select grid electrode 50 and the upper part of the pad pattern 70 are formed of metal silicide to have a lower resistance than polysilicon (p-Si) and to prevent electrical bridging between adjacent components, the above references... Figure 2A The described three-dimensional storage device 100A can provide high performance while maintaining reliability.

[0053] Reference Figure 2B ,and Figure 2A Compared to the three-dimensional storage device 100A shown, a three-dimensional storage device 100B according to an exemplary embodiment of the present disclosure may not include the cover insulating layer 87 and the access plug 88. For example, in the three-dimensional storage device 100B, the cover insulating layer 87 and the access plug 88 may be omitted. The upper pad pattern 72 of the pad pattern 70 may be in direct contact with the bit line BL. The common source plug 85 may be recessed lower than the upper pad pattern 72 of the pad pattern 70. For example, the top surface of the common source plug 85 may be located at a level lower than the level of the bottom surface of the upper pad pattern 72. For example, with Figure 2A Unlike the illustrated three-dimensional memory device 100A, the three-dimensional memory device 100B may further include a plug insulating layer 86 disposed between the common source plug 85 and the bit line BL. Other undescribed components can be found in [reference needed]. Figure 2A To understand.

[0054] Reference Figure 2C ,and Figure 2A and Figure 2B Compared to the three-dimensional storage devices 100A and 100B shown, a three-dimensional storage device 100C according to an exemplary embodiment of the present disclosure may have an upper string select line gate electrode 52 having a flat upper surface. For example, the upper surface of the upper string select line gate electrode 52 of the string select line gate electrode 50 may be flat and not recessed. Other undescribed elements may be referred to Figure 2A and Figure 2B To understand.

[0055] Reference Figure 2D ,and Figure 2C Compared to the three-dimensional memory device 100C shown, the three-dimensional memory device 100D according to an embodiment of the present disclosure may further include a plug insulating layer 86. The plug insulating layer 86 may be disposed between the common source plug 85 and the bit line BL. Figure 2C Compared to the three-dimensional storage device 100C shown, the three-dimensional storage device 100D may not include the cover insulating layer 87 and the access plug 88. The upper pad pattern 72 of the pad pattern 70 can directly contact the bit line BL. The plug insulating layer 86 can be referenced. Figure 1 It extends in the column direction. Other undescribed components can be found in [reference]. Figure 2A-2C To understand.

[0056] Reference Figure 2E and Figure 2F ,and Figures 2A to 2D Compared to the three-dimensional memory devices 100A-100D shown, the three-dimensional memory devices 100E and 100F, each according to an exemplary embodiment of the present disclosure, may each include a lower buffer insulating layer 48 and an upper buffer insulating layer 49 located between the lower vertical channel structure VC1 and the serial select line gate electrode 50. The top surface of the word line separating insulating layer 83, the top surface of the common source plug 85, and the top surface of the lower buffer insulating layer 48 may be coplanar. Figure 2F In, with Figure 2E Compared to the three-dimensional storage device 100E shown, the three-dimensional storage device 100F may not have a pass-through plug 88. Other undescribed components can be found in [reference needed]. Figure 2A-2D To understand.

[0057] Reference Figures 2G to 2I ,and Figures 2A to 2FCompared to the three-dimensional memory devices 100A-100F shown, the three-dimensional memory devices 100G-100I according to an exemplary embodiment of the present disclosure may not include the logic circuit layer 11. Furthermore, the common source layer 25 can be formed directly on the substrate 10. For example, the common source layer 25 can be disposed between the substrate 10 and the cell stack CS, and as... Figures 2A-2F As shown, a logic circuit layer 11 is interposed between the common source layer 25 and the substrate 10, or as shown... Figure 2G-2I As shown, no logic circuit layer 11 is inserted between the common source layer 25 and the substrate 10. The lower channel layer 45 and the common source layer 25 of the lower vertical channel structure VC1 can be directly connected. The bottom storage layer 41x and the bottom lower channel layer 45x can be partially disposed at the bottom of the lower vertical channel structure VC1. The bottom storage layer 41x and the bottom lower channel layer 45x can protrude into the substrate 10. The storage layer 41 and the bottom storage layer 41x of the lower vertical channel structure VC1 can be separated by the common source layer 25. For example, the lower vertical channel structure VC1 may include a protrusion protruding into the substrate 10 and the bottom storage layer 41x is disposed at the protrusion. The protrusion of the lower vertical channel structure VC1 may correspond to a recessed portion of the substrate 10. (Refer to...) Figure 2G The bit line BL can be directly formed on the upper pad pattern 72. (Refer to...) Figure 2H The access plug 88 can be formed between the upper pad pattern 72 and the bit line BL. (See reference...) Figure 2I The upper selection grid electrode 52 may have a flat top surface. In an exemplary embodiment of this disclosure, Figure 2I The access plug 88 can be omitted. Other undescribed components can be found in [reference needed]. Figures 2A-2F To understand.

[0058] Similar to the three-dimensional memory device 100A described above, the three-dimensional memory devices 100B-100I described above can provide high performance and maintain reliability because the upper part of the serial select line gate electrode 50 and the upper part of the pad pattern 70 are formed of metal silicide to have a lower resistance than that of polysilicon (p-Si) and to prevent electrical bridging between adjacent components.

[0059] Figures 3 to 25 This is a diagram illustrating a method for manufacturing a three-dimensional storage device according to an exemplary embodiment of the present disclosure. Figure 3-5 and Figure 22-25 Is with Figure 1 The longitudinal section view corresponding to line I-I'. Figures 6 to 21 yes Figure 5 A magnified view of region A.

[0060] Reference Figure 3A method for manufacturing a three-dimensional memory device according to an exemplary embodiment of the present disclosure may include forming a logic circuit layer 11 on a substrate 10, forming a common source layer 25 on the logic circuit layer 11, and forming a molded stacked MS on the common source layer 25.

[0061] Substrate 10 may include a silicon (Si) wafer. In an exemplary embodiment of this disclosure, substrate 10 may include, for example, an epitaxial layer, a silicon-on-insulator (SOI) layer, or other semiconductor material layers.

[0062] The formation of logic circuit layer 11 may include forming transistor 12 and metal interconnect 17 on substrate 10, and forming a lower insulating layer 20 covering transistor 12 and metal interconnect 17. The lower insulating layer 20 may include at least one of silicon oxide (SiO2), silicon nitride (Si3N4), and combinations thereof.

[0063] The formation of the common source layer 25 may include performing a deposition process to form N-doped polycrystalline silicon (p-Si) containing N-type impurities such as, for example, phosphorus (P) or arsenic (As).

[0064] The formation of a molded stacked MS may include alternately stacking multiple molded layers 31 and multiple sacrificial layers 32 by performing a deposition process. The molded layers 31 may include an insulator such as silicon oxide (SiO2). The sacrificial layers 32 may include a material that has etch selectivity relative to the material of the common source layer 25 and the molded layers 31. For example, the sacrificial layers 32 may include one of, for example, silicon nitride (Si3N4), silicon oxide nitride (SiON), silicon carbide (SiC), silicon germanium (SiGe), and other insulators.

[0065] Reference Figure 4 The method may include forming a lower vertical channel structure VC1 that vertically penetrates the molded stack MS to connect to a common source layer 25. Forming the lower vertical channel structure VC1 may include forming a lower vertical channel via that vertically penetrates the molded stack MS to expose the common source layer 25, and forming a storage layer 41, a lower channel layer 45, and a lower gap fill pattern 47 in the lower vertical channel via.

[0066] The formation of the memory layer 41 may include conformally forming a memory material layer to a predetermined thickness on the inner and bottom surfaces of the lower vertical channel via, and performing an etch-back process to partially remove the memory material layer on the bottom surface of the lower vertical channel via. The memory layer 41 may be formed on the bottom surface and sidewalls of the lower vertical channel via in a shape having an opening at its central lower surface. For example, the central portion of the memory layer 41 on the bottom surface of the lower vertical channel via may be removed.

[0067] The formation of the lower channel layer 45 may include conformally forming a channel material layer to a predetermined thickness on the inner surface of the memory layer 41 to partially fill the lower vertical channel via, and performing an etch-back process to partially remove the channel material layer on the bottom surface of the lower vertical channel via. The lower channel layer 45 may include an intrinsic semiconductor material. For example, the lower channel layer 45 may include undoped polysilicon (p-Si). The lower channel layer 45 may be in direct contact with the common source layer 25.

[0068] Forming the lower gap fill pattern 47 may include forming a lower gap fill insulator on the inner surface of the lower channel layer 45 to adequately fill the remaining portion of the lower vertical channel via, and performing a planarization process such as chemical mechanical polishing (CMP). For example, the lower gap fill pattern 47 may include silicon oxide (SiO2). The upper surface of the molded stacked MS and the upper surface of the lower vertical channel structure VC1 may be coplanar.

[0069] Reference Figure 5 The method may include forming a lower buffer insulating layer 48 on a molded stack MS and a lower vertical channel structure VC1, and forming an initial series select line gate electrode 50p on the lower buffer insulating layer 48. The formation of the lower buffer insulating layer 48 may include performing a deposition process to completely form a silicon oxide (SiO2) layer to completely cover the molded stack MS and the lower vertical channel structure VC1. The formation of the initial series select line gate electrode 50p may include forming a series select line gate material layer on the lower buffer insulating layer 48, and forming a series select line separation trench SST to separate the series select line gate material layer. The series select line separation trench SST may be arranged between the lower vertical channel structures VC1 to reference... Figure 1 The top view has a wavy or zigzag shape.

[0070] Reference Figure 6 The method may include forming a sacrificial buffer insulating layer 55 on the initial string select line gate electrode 50p and forming a mask pattern 56 on the sacrificial buffer insulating layer 55. The sacrificial buffer insulating layer 55 may include silicon oxide (SiO2), and the mask pattern 56 may include silicon nitride (Si3N4) to have etch selectivity relative to the silicon oxide (SiO2) of the sacrificial buffer insulating layer 55. The sacrificial buffer insulating layer 55 filling the string select line separation trench SST may be formed as a string select line separation pattern SSP.

[0071] Storage layer 41 may include a barrier layer 42, a charge trap layer 43, and a tunnel insulating layer 44. For example, the barrier layer 42 and the tunnel insulating layer 44 may include silicon oxide (SiO2), and the charge trap layer 43 may include silicon nitride (Si3N4) or a high-dielectric metal oxide. For example, the barrier layer 42, the charge trap layer 43, and the tunnel insulating layer 44 may be sequentially formed on the inner side surface of the lower vertical channel via and on a portion of the bottom surface of the lower vertical channel via in the recessed portion of the common source layer 25.

[0072] Reference Figure 7 The method may include forming an upper vertical channel hole H that is perpendicularly aligned with the lower vertical channel structure VC1. For example, the upper vertical channel hole H and the lower vertical channel structure VC1 may overlap and be arranged concentrically. The lower end of the upper vertical channel hole H may partially recess the upper part of the lower gap filling pattern 47, thereby exposing the lower gap filling pattern 47 of the lower vertical channel structure VC1.

[0073] Reference Figure 8 The method may include forming an insulating pad 61 and a sacrificial pad 62 on the inner surface of the upper vertical channel hole H. The insulating pad 61 and the sacrificial pad 62 may be conformally formed to have a thickness that does not completely fill the upper vertical channel hole H by performing a deposition process. An etch-back process may be performed to partially remove the insulating pad 61 and the sacrificial pad 62 on the bottom surface of the upper vertical channel hole H. The insulating pad 61 and the sacrificial pad 62 may have a cylindrical shape or a straw shape. For example, in a top view, the upper vertical channel hole H may have a circular shape, and the insulating pad 61 and the sacrificial pad 62 may each have an optical disc shape. The insulating pad 61 may include silicon oxide (SiO2), and the sacrificial pad 62 may include polycrystalline silicon (p-Si). Therefore, the sacrificial pad 62 may have etch selectivity relative to the insulating pad 61. The insulating pad 61 and the sacrificial pad 62 may extend along the sidewalls of the upper vertical channel hole H into the lower vertical channel structure VC1. The bottom end of the sacrificial pad 62 may not contact the lower gap fill pattern 47. For example, a portion of the insulating pad 61 may be formed between the bottom end of the sacrificial pad 62 and the lower gap fill pattern 47. The insulating pad 61, the sacrificial buffer insulation layer 55, the lower buffer insulation layer 48, and the lower gap fill pattern 47 may comprise the same material. For example, the interfaces between the insulating pad 61 and the sacrificial buffer insulation layer 55, the insulating pad 61 and the lower buffer insulation layer 48, and the insulating pad 61 and the lower gap fill pattern 47 may disappear. For example, in this case, no clear interface may be observed between any two adjacent elements in contact with each other among the insulating pad 61, the sacrificial buffer insulation layer 55, the lower buffer insulation layer 48, and the lower gap fill pattern 47.

[0074] Reference Figure 9The method may include performing a wet etching process to recess the upper portion of the insulating pad 61 and remove the upper portion of the lower gap fill pattern 47 of the lower vertical channel structure VC1. The insulating pad 61 and the lower gap fill pattern 47 may be formed of the same material and thus can be removed by the same wet etching process. During this process, the lower portion of the insulating pad 61 may also be removed. Therefore, an annular recess Ra surrounding the upper portion of the sacrificial pad 62 may be formed between the sacrificial pad 62 and the mask pattern 56, and a vacancy Va may be formed in the upper portion of the lower vertical channel structure VC1. The upper and lower portions of the sacrificial pad 62 may protrude upward and downward, respectively, by removing the insulating pad 61 from its sidewalls. The lower surface of the vacancy Va may be located at the mid-level of the second uppermost molded layer 31b between the uppermost sacrificial layer 32a and the second uppermost sacrificial layer 32b. The upper surface of the vacancy Va may be located at the same level as the upper surface of the uppermost molded layer 31a. Vacancies can also expose the lower channel layer 45 of the lower vertical channel structure VC1.

[0075] Reference Figure 10 The method may include performing a wet etching process to remove the sacrificial pad 62 in the upper vertical channel hole H and the lower channel layer 45 exposed in the vacancy Va. The sacrificial pad 62 and the lower channel layer 45 may be formed of the same material and therefore can be removed by the same wet etching process. The tunnel insulation layer 44 of the storage layer 41 may be partially exposed on the sidewalls of the vacancy Va. The top of the lower channel layer 45 and the upper surface of the lower gap fill pattern 47 may be exposed on the lower surface of the vacancy Va. For example, the insulating pad 61 may remain only on the inner surface of the upper vertical channel hole H.

[0076] Reference Figure 11 The method may include conformally forming an upper channel layer 65 in the upper vertical channel via H and the vacancy Va. The upper channel layer 65 may include undoped polysilicon (p-Si). For example, the upper channel layer 65 and the lower channel layer 45 may be formed of the same material. The upper channel layer 65 may include: a first upper channel layer 65a formed on an insulating pad 61 in the upper vertical channel via H; a second upper channel layer 65b formed on the sidewall of the tunnel insulating layer 44 exposed in the vacancy Va; and a third upper channel layer 65c formed on the upper surface of the lower gap fill pattern 47. For example, in the vacancy Va, the upper channel layer 65 may be formed on the exposed surface of the tunnel insulating layer 44, the exposed upper surface of the lower gap fill pattern 47, the exposed top end of the lower channel layer 45, the exposed lower surface of the lower buffer insulating layer 48, and the exposed bottom end of the insulating pad 61. The upper channel layer 65 can be formed on the top of the insulating pad 61 and on the exposed sidewalls and exposed upper surface of the mask pattern 56. Therefore, the lower channel layer 45 and the upper channel layer 65 can be electrically and physically connected to each other.

[0077] Reference Figure 12 The method may include forming an upper gap-fill pattern 67 in a vacancy Va and an upper vertical channel via H. The upper gap-fill pattern 67 may fill the vacancy Va to cover the surface of the upper channel layer 65 in the vacancy Va. The lower portion of the upper gap-fill pattern 67 formed in the vacancy Va may have a width greater than the upper portion of the upper gap-fill pattern 67 formed in the upper vertical channel via H. In an exemplary embodiment of this disclosure, a gap Vb may be formed in the vacancy Va. For example, a gap Vb may be formed in the lower portion of the upper gap-fill pattern 67. The upper gap-fill pattern 67 may include silicon oxide (SiO2).

[0078] Reference Figure 13 The method may include performing an etch-back process to partially remove the upper portion of the upper gap fill pattern 67, thereby forming a recess Rb in the upper vertical channel hole H. The lower surface of the recess Rb may be positioned at the middle level of the sacrificial buffer insulating layer 55. The upper channel layer 65 may be partially exposed on the sidewalls of the recess Rb.

[0079] Reference Figure 14 The method may include forming a pad material layer 70a in a recess Rb by performing a deposition process. The pad material layer 70a may include N-doped polysilicon (p-Si). Because the pad material layer 70a and the upper channel layer 65 are in contact with and connected to each other, N-type impurities in the pad material layer 70a may diffuse outwards into the upper channel layer 65, which may include undoped polysilicon (p-Si). The diffusion distance of the N-type impurities may be located at a level higher than the intermediate level of the initial string select gate electrode 50p. For example, the initial string select gate electrode 50p and the upper channel layer 65 including the diffused N-type impurities may horizontally overlap each other.

[0080] Reference Figure 15 The method may include forming a preliminary pad pattern 70p by performing a planarization process such as CMP. During the CMP process, the mask pattern 56, the material on the top surface of the mask pattern 56, and the material in the upper portion of the upper vertical channel hole H may be removed. The upper surface of the preliminary pad pattern 70p, the top of the insulating liner 61, and the upper surface of the sacrificial buffer insulation layer 55 may be coplanar.

[0081] Reference Figure 16 The method may include, for example, removing the upper portion of the insulating pad 61 and the sacrificial buffer insulating layer 55 by performing an etch-back process. After removing the upper portion of the insulating pad 61 and the sacrificial buffer insulating layer 55, the surface of the preliminary pad pattern 70p, the upper sidewall of the upper channel layer 65, the top of the remaining insulating pad 61, the upper surface of the preliminary string select line gate electrode 50p, and the upper surface of the string select line separator pattern SSP may be exposed.

[0082] Reference Figure 17 The method may include fully forming a spacer material layer 75a by performing a deposition process. For example, the spacer material layer 75a may be conformally formed on all exposed surfaces, such as the surface of the initial pad pattern 70p, the upper sidewall of the upper channel layer 65, the top of the insulating pad 61, the upper surface of the initial string select line gate electrode 50p, and the upper surface of the string select line separator pattern SSP. The spacer material layer 75a may include silicon oxide (SiO2).

[0083] Reference Figure 18 The method may include forming a spacer 75 by performing an etch-back process. The spacer 75 may be formed around the sidewalls of the initial pad pattern 70p and the upper sidewalls of the upper channel layer 65, and formed on the portion of the upper surface of the initial string select gate electrode 50p adjacent to the insulating pad 61.

[0084] Reference Figure 19 The method may include performing an etching process using a spacer 75 as an etching mask to recess the upper surface of the preliminary pad pattern 70p and the upper surface of the preliminary string select line gate electrode 50p. For example, the top surface of the preliminary string select line gate electrode 50p may be partially recessed, such that the preliminary string select line gate electrode 50p may include protruding and recessed portions. The upper portion of the string select line separator pattern SSP may protrude upward from the recessed upper surface of the preliminary string select line gate electrode 50p.

[0085] Reference Figure 20The method may include forming a pad pattern 70 and a string select gate electrode 50 by performing a process that becomes silicide. The pad pattern 70, including a lower pad pattern 71 and an upper pad pattern 72, may be formed by silicideing the upper portion of a preliminary pad pattern 70p, and the string select gate electrode 50, including a lower string select gate electrode 51 and an upper string select gate electrode 52, may be formed by silicideing the exposed upper portion of the preliminary string select gate electrode 50p. Because the upper string select gate electrode 52 is formed in the upper portion of the preliminary string select gate electrode 50p, the upper string select gate electrode 52 may include protruding portions and recessed portions. The protruding portion of the upper string select gate electrode 52 may surround the sidewall of the upper vertical channel structure VC2. The lower pad pattern 71 and the lower string select gate electrode 51 may include N-doped polysilicon (p-Si), and the upper pad pattern 72 and the upper string select gate electrode 52 may include metal silicide. For example, the upper pad pattern 72 and the upper string select line gate electrode 52 may include at least one of nickel silicide (NiSi), titanium silicide (TiSi), cobalt silicide (CoSi), tungsten silicide (WSi), and other metal silicides. In an exemplary embodiment of this disclosure, the upper pad pattern 72 and the upper string select line gate electrode 52 may include nickel silicide (NiSi). Nickel silicide (NiSi) is formed by the infiltration of nickel (Ni) atoms into silicon (Si), so that the volume of the polycrystalline silicon (p-Si) pattern does not increase. Therefore, structural instability and bridging phenomena of the upper pad pattern 72 and the upper string select line gate electrode 52 due to volume expansion can be prevented. Furthermore, because the upper surface of the preliminary pad pattern 70p and the upper surface of the preliminary string select line gate electrode 50p are recessed and a process to form silicide is performed on the upper part of the preliminary pad pattern 70p and the upper part of the preliminary string select line gate electrode 50p, the volume expansion of the metal silicide can be limited to allow only upward expansion, and lateral expansion that would narrow the gap between adjacent elements (e.g., adjacent upper string select line gate electrodes 52) and form a bridge can be avoided.

[0086] Reference Figure 21 The method may include forming an upper insulating layer 80 by performing a deposition process. The upper insulating layer 80 and the spacer 75 may comprise the same material. Therefore, the interface between the upper insulating layer 80 and the spacer 75 may be absent. For example, there may be no interface between the upper insulating layer 80 and the spacer 75. The upper insulating layer 80 and the string select line separator pattern SSP may comprise the same material. Therefore, the interface between the upper insulating layer 80 and the string select line separator pattern SSP may be absent. For example, there may be no interface between the upper insulating layer 80 and the string select line separator pattern SSP.

[0087] Reference Figure 22The method may include forming word line separator trenches (WSTs). In one exemplary embodiment of this disclosure, the word line separator trenches (WSTs) may be formed in the column direction between a plurality of vertical channel structures VC1 and VC2 (see [link to documentation]). Figure 1 Extending upwards, multiple word line separating grooves (WSTs) can be formed and spaced apart from each other in the line direction. For example, see reference... Figure 1 and Figure 22 Four vertical channel structures VC1 and VC2, aligned on the same line in the row direction, can be located between two adjacent word line separator trenches (WSTs). Formation of the word line separator trenches (WSTs) may include performing an etching process to vertically penetrate the upper insulating layer 80, the lower buffer insulating layer 48, and the molded stacked MS to expose the common source layer 25. Although not explicitly stated... Figure 22 As shown in the figure, but in an exemplary embodiment of this disclosure, the gap Vb can be like Figure 21 It is formed in the lower part of the upper gap filling pattern 67, as shown in the middle.

[0088] Reference Figure 23 The method may include removing the sacrificial layer 32 and forming word lines 81. Removing the sacrificial layer 32 may include performing a wet etching process to remove the sacrificial layer 32 through word line separation trenches (WST). Forming the word lines 81 may include forming a barrier material layer and an electrode material layer in the space where the sacrificial layer 32 has been removed, and performing a back etching process. The barrier material layer may include: a barrier insulating material, such as, for example, aluminum oxide (Al2O3), hafnium oxide (HfO2), etc.; and a conductive barrier material, such as, for example, titanium nitride (TiN), tantalum nitride (TaN), etc. The electrode material layer may include metals, such as, for example, tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), etc.

[0089] Reference Figure 24 The method may include forming a word line separator insulating layer 83 on the inner sidewall of a word line separator trench WST, and forming a common source plug 85 on the inner sidewall of the word line separator insulating layer 83 to fill the remaining portion of the word line separator trench WST. The common source plug 85 may have a dam shape. The method may also include planarizing the top surface of the word line separator insulating layer 83, the top surface of the common source plug 85, and the top surface of the upper insulating layer 80 by performing a planarization process such as CMP. The common source plug 85 may be electrically connected to the common source layer 25, but electrically insulated from the word line 81, because the sidewall of the common source plug 85 may be covered by the word line separator insulating layer 83.

[0090] Reference Figure 25The method may include forming a cap insulating layer 87 on the upper insulating layer 80 and forming a via plug 88. The cap insulating layer 87 may include at least one of silicon oxide (SiO2), silicon nitride (Si3N4), silicon nitride oxide (SiON), and other insulators. Forming the via plug 88 may include forming a via hole that perpendicularly penetrates the cap insulating layer 87 and the upper insulating layer 80 to expose the top surface of the upper pad pattern 72, and filling the interior of the via hole with a conductive material. For example, the via plug 88 may include a metal, such as tungsten (W).

[0091] Subsequently, referring to Figure 2A The method may include forming a bit line BL on the cover insulation layer 87 that is connected to the access plug 88.

[0092] Figure 26 and Figure 27 A method for manufacturing a three-dimensional storage device according to an exemplary embodiment of the present disclosure is shown. Figure 26 and Figure 27 Is with Figure 1 The longitudinal section view corresponding to line I-I'.

[0093] Reference Figure 26 A method for manufacturing a three-dimensional storage device according to an exemplary embodiment of the present disclosure may include performing a reference... Figures 3 to 24 The described process also includes performing an etch-back process to recess the top surface of the common source plug 85, thereby forming a recessed space Rc. The recessed top surface of the common source plug 85 may be located at a level sufficiently lower than the top surface of the upper pad pattern 72.

[0094] Reference Figure 27 The method may include filling a plug insulator into a recessed space Rc, and performing a planarization process such as CMP to expose the top surface of the upper pad pattern 72 and form a plug insulator layer 86. Subsequently, refer to... Figure 2B The method may include forming bit lines BL on the upper insulating layer 80 that are in direct contact with the upper pad pattern 72.

[0095] Figure 28 This is a diagram illustrating a method for manufacturing a three-dimensional storage device according to an exemplary embodiment of the present disclosure. Figure 28 Is with Figure 5 The magnified view corresponding to region A.

[0096] Reference Figure 28 A method for manufacturing a three-dimensional storage device according to an exemplary embodiment of the present disclosure may include performing a reference... Figures 3 to 18The described process also includes performing a silicide process to form a pad pattern 70 and a string select gate electrode 50. The top surfaces of the pad pattern 70 and the string select gate electrode 50 may not be recessed. Because the silicide process is performed on the upper portion of the initial string select gate electrode 50p, the volume expansion of the metal silicide can be limited to allow only upward expansion, and lateral expansion that would narrow the spacing between adjacent components (e.g., adjacent upper string select gate electrodes 52) and form a bridge can be avoided. Subsequently, the method may include performing a reference process. Figures 21 to 25 The described process and reference Figure 2C A bit line BL is formed on the cover insulation layer 87 to connect to the access plug 88.

[0097] In one exemplary embodiment of this disclosure, the method may include performing a reference Figure 21-24 and Figure 26-27 The described process and reference Figure 2D A bit line BL is formed on the upper insulating layer 80 that is in direct contact with the upper pad pattern 72.

[0098] Figure 29 and Figure 30 This is a diagram illustrating a method for forming a three-dimensional storage device according to an exemplary embodiment of the present disclosure. Figure 29 and Figure 30 Is with Figure 1 The longitudinal section view corresponding to line I-I'.

[0099] Reference Figure 29 A method for manufacturing a three-dimensional storage device according to an exemplary embodiment of the present disclosure may include performing a reference... Figure 3 and Figure 4 The described process involves forming a lower buffer insulation layer 48 on the lower vertical channel structure VC1 and the molded stack MS, and forming word line separation trenches WST.

[0100] Reference Figure 30 This method may include executing a reference Figure 23 The described process is used to form word lines 81 and references. Figure 24 The described process involves forming a word line separator insulating layer 83 and a common source plug 85, as well as forming an upper buffer insulating layer 49. The upper buffer insulating layer 49 may include at least one of, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxide nitride (SiON), and other insulators. In an exemplary embodiment of this disclosure, the upper buffer insulating layer 49 may include the same material as the lower buffer insulating layer 48.

[0101] Subsequently, the method may include executing a reference. Figures 5 to 21 The described process and reference Figure 2EForming the access plug 88 and bit line BL.

[0102] In one exemplary embodiment of this disclosure, the method may include performing a reference Figures 5 to 21 Described process and reference Figure 27 The described process (e.g.) Figure 27 CMP process), and reference Figure 2F A bit line BL is formed on the upper insulating layer 80 that is in direct contact with the upper pad pattern 72.

[0103] Figures 31 to 37 This is a view illustrating a method for forming a three-dimensional storage device according to an exemplary embodiment of the present disclosure. Figures 31 to 37 Is with Figure 1 The longitudinal section view corresponding to line I-I'.

[0104] Reference Figure 31 A method for forming a three-dimensional memory device according to an exemplary embodiment of the present disclosure may include forming a sacrificial source insulating layer 21 on a substrate 10 and forming a first preliminary common source layer 25p1 on the sacrificial source insulating layer 21. The sacrificial source insulating layer 21 may include a lower sacrificial source insulating layer 22, an intermediate sacrificial source insulating layer 23, and an upper sacrificial source insulating layer 24. For example, the lower sacrificial source insulating layer 22 and the upper sacrificial source insulating layer 24 may include silicon oxide (SiO2), and the intermediate sacrificial source insulating layer 23 may include silicon nitride (Si3N4). The molded stacked MS may include a molding layer 31 and a sacrificial layer 32. As described above, the molding layer 31 may include silicon oxide (SiO2), and the sacrificial layer 32 may include silicon nitride (Si3N4). The first preliminary common source layer 25p1 may include undoped polysilicon (p-Si) or N-doped polysilicon (p-Si).

[0105] Reference Figure 32The method may include: forming a lower vertical channel structure VC1 that vertically penetrates a molded stack MS, a first preliminary common source layer 25p1, and a sacrificial source insulating layer 21 to connect to a substrate 10; and forming a lower buffer insulating layer 48 on the lower vertical channel structure VC1 and the molded stack MS. The formation of the lower vertical channel structure VC1 may include forming a lower vertical channel via that vertically penetrates the molded stack MS, the first preliminary common source layer 25p1, and the sacrificial source insulating layer 21 to expose the substrate 10, and forming a storage layer 41, a lower channel layer 45, and a lower gap fill pattern 47 in the lower vertical channel via. The lower buffer insulating layer 48 may include at least one of, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxide nitride (SiON), silicon carbide (SiC), silicon germanium (SiGe), polycrystalline silicon (p-Si), photoresist, and various other insulating materials. In one exemplary embodiment of this disclosure, the lower buffer insulating layer 48 may include both a silicon oxide (SiO2) layer and a silicon nitride (Si3N4) layer.

[0106] Reference Figure 33 The method may include forming a word line separator trench (WST) and forming a sacrificial spacer 82 on the inner sidewall of the word line separator trench (WST). Forming the word line separator trench (WST) may include performing an etching process to vertically penetrate the lower buffer insulating layer 48, the molded stack MS, the first preliminary common source layer 25p1, and the upper sacrificial source insulating layer 24, such that the word line separator trench (WST) can expose the intermediate sacrificial source insulating layer 23 of the sacrificial source insulating layer 21.

[0107] Reference Figure 34 This method may include completely removing the sacrificial source insulating layer 21 via a word line separating trench (WST) to form an empty space Vc. During this process, the memory layer 41 of the lower vertical channel structure VC1 may be partially removed. For example, an undercut UC may be formed. The bottom end of the memory layer 41 and the bottom end of the lower channel layer 45 may be retained as a bottom memory layer 41x and a bottom lower channel layer 45x at a location below the top surface of the substrate 10.

[0108] Reference Figure 35 The method may include forming polysilicon (p-Si) in the empty space Vc in which the sacrificial source insulating layer 21 has been removed and in the word line separator trench WST to form a second preliminary common source layer 25p2. The polysilicon (p-Si) may include N-doped polysilicon (p-Si). Therefore, the second preliminary common source layer 25p2 may cover the sacrificial spacer 82. For example, the second preliminary common source layer 25p2 may have an "L" shape. The second preliminary common source layer 25p2 and the lower channel layer 45 of the lower vertical channel structure VC1 may be connected to each other. The polysilicon (p-Si) may fill a large portion of the word line separator trench WST.

[0109] Reference Figure 36 The method may include removing polysilicon (p-Si) and sacrificial spacers 82 from the word line separator trench (WST) to form a common source layer 25. A molded stack of silicon (MS) may be exposed on the sidewalls of the word line separator trench (WST). The top surface of the common source layer 25 may be exposed on the bottom surface of the word line separator trench (WST).

[0110] Reference Figure 37 The method may include removing the sacrificial layer 32 through a word line separating trench (WST), forming word lines 81 in the space where the sacrificial layer 32 has been removed, forming a word line separating insulating layer 83 and a common source plug 85 in the word line separating trench (WST), and forming an upper buffer insulating layer 49 on the top surface of the lower buffer insulating layer 48, the top surface of the word line separating insulating layer 83, and the top surface of the common source plug 85. The method may further include planarizing the top surfaces of the lower buffer insulating layer 48, the word line separating insulating layer 83, and the common source plug 85 to be coplanar. The upper buffer insulating layer 49 may include silicon oxide (SiO2).

[0111] Subsequently, the method may include executing a reference. Figures 5 to 21 Described process and reference Figure 27 The described process (e.g.) Figure 27 CMP process), and reference Figure 2G The bit line BL is formed.

[0112] In one exemplary embodiment of this disclosure, the method may include performing a reference Figures 5 to 21 The described process and reference Figure 2H Forming the access plug 88 and bit line BL.

[0113] In one exemplary embodiment of this disclosure, the method may include performing a reference Figures 5 to 18 , Figures 20 to 21 The described process and reference Figure 2I This forms the path plug 88 and bit line BL. Referencing is optional. Figure 19 This involves recessing the upper surface of the initial pad pattern 70p and the upper surface of the initial string selection grid electrode 50p. (See reference...) Figure 28 Clearly understand the reference Figure 20 The process of forming the pad pattern 70 and the string select line gate electrode 50 into a silicide is performed. For example, the top surface of the pad pattern 70 and the top surface of the string select line gate electrode 50 can be as follows: Figure 28 The area shown is not recessed.

[0114] The serial select line gate electrode of the three-dimensional memory device according to an exemplary embodiment of the present disclosure includes a silicide layer, and therefore has lower resistance.

[0115] The pad pattern of the three-dimensional storage device according to an exemplary embodiment of the present disclosure includes a silicide layer, and therefore has lower resistance.

[0116] Because the serial select line gate electrodes of the three-dimensional storage device according to an exemplary embodiment of the present disclosure are formed in a recessed state, electrical bridging between adjacent components is prevented.

[0117] Although this disclosure has been described in conjunction with some specific exemplary embodiments illustrated in the accompanying drawings, those skilled in the art will understand that various changes and modifications may be made to the exemplary embodiments without departing from the spirit and scope of this disclosure as defined in the appended claims.

[0118] This application claims priority to Korean Patent Application No. 10-2019-0117285, filed on September 24, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A three-dimensional storage device, comprising: Substrate; Unit stacks disposed on the substrate; Serial selection line grid electrodes disposed on the cell stack; Vertically penetrates the lower vertical channel structure of the unit stack; An upper vertical channel structure that vertically penetrates the string select line gate electrode and connects to the lower vertical channel structure; and Bit lines are set on the upper vertical channel structure. The string select line gate electrode includes a lower string select line gate electrode and an upper string select line gate electrode formed on the upper surface of the lower string select line gate electrode. The lower string select gate electrode comprises N-doped polycrystalline silicon, and The upper selection line gate electrode includes silicide. The upper select line gate electrode is in direct contact with the lower select line gate electrode.

2. The three-dimensional storage device according to claim 1, wherein... The lower vertical channel structure includes: Lower gap fill pattern; The lower channel layer surrounding the sidewalls of the lower gap filling pattern; as well as Storage layer surrounding the sidewalls of the lower channel layer, The upper vertical channel structure includes: Upper gap fill pattern; The upper channel layer surrounding the sidewalls of the upper gap-filling pattern; and Insulating pads surrounding the sidewalls of the upper channel layer, and The upper vertical channel structure includes a lower portion having a first width and an upper portion having a second width, wherein the first width is greater than the second width.

3. The three-dimensional storage device according to claim 2, wherein the upper channel layer comprises: The first upper channel layer in contact with the insulating pad; A second upper channel layer that contacts the storage layer of the lower vertical channel structure; as well as The third upper channel layer that contacts the lower gap filling pattern of the lower vertical channel structure.

4. The three-dimensional storage device according to claim 3, wherein... The first upper channel layer and the second upper channel layer extend vertically, and The third upper channel layer extends horizontally.

5. The three-dimensional storage device of claim 4, wherein the lower channel layer and the second upper channel layer are vertically aligned.

6. The three-dimensional storage device according to claim 3, wherein the upper gap filling pattern comprises: The upper part surrounded by the first upper channel layer; as well as The lower part surrounded by the second upper channel layer, The upper portion of the upper gap filling pattern has a third width, which is narrower than the fourth width of the lower portion of the upper gap filling pattern.

7. The three-dimensional storage device according to claim 6, further comprising a void formed in the lower portion of the upper gap-filling pattern.

8. The three-dimensional storage device according to claim 3, wherein the third upper channel layer is disposed between the lower gap filling pattern and the upper gap filling pattern.

9. The three-dimensional storage device of claim 1, wherein the upper serial select line gate electrode comprises: The protruding portion adjacent to the upper vertical channel structure; as well as The recessed portion spaced apart from the upper vertical channel structure, The protruding portion has a disc shape in the top view.

10. The three-dimensional storage device according to claim 3, further comprising a pad pattern disposed between the upper vertical channel structure and the bit line. The pad pattern includes a lower pad pattern containing N-doped polycrystalline silicon and an upper pad pattern containing silicide.

11. The three-dimensional storage device of claim 10, wherein the bit line is in direct contact with the upper pad pattern.

12. The three-dimensional storage device of claim 10, wherein the outer surface of the pad pattern and the outer surface of the first upper channel layer are perpendicularly aligned.

13. The three-dimensional storage device of claim 1 further includes a string select line separator pattern that contacts the sidewall of the lower string select line gate electrode and the sidewall of the upper string select line gate electrode.

14. The three-dimensional memory device of claim 1, further comprising a common source layer disposed between the substrate and the cell stack. The common source layer comprises N-doped polycrystalline silicon.

15. The three-dimensional memory device of claim 14, further comprising a logic circuit layer disposed between the substrate and the common source layer. The logic circuit layer includes transistors, metal interconnects, and a lower insulating layer covering the transistors and the metal interconnects.

16. The three-dimensional storage device of claim 14, wherein the common source layer is connected to the substrate.

17. The three-dimensional storage device according to claim 1, wherein... The lower vertical channel structure includes a protrusion that extends into the substrate. The lower vertical channel structure also includes a bottom storage layer disposed at the protruding portion, and The bottom storage layer is separate from the storage layer.

18. A three-dimensional storage device, comprising: Substrate; A common source layer disposed on the substrate; The cell stack is disposed on the common source layer; Serial selection line grid electrodes disposed on the cell stack; A lower vertical channel structure that vertically penetrates the cell stack and connects to the common source layer; An upper vertical channel structure that vertically penetrates the string select line gate electrode and connects to the lower vertical channel structure; Pad pattern disposed on the upper vertical channel structure; as well as Bit lines are set on the pad pattern. The pad pattern includes a lower pad pattern and an upper pad pattern formed on the lower pad pattern. The underlying pad pattern comprises N-doped polycrystalline silicon, and The upper pad pattern includes silicon compounds.

19. The three-dimensional storage device according to claim 18, wherein The string select line gate electrode includes a lower string select line gate electrode and an upper string select line gate electrode formed on the lower string select line gate electrode. The lower string select gate electrode comprises N-doped polycrystalline silicon, and The upper selection line gate electrode comprises silicide.

20. A three-dimensional storage device, comprising: Substrate; A logic circuit layer disposed on the substrate, the logic circuit layer including transistors, metal interconnects, and a lower insulating layer covering the transistors and the metal interconnects; A common source layer is disposed on the logic circuit layer; The cell stack is disposed on the common source layer; A lower vertical channel structure that vertically penetrates the cell stack and connects to the common source layer; A series-selective grid electrode is disposed on the cell stack and the lower vertical channel structure; An upper vertical channel structure that vertically penetrates the string select line gate electrode and connects to the lower vertical channel structure; Pad pattern disposed on the upper vertical channel structure; as well as Bit lines are set on the pad pattern. The pad pattern includes a lower pad pattern and an upper pad pattern formed on the lower pad pattern. The string select line gate electrode includes a lower string select line gate electrode and an upper string select line gate electrode formed on the lower string select line gate electrode. The lower pad pattern and the lower string select gate electrode comprise N-doped polysilicon, and The upper pad pattern and the upper string select grid electrode comprise silicide.

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