High-voltage DMOS transistor

Abstract

An improved structure of a lateral n-channel LDMOS transistor is provided to avoid gate-oxide breakdown that occurs during transistor operation. The LDMOS transistor includes a dielectric isolation structure that physically isolates a region including a parasitic NPN transistor from a region that generates a hole current due to weak impact ionization (i.e., the extended drain region of the LDMOS transistor). According to an embodiment of the present disclosure, this can be achieved using a vertical trench between the two regions. Further embodiments are also proposed to reduce the gain of the parasitic NPN transistor and reduce the back-gate resistance in order to further improve the robustness of the LDMOS transistor.

Description

Technical Field

[0001] The present disclosure relates to an n-channel LDMOS transistor having an improved structure to improve the robustness of the transistor during its operation. In particular, the present invention relates to an n-channel LDMOS transistor having an improved structure to completely avoid or at least reduce the occurrence of gate oxide breakdown during the operation of the transistor. Background Art

[0002] High-voltage integrated circuits or HVICs are mainly used in power conversion applications. Lateral double-diffused MOS transistors or LDMOSs are common components of HVICs. The inventors have recognized that gate-oxide breakdown can occur in n-channel LDMOS devices during device operation and can lead to the ultimate failure of the device. This type of breakdown is different from gate oxide breakdown, which is a manufacturing defect, because the former occurs during device operation. Therefore, an improved, robust device structure is needed to address the problem of gate oxide breakdown during the operation of n-channel LDMOS devices. Summary of the Invention

[0003] An improved structure of a lateral n-channel LDMOS transistor is provided to avoid gate-oxide breakdown occurring during transistor operation. The LDMOS transistor includes a dielectric isolation structure that physically isolates a region including a parasitic NPN transistor from a region that generates a hole current due to weak impact ionization (i.e., the extended drain region of the LDMOS transistor). According to an embodiment of the present disclosure, this can be achieved using a vertical trench between the two regions. Further embodiments are also proposed to reduce the gain of the parasitic NPN transistor and reduce the back-gate resistance in order to further improve the robustness of the LDMOS transistor.

[0004] According to a first aspect of the present disclosure, there is provided an LDMOS transistor, comprising: a drain; a gate; a source; and a back-gate; wherein the LDMOS transistor further includes an isolation structure configured to physically isolate a first region including the drain of the LDMOS transistor from a second region that has a parasitic bipolar junction transistor in use.

[0005] According to a second aspect of the present disclosure, a lateral n-channel LDMOS transistor is provided, comprising: a drain; a gate; a source; and a back gate; wherein the LDMOS transistor further comprises: a field oxide region extending laterally between the drain and the gate; a gate oxide region extending laterally between an edge of the field oxide region and the source; a p-doped region configured to reduce the gain of a parasitic bipolar transistor in use, the p-doped region being embedded in a p-well region below the source and the back gate, wherein the p-doped region comprises: a buried p-doped layer isolated from the source and the back gate by a remaining portion of the p-well region, and wherein an edge of the buried p-doped layer is configured to be aligned with an edge of the gate near a transition between the field oxide region and the gate oxide region.

[0006] According to a third aspect of the present disclosure, a lateral n-channel LDMOS transistor is provided, comprising: a first region configured to act as a virtual JFET in use; a second region configured to act as a virtual MOSFET in use, wherein the first region generates a first current due to weak impact ionization during use, wherein the second region generates a second current due to a parasitic NPN transistor in the second region during use, and wherein the first region is configured to be isolated from the second region such that the first current is not proportional to the second current. Description of the Drawings

[0007] Figure 1A is a cross-sectional view through an n-channel LDMOS device.

[0008] Figure 1B is during Figure 1A an example of a gate oxide breakdown mechanism that occurs during operation of the device.

[0009] Figure 2 illustrates Figure 1A an example doping concentration profile of different regions of the device.

[0010] Figure 3A is a reference circuit schematic of an LDMOS device when the parasitic NPN bipolar transistor is off.

[0011] Figure 3B is a circuit schematic of an LDMOS device for activating a parasitic NPN bipolar transistor.

[0012] Figure 3C(i) is a cross-section of an LDMOS device showing the concept of a PNP transistor as a reverse gate current source during transient mode operation of the LDMOS device.

[0013] Figure 3C(ii) is a circuit diagram of the concept shown in Figure 3C(i).

[0014] Figure 4A is a cross-sectional view of an n-channel LDMOS device according to a first embodiment of the present disclosure.

[0015] Figure 4B shows Figure 4A the electrical connections in the LDMOS device of

[0016] Figure 5A is a cross-sectional view of an n-channel LDMOS device according to another embodiment of the present disclosure.

[0017] Figure 5B shows an example doping concentration profile of different regions of the device of FIG. 5;

[0018] Figure 6 is a cross-sectional view of an n-channel LDMOS device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] The present disclosure relates to an n-channel LDMOS transistor having an improved structure to enhance the robustness of the transistor during its operation. In particular, the present invention relates to an n-channel LDMOS transistor having a modified structure to completely avoid or at least reduce the occurrence of gate oxide breakdown during the operation of the transistor. The occurrence of gate oxide breakdown can be reduced by modifying the dimensions and / or alignment of the various structures in the LDMOS device. However, the inventors have found that such a solution is very restrictive from the perspective of design and manufacturing. The inventors have recognized that the occurrence of gate oxide breakdown is related to the activation of a parasitic NPN bipolar transistor in the transient operating mode of the LDMOS transistor. In particular, the inventors have recognized that in the transient mode, due to weak ionization, the hole current density is proportional to the current from the parasitic NPN bipolar transistor, and it is this hole current that tunnels through the gate oxide under high electric fields, causing the breakdown of the oxide. More importantly, the inventors have recognized that during the transient operating mode of the LDMOS device (e.g., during a glitch), the hole current caused by weak ionization can be understood to be emitted from the emitter of a PNP transistor. It can be understood that this PNP bipolar junction transistor works together with the parasitic NPN bipolar junction transistor to generate a current I NPN proportional to the current I PNP .

[0020] To avoid or at least reduce the breakdown of the gate oxide in the transient mode, the inventors have modified the structure of the LDMOS transistor such that the above mechanism is prevented or at least the likelihood of its occurrence is reduced.

[0021] The structure of an LDMOS transistor can be modified to reduce the gain of a parasitic NPN bipolar junction transistor that is activated when the LDMOS transistor operates in a transient mode, such as due to spikes or glitches in the power supply. One such structure is disclosed by providing a buried p-doped region in the p-well region below the source and back-gate of the LDMOS transistor. The buried p-doped region serves to add dopants to the base of the parasitic NPN bipolar transistor, thereby reducing the gain of the parasitic NPN bipolar transistor. As described above, the incorporation of the buried p-region also helps to reduce the back-gate resistance, thereby reducing the likelihood of the parasitic NPN bipolar transistor being activated in the transient mode.

[0022] In another embodiment, a highly doped p-type region is placed directly under the source and back-gate such that it forms a junction with the n-doped region of the source and the p-doped region of the back-gate. This modification to the LDMOS structure also has the effect of reducing the gain of the parasitic NPN bipolar transistor as well as reducing the back-gate resistance, thereby reducing the likelihood of activating the parasitic bipolar transistor in the transient mode.

[0023] However, most importantly, the inventors have devised a variant to avoid gate oxide breakdown by physically isolating the region including the parasitic NPN transistor from the region that generates hole current, i.e., the extended drain region of the LDMOS transistor. According to an embodiment of the present disclosure, this can be achieved using a vertical trench between the two regions. This embodiment has the additional advantage that the second region does not need to be adjacent to the first region and can be placed at a desired location on the chip implementing the LDMOS device, thereby providing greater freedom in chip design, especially when optimizing the use of a given chip area.

[0024] As used herein, terms such as "above", "below", "to the side of", etc. refer to components or regions as illustrated in the drawings and are not intended to limit real-world devices.

[0025] Figure 1A A cross-section of an n-channel LDMOS device 100 on a silicon oxide substrate 101 is shown. A dielectric layer of silicon dioxide 101b (buried oxide or BOX layer) covers the bulk silicon support wafer 101a. Figure 1AThe doped silicon region 102, which is a p-doped region or a p-substrate, covers the buried oxide layer 101b. The p-substrate can be a multi-layer substrate, which includes a buried p-doped silicon layer 102a directly above the buried oxide 101b and a p-doped epitaxially grown silicon layer 102b directly above the buried p-doped silicon layer. The LDMOS device also includes an n-doped region or n-well 103 embedded in a part of the p-substrate. The device also includes a p-doped region or p-well 104 also embedded in the p-substrate, where the p-well is laterally adjacent to the n-well. As will be explained in a later section, the n-well 103 forms an extended drain drift region of the n-channel LDMOS device. The n-well region 103 can be a multi-layer region including a buried n-doped region 103a included in the p-substrate and an n-doped region 103b above the buried n-doped region. Figure 2 illustrates Figure 1A an example doping concentration profile of different regions of the device.

[0026] The device also includes a dielectric trench 108 on at least one side of the device, where the dielectric trench 108 is isolated from the bulk silicon region of the device. In Figure 1A this case, the device includes a dielectric trench 108 close to the p-well 104.

[0027] The device includes a gate 105, a back gate 106, a source 107, and a drain 108.

[0028] As Figure 1A shown, the source 107 and the drain 108 are on the laterally opposite sides of the gate 105. The back gate 106 is laterally adjacent to the source 107. The source 107 includes an n-doped region 107a embedded in the top surface of the p-well 104, where the n-type doped region 107a has a higher total dopant concentration than the n-type well 103. The back gate 106 includes a p-doped region 106a embedded in the top surface of the p-well and laterally adjacent to the n-doped region 107a, where the p-doped region 106a has a higher total dopant concentration than the p-well 104. The drain 108 includes an n-doped region 108a embedded in the top surface of the n-doped region. The n-type doped region 108a has a higher total dopant concentration than the n-type well 103. The drain 108 includes an n-doped region 108a embedded in the top surface of the n-well 103. The n-doped region 108a has a higher total dopant concentration than the n-well 103.

[0029] The device also includes a dielectric region 110 on the top surface. Electrical contacts to the source 107 and to the drain 108 are formed using metal vias 107b, 108b respectively, which extend through holes in the dielectric layer to contact the regions 107a of the source 107 and 108a of the drain 108 respectively. The dielectric region, preferably an oxide layer, includes LOCOS oxide regions 110a, 110b, and a gate oxide region 110c.

[0030] The gate 105 includes a polysilicon gate layer 105a extending over a portion of the n-well 103 and a portion of the p-well 104, and the polysilicon layer 105a is separated from the n-well and the p-well by the LOCOS oxide 110a and the gate oxide 110c.

[0031] Figure 1A A resurf structure including a first field plate 112a of a predetermined length is also shown. The first field plate 112a is embedded in the dielectric region 110 and is electrically connected to a metal, and the metal extends through the dielectric region 110 to contact the gate polysilicon layer 110. The resurf structure also includes a second field plate 112b having a predetermined length on the surface of the dielectric region 110. The second field plate 112b is located above the first field plate 112a and is connected to the first field plate 112a through a metal via hole extending through the dielectric region 110. Figure 1A The first field plate 112a in [] also serves as a gate contact.

[0032] Figure 1A It is shown that the LOCOS field oxide region 110a has a predetermined lateral distance that extends towards the gate between the drains. The LOCOS field oxide region 110a has a predetermined depth that extends vertically through the top surface of the device into the n-well 103. The gate oxide 110c extends laterally between one end (bird's beak) of the LOCOS field oxide region 110a and the n-doped region 107a of the source 107 above the surface of the device. The gate oxide region is thinner than the field oxide region. The thickness of the gate oxide 110c can be at least two orders of magnitude smaller than the thickness of the LOCOS field oxide 110a. For example, the gate oxide region can have a thickness of at least 15 nm, while the LOCOS field oxide can have a thickness of at least 400 nm.

[0033] In practical applications, as Figure 1A shown, the source terminal 107b is electrically shorted to the back gate terminal 106b, and the two terminals are maintained at the same potential to avoid activating the parasitic NPN bipolar junction transistor.

[0034] As Figure 1A shown, applying an electric potential at the gate causes a conductive inversion layer or channel 114 to form between the source 107 and the drain 108. Subsequent biasing of the drain 108 of the device relative to the source 107 allows majority carriers or electrons to move from the source 107 via the conductive channel 114 to the drain 108. Figure 1A A depletion region is also shown, which extends into the channel region and also through the lightly doped extended drift region, thereby diluting the internal electric field and enabling high-voltage operation.

[0035] The depletion region creates an internal electric field that is lower than the critical electric field required to initiate an avalanche ionization chain reaction (defining the breakdown voltage V BD ) of the device. However, the combination of the channel current and the electric field across the extended drift region creates weak impact ionization, generating minority carriers or holes for the n-channel LDMOS device - this hole current or back-gate current I bg flows from the drain drift region towards the source / back-gate direction.

[0036] The rupture of the gate oxide depends on the density of the above-mentioned hole current and the electric field strength across the gate oxide 110c. As Figure 1B shown, due to the electric field across the gate oxide, during the transient mode operation of the LDMOS device, the gate oxide ruptures due to the back-gate current tunneling through the gate oxide.

[0037] In the practical application of the LDMOS device, the short circuit from the source terminal 107b to the back-gate terminal 106b prevents the activation of the parasitic NPN bipolar junction transistor 113. However, despite the connection being shorted, the parasitic NPN transistor can be activated due to the following reasons: faults caused by power supply voltage spikes (such as voltage overshoot). During this transient operating mode of the LDMOS device, it is observed that the hole current caused by weak impact ionization is proportional to the number of electrons injected into the drain.

[0038] The present inventors were able to reproduce the rupture of the gate oxide during the transient mode operation of the LDMOS device using the test circuit 300 as shown in Figure 3A and 3B to model the LDMOS device. The test circuit 300 includes an n-channel LDMOS transistor 301 coupled to an NPN bipolar junction transistor 302, where the transistor 302 represents the parasitic NPN transistor, which can be activated during the operation of the n-channel LDMOS as described above. The test circuit 300 also includes a capacitor 303 for modeling the back-gate capacitance and a resistor 304 for modeling the back-gate resistance. Figure 3A Figure 300 shows the test circuit 300 where the parasitic NPN transistor is in the "off" mode, i.e., not activated. Figure 3B Figure 300 shows the test circuit where the parasitic NPN is in the "on" mode, that is, Figure 3B simulating the n-channel LDMOS where the parasitic NPN transistor is activated during the device operation.

[0039] Using the test circuit 300, the inventors activated the parasitic NPN bipolar transistor 302 and observed a significant increase in the hole density, especially at the transition between the field oxide 110a and the gate oxide 110c compared to the corresponding hole density in the reference circuit (see Figure 1A ). For the use of Figure 3BIn the tests performed by circuit 300, the inventors found that, compared with the reference circuit in which the parasitic bipolar junction transistor is turned off, the forced activation of the parasitic NPN bipolar transistor caused the hole density at the transition from the field oxide to the gate oxide to increase by three orders of magnitude. For Figure 3A the test circuit in, the inventors observed ruptures in the gate oxide at the transition from the field oxide to the gate oxide. Figure 3B For

[0040] Figure 3C(i) is a simplified cross-sectional view of the device shown in Figure 1A . An important insight of the inventors is that during the transient operating mode of the LDMOS device (e.g., during a glitch), the hole current caused by weak impact ionization can be understood as being emitted from the emitter of the PNP transistor, as shown in the cross-section of Figure 3C(i). As shown in Figure 3C(ii), the test circuit 300 can be used to model the transient mode operation of the LDMOS device. As shown in Figure 3C(ii), the PNP bipolar junction transistor 305 can be understood to work together with the parasitic NPN bipolar junction transistor 302 to generate current I PNP , which flows in a direction opposite to the current I NPN generated by the parasitic NPN bipolar junction transistor 302. Therefore, the emitter of the PNP transistor 305 can be regarded as the emitter of holes, and the two bipolar junction transistors 302, 305 operate together, as shown in Figure 3C(ii), so that the effect of weak impact ionization causing minority carriers to flow towards the source is proportional to I NPN .

[0041] The inventors found that gate oxide rupture occurs during the transient mode operation of the device, especially when the gain product of the two bipolar transistors exceeds 1. To solve this problem, the inventors proposed an improvement to the LDMOS device, which will be explained in detail below.

[0042] Now, we will describe different embodiments of the present disclosure with reference to Figures 4-6, in which the structure of the LDMOS transistor is modified to avoid or at least reduce gate oxide rupture during the transient mode operation of the LDMOS device.

[0043] Figure 4A is the first embodiment 400 of the LDMOS device according to the present disclosure. The designed Figure 4A LDMOS device in can avoid the above-mentioned gate oxide rupture during the transient mode operation of the device. The LDMOS device 400 has a first part 401 and a second part 402, where the first part 401 and the second part 402 are separated by a vertical trench 403. The trench 403 is electrically insulated from the two parts. The trench is filled with a dielectric layer, preferably an oxide layer.

[0044] The first portion 401 is formed on a silicon oxide substrate (not shown). The first portion includes a p-substrate 401a similar to the p-substrate described for the device in Figure 1A above. The first portion also includes an n-well region 401b above the p-substrate 401a, similar to the n-well structure described for the device in Figure 1A above.

[0045] In Figure 4A above, the drain 401c is adjacent to the first side 404 of the device. The first portion 401 also includes a second n-doped region 401d adjacent to the trench. The n-well 401b extends laterally from the drain 401c to the second n-doped region 401d. The drain 401c and the second n-doped region 401d are embedded in the top surface of the n-well region 401b.

[0046] The first portion 401 also includes a polysilicon structure 401e of a predetermined length, which is separated from the top surface of the device, particularly from the top surface of the n-well 401b, by a dielectric layer (preferably a LOCOS oxide layer 405). The first portion also includes a p-doped back gate 401f, wherein the p-doped back gate is laterally located between the polysilicon structure 401e and the second n-doped region 401d, and the p-doped back gate is laterally separated from the polysilicon structure 401e and the second n-doped region 401d by a dielectric region such as a LOCOS oxide region 405.

[0047] The second portion 402 is also formed on a silicon oxide substrate (not shown). The second portion includes a p-substrate 402a. The p-substrate 402a of the second portion 402 is thicker than the p-substrate 401a of the first portion 401. In Figure 4A above, each of the p-substrates 401a, 402a for the first portion and the second portion respectively includes a buried p-doped silicon layer on a BOX layer and a p-doped silicon layer epitaxially grown directly above the buried p-doped silicon layer. In Figure 4A above, the epitaxially grown p-doped layer of the p-substrate 402a of the second portion 402 is thicker than the epitaxially grown p-doped layer of the p-substrate 401a of the first portion 401. The second portion 402 also includes a p-doped region or p-well 402b directly above the p-substrate 402a.

[0048] The second portion includes a first n-doped region 402c and a second n-doped region or source 402d on laterally opposite sides of a gate structure 402e, which includes a polysilicon gate layer 402e(i) on a gate oxide 402e(ii), wherein the polysilicon gate layer 402e(i) is separated from the surface of the p-well 402b by the gate oxide 402e(ii), similar to Figure 1AThe gate of the device in the middle. The first n-doped region 402c of the second part is laterally located between the trench 403 and the gate structure 402e. The source 402d is laterally located between the gate structure 402e and the p-doped back-gate region 402f, where the source is laterally separated from the gate and the p-doped back-gate region by a dielectric region such as a LOCOS oxide region.

[0049] The device also includes a dielectric layer (not shown) on the top surface of the device and on the polysilicon structure, similar to Figure 1A the device of. The above-mentioned LOCOS oxide region also forms part of the dielectric layer. Electrical contacts to the drain, polysilicon structure, back-gate, and n-doped regions in the two parts can be formed using corresponding metal vias extending through holes in the dielectric layer. The device may also include a surface structure 401g similar to Figure 1A the surface structure 112 in the device 100 of.

[0050] Figure 4B is Figure 4A a simplified version of the device in, showing Figure 4A the electrical connections between different regions of the LDMOS device of. Figure 4B shows that the back-gate 402f of the second part is electrically coupled to the back-gate 401f of the first part, the p-substrate 401a of the first part, the polysilicon structure 401e of the first part, and the field plate of the resurf structure 401g of the first part. The second n-doped region 401d of the first part is electrically coupled to the first n-doped region 402c of the second part. As Figure 4B shown, the back-gate terminal for the Figure 4B LDMOS device is at the back-gate 402f of the second part. As Figure 4B shown, Figure 4B the drain terminal of the LDMOS device of is at the drain 401c of the first part. As Figure 4B shown, Figure 4B the gate terminal of the LDMOS device of is at the gate 402e(i) of the second part. As Figure 4B shown, Figure 4B the source terminal of the LDMOS device of is at the source 402d of the second part. In some embodiments, the source terminal and the back-gate terminal can be short-circuited.

[0051] Figure 4A also indicates that during the operation of the LDMOS device, the first part 401 acts as an effective high-voltage JFET, while the second part 402 acts as an effective low-voltage MOSFET. Then, the bottom gate of the high-voltage JFET is the p-doped silicon layer of the epitaxially grown p-substrate 401a, whose bottom potential is kept at the same potential as the back-gate 401f, and the back-gate 401f serves as the top gate of the effective high-voltage JFET. As Figure 4AAs shown by the dashed line in, the depletion region spreads from the top and bottom gates of the effective high-voltage JFET. The depletion region can be configured to pinch off the drain 401c from the second n-doped region or the effective source 401d of the JFET at a pinch-off voltage defined by the dopant concentration of the n-well 401b. This isolates the effective source 401d of the JFET from the high-voltage potential applied to the drain, and the n-well serves as a voltage divider. As Figure 4B shown, the electron current (blue dashed line) from the source terminal of the JFET (or the second n-doped region 401d of the first part) to the drain terminal flows between the depletion regions.

[0052] The inventors have found that in the transient mode, the hole current is proportional to the current I of the parasitic NPN bipolar junction transistor. The above problem NPN is not observed in the Figure 4A device structure. This is first because in the Figure 4A device, the parasitic bipolar transistor NPN is isolated from the n-well region by a vertical trench 403, in which the hole current is generated due to weak impact ionization. Second, in the Figure 4A device, the hole current generated due to weak impact ionization sinks to ground from the back-gate contact. As a result, Figure 4A the device structure overcomes the problem of gate oxide breakdown that occurs during the transient mode operation of the n-channel LDMOS device.

[0053] In the chip implementing the Figure 4A LDMOS device, the second part 402 does not need to be placed adjacent to the first part 401 - that is, since the physical structure of the second part 402 is dielectrically isolated from the first part 401 using the trench 403, additional design freedom can be achieved by placing the second part 402 elsewhere if needed, for example, to optimize the use of the chip area, provided that the external electrical connection between the two parts is still made as described above.

[0054] Figure 5A Another embodiment 500 of the LDMOS device according to the present disclosure is shown. The device structure is similar to the Figure 1A LDMOS device in. However, in the Figure 5A device, both the n-well region 503 and the p-well region 504 are multi-layer regions. The n-well region 503 includes an n-doped buried layer 503a and an additional n-doped region 503b above the buried n-doped region. The multi-layer p-well region 504 includes a buried p-doped region 504a directly above the p-type epitaxial region 502b and an additional p-doped region 504b above the buried p-doped region 504a. The n-well region 503 is close to the first side of the device 500a. The p-well region 504 is close to the trench 505, which is located on the second side 500b of the device opposite to the first side 500a. InFigure 5A In the device 500, the buried n-doped region 503a and the buried p-doped region 504a are directly above the epitaxially grown p-doped layer 502b of the p-substrate. The n-doped region 503b extends a predetermined length on the junction 511 between the buried p-type well 504a and the n-type well 503a region in the direction towards the trench 505.

[0055] Figure 5B Shows Figure 5A An example doping concentration profile of different p-doped regions of the device.

[0056] The inventors have found that the incorporation of the buried p-well region 504a has the effect of reducing the gain of the parasitic NPN bipolar transistor, the gain of which can be activated during the transient mode operation of the LDMOS device. The buried p-well region 504a serves to add dopants to the base of the parasitic NPN bipolar transistor, which in turn reduces its gain. Considering the above discussion regarding the gate oxide breakdown problem during the transient mode, reducing the gain of the NPN transistor will in turn have the effect of reducing the hole current density, which is proportional to the current generated by the NPN transistor. Another advantage of incorporating the buried p-well region 504a is that the buried layer serves to reduce the back-gate resistance. This in turn reduces the likelihood of any transient glitch in the power supply turning on the parasitic bipolar transistor, making the device more robust. As a result of Figure 5A the above advantages associated with the device structure, the likelihood of gate oxide breakdown during the transient mode operation of the LDMOS device is reduced.

[0057] In practical applications, as also Figure 5A shown, the junction 511 between the edge of the buried p-well region 504a or the equivalent buried n-well region 503a and the buried p-well region is configured to be close to the bird's beak defined by the LOCOS field oxide region 510a at the edge of the gate polysilicon layer, where the bird's beak also forms a transition 510b between the LOCOS field oxide region 510a and the thin gate oxide region 510c. Such alignment can be achieved during the fabrication of the device by aligning the edge of the buried p-well region 504a or equivalently, aligning the junction 511 between the buried n-well region 503a and the buried p-well region with the edge of the gate mask. The inventors have found that aligning the edge of the buried p-well region 504a with the gate mask in this way can further enhance the effect of reducing the gain of the parasitic NPN bipolar transistor. The inventors have found that when the tolerance of the alignment of the edge of the buried p-well region 504a with the edge of the gate mask is between approximately 0.5 μm and 1 μm (more preferably around 1 μm), unwanted outward diffusion from the buried p-well region 504a can be avoided.

[0058] Figure 6 is another embodiment of the LDMOS device 600 according to the present disclosure. Figure 6 The cross-section of Figure 5A is a simplified form of the cross-section of Figure 6 , except that it includes a p-type implant region 604c under the source and back gate of the LDMOS device. The implant region has a higher dopant concentration than the surrounding p-well region 604b. Preferably, the implant region has a total dopant concentration of 1E18 cm -3 . The implant region 604c can be combined with or separately combined with the buried p-doped region 604a as shown in Figure 6 . By injecting dopants under the source 607 and back gate 608 of the NDMOS 600 using kinetic energy, the inventors found that the implant region 604c can be positioned such that the MOS action along the inversion channel (see the channel 114 in Figure 1A ) is not affected laterally. However, due to the additional p-type dopants in the base of the parasitic NPN transistor, the vertical parasitic bipolar action during the transient mode has been greatly reduced. In addition, the highly doped region on the source 607 protects it from any potential drop caused by the transient back gate current. This can prevent the transient glitch from turning on the parasitic bipolar transistor because the implant region also helps to reduce the back gate resistance.

[0059] Example

[0060] Now, we will describe a method for manufacturing an LDMOS transistor according to the embodiments described in the above disclosure by way of the following examples.

[0061] Example 1 is a method for manufacturing an LDMOS transistor, including: providing a wafer; forming a drain, a gate, a source, and a back gate; and forming an isolation structure configured to physically isolate a first region including the gate of the LDMOS transistor from a second region having a parasitic bipolar junction transistor during use.

[0062] Example 2 is a method for manufacturing an LDMOS transistor according to Example 1, wherein the method includes forming an n-channel LDMOS transistor.

[0063] Example 3 is a method for manufacturing an LDMOS transistor according to Example 1, wherein the method includes forming a p-channel LDMOS transistor.

[0064] Example 4 is a method for manufacturing an LDMOS transistor according to Example 1, wherein forming the isolation structure includes forming a dielectric trench.

[0065] Example 5 is a method of fabricating a lateral n-channel LDMOS transistor, comprising: providing a wafer; forming a drain, a gate, a source, and a back gate; and forming a laterally extending field oxide region between the drain and the gate; forming a laterally extending gate oxide region between an edge of the field oxide region and the source; forming a p-doped region, wherein the p-doped region is configured to reduce the gain of a parasitic bipolar transistor in use; forming a p-doped buried layer in the p-doped region such that the buried layer is isolated from the source and the back gate by a remainder of the p-doped region, wherein forming the p-doped buried layer further comprises aligning an edge of the p-doped buried layer with an edge of the gate near a transition between the field oxide region and the gate oxide region.

[0066] Example 6 is a method of fabricating a lateral n-channel LDMOS transistor according to Example 5, wherein forming the p-doped buried layer comprises implanting the p-doped buried layer using a higher dopant concentration than a remainder of the p-doped region.

[0067] Example 7 is a method of fabricating a lateral n-channel LDMOS transistor according to Example 5 or 6, wherein forming the p-doped region comprises: forming a p-doped buried layer on a p-type epitaxial layer; and forming a p-well region on the p-doped buried layer, wherein the source and the back gate are formed in the p-well region.

[0068] Although the present disclosure has been described in accordance with certain embodiments, the embodiments may be combined to provide other embodiments. Additionally, certain features shown in the context of one embodiment may also be incorporated into other embodiments. Although the present disclosure has been described in the context of n-channel LDMOS transistors, the teachings of the present disclosure are equally applicable to p-channel LDMOS transistors.

Claims

1. An LDMOS transistor, comprising: An n-doped drain in an n-well; A gate; An n-doped source in a p-well; And A p-doped back gate including a first p-doped back gate region in the n-well and a second p-doped back gate region in the p-well; Wherein the LDMOS transistor further includes a trench isolation structure filled with oxide, the isolation structure being configured to physically isolate a first region of the n-well including the drain of the LDMOS transistor from a second region of the p-well including the source of the LDMOS transistor, the second region having a parasitic bipolar junction transistor in use, Wherein the first p-doped back gate region in the n-well of the LDMOS transistor is electrically coupled to the second p-doped back gate region in the p-well of the LDMOS transistor, and Wherein the first n-doped region in the n-well of the LDMOS transistor is electrically coupled to the second n-doped region in the p-well of the LDMOS transistor, the gate being formed on the p-well between the second n-doped region and the n-doped source, wherein the second n-doped region, the p-well and the n-doped source constitute the parasitic bipolar junction transistor, Wherein the first region further includes a first p-type epitaxial layer, and the n-well is formed on the first p-type epitaxial layer, Wherein the second region further includes a second p-type epitaxial layer, the p-well is formed on the second p-type epitaxial layer, and wherein the second p-type epitaxial layer is thicker than the first p-type epitaxial layer.

2. The LDMOS transistor according to claim 1, wherein the gate includes a polysilicon-on-oxide structure in the second region.

3. The LDMOS transistor according to claim 1, wherein the back gate includes a p-doped structure in the first region, the p-doped structure being coupled in use to: a polysilicon-on-oxide structure in the first region, a p-doped substrate in the first region, and a p-doped structure in the second region.

4. The LDMOS transistor according to claim 1, wherein the source is coupled to the p-doped back gate.

5. The LDMOS transistor according to claim 1, wherein the first region further includes a resurf structure configured to control the charge distribution in the first region in use.

6. The LDMOS transistor according to claim 5, wherein the resurf structure includes: A first field plate; And A second field plate, Wherein the second field plate is located above the first field plate, and wherein the second field plate is parallel to the first field plate, and wherein the second field plate is configured to be coupled to the first field plate.

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