Storage device group, storage system, and operation method of storage device

Abstract

Provided are a storage device group, a storage system, and an operating method of a storage device. The storage device group includes a reconfigurable logic chip and a storage device. The logic chip includes a retimer configured to generate an output signal by adjusting an input signal received from an external device, and an operation circuit configured to perform an operation function. The storage device includes a first port connected to the retimer, a second port connected to the operation circuit, and a controller configured to control data transmission and reception via the first port and the second port.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0162880, filed on December 9, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] Methods and apparatuses consistent with example embodiments relate to a storage device, and more particularly, to a storage device group including a storage device and a reconfigurable logic chip, a storage system including the storage device group, and an operating method of the storage device. BACKGROUND

[0003] In order to improve the processing speed of a storage system, an accelerator can be added to the storage system, and the accelerator assists the operation of a host by performing some of the operations performed by the host. The accelerator can be a dedicated hardware accelerator performing a set function or an accelerator reconfigurable according to a design file such as a field programmable gate array (FPGA) image. Recently, as the host performs various applications and requires high-speed processing for each application, the demand for a reconfigurable accelerator such as an FPGA reconfigurable according to various applications is increasing. SUMMARY

[0004] Example embodiments provide a storage device group capable of minimizing input and output delays by performing communication with a host using a retimer, a storage system including the same, and an operating method of the storage device group.

[0005] According to an aspect of example embodiments, there is provided a storage device group including: a reconfigurable logic chip including a retimer configured to generate an output signal by adjusting an input signal received from an external device, and an operation circuit configured to perform an operation function; and a storage device including a first port connected to the retimer, a second port connected to the operation circuit, and a controller configured to control data transmission and reception via the first port and the second port.

[0006] According to an aspect of example embodiments, there is provided a storage system including: a host; a retimer communicably connected with the host; a storage device including a controller, the storage device configured to receive a request from the host via the retimer and generate input data corresponding to the received request; and a reconfigurable logic chip configured to receive the input data from the storage device, generate output data by performing an operation corresponding to the received request using the input data, and provide the output data to the storage device.

[0007] According to an aspect of the example embodiments, there is provided an operating method of a storage device connected to a reconfigurable logic chip including a retimer and an operation circuit, the storage device including a first port connected to the retimer and a second port connected to the operation circuit, the operating method including: receiving a request of a host via the first port; generating input data corresponding to the received request; providing the input data to the operation circuit via the second port; obtaining output data corresponding to the input data from the operation circuit via the second port; generating response data corresponding to the received request based on the output data; and transmitting the generated response data to the host via the first port and the retimer. BRIEF DESCRIPTION OF DRAWINGS

[0008] The above and other aspects, features, and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a block diagram schematically illustrating a storage system according to an example embodiment;

[0010] Figure 2 is a block diagram illustrating in detail a storage device group according to an example embodiment;

[0011] Figure 3 is a block diagram for describing an operating method of a storage device group according to an example embodiment;

[0012] Figure 4 is a flowchart of an example of an operation of a reconfigurable logic chip and a controller according to an example embodiment;

[0013] Figure 5 is a flowchart of an example of an operation of a reconfigurable logic chip and a controller according to an example embodiment;

[0014] Figure 6 is a block diagram illustrating a configuration of a controller according to an example embodiment;

[0015] Figure 7 is a block diagram illustrating a configuration of a controller according to an example embodiment;

[0016] Figure 8 is a block diagram for describing an operating method of a storage device group according to an example embodiment;

[0017] Figure 9 is a block diagram for describing an operating method of a storage device group according to an example embodiment;

[0018] Figure 10 is a flowchart of an example of an operation of a volatile memory, a reconfigurable logic chip, and a controller according to an example embodiment;

[0019] Figure 11is a block diagram illustrating a storage device group according to an example embodiment in detail;

[0020] Figure 12 is a block diagram illustrating a storage device group according to an example embodiment in detail;

[0021] Figure 13 is a block diagram illustrating a storage device group according to an example embodiment in detail;

[0022] Figure 14 is a block diagram illustrating a storage device group according to an example embodiment in detail;

[0023] Figure 15 is a flowchart of an operating method of a storage device according to an example embodiment; and

[0024] Figure 16 is a diagram of a network system according to an example embodiment. DETAILED DESCRIPTION

[0025] Figure 1 is a block diagram schematically illustrating a storage system SS according to an example embodiment.

[0026] Referring to Figure 1 , the storage system SS includes a storage device group 10 and a host 300. The storage device group 10 can include a storage device 100 and a reconfigurable logic chip 200, and can be referred to as a smart storage device. The storage device 100 can include a first port PT1 and a second port PT2, and thus the storage device 100 can be referred to as a dual-port storage device. The reconfigurable logic chip 200 can include a retimer 210 and an operation circuit 220.

[0027] The storage system SS can be implemented as, for example, a personal computer (PC), a data server, a network-combined storage, an Internet of Things (IoT) device, or a portable electronic device. The portable electronic device can be a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital camera, a digital camcorder, an audio device, a portable multimedia player (PMP), a personal navigation device (PND), an MP3 player, a handheld game console, an electronic book, or a wearable device.

[0028] According to some example embodiments, the storage device 100 can be an internal memory embedded in an electronic device. For example, the storage device 100 can be a solid state drive (SSD), an embedded universal flash storage (UFS) memory device, or an embedded multimedia card (eMMC). According to some example embodiments, the storage device 100 can be an external memory detachably attached to an electronic device. For example, the storage device 100 can be a UFS memory card, a compact flash (CF) card, a secure digital (SD) card, a micro SD card, a mini SD card, an extreme digital (xD) card, or a memory stick.

[0029] According to example embodiments, the storage device 100 can be implemented as a first chip, and the reconfigurable logic chip 200 can be implemented as a second chip. The first chip and the second chip can be electrically connected to each other and mounted on a single board. According to example embodiments, the storage device 100 can be implemented as a first chip, and the reconfigurable logic chip 200 can be implemented as a second chip. The first chip and the second chip can constitute a package on package (POP). However, example embodiments are not limited thereto, and the storage device group 10 can be constituted of the storage device 100 and the reconfigurable logic chip 200 electrically connected to each other.

[0030] According to example embodiments, the reconfigurable logic chip 200 can include a field programmable gate array (FPGA) chip. However, example embodiments are not limited thereto, and the reconfigurable logic chip 200 can include a programmable logic device (PLD) or a complex PLD (CPLD). The reconfigurable logic chip 200 can be used as an accelerator for assisting the operation of the host 300 by performing some of the operations performed by the host 300.

[0031] The reconfigurable logic chip 200 can include a retimer 210 that generates an output signal by adjusting an input signal when the signal is input from an external device. The retimer 210 can remove jitter of the input signal, repair damage, and transmit the recovered input signal by using a local clock signal. According to example embodiments, the retimer 210 can receive data from the host 300, adjust the received data, and transmit the adjusted data to the storage device 100. In addition, the retimer 210 can receive data from the storage device 100, adjust the received data, and transmit the adjusted data to the host 300. The retimer 210 can include a peripheral component interconnect express (PCIe) retimer according to a PCIe protocol. However, example embodiments are not limited thereto, and the retimer 210 can include a retimer according to another protocol.

[0032] The re-timer 210 can transmit a signal only via a physical layer. Accordingly, by using the re-timer 210, the storage device group 10 can improve a data transmission and reception speed with the host 300. Specifically, the re-timer 210 can transmit a signal only via a physical layer without a transaction layer and a data link layer. On the other hand, in a case where a switch (e.g., a PCIe switch) that can be used as an interface for transmitting a signal, instead of the re-timer 210, a signal can be transmitted via all of a transaction layer, a data link layer, and a physical layer. Accordingly, the storage device group 10 can improve an input and output speed of a signal by using the re-timer 210 instead of a switch that transmits a signal via a plurality of layers.

[0033] It has been described that the storage device group 10 includes the re-timer 210, but example embodiments are not limited thereto, and the storage device group 10 can include an interface capable of transmitting a signal instead of the re-timer 210. For example, the storage device group 10 can include a repeater including the re-timer 210 and a redriver.

[0034] The reconfigurable logic chip 200 can include an operation circuit 220 capable of performing an operation function. According to an example embodiment, the operation circuit 220 can receive input data from the storage device 100, perform an operation on the input data, and transmit output data generated as a result to the storage device 100. For example, the operation circuit 220 can perform various operations (such as encryption, decryption, compression, decompression, pattern matching, sorting, and searching) by using input data. Further, operations that can be performed by the operation circuit 220 are not limited to the above operations. According to an example embodiment, the operation circuit 220 can perform an operation according to a predetermined configuration. The reconfigurable logic chip 200 can be reconfigured (also referred to as reconfigured) during operation, and thus, the operation circuit 220 can be changed to a second operation circuit while operating as a first operation circuit.

[0035] The storage device 100 can communicate with the host 300 via the first port PT1. Specifically, the storage device 100 can be connected to the re-timer 210 via the first port PT1. Further, the storage device 100 can communicate with the host 300 according to a first interface protocol via the first port PT1 and the re-timer 210. For example, the first interface protocol can be PCIe. However, example embodiments are not limited thereto, and the first interface protocol can be Universal Serial Bus (USB), PCI, Advanced Technology (AT) Attachment (ATA), Serial AT Attachment (SATA), Parallel AT Attachment (PATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0036] The storage device 100 can communicate with the operation circuit 220 of the reconfigurable logic chip 200 via the second port PT2. Specifically, the storage device 100 can be connected to the operation circuit 220 via the second port PT2. Also, the storage device 100 can communicate with the operation circuit 220 according to a second interface protocol via the second port PT2. According to an example embodiment, the first port PT1 and the second port PT2 of the storage device 100 can be different from each other. In other words, the storage device 100 can transmit and receive data to and from the host 300 via the first port PT1, and transmit and receive data to and from the operation circuit 220 of the reconfigurable logic chip 200 via the second port PT2. Also, the second interface protocol and the first interface protocol can be the same protocol. However, example embodiments are not limited thereto, and the second interface protocol and the first interface protocol can be different from each other.

[0037] As such, the storage device 100 can transmit and receive data to and from the host 300 by being connected to the re-timer 210 of the reconfigurable logic chip 200 via the first port PT1, and transmit and receive data to and from the reconfigurable logic chip 200 by being connected to the operation circuit 220 of the reconfigurable logic chip 200 via the second port PT2.

[0038] Also, the storage device group 10 can transmit and receive data by using the re-timer 210 that performs data transmission and reception via a physical layer, instead of the switch that performs data transmission and reception via a plurality of layers, minimizing input and output delay.

[0039] Also, the storage device group 10 can transmit and receive data to and from the host 300 by being connected to the re-timer 210 of the reconfigurable logic chip 200 via the first port PT1, and transmit and receive data to and from the reconfigurable logic chip 200 by being connected to the operation circuit 220 of the reconfigurable logic chip 200 via the second port PT2. Figure 1 It is described that the storage device group 10 includes the reconfigurable logic chip 200, but example embodiments are not limited thereto, and the storage device group 10 can include a general-purpose operation unit (such as a central processing unit (CPU) or a graphic processing unit (GPU) capable of performing an operation function) instead of the reconfigurable logic chip 200. When the storage device group 10 includes the general-purpose operation unit, the general-purpose operation unit can include a re-timer connected to the first port PT1 of the storage device 100 and an operation circuit connected to the second port PT2 of the storage device 100.

[0040] Figure 2 is a block diagram illustrating the storage device group 10 according to an example embodiment in detail. Specifically, Figure 2 is a block diagram illustrating the storage device group 10 of Figure 1 in detail.

[0041] Referring to Figure 2The storage device group 10 can include a storage device 100 and a reconfigurable logic chip 200. The storage device 100 can include a controller 110 and a non-volatile memory (NVM) 120. According to an example embodiment, the controller 110 and the NVM 120 can be implemented as separate chips. The reconfigurable logic chip 200 can include a re-timer 210 and an operation circuit 220.

[0042] The host 300 can transmit a host command requesting a specific operation (such as a write request or a read request) to the storage device group 10. According to an example embodiment, the host 300 can transmit data related to the host command to the storage device group 10 together with the host command.

[0043] The storage device group 10 can receive the host command via the re-timer 210 of the reconfigurable logic chip 200. The re-timer 210 can adjust the received host command, and transmit the adjusted host command to the storage device 100. According to an example embodiment, the re-timer 210 can transmit the adjusted host command to the controller 110 including the first port PT1. According to an example embodiment, the re-timer 210 can adjust data related to the received host command, and transmit the adjusted data to the controller 110 including the first port PT1.

[0044] The storage device 100 can receive the host command and generate a command by analyzing the host command. According to an example embodiment, the controller 110 can analyze the host command received via the re-timer 210 and the first port PT1, and generate a command for controlling the operation circuit 220 when it is determined that the operation of the operation circuit 220 is required. According to an example embodiment, the controller 110 can include a scheduler for decoding the host command and generating the command as described above.

[0045] The controller 110 can generate input data required to perform the operation requested by the host 300. According to an example embodiment, when it is determined that the operation of the operation circuit 220 is required, the controller 110 can generate the input data by using data received from the host 300, or generate the input data by reading data from the NVM 120.

[0046] The storage device 100 can provide the generated input data to the operation circuit 220 via the second port PT2. According to an example embodiment, the reconfigurable logic chip 200 can include a third port PT3 connected to the operation circuit 220 and distinguished from the re-timer 210, and the storage device group 10 can include a root (e.g., a PCIe bus) connecting the second port PT2 and the third port PT3. Further, the controller 110 can transmit the generated input data to the operation circuit 220 via the second port PT2 and the third port PT3. According to an example embodiment, the host 300 can transmit a command indicating the operation requested by the host 300 together with the input data.

[0047] The operation circuit 220 can receive input data, and generate output data by performing an operation corresponding to an operation requested by the host 300 using the received input data. For example, when the operation circuit 220 receives a command indicating compression, the operation circuit 220 can generate output data by compressing the input data. Then, the operation circuit 220 can provide the generated output data to the storage device 100 via the second port PT2. According to an example embodiment, the operation circuit 220 can transmit the output data to the controller 110 via the third port PT3 and the second port PT2.

[0048] Further, the storage device 100 can receive output data, and generate response data regarding a host command based on the received output data. According to an example embodiment, the controller 110 can receive output data via the second port PT2, and generate response data regarding a host command based on the received output data. Here, the response data can include information indicating whether an operation corresponding to the host command is completed. According to an example embodiment, the controller 110 can perform an additional operation in response to a request of the host 300. For example, when the request of the host 300 is a write request, the controller 110 can write output data received from the operation circuit 220 to the NVM 120, and generate response data regarding the write request.

[0049] Further, the storage device 100 can transmit the response data to the host 300. According to an example embodiment, the controller 110 can transmit the response data to the retimer 210 via the first port PT1. The retimer 210 can adjust the received response data, and transmit the adjusted response data to the host 300.

[0050] Figure 3 is a block diagram for describing an operation method of the storage device group 10 according to an example embodiment. Specifically, Figure 3 is a flowchart illustrating an operation method of the storage device group 10 of Figure 2 .

[0051] The host 300 and the storage device group 10 can operate based on the same protocol. For example, the host 300 and the storage device group 10 can operate based on a Non-Volatile Memory Express (NVMe) protocol. However, example embodiments are not limited thereto, and another protocol can be used. Further, for convenience of description, it will be described on the assumption that the host 300 and the storage device group 10 operate based on the NVMe protocol and the interfaces included in the host 300 and the storage device group 10, respectively, are PCIe devices supporting the NVMe protocol. Figure 3 .

[0052] Referring to Figure 2 and Figure 3The host 300 can generate a host command to be transmitted to the storage device group 10. According to an example embodiment, the host 300 can include an NVMe driver. The host 300 can generate the host command based on the NVMe protocol by using the NVMe driver.

[0053] The host 300 can transmit the host command generated based on the NVMe protocol to the storage device group 10. According to an example embodiment, the host 300 can transmit the host command to the retimer 210, the retimer 210 can adjust the host command, and transmit the adjusted host command to the controller 110 via the first port PT1 (operation ①). Then, the controller 110 can generate input data required to perform an operation requested by the host 300 based on the NVMe protocol. According to an example embodiment, the controller 110 can also generate a command indicating the operation requested by the host 300 based on the NVMe protocol.

[0054] Then, the controller 110 can transmit the input data to the operation circuit 220 via the second port PT2 (operation ②). According to an example embodiment, the controller 110 can directly transmit the command and the input data to the operation circuit 220 via the second port PT2 and the third port PT3. Then, the operation circuit 220 can receive the command and the input data, and perform an operation corresponding to the received command by using the input data. The operation circuit 220 can generate output data based on the NVMe protocol by performing the operation. In this regard, the operation circuit 220 can include an NVMe driver.

[0055] Next, the operation circuit 220 can transmit the output data to the controller 110 via the second port PT2 (operation ③). According to an example embodiment, the operation circuit 220 can directly transmit the output data to the controller 110 via the third port PT3 and the second port PT2. Then, the controller 110 can receive the output data based on the NVMe protocol and generate response data regarding the host command.

[0056] Then, the controller 110 can transmit the response data generated based on the NVMe protocol to the host 300. According to an example embodiment, the controller 110 can transmit the response data to the retimer 210, the retimer 210 can adjust the response data, and transmit the adjusted response data to the host 300 via the first port PT1 (operation ④).

[0057] Figure 4 is a flowchart of an example of the operation of the reconfigurable logic chip 200 and the controller 110 according to an example embodiment. Specifically, Figure 4 is a diagram illustrating Figure 3a flowchart of an example of the operation of the reconfigurable logic chip 200 and the controller 110. For ease of description, the description will also be made under the assumption that the host 300 and the storage device group 10 operate based on the NVMe protocol and the interfaces included in the host 300 and the storage device group 10, respectively, follow a PCIe method supporting the NVMe protocol Figure 4 .

[0058] Referring to Figure 3 and Figure 4 In operation S110, the reconfigurable logic chip 200 can receive a host command. Specifically, the re-timer 210 of the reconfigurable logic chip 200 can receive the host command. Then, in operation S120, the reconfigurable logic chip 200 can perform signal processing on the host command. Specifically, the re-timer 210 of the reconfigurable logic chip 200 can remove jitter of the host command and repair damage to perform signal processing (e.g., adjust the host command) on the host command.

[0059] Then, in operation S125, the reconfigurable logic chip 200 can transmit the adjusted host command to the controller 110. Specifically, the re-timer 210 of the reconfigurable logic chip 200 can transmit the host command on which the signal processing is performed to the controller 110 via the first port PT1. Then, in operation S130, the controller 110 can generate input data based on the received host command.

[0060] Then, in operation S135, the reconfigurable logic chip 200 can transmit a polling signal to the controller 110. Specifically, the operation circuit 220 of the reconfigurable logic chip 200 can transmit the polling signal requesting the input data to the controller 110 via the second port PT2. According to an example embodiment, the operation circuit 220 can transmit the polling signal to the controller 110 according to a method agreed upon in advance with the controller 110. According to an example embodiment, the operation circuit 220 can transmit the polling signal to the controller 110 according to a preset period.

[0061] Further, in operation S140, the controller 110 can transmit the input data to the reconfigurable logic chip 200 in response to the polling signal. Specifically, the controller 110 can remain in a standby state after generating the input data. The controller 110 can transmit the input data to the operation circuit 220 of the reconfigurable logic chip 200 via the second port PT2 upon receiving the polling signal from the operation circuit 220. Example embodiments are not limited thereto, and the controller 110 can generate the input data after receiving the polling signal from the operation circuit 220 and transmit the generated input data to the operation circuit 220. According to an example embodiment, the controller 110 can transmit a command indicating an operation requested by the host 300 to the operation circuit 220 together with the input data.

[0062] Then, in operation S150, the reconfigurable logic chip 200 can perform data processing based on the received input data. Specifically, the operation circuit 220 of the reconfigurable logic chip 200 can generate output data by performing an operation corresponding to the received command using the input data. In operation S155, the reconfigurable logic chip 200 can transmit the output data to the controller 110. Specifically, the operation circuit 220 of the reconfigurable logic chip 200 can transmit the output data to the controller 110 via the second port PT2.

[0063] Then, in operation S160, the controller 110 can generate response data based on the output data. Then, in operation S165, the controller 110 can transmit the response data to the reconfigurable logic chip 200. Specifically, the controller 110 can transmit the response data to the re-timer 210 of the reconfigurable logic chip 200 via the first port PT1. Then, in operation S170, the reconfigurable logic chip 200 can perform signal processing on the response data. Specifically, the re-timer 210 of the reconfigurable logic chip 200 can remove jitter of the response data and repair damage to perform signal processing (e.g., adjust the response data) on the response data. Then, in operation S180, the reconfigurable logic chip 200 can transmit the adjusted response data to the host 300. Specifically, the re-timer 210 of the reconfigurable logic chip 200 can transmit the response data on which the signal processing is performed to the host 300.

[0064] Figure 5 is a flowchart of an example of the operation of the reconfigurable logic chip 200 and the controller 110 according to an example embodiment. Specifically, Figure 5 is a modification example of Figure 4 According to an example embodiment, the operation S210 to S230 of Figure 5 The operation S110 to S130 of Figure 4 The operation S110 to S130 of

[0065] Referring to Figure 5 In operation S235, the controller 110 can transmit an interrupt signal to the reconfigurable logic chip 200. Specifically, the controller 110 can transmit the interrupt signal indicating the data transmission schedule to the operation circuit 220 of the reconfigurable logic chip 200 via the second port PT2. According to an example embodiment, the controller 110 can transmit the interrupt signal to the operation circuit 220 according to a method agreed upon in advance with the operation circuit 220.

[0066] Then, in operation S240, the controller 110 can transmit the input data to the reconfigurable logic chip 200. Specifically, the controller 110 can transmit the input data to the operation circuit 220 via the second port PT2 after transmitting the interrupt signal. Example embodiments are not limited thereto, and the controller 110 can generate the input data after transmitting the interrupt signal to the operation circuit 220, and transmit the generated input data to the operation circuit 220. According to an example embodiment, the controller 110 can transmit a command indicating an operation requested by the host 300 to the operation circuit 220 together with the input data. Further, because operations S250 to S280 can be substantially the same as operations S150 to S180 of the storage device group 10, Figure 4 , a repetitive description thereof is omitted.

[0067] As such, because the storage device group 10 according to an example embodiment consistent with Figure 4 and Figure 5 transmits and receives data based on the same protocol, the controller 110 and the reconfigurable logic chip 200 can directly transmit and receive data to and from each other.

[0068] Figure 6 is a block diagram illustrating a configuration of the controller 110 according to an example embodiment. Specifically, Figure 6 is a block diagram of a configuration of the controller 110 of Figure 2 .

[0069] Referring to Figure 6 , the controller 110 includes a processor 111, a host interface (IF) 112, an FPGA IF 113, an NVM IF 114, and a memory 115, which communicate with each other via a bus 116. For example, the reconfigurable logic chip 200 can include an FPGA.

[0070] The processor 111 can include a central processor or a microprocessor, and control overall operations of the controller 110. According to an example embodiment, the processor 111 can be configured as a multi-core processor, and for example, can be configured as a dual-core processor or a quad-core processor. According to an example embodiment, the processor 111 can control overall operations related to a host command received from the host. For example, the processor 111 can generate input data based on the received host command, and generate response data based on the received output data.

[0071] The host IF 112 can provide an IF between the host 300 and the controller 110 via the re-timer 210 of Figure 1 , and for example, can include the first port PT1 of Figure 1 . The FPGA IF 113 can provide an IF between the controller 110 and the operation circuit 220 of the reconfigurable logic chip 200, i.e., the operation circuit 220 of Figure 1 , and for example, can include the second port PT2 of Figure 1a second port PT2 of the controller 110.

[0072] According to an example embodiment, the host IF 112 can receive a host command from the re-timer 210 of the controller 110, and provide the received host command to the processor 111. Also, the FPGA IF 113 can receive input data from the processor 111, and provide the received input data to the operation circuit 220 of the controller 110. Also, the FPGA IF 113 can receive output data from the operation circuit 220 of the controller 110, and provide the received output data to the processor 111. Also, the host IF 112 can receive response data from the processor 111, and provide the received response data to the re-timer 210 of the controller 110. Figure 1 Figure 1 According to an example embodiment, the host IF 112 can receive a host command from the re-timer 210 of the controller 110, and provide the received host command to the processor 111. Also, the FPGA IF 113 can receive input data from the processor 111, and provide the received input data to the operation circuit 220 of the controller 110. Also, the FPGA IF 113 can receive output data from the operation circuit 220 of the controller 110, and provide the received output data to the processor 111. Also, the host IF 112 can receive response data from the processor 111, and provide the received response data to the re-timer 210 of the controller 110. Figure 1 Figure 1 According to an example embodiment, the host IF 112 can receive a host command from the re-timer 210 of the controller 110, and provide the received host command to the processor 111. Also, the FPGA IF 113 can receive input data from the processor 111, and provide the received input data to the operation circuit 220 of the controller 110. Also, the FPGA IF 113 can receive output data from the operation circuit 220 of the controller 110, and provide the received output data to the processor 111. Also, the host IF 112 can receive response data from the processor 111, and provide the received response data to the re-timer 210 of the controller 110.

[0073] The NVM IF 114 can provide an IF between the controller 110 and the NVM 120. The memory 115 operates according to the control of the processor 111, and can be used as an operation memory, a buffer memory, or a cache memory. For example, the memory 115 can be configured as a volatile memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or a NVM such as a phase change random access memory (PRAM) or a flash memory.

[0074] Figure 7 is a block diagram illustrating a configuration of the controller 110' according to an example embodiment. Specifically, Figure 7 is a diagram of a modified example of the controller 110' according to an example embodiment. Figure 6 Referring to

[0075] , the controller 110' includes a processor 111', a host IF 112, an FPGA IF 113, an NVM IF 114, a memory 115, and a volatile memory (VM) IF 117 which communicate with each other via a bus 116. Hereinafter, differences between the controller 110' and the controller 110 will be mainly described. Figure 7 Figure 6

[0076] The VM IF 117 can provide an IF between the controller 110' and a VM (for example, a VM included in a storage device disposed outside the controller 110'). According to an example embodiment, the processor 111' can transmit data to and receive data from the operation circuit 220 of the controller 110' via the VM IF 117. Also, the processor 111' can transmit data to and receive data from the VM via the VM IF 117. Figure 1 Figure 1 ​​​​​The operating circuit 220 of the storage device 100a uses the VM during an operation period of receiving data. For example, the processor 111' can generate input data based on a received host command, and load the generated input data on the VM via the VM IF 117. Also, the processor 111' can read output data generated by the operating circuit 220 of the storage device 100a from the VM via the VM IF 117. Detailed descriptions thereof will be described with reference to Figure 1 Figure 8

[0077] Figure 8 is a block diagram for describing an operating method of the storage device group 10a according to an example embodiment. In other words, the storage device group 10a can include the controller 110' including Figure 8 Figure 7 is a diagram of the storage device group 10a including the controller 110' of Figure 7 In other words, the controller 110a can be substantially the same as the controller 110' of Figure 8 The storage device group 10a can include the VM 400a, which can be connected to the controller 110a via the VM IF 117 of Figure 7 The VM 400a can include a VM such as a DRAM according to an example embodiment. The storage device group 10a can include the reconfigurable logic chip 200a and the storage device 100a.

[0078] The reconfigurable logic chip 200a and the storage device 100a can make a prior agreement on a specific memory region, and transmit and receive data by using the agreed memory region. For example, the reconfigurable logic chip 200a and the storage device group 10a can load data to be transmitted on an agreed memory region, and read data to be received from the agreed memory region.

[0079] According to an example embodiment, the memory region agreed between the reconfigurable logic chip 200a and the storage device 100a can be a partial region of the VM 400a of the storage device 100a. The reconfigurable logic chip 200a and the storage device 100a can each store an address regarding the partial region of the VM 400a, and access the partial region of the VM 400a based on the stored address when data transmission and reception is required.

[0080] The host 300 can transmit a host command to the storage device group 10a with reference to Figure 8 According to an example embodiment, the host 300 can transmit the host command to the re-timer 210, the re-timer 210 can adjust the host command, and transmit the adjusted host command to the controller 110a via the first port PT1 (operation ①).

[0081] Then, the controller 110a can generate a command indicating an operation requested by the host 300 based on the host command, and input data required to perform the operation requested by the host 300.​​​

[0082] Then, the controller 110a can load the input data on the VM 400a (operation ②). According to an example embodiment, the controller 110a can load the input data on a portion of the VM 400a that is agreed in advance with the reconfigurable logic chip 200a. Next, the operation circuit 220a can obtain the input data by accessing the VM 400a via the second port PT2 (operation ③). According to an example embodiment, the controller 110a can transmit a command indicating an operation requested by the host 300 to the operation circuit 220a via the second port PT2. Then, the operation circuit 220a can perform the operation by using the input data, by accessing the VM 400a via the Figure 7 VM IF 117 of the host 300 and the root connecting the third port PT3 and the second port PT2. Then, the operation circuit 220a can perform the operation by using the input data. The operation circuit 220a can generate output data by performing the operation.

[0083] Next, the operation circuit 220a can load the output data on the VM 400a via the second port PT2 (operation ④). According to an example embodiment, the operation circuit 220a can load the output data on the portion of the VM 400a that is agreed in advance with the reconfigurable logic chip 200a, by accessing the VM 400a via the Figure 7 VM IF 117 of the host 300 and the root connecting the third port PT3 and the second port PT2. Then, the controller 110a can obtain the output data from the VM 400a (operation ⑤). According to an example embodiment, the controller 110a can read the output data from the portion of the VM 400a that is agreed in advance with the reconfigurable logic chip 200a. Then, the controller 110a can generate response data regarding the host command based on the output data.

[0084] Next, the controller 110a can transmit the response data to the host 300 (operation ⑥). According to an example embodiment, the controller 110a can transmit the response data to the re-timer 210, which can adjust the response data and transmit the adjusted response data to the host 300 via the first port PT1.

[0085] Figure 9 is a block diagram for describing an operation method of the storage device group 10b according to an example embodiment. Specifically, Figure 9 is a diagram of a modified example of the Figure 8 according to an example embodiment. Referring to Figure 9According to the current embodiment, the storage device group 10b can include a VM 400b, which can be connected to the reconfigurable logic chip 200b via a VM IF of the reconfigurable logic chip 200b and can not be connected to the controller 110b. According to an example embodiment, the VM 400b can include a VM such as a DRAM.

[0086] The reconfigurable logic chip 200b and the storage device 100b can pre-appoint a specific memory region and transmit and receive data by using the appointed memory region. The memory region appointed between the reconfigurable logic chip 200b and the storage device 100b can be a partial region of the VM 400b of the storage device 100b.

[0087] Referring to Figure 9 The host 300 can transmit a host command to the storage device group 10b. According to an example embodiment, the host 300 can transmit the host command to the re-timer 210, which can adjust the host command and transmit the adjusted host command to the controller 110b via the first port PT1 (operation ①). Then, the controller 110b can generate a command indicating an operation requested by the host 300 based on the host command and input data required to perform the operation requested by the host 300.

[0088] Next, the controller 110b can load the input data on the VM 400b via the second port PT2 (operation ②). According to an example embodiment, the controller 110b can access the VM 400b via the VM IF of the reconfigurable logic chip 200b and a root connecting the second port PT2 and the third port PT3 and load the input data on a pre-appointed region of the VM 400b.

[0089] The operation circuit 220b can obtain the input data from the VM 400b (operation ③). According to an example embodiment, the controller 110b can transmit the command indicating the operation requested by the host 300 to the operation circuit 220b via the second port PT2. Then, the operation circuit 220b can read the input data from a partial region of the VM 400b pre-appointed with the storage device 100b. Then, the operation circuit 220b can perform an operation by using the input data. The operation circuit 220b can generate output data by performing the operation.

[0090] Next, the operation circuit 220b can load the output data on the VM 400b (operation ④). According to an example embodiment, the operation circuit 220b can load the output data on a portion region of the VM 400b agreed in advance with the storage apparatus 100b. Next, the controller 110b can obtain the output data by accessing the VM 400b through the second port PT2 (operation ⑤). According to an example embodiment, the controller 110b can access the VM 400b through the VM IF of the reconfigurable logic chip 200b and the root connecting the second port PT2 and the third port PT3, and read the output data from the portion region agreed in advance of the VM 400b. Then, the controller 110b can generate response data on the host command based on the output data.

[0091] Next, the controller 110b can transmit the response data to the host 300 (operation ⑥). According to an example embodiment, the controller 110b can transmit the response data to the re-timer 210, which can adjust the response data and transmit the adjusted response data to the host 300 through the first port PT1.

[0092] Figure 10 is a flowchart of an example of the operations of the VMs 400a and 400b, the reconfigurable logic chips 200a and 200b, and the controllers 110a and 110b according to an example embodiment. Specifically, Figure 10 is a flowchart of an example of the operations of the VMs 400a and 400b, the reconfigurable logic chips 200a and 200b, and the controllers 110a and 110b.

[0093] Referring to Figure 10 In operation S300, the reconfigurable logic chips 200a and 200b can receive the host command. Specifically, the re-timers 210 of the reconfigurable logic chips 200a and 200b can receive the host command. Then, the reconfigurable logic chips 200a and 200b can perform signal processing on the host command. Specifically, the re-timers 210 of the reconfigurable logic chips 200a and 200b can remove jitter of the host command and repair damage to perform signal processing (e.g., adjustment) on the host command.

[0094] Then, in operation S305, the reconfigurable logic chips 200a and 200b can transmit the adjusted host command to the controllers 110a and 110b. Specifically, the re-timers 210 of the reconfigurable logic chips 200a and 200b can transmit the host command on which the signal processing is performed to the controllers 110a and 110b through the first port PT1. Then, in operation S310, the controllers 110a and 110b can generate input data based on the received host command.

[0095] Then, in operation S315, the controllers 110a and 110b can transmit the input data to the VMs 400a and 400b. Specifically, the controllers 110a and 110b can transmit the input data along with a command requesting to write the input data to a portion of the VMs 400a and 400b that are previously agreed with the reconfigurable logic chips 200a and 200b to the VMs 400a and 400b.

[0096] Then, in operation S320, the VMs 400a and 400b can load the input data. Next, in operation S325, the VMs 400a and 400b can transmit a response message indicating completion of the loading to the controllers 110a and 110b. Specifically, the VMs 400a and 400b can load the input data on the previously agreed region, and transmit a response message indicating completion of the loading to the controllers 110a and 110b. Then, in operation S330, the controllers 110a and 110b can transmit a command indicating an operation requested by the host 300 to the reconfigurable logic chips 200a and 200b.

[0097] Then, in operation S335, the reconfigurable logic chips 200a and 200b can transmit a read command to the VMs 400a and 400b. Specifically, the operation circuits 220a and 220b of the reconfigurable logic chips 200a and 200b can transmit a read command requesting to read data written in an address of the previously agreed region to the VMs 400a and 400b in response to the received command.

[0098] Then, in operation S340, the VMs 400a and 400b can read the input data. Next, in operation 345, the VMs 400a and 400b can transmit the read input data to the reconfigurable logic chips 200a and 200b. Specifically, the VMs 400a and 400b can read the input data loaded on the previously agreed region, and transmit the read input data to the operation circuits 220a and 220b of the reconfigurable logic chips 200a and 200b.

[0099] Then, in operation S350, the reconfigurable logic chips 200a and 200b can perform data processing based on the received input data. Specifically, the operation circuits 220a and 220b of the reconfigurable logic chips 200a and 200b can generate output data by performing operations corresponding to the received command using the input data. In operation S355, the reconfigurable logic chips 200a and 200b can transmit the output data to the controllers 110a and 110b. Specifically, the operation circuits 220a and 220b of the reconfigurable logic chips 200a and 200b can transmit the output data to the VMs 400a and 400b together with a command requesting to write the output data to a portion of the region of the storage devices 100a and 100b previously agreed with the VMs 400a and 400b.

[0100] Then, in operation S360, the VMs 400a and 400b can load the output data. Next, in operation S365, the VMs 400a and 400b can transmit a response message indicating completion of the loading to the reconfigurable logic chips 200a and 200b. Specifically, the VMs 400a and 400b can load the output data on the previously agreed region and transmit a response message indicating completion of the loading to the operation circuits 220a and 220b of the reconfigurable logic chips 200a and 200b.

[0101] Then, in operation S370, the reconfigurable logic chips 200a and 200b can transmit a response message indicating completion of the operation to the controllers 110a and 110b. Specifically, the operation circuits 220a and 220b of the reconfigurable logic chips 200a and 200b can transmit a response message indicating completion of the operation to the controllers 110a and 110b. Then, in operation S375, the controllers 110a and 110b can transmit a read command to the VMs 400a and 400b. Specifically, the controllers 110a and 110b can transmit a read command requesting to read data written to an address of the previously agreed region to the VMs 400a and 400b.

[0102] Then, in operation S380, the VMs 400a and 400b can read the output data. Next, in operation S385, the VMs 400a and 400b can transmit the read output data to the controllers 110a and 110b. Specifically, the VMs 400a and 400b can read the output data loaded on the previously agreed region and transmit the read output data to the controllers 110a and 110b.

[0103] Then, in operation S390, the controllers 110a and 110b can generate response data based on the output data. Then, in operation S395, the controllers 110a and 110b can transmit the response data to the reconfigurable logic chips 200a and 200b. Specifically, the controllers 110a and 110b can transmit the response data to the re-timers 210 of the reconfigurable logic chips 200a and 200b via the first ports PT1. Then, in operation S400, the reconfigurable logic chips 200a and 200b can transmit the response data to the host 300. Specifically, the re-timers 210 of the reconfigurable logic chips 200a and 200b can remove jitter of the response data and repair damage to perform signal processing (e.g., adjust the response data) on the response data. Then, the re-timers 210 of the reconfigurable logic chips 200a and 200b can transmit the adjusted response data to the host 300.

[0104] As such, because Figure 10 The storage device group according to the example embodiment uses a VM, so even when the host 300, the controllers 110a and 110b, and the reconfigurable logic chips 200a and 200b operate based on different protocols, they can communicate with each other.

[0105] Figure 11 is a block diagram that illustrates the storage device group 10c according to the example embodiment in detail. Specifically, Figure 11 is a block diagram that illustrates a modified example of the storage device group 10 of Figure 2 According to the example embodiment. Referring to Figure 11 , the storage device group 10c can include the storage device 100c and the reconfigurable logic chip 200c. The storage device 100c can include the controller 110c and the NVM 120, and the reconfigurable logic chip 200c can include the re-timer 210 and the operation circuit 220c.

[0106] Referring to Figure 11 , the controller 110c can include a fourth port PT4 in addition to the first port PT1 connected to the re-timer 210 and the second port PT2 connected to the third port PT3. The reconfigurable logic chip 200c can include a fifth port PT5 connected to the operation circuit 220c and distinguished from the third port PT3. The storage device group 10c can include a root that connects the fourth port PT4 and the fifth port PT5. Here, the root that connects the fourth port PT4 and the fifth port PT5 can perform a function of connecting a side band of the storage device 100c and the reconfigurable logic chip 200c, and can be an I2C / SM bus.

[0107] The controller 110c can receive a host command via the re-timer 210 and the first port PT1. Then, the controller 110c can generate a command indicating an operation requested by the host 300 and input data required to perform the operation requested by the host 300 in response to the received host command.

[0108] Then, the controller 110c can provide the command to the operation circuit 220c via the fourth port PT4 instead of the second port PT2. According to an example embodiment, the controller 110c can transmit the command to the operation circuit 220c via a root (e.g., an I2C / SM bus) connecting the fourth port PT4 and the fifth port PT5.

[0109] Then, the controller 110c can transmit the input data to the operation circuit 220c via the second port PT2. According to an example embodiment, when the host 300 and the storage group 10c operate based on the same protocol (e.g., an NVMe protocol), the controller 110c can directly transmit the input data to the operation circuit 220c via a root (e.g., a PCIe bus) connecting the second port PT2 and the third port PT3.

[0110] Then, the operation circuit 220c can perform an operation corresponding to the request of the host 300 based on the input data and the command received via different roots. According to an example embodiment, the operation circuit 220c can perform an operation corresponding to the command received via the fourth port PT4 and the fifth port PT5 by using the input data received via the second port PT2 and the third port PT3. The operation circuit 220c can generate output data based on the NVMe protocol by performing the operation.

[0111] Next, the operation circuit 220c can transmit the output data to the controller 110c via the second port PT2. According to an example embodiment, the operation circuit 220c can directly transmit the output data to the controller 110c via the third port PT3 and the second port PT2.

[0112] Figure 12 is a block diagram illustrating a storage group 10d according to an example embodiment in detail. Specifically, Figure 12 is a block diagram illustrating a modification example of the storage group 10c according to an example embodiment. Figure 11 is a block diagram illustrating a modification example of the storage group 10c according to an example embodiment. Referring to Figure 12 The storage group 10d can further include a VM 400d. The VM 400d can be connected to the controller 110d via a VM IF of the controller 110d, and can not be connected to the reconfigurable logic chip 200d. According to an example embodiment, the VM 400d can include a VM such as a DRAM.

[0113] Referring to Figure 12The controller 110d can receive the host command via the retimer 210 and the first port PT1. Then, the controller 110d can generate a command indicating an operation requested by the host 300 and input data required to perform the operation requested by the host 300 in response to the received host command.

[0114] Then, the controller 110d can provide the command to the operation circuit 220d via the fourth port PT4 instead of the second port PT2. According to an example embodiment, the controller 110d can transmit the command to the operation circuit 220d via a root (e.g., an I2C / SM bus) connecting the fourth port PT4 with the fifth port PT5.

[0115] Then, the controller 110d can store the input data in the VM 400d. According to an example embodiment, the controller 110d can store the input data in a portion of the VM 400d agreed in advance with the reconfigurable logic chip 200d. Next, the operation circuit 220d can obtain the input data by accessing the VM 400d via the second port PT2 instead of the fourth port PT4. According to an example embodiment, the operation circuit 220d can obtain the input data by accessing the agreed portion of the VM 400d via the VM IF and a root connecting the third port PT3 with the second port PT2. Then, the operation circuit 220d can perform the operation by using the input data. The operation circuit 220d can generate output data by performing the operation.

[0116] Next, the operation circuit 220d can store the output data on the VM 400d via the second port PT2. According to an example embodiment, the operation circuit 220d can store the output data in the agreed portion of the VM 400d by accessing the VM 400d via the VM IF and a root connecting the third port PT3 with the second port PT2. Then, the controller 110d can obtain the output data from the VM 400d. According to an example embodiment, the controller 110d can read the output data from the portion of the VM 400d agreed in advance with the reconfigurable logic chip 200d.

[0117] Figure 13 is a block diagram illustrating a storage device group 10e according to an example embodiment in detail. Specifically, Figure 13 is a block diagram illustrating a modification example of the storage device group 10d according to an example embodiment. Referring to Figure 12 is a block diagram illustrating a modification example of the storage device group 10d according to an example embodiment. Referring to Figure 13 The storage device group 10e can additionally include a VM 400e. The VM 400e can be connected to the operation circuit 220e via the VM IF of the reconfigurable logic chip 200e, and can not be connected to the controller 110e. According to an example embodiment, the VM 400e can include a VM such as a DRAM.

[0118] Referring to Figure 13 , the controller 110e can receive the host command via the re-timer 210 and the first port PT1. Then, the controller 110e can generate a command indicating an operation requested by the host 300 and input data required to perform the operation requested by the host 300 in response to the received host command.

[0119] Then, the controller 110e can provide the command to the operation circuit 220e via the fourth port PT4 instead of the second port PT2. According to an example embodiment, the controller 110e can transmit the command to the operation circuit 220e via a root (e.g., an I2C / SM bus) connecting the fourth port PT4 and the fifth port PT5.

[0120] Next, the controller 110e can store the input data in the VM 400e via the second port PT2. According to an example embodiment, the controller 110e can access the VM 400e via the VM IF of the reconfigurable logic chip 200e and a root (e.g., a PCIe bus) connecting the second port PT2 and the third port PT3, and store the input data in a pre-agreed area of the VM 400e.

[0121] Then, the operation circuit 220e can read the input data from the pre-agreed area of the VM 400e. Then, the operation circuit 220e can perform an operation by using the input data. The operation circuit 220e can generate output data by performing the operation. Next, the operation circuit 220e can store the output data in the pre-agreed area of the VM 400e.

[0122] Next, the controller 110e can obtain the output data by accessing the VM 400e via the second port PT2. According to an example embodiment, the controller 110e can access the VM 400e via the VM IF of the reconfigurable logic chip 200e and a root connecting the second port PT2 and the third port PT3, and read the output data from the pre-agreed area of the VM 400e.

[0123] As such, the storage apparatus 100e according to Figure 13 may respectively include a root for transmitting data to and receiving data from the host 300, a root for transmitting a command to the reconfigurable logic chip 200e, and a root for transmitting input data to the reconfigurable logic chip 200e.

[0124] Figure 14 is a block diagram illustrating in detail a storage apparatus group 10f according to an example embodiment. As with Figure 1The storage device group 10f can be configured such that the re-timer 500 is disposed outside the reconfigurable logic chip 600, differently from the storage device group 10. According to an example embodiment, the storage device 100 can be implemented via a first chip, the reconfigurable logic chip 200 can be implemented via a second chip, and the re-timer 500 can be implemented via a third chip, wherein the first chip to the third chip can configure a package on package (POP). The controller 110f of the storage device 100f can include a first port PT1 and a second port PT2, and the reconfigurable logic chip 600 can include the operation circuit 610 and a third port PT3. According to an example embodiment, the storage device group 10f can include a root (e.g., a PCIe bus) connecting the second port PT2 and the third port PT3.

[0125] One end of the re-timer 500 can be connected to the host 300, and the other end of the re-timer 500 can be connected to the first port PT1 of the controller 110f. Accordingly, the re-timer 500 can perform transmission and reception of data between the host 300 and the controller 110f. The re-timer 500 can receive a host command from the host 300, adjust the received host command, and transmit the adjusted host command to the controller 110f via the first port PT1. Then, the re-timer 500 can receive response data from the controller 110f via the first port PT1, adjust the received response data, and transmit the adjusted response data to the host 300. According to an example embodiment, the controller 110f can include a host IF including the first port PT1. The host IF of the controller 110f can communicate with the re-timer 500 according to a first interface protocol.

[0126] The controller 110f can transmit and receive data to and from the operation circuit 610 via the second port PT2. According to an example embodiment, the controller 110f can transmit and receive data to and from the operation circuit 610 via a bus connecting the second port PT2 and the third port PT3. According to an example embodiment, the controller 110f can include an FPGA IF including the second port PT2. The FPGA IF of the controller 110f can communicate with the operation circuit 610 via a second interface protocol. The method of transmitting and receiving data to and from the operation circuit 610 via the second port PT2 performed by the controller 110f can be the same as the method of transmitting and receiving data to and from the operation circuit 610 via the second port PT2 described above with reference to FIGS. 1 to 6. Figure 3 、 Figure 8 and Figure 9The described method is substantially the same. In other words, the controller 110f can transmit and receive the generated data to and from the operation circuit 610 directly via the second port PT2 based on the same protocol. Alternatively, the controller 110f can access a region (e.g., a partial region of a VM) agreed in advance with the reconfigurable logic chip 600 via the second port PT2. Then, the controller 110f can transmit data to or receive data from the operation circuit 610 by storing data in the region agreed in advance or reading data stored in the region agreed in advance.

[0127] Figure 15 is a flowchart of an operation method of a storage device according to an example embodiment. Specifically, the operation method of the storage device can include operations performed by Figure 3 the storage device 100 of FIG. 1, Figure 8 the storage device 100a of FIG. 2, Figure 9 the storage device 100b of FIG. 3, Figure 11 the storage device 100c of FIG. 4, Figure 12 the storage device 100d of FIG. 5, Figure 13 the storage device 100e of FIG. 6, and Figure 14 the storage device 100f of FIG. 7 in a time sequence.

[0128] Referring to Figure 15 , the storage device can receive a request of a host via a first port connected to a re-timer (operation S410). According to an example embodiment, the storage device can receive data related to a host command along with the host command via the first port. According to an example embodiment, the storage device can receive the data related to the host command via the first port after receiving the host command via the first port.

[0129] Then, the storage device can generate input data corresponding to the received request (operation S420). According to an example embodiment, the storage device can generate a command indicating an operation requested by the host and input data required to perform the operation requested by the host in response to the host command received via the re-timer and the first port.

[0130] Then, the storage device can provide the input data to an operation circuit via a second port connected to the operation circuit (operation S430). According to an example embodiment, the storage device can transmit the command along with the input data to the operation circuit. According to an example embodiment, the storage device can transmit the command to the operation circuit and then transmit the input data to the operation circuit consecutively. According to an example embodiment, the storage device can generate the input data according to a preset protocol and transmit the generated input data directly to the operation circuit via the second port. According to an example embodiment, the storage device can store the input data in a region (e.g., a VM) agreed in advance with a reconfigurable logic chip via the second port.

[0131] Then, the storage device can obtain output data corresponding to the input data from the operation circuit via the second port (operation S440). According to an example embodiment, the storage device can directly receive the output data generated by the operation circuit according to the preset protocol via the second port. According to an example embodiment, the storage device can obtain the output data by reading the output data stored in an area (e.g., a VM) previously agreed with the reconfigurable logic chip via the second port.

[0132] Further, the storage device can generate response data corresponding to the received request based on the output data (operation S450). Next, the storage device can transmit the response data to the host via the first port (operation S460). According to an example embodiment, the storage device can transmit the response data to the host via the first port and the re-timer.

[0133] As such, the storage device can transmit and receive data to and from the host via the first port and the re-timer, and can transmit and receive data to and from the reconfigurable logic chip by connecting to the operation circuit of the reconfigurable logic chip via the second port.

[0134] Further, the storage device group can minimize input and output delays by transmitting and receiving data using the re-timer that performs data transmission and reception via the physical layer, instead of the switch that performs data transmission and reception via a plurality of layers.

[0135] Figure 16 is a diagram of a network system 1000 according to an example embodiment.

[0136] Referring to Figure 16 , the network system 1000 can include a server system 1100 and a plurality of terminals 1210 to 1230 (e.g., terminal 1, terminal 2, …, terminal n, n is a natural number greater than 2) that communicate with the server system 1100 via a network NET. The server system 1100 can include a server 1110 and an SSD 1120. Here, the SSD 1120 can correspond to the storage device 100, 100a, 100b, 100c, 100d, 100e, or 100f of the above-described example embodiments. According to some example embodiments, the SSD 1120 can be implemented by using the above-described example embodiments with reference to Figures 1 to 15 .

[0137] As such, the storage device can transmit and receive data to and from the host via the first port and the re-timer, and can transmit and receive data to and from the reconfigurable logic chip by connecting to the operation circuit of the reconfigurable logic chip via the second port. Figures 1 to 3 , Figures 5 to 9 and Figures 11 to 14The at least one of the re-timer, reconfigurable logic chip, operation circuit, controller, processor, and other elements represented by the blocks shown in the drawings can be implemented as various numbers of hardware, software, and / or firmware structures that perform the above-described corresponding functions according to exemplary embodiments. For example, the at least one of the re-timer, reconfigurable logic chip, operation circuit, controller, processor, and other elements can use a direct circuit structure such as a memory, a processor, a logic circuit, a look-up table, etc. that can perform the corresponding function by control of one or more microprocessors or other control apparatuses. Also, the at least one of the re-timer, reconfigurable logic chip, operation circuit, controller, processor, and other elements can be specifically embodied by a part of a module, a program, or a code, which contains one or more executable instructions for performing specified functions. Also, the at least one of the re-timer, reconfigurable logic chip, operation circuit, controller, processor, and other elements can further include or can be implemented by a processor (such as a central processing unit (CPU), a microprocessor, etc.) that performs the corresponding function. Two or more of the re-timer, reconfigurable logic chip, operation circuit, controller, processor, and other elements can be combined into one single component, element, module, or unit that performs all operations or functions of the two or more of the re-timer, reconfigurable logic chip, operation circuit, controller, processor, and other elements. Also, at least part of functions of the at least one of the re-timer, reconfigurable logic chip, operation circuit, controller, processor, and other elements can be performed by another of the components. Further, although not shown in each of the block diagrams above, communication between the components can be performed through a bus. Functional aspects of the above example embodiments can be implemented in algorithms that are executed on one or more processors. Furthermore, the re-timer, reconfigurable logic chip, operation circuit, controller, processor, or other elements, or processing steps represented by blocks can employ any number of technologies for electronic configuration, signal processing and / or control, data processing, and so on.

[0138] While example embodiments have been described, it will be understood that various changes and modifications can be made therein without departing from the spirit and scope of the claims.

Claims

1. A storage device group comprising: a first chip including: a re-timer configured to generate an output signal by adjusting an input signal received from an external device, and an operation circuit configured to perform an operation function; and a second chip separate from the first chip and including: a non-volatile memory, a first port connected to the re-timer, a second port connected to the operation circuit, and a controller configured to: control transmission and reception of data via the first port and the second port, generate input data based on a request received from a host via the re-timer and the first port, and provide the input data to the operation circuit via the second port.

2. The storage device group of claim 1, wherein, The controller is further configured to: transmit and receive data to and from the host via a first connection between the re-timer and the first port; and transmit and receive data to and from the operation circuit via a second connection between the operation circuit and the second port.

3. The storage device set of claim 1, wherein, The operation circuit is further configured to: generate output data by performing an operation corresponding to the received request using the input data, and provide the output data to the controller via the second port.

4. The storage device set of claim 3, wherein, The controller is further configured to: generate response data corresponding to the received request based on the output data, and transmit the response data to the host via the re-timer and the first port.

5. The storage device set of claim 4, wherein, The controller is further configured to: store the input data in a memory area that is publicly accessible by the operation circuit via the second port.

6. The storage device set of claim 5, wherein, The operation circuit is further configured to: read the input data by accessing the memory area, and store the output data in the memory area.

7. The storage device set of claim 6, wherein, The controller is further configured to: read the output data by accessing the memory area, and generate the response data corresponding to the received request based on the output data.

8. The storage device set of claim 5, wherein, The memory area is provided in a volatile memory in the first chip or a volatile memory in the second chip.

9. The storage device set of claim 4, wherein, The controller and the operation circuit are configured to perform the operation based on a non-volatile memory express (NVMe) protocol, and wherein the controller is further configured to: generate the input data based on the NVMe protocol, and directly transmit the input data to the operation circuit via the second port.

10. The storage device set of claim 9, wherein, The controller is further configured to: directly transmit the input data to the operation circuit via the second port based on the request and a polling signal received from the operation circuit via the second port.

11. The set of storage devices of claim 9, wherein, The controller is further configured to: directly transmit an interrupt signal indicating a data transfer schedule to the operation circuit via the second port, and directly transmit the input data to the operation circuit via the second port.

12. The storage device set of claim 9, wherein, The operation circuit is further configured to: generate the output data by performing the operation corresponding to the received request based on the NVMe protocol, and directly transmit the output data to the controller via the second port.

13. The storage device set of claim 1, wherein, The controller is further configured to: generate a control command based on the request received from the host via the first port, and transmit the generated control command to the operation circuit via a third port different from the first port and the second port.

14. The set of storage devices of claim 13, wherein, The controller and the operation circuit are configured to: transmit and receive data related to the control command via the second port. 15.A storage system comprising: a host; A first chip includes a re-timer and an operation circuit, wherein the re-timer is communicatively connected with a host; and A second chip, separate from the first chip, includes a non-volatile memory and a controller, wherein the controller is configured to: receive a request from the host via the re-timer, and generate input data corresponding to the received request, wherein the first chip is configured to: receive the input data from the second chip, generate output data by performing an operation corresponding to the received request using the input data, and provide the output data to the second chip.

16. The storage system of claim 15, wherein, The second chip includes: A first interface, communicatively connected with the re-timer; and A second interface, communicatively connected with the first chip.

17. An operation method of a second chip connected to a first chip, the first chip being separate from the second chip and including a re-timer and an operation circuit, the second chip including a non-volatile memory, a first port connected to the re-timer, and a second port connected to the operation circuit, the operation method comprising: receiving a request of a host via the first port; generating input data corresponding to the received request; providing the input data to the operation circuit via the second port; obtaining output data corresponding to the input data from the operation circuit via the second port; generating response data corresponding to the received request based on the output data; and sending the generated response data to the host via the first port and the re-timer. The step of providing the input data to the operation circuit includes storing the input data in a memory area that is commonly accessible by the second chip and the first chip, and 18. The method of operation of claim 17, wherein, wherein the step of obtaining the output data from the operation circuit includes identifying the output data stored in the memory area. The step of generating the input data includes generating the input data according to a non-volatile memory express protocol, 19. The method of operating according to claim 17, wherein, wherein the step of providing the input data to the operation circuit includes directly sending the input data to the operation circuit via the second port, and wherein the step of obtaining the output data from the operation circuit includes directly obtaining the output data generated according to the non-volatile memory express protocol from the operation circuit via the second port. ​

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