A semiconductor discharge tube, a manufacturing method thereof, and an overvoltage protection device
By forming grooves on the semiconductor substrate and diffusing the third conductive type diffusion region, the problem of high residual pressure during lightning surge of the semiconductor discharge tube is solved, and lower residual pressure and higher flow capacity are achieved, reducing process difficulty.
Patent Information
- Application Number
- CN202110712130.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-06-25
- Publication Date
- 2025-07-22
- Estimated Expiration
- 2041-06-25
AI Technical Summary
The residual pressure of existing semiconductor discharge tubes is higher during lightning surges, resulting in an increased risk of equipment damage.
A groove is formed on one side of the semiconductor substrate, and a diffusion region of the third conductive type is formed along the groove, thereby increasing the diffusion depth and reducing the body region thickness, thereby reducing the series resistance in the chip body.
It effectively reduces the residual pressure during lightning surges, protects the equipment from damage, improves the flow capacity of semiconductor discharge tubes and reduces process difficulty.
Smart Images
Figure CN113314594B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor discharge tube, a manufacturing method thereof, and an overvoltage protection device. Background Art
[0002] A semiconductor discharge tube (Thyristor Sure Suppresser, abbreviated as TSS), also known as a solid discharge tube, is a switching type overvoltage protection device. The semiconductor discharge tube can be connected in parallel at both ends of the power receiving device. When overvoltage such as lightning strike and surge interference occurs, the semiconductor discharge tube will conduct to discharge the surge voltage and surge current, thereby protecting the subsequent power receiving device and preventing the power receiving device from being damaged due to high surge voltage.
[0003] The semiconductor discharge tube is made using the thyristor principle and relies on the breakdown current of the PN junction to trigger the device to conduct and discharge, and can pass a large surge current or pulse current. In the prior art, when a lightning surge occurs, the residual voltage of the semiconductor discharge tube is relatively high. Summary of the Invention
[0004] Embodiments of the present invention provide a semiconductor discharge tube, a manufacturing method thereof, and an overvoltage protection device to reduce the residual voltage during lightning surges.
[0005] In a first aspect, an embodiment of the present invention provides a manufacturing method of a semiconductor discharge tube, including:
[0006] Providing a semiconductor substrate of a first conductivity type, the semiconductor substrate including at least one device unit area;
[0007] In any one of the device unit areas, forming a first diffusion region and a second diffusion region of a second conductivity type on the semiconductor substrate, the first diffusion region and the second diffusion region being separated by a body region of the first conductivity type of the semiconductor substrate; wherein, the first conductivity type and the second conductivity type are different;
[0008] In any one of the device unit areas, forming a groove on one side of the semiconductor substrate, wherein the groove and the first diffusion region are on the same side of the semiconductor substrate;
[0009] Diffusing into the semiconductor substrate along the groove to form a third diffusion region of the first conductivity type, wherein the third diffusion region is in contact with both the first diffusion region and the body region of the semiconductor substrate;
[0010] In any one of the device unit areas, forming a fourth diffusion region of the first conductivity type in the first diffusion region, wherein the third diffusion region and the fourth diffusion region are spaced apart;
[0011] In any device unit region, a corresponding first conductive block is formed, wherein the first conductive block is electrically connected to the first diffusion region and the fourth diffusion region, and on the shortest current flow path from the third diffusion region to the nearest short-circuit point through the first diffusion region, it passes through that part of the first diffusion region in contact with the fourth diffusion region; wherein the short-circuit point is the contact part between the first diffusion region and the first conductive block.
[0012] Electrically connect the first conductive block and the second diffusion region in any device unit region to different electrodes.
[0013] Furthermore, the depth of the groove is greater than or equal to the depth of the first diffusion region, wherein the depth direction of the groove is parallel to the thickness direction of the semiconductor substrate, and the depth direction of the first diffusion region is parallel to the thickness direction of the semiconductor substrate.
[0014] Furthermore, the third diffusion region is arranged around the groove, the first diffusion region is arranged around the third diffusion region, and a plurality of short-circuit points are arranged at intervals in the fourth diffusion region, and the plurality of short-circuit points are located around the third diffusion region.
[0015] Furthermore, in any device unit region, the first diffusion region and the second diffusion region are located on opposite sides of the semiconductor substrate; the first diffusion region and the second diffusion region are opposite along the thickness direction of the semiconductor substrate.
[0016] There are at least two device unit regions, and the at least two device unit regions include an adjacent first device unit region and a second device unit region; the first diffusion region of the first device unit region and the second diffusion region of the second device unit region are located on the same side of the semiconductor substrate.
[0017] In the adjacent first device unit region and second device unit region, the first diffusion region and the second diffusion region located on the same side of the semiconductor substrate are connected and communicated as the same diffusion region.
[0018] Furthermore, the doping concentration of the third diffusion region is greater than the doping concentration of the body region; the third diffusion region and the second diffusion region are arranged at intervals.
[0019] In any device unit region, the depth of the fourth diffusion region is less than the depth of the first diffusion region; the depth direction of the fourth diffusion region is parallel to the thickness direction of the semiconductor substrate.
[0020] The first conduction type is electron type, and the second conduction type is hole type; or, the first conduction type is hole type, and the second conduction type is electron type.
[0021] In a second aspect, an embodiment of the present invention further provides a semiconductor discharge tube, including:
[0022] A semiconductor substrate of a first conductivity type, the semiconductor substrate including at least one device unit region; in any device unit region, a first diffusion region and a second diffusion region of a second conductivity type are disposed on the semiconductor substrate, and the first diffusion region and the second diffusion region are separated by a body region of the first conductivity type of the semiconductor substrate; wherein, the first conductivity type and the second conductivity type are different; a groove is disposed on one side of the semiconductor substrate, wherein the groove and the first diffusion region are on the same side of the semiconductor substrate; a third diffusion region of the first conductivity type extending into the semiconductor substrate along the groove, wherein the third diffusion region is in contact with both the first diffusion region and the body region of the semiconductor substrate; a fourth diffusion region of the first conductivity type is disposed in the first diffusion region, wherein the third diffusion region and the fourth diffusion region are spaced apart;
[0023] In any device unit region, a corresponding first conductive block is disposed, wherein the first conductive block is electrically connected to the first diffusion region and the fourth diffusion region, and on the shortest current flow path from the third diffusion region through the first diffusion region to the nearest short-circuit point, it passes through that part of the first diffusion region in contact with the fourth diffusion region; wherein, the short-circuit point is the contact part between the first diffusion region and the first conductive block;
[0024] Two electrodes, in any device unit region, the first conductive block and the second diffusion region are electrically connected to different electrodes.
[0025] Further, the depth of the groove is greater than or equal to the depth of the first diffusion region, wherein the depth direction of the groove is parallel to the thickness direction of the semiconductor substrate, and the depth direction of the first diffusion region is parallel to the thickness direction of the semiconductor substrate.
[0026] Further, the third diffusion region surrounds the groove, the first diffusion region surrounds the third diffusion region, and a plurality of spaced short-circuit points are disposed in the fourth diffusion region, and the plurality of short-circuit points are located around the third diffusion region.
[0027] Further, in any device unit region, the first diffusion region and the second diffusion region are located on opposite sides of the semiconductor substrate; the first diffusion region and the second diffusion region are opposite along the thickness direction of the semiconductor substrate;
[0028] The device unit regions are at least two, and the at least two device unit regions include an adjacent first device unit region and a second device unit region; the first diffusion region of the first device unit region and the second diffusion region of the second device unit region are on the same side of the semiconductor substrate;
[0029] In the adjacent first device unit region and second device unit region, the first diffusion region and the second diffusion region on the same side of the semiconductor substrate are connected and communicated as the same diffusion region;
[0030] The doping concentration of the third diffusion region is greater than that of the body region; the third diffusion region and the second diffusion region are spaced apart.
[0031] In any device unit region, the depth of the fourth diffusion region is less than that of the first diffusion region; the depth direction of the fourth diffusion region is parallel to the thickness direction of the semiconductor substrate.
[0032] The first conduction type is electron type, and the second conduction type is hole type; or, the first conduction type is hole type, and the second conduction type is electron type.
[0033] Thirdly, an overvoltage protection device provided by an embodiment of the present invention includes a semiconductor discharge tube provided by any embodiment of the present invention.
[0034] In the technical solution of the embodiment of the present invention, by forming a groove on one side of the semiconductor substrate of the semiconductor discharge tube, wherein the groove and the first diffusion region are on the same side of the semiconductor substrate; forming a third diffusion region of the first conduction type extending into the semiconductor substrate along the groove, the diffusion depth of the third diffusion region can be increased, the thickness of the body region can be reduced, and the resistance of the body region can be reduced, that is, the series resistance in the chip body can be reduced, thereby reducing the residual voltage of the semiconductor discharge tube during lightning surges. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Figure 1 It is a flowchart of a manufacturing method of a semiconductor discharge tube provided by an embodiment of the present invention;
[0036] Figure 2 It is a cross-sectional structure schematic diagram of the semiconductor discharge tube corresponding to steps 110 to 140;
[0037] Figure 3 It is a cross-sectional structure schematic diagram of the semiconductor discharge tube corresponding to steps 150 to 170;
[0038] Figure 4 It is a top view structure schematic diagram of the semiconductor discharge tube corresponding to step 140;
[0039] Figure 5 It is a top view structure schematic diagram of the semiconductor discharge tube corresponding to step 150;
[0040] Figure 6 It is a top view structure schematic diagram of the semiconductor discharge tube corresponding to step 160;
[0041] Figure 7 It is a cross-sectional structure schematic diagram of a semiconductor discharge tube provided by an embodiment of the present invention;
[0042] Figure 8 It is a schematic diagram of the volt-ampere characteristic curve of a unidirectional semiconductor discharge tube provided by an embodiment of the present invention;
[0043] Figure 9 Schematic cross-sectional structure diagram of another semiconductor discharge tube provided by an embodiment of the present invention;
[0044] Figure 10 Schematic cross-sectional structure diagram of another semiconductor discharge tube provided by an embodiment of the present invention;
[0045] Figure 11 Schematic diagram of the volt-ampere characteristic curve of a bidirectional semiconductor discharge tube provided by an embodiment of the present invention;
[0046] Figure 12 Schematic structure diagram of an overvoltage protection device provided by an embodiment of the present invention;
[0047] Figure 13 Schematic cross-sectional structure diagram of a semiconductor discharge tube in the prior art. Detailed implementation manners
[0048] The present invention will be further described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. In addition, it should be noted that for the sake of description, only parts related to the present invention are shown in the drawings, rather than all structures.
[0049] An embodiment of the present invention provides a manufacturing method of a semiconductor discharge tube. Figure 1 Flow chart of a manufacturing method of a semiconductor discharge tube provided by an embodiment of the present invention. Figure 2 Schematic cross-sectional structure diagram of a semiconductor discharge tube corresponding to steps 110 to 140. Figure 3 Schematic cross-sectional structure diagram of a semiconductor discharge tube corresponding to steps 150 to 170. The manufacturing method of the semiconductor discharge tube can be used to manufacture the semiconductor discharge tube provided in any embodiment of the present invention. The manufacturing method of the semiconductor discharge tube specifically includes the following steps:
[0050] Step 110: Provide a semiconductor substrate of a first conductivity type, and the semiconductor substrate includes at least one device unit region.
[0051] Among them, the first conductivity type is an electron type (N type), or a hole type (P type). The semiconductor substrate 10 can be an N-type semiconductor substrate, which can be formed by doping an appropriate amount of pentavalent elements such as arsenic, phosphorus, and antimony in a pure intrinsic semiconductor such as germanium or silicon. The semiconductor substrate 10 can also be a P-type semiconductor substrate, which can be formed by doping an appropriate amount of trivalent elements such as boron, indium, and gallium in a pure intrinsic semiconductor such as germanium or silicon. Figure 2 and Figure 3 Exemplarily, the case where the semiconductor substrate 10 includes a device unit region 11 is drawn.
[0052] Step 120: In any device unit region, form a first diffusion region and a second diffusion region of a second conductivity type on a semiconductor substrate. The first diffusion region and the second diffusion region are separated by a body region of a first conductivity type of the semiconductor substrate; wherein, the first conductivity type and the second conductivity type are different.
[0053] Optionally, the first conductivity type is electron type (N type), and the second conductivity type is hole type (P type); or, the first conductivity type is hole type (P type), and the second conductivity type is electron type (N type). Elements such as arsenic, phosphorus, or antimony can be doped in the N-type diffusion region, and elements such as boron, indium, or gallium can be doped in the P-type diffusion region. The first diffusion region 101 can be formed by processes such as diffusion process or ion implantation method. The second diffusion region 102 can be formed by processes such as diffusion process or ion implantation method. Optionally, in any device unit region 11, the first diffusion region 101 and the second diffusion region 102 are located on opposite sides of the semiconductor substrate 10. Compared with the scheme where the first diffusion region 101 and the second diffusion region 102 are located on the same side of the semiconductor substrate 10, the device size can be reduced and the process difficulty can be lowered under the condition that the performance such as the current-carrying capacity of the two schemes is the same. Optionally, in any device unit region 11, the first diffusion region 101 and the second diffusion region 102 are opposite to each other along the thickness direction Z of the semiconductor substrate 10.
[0054] Step 130: In any device unit region, form a groove on one side of the semiconductor substrate, wherein the groove is on the same side of the semiconductor substrate as the first diffusion region.
[0055] The groove 106 can be formed by processes such as photolithography, dry etching, or wet etching. Optionally, the depth of the groove 106 is greater than or equal to the depth of the first diffusion region 101, wherein the depth direction of the groove 106 is parallel to the thickness direction Z of the semiconductor substrate 10, and the depth direction of the first diffusion region 101 is parallel to the thickness direction Z of the semiconductor substrate 10. The groove 106 can penetrate through the first diffusion region 101. The groove 106 may not penetrate through the body region 104.
[0056] Step 140: Form a third diffusion region of a first conductivity type extending into the semiconductor substrate along the groove, wherein the third diffusion region is in contact with both the first diffusion region and the body region of the semiconductor substrate.
[0057] The third diffusion region 103 can be formed by processes such as oxidation, photolithography, and diffusion process or ion implantation method. Figure 4 is a top view structural schematic diagram of a semiconductor discharge tube corresponding to Step 140. Figure 2 The cross-sectional structural schematic diagram corresponding to Step 140 in [Figure number] is along Figure 4Schematic cross-sectional structure diagram in the A1A1 direction. The first direction X and the second direction Y can be perpendicular to the thickness direction Z of the semiconductor substrate 10. The first direction X can be perpendicular to the second direction Y. Optionally, the doping concentration of the third diffusion region 103 is greater than that of the body region 104. The third diffusion region 103 serves as a low breakdown point for adjusting the breakdown voltage V BR of the size. In any device unit region 11, the third diffusion region 103 and the second diffusion region 102 are arranged at intervals. By grooving and diffusing along the groove 106 to form the third diffusion region 103, the diffusion depth of the third diffusion region 103 can be increased, and the thickness of the body region 104 can be reduced to reduce the series resistance in the chip body, thereby reducing the residual voltage of the semiconductor discharge tube during lightning surge.
[0058] Step 150: In any device unit region, a fourth diffusion region of the first conduction type is formed in the first diffusion region, where the third diffusion region and the fourth diffusion region are arranged at intervals.
[0059] Among them, the fourth diffusion region 105 can be formed by processes such as oxidation, photolithography, diffusion process or ion implantation method. Figure 5 It is a top view structure diagram of the semiconductor discharge tube corresponding to step 150. Figure 3 The cross-sectional structure diagram corresponding to step 150 in is along Figure 5 the schematic cross-sectional structure diagram in the A1A1 direction in. Optionally, in any device unit region 11, the depth of the fourth diffusion region 105 is less than the depth of the first diffusion region 101. The depth direction of the fourth diffusion region 105 is parallel to the thickness direction Z of the semiconductor substrate 10. Along the thickness direction Z of the semiconductor substrate 10, the projection of the fourth diffusion region 105 on the semiconductor substrate 10 is located within the projection of the first diffusion region 101 on the semiconductor substrate 10.
[0060] Step 160: In any device unit region, a corresponding first conductive block is formed, where the first conductive block is electrically connected to the first diffusion region and the fourth diffusion region, and on the shortest current flow path from the third diffusion region through the first diffusion region to the nearest short-circuit point, passing through that part of the first diffusion region in contact with the fourth diffusion region; where the short-circuit point is the contact part between the first diffusion region and the first conductive block.
[0061] Among them, Figure 6 It is a top view structure diagram of the semiconductor discharge tube corresponding to step 160. Figure 3 The cross-sectional structure diagram corresponding to step 160 in is along Figure 6Schematic cross-sectional structure diagram in the A1A1 direction. The first conductive block 20 may include at least one of the following metal materials: tungsten, copper, aluminum, etc. The number of short-circuit points 1011 may be one or more. When the number of short-circuit points 1011 is multiple, the multiple short-circuit points 1011 are arranged at intervals. The nearest short-circuit point 101 may be one or more.
[0062] Step 170: Electrically connect the first conductive block and the second diffusion region in any device unit region to different electrodes.
[0063] Among them, the material of the electrode may include at least one of the following metal materials: copper, aluminum, etc. Figure 3 Exemplarily, the situation where the first conductive block 20 is electrically connected to the electrode 30 and the second diffusion region 102 is electrically connected to the electrode 40 is drawn.
[0064] Figure 7 This is a schematic cross-sectional structure diagram of a semiconductor discharge tube provided by an embodiment of the present invention. Figure 7 Exemplarily, the situation where the semiconductor discharge tube is a unidirectional semiconductor discharge tube is drawn. Exemplarily, taking the first conduction type as the electron type (N type) and the second conduction type as the hole type (P type) as an example, the second diffusion region 102 may be denoted as P1, the first diffusion region 101 may be denoted as P2, the third diffusion region 103 may be denoted as N2, the body region 104 may be denoted as N1, the fourth diffusion region 105 may be denoted as N3, a positive voltage is applied to the electrode 40, a negative voltage is applied to the electrode 30, the N1P1 junction is forward-biased and conducts, the N2P2 junction is reverse-biased. When the voltage between the two electrodes is higher than the breakdown voltage of N2P2, the current I passes through the P2 region and reaches the electrode 30. Figure 7 Exemplarily, the current path of the current I is drawn. After the voltage drop on the contact portion 1012 between the first diffusion region 101 and the fourth diffusion region 105 (located on the shortest current path from the third diffusion region 103 through the first diffusion region 101 to the nearest short-circuit point 1011) reaches 0.7V, the N3 region is turned on, and the semiconductor discharge tube TSS formed by P1N1P2N3 is turned on.
[0065] By grooving and diffusing along the groove 106 to form the third diffusion region 103, the diffusion depth of the third diffusion region 103 can be increased, the thickness of the body region 104 can be reduced, the resistance of the body region 104 can be reduced, that is, the series resistance in the chip body can be reduced, thereby reducing the residual voltage of the semiconductor discharge tube during lightning surges, and solving the problems in the prior art that it is difficult to achieve the diffusion depth of the third diffusion region and a large injection energy is required, resulting in a large body resistance of the semiconductor discharge tube and a large residual voltage during lightning surges, as Figure 13 shown. Figure 13It is a schematic cross-sectional structure diagram of a semiconductor discharge tube in the prior art. It should be noted that when forming the third diffusion region 103, there is no need to increase parameters such as the diffusion concentration and energy in processes such as the diffusion process or the ion implantation method, thereby reducing the process difficulty.
[0066] In the technical solution of this embodiment, a groove is formed on one side of the semiconductor substrate of the semiconductor discharge tube, wherein the groove and the first diffusion region are on the same side of the semiconductor substrate; a third diffusion region of the first conductivity type extending into the semiconductor substrate along the groove is formed, which can increase the diffusion depth of the third diffusion region, reduce the thickness of the body region, and reduce the resistance of the body region, that is, reduce the series resistance in the chip body, thereby reducing the residual voltage of the semiconductor discharge tube during lightning surges.
[0067] Figure 8 It is a schematic diagram of the volt-ampere characteristic curve of a unidirectional semiconductor discharge tube provided by an embodiment of the present invention. Among them, the horizontal axis V represents the voltage between the two electrodes of the semiconductor discharge tube, and the vertical axis I represents the current of the semiconductor discharge tube, V RM is the off-state voltage of the semiconductor discharge tube 100, I RM is the leakage current of the semiconductor discharge tube 100, and the off-state voltage V RM represents the highest voltage at which the semiconductor discharge tube 100 does not conduct. At this voltage, there is only a very small leakage current I RM . V BR is the breakdown voltage of the semiconductor discharge tube 100, which is the voltage when passing through a specified test current and represents the marking voltage at which the semiconductor discharge tube 100 starts to conduct. V BO is the turn-on voltage of the semiconductor discharge tube 100, I BO is the turn-on current of the semiconductor discharge tube 100. When the voltage across the semiconductor discharge tube 100 (for example, applying a positive voltage to electrode 40 and a negative voltage to electrode 30 in Figure 7 ) rises to reach the turn-on voltage V BO (the corresponding current is the turn-on current I BO ), the semiconductor discharge tube 100 is fully conductive, presenting a very small impedance, and the voltage across the semiconductor discharge tube 100 immediately drops to a very low value. I PP is the peak pulse current of the semiconductor discharge tube 100, which is the maximum pulse current that the semiconductor discharge tube 100 can withstand. I H is the holding current of the semiconductor discharge tube 100, which is the minimum current for the semiconductor discharge tube 100 to continue to maintain the conductive state. Once the current flowing through the semiconductor discharge tube 100 is less than the holding current I H , the semiconductor discharge tube 100 returns to the cut-off state. V F is the reverse cut-off voltage of the semiconductor discharge tube 100. When the reverse voltage across the semiconductor discharge tube 100 (for example, in Figure 7When a negative voltage is applied to the electrode 40 and a positive voltage is applied to the electrode 30 in it, when (the voltage) exceeds the reverse cut-off voltage, the semiconductor discharge tube 100 will be broken down and damaged.
[0068] Optionally, on the basis of the above embodiments, continue to refer to Figures 2 to 7 , the third diffusion region 103 is arranged around the groove 106, the first diffusion region 101 is arranged around the third diffusion region 103, and a plurality of short-circuit points 1011 are arranged at intervals in the fourth diffusion region 105. The plurality of short-circuit points 1011 are located around the third diffusion region 103, which can increase the area of the fourth diffusion region 105 and improve the current-carrying capacity of the semiconductor discharge tube 100.
[0069] Among them, the shape of the groove 106 may include a hemispherical shape, or a spherical surface smaller than a hemispherical surface, etc. The groove 106 is located inside the first diffusion region 101. Compared with the scheme of arranging the groove at the junction of the first diffusion region and the body region, that is, the groove is located outside the first diffusion region, the current-carrying capacity of the semiconductor discharge tube 100 can be improved. The groove 106 is located inside the first diffusion region 101. Compared with the scheme of arranging the groove around the outside of the first diffusion region in a circle, under the condition that the performance such as the current-carrying capacity of the two schemes is the same, the device size can be reduced.
[0070] Optionally, on the basis of the above embodiments, Figure 9 is a schematic cross-sectional structure diagram of another semiconductor discharge tube provided by an embodiment of the present invention. Before electrically connecting the first conductive block and the second diffusion region in any device unit region to different electrodes, it further includes: forming a second conductive block on the second diffusion region.
[0071] Among them, the second conductive block 50 is located on one side of the semiconductor substrate 10, and the second conductive block 50 covers the second diffusion region 102. The second conductive block 50 is electrically connected to the second diffusion region 102. The side of the second conductive block 50 away from the second diffusion region 102 is electrically connected to the corresponding electrode to realize the electrical connection between the second diffusion region 102 and the corresponding electrode. The second conductive block 50 may include a metal material. The second conductive block 50 may include at least one of the following metal materials: tungsten, copper, aluminum, etc.
[0072] Figure 9Exemplarily, the case where the first conduction type is hole type (P type) and the second conduction type is electron type (N type) is drawn. The second diffusion region 102 can be denoted as N1, the first diffusion region 101 can be denoted as N2, the third diffusion region 103 can be denoted as P2, the body region 104 can be denoted as P1, the fourth diffusion region 105 can be denoted as P3. A negative voltage is applied to the electrode 40 and a positive voltage is applied to the electrode 30. The N1P1 junction is forward-biased and conducting, and the N2P2 junction is reverse-biased. When the voltage between the two electrodes is higher than the breakdown voltage of N2P2, the current flows out from the electrode 30, passes through P2N2P1N1, and reaches the electrode 40. After the voltage drop on the contact portion 1012 between the first diffusion region 101 and the fourth diffusion region 105 (located on the shortest current flow path from the third diffusion region 103 through the first diffusion region 101 to the nearest short-circuit point 1011) reaches 0.7V, the P3 region is turned on, and the semiconductor discharge tube TSS formed by N1P1N2P3 is turned on. It should be noted that Figure 7 and Figure 9 The corresponding technical solution is applicable to surge voltages in different directions. When a surge interference occurs, the current flow path is the same, the current direction is opposite, and the voltage direction is opposite.
[0073] Optionally, on the basis of the above embodiment, continue to refer to Figure 9 , a passivation groove 107 is provided at the four peripheral edges of the semiconductor substrate 10. An insulating layer may be covered on the passivation groove 107.
[0074] Optionally, on the basis of the above embodiment, Figure 10 This is a schematic cross-sectional structure diagram of another semiconductor discharge tube provided by an embodiment of the present invention. The device unit region 11 is at least two. The multiple device unit regions 11 may be arranged at intervals.
[0075] Optionally, on the basis of the above embodiment, continue to refer to 10. At least two device unit regions 11 include an adjacent first device unit region 11-1 and a second device unit region 11-2; the first diffusion region 101 of the first device unit region 11-1 and the second diffusion region 102 of the second device unit region 11-2 are located on the same side of the semiconductor substrate 10.
[0076] Among them, Figure 10 Exemplarily, the case where the semiconductor discharge tube 100 is a bidirectional semiconductor discharge tube is drawn. Figure 11 This is a schematic diagram of the volt-ampere characteristic curve of a bidirectional semiconductor discharge tube provided by an embodiment of the present invention. As Figure 11 shown, the volt-ampere characteristic curve of the bidirectional semiconductor discharge tube is located in the first quadrant and the third quadrant, and is symmetric about the origin. When a positive voltage is applied to the electrode 40 and a negative voltage is applied to the electrode 30, and the voltage between the two electrodes is higher than the breakdown voltage V of the semiconductor discharge tube 100 BRWhen one of the device unit regions 11 is turned on; when a negative voltage is applied to the electrode 40 and a positive voltage is applied to the electrode 30, and the voltage between the two electrodes is higher than the breakdown voltage V of the semiconductor discharge tube 100 BR When the other device unit region 11 is turned on. The two device unit regions 11 are not turned on simultaneously, so that when a positive surge interference or a negative surge interference occurs, the semiconductor discharge tube 100 can be turned on to discharge the surge current and the surge voltage.
[0077] Optionally, on the basis of the above embodiments, continue to refer to Figure 10 In the first device unit region 11-1 and the second device unit region 11-2 arranged adjacent to each other, the first diffusion region 101 and the second diffusion region 102 on the same side of the semiconductor substrate 10 are connected as the same diffusion region.
[0078] Wherein, as Figure 10 shown, the first diffusion region 101 of the first device unit region 11-1 and the second diffusion region 102 of the second device unit region 11-2 are connected as the same diffusion region, and the second diffusion region 102 of the first device unit region 11-1 and the first diffusion region 101 of the second device unit region 11-2 are connected as the same diffusion region.
[0079] An embodiment of the present invention provides a semiconductor discharge tube. The semiconductor discharge tube is manufactured by the manufacturing method of the semiconductor discharge tube provided in any embodiment of the present invention. On the basis of the above embodiments, continue to refer to Figure 7 The semiconductor discharge tube includes: a semiconductor substrate 10, a first conductive block 20, and two electrodes.
[0080] Wherein, the semiconductor substrate 10 is of a first conductivity type, and the semiconductor substrate 10 includes at least one device unit region 11.
[0081] In any device unit region 11, a first diffusion region 101 and a second diffusion region 102 of a second conductivity type are provided on the semiconductor substrate 10, and the first diffusion region 101 and the second diffusion region 102 are separated by a body region 104 of the first conductivity type of the semiconductor substrate 10; wherein, the first conductivity type and the second conductivity type are different.
[0082] In any device unit region 11, a groove 106 is provided on one side of the semiconductor substrate 10, wherein the groove 106 and the first diffusion region 101 are on the same side of the semiconductor substrate 10.
[0083] A third diffusion region 103 of the first conductivity type extending into the semiconductor substrate 10 along the groove 106, wherein the third diffusion region 103 is in contact with both the first diffusion region 101 and the body region 104 of the semiconductor substrate 10.
[0084] In any device unit region 11, a fourth diffusion region 105 of a first conductivity type is disposed within a first diffusion region 101, wherein the third diffusion region 103 and the fourth diffusion region 105 are spaced apart.
[0085] In any device unit region 11, a corresponding first conductive block 20 is provided, wherein the first conductive block 20 is electrically connected to the first diffusion region 101 and the fourth diffusion region 105, and is on the shortest current flow path from the third diffusion region 103 through the first diffusion region 101 to the nearest short - circuit point 1011, passing through that part of the first diffusion region 101 in contact with the fourth diffusion region 105; wherein the short - circuit point 1011 is the contact part between the first diffusion region 101 and the first conductive block 20.
[0086] In any device unit region 11, the first conductive block 20 and the second diffusion region 102 are electrically connected to different electrodes.
[0087] In the technical solution of this embodiment, by providing a groove on one side of the semiconductor substrate of the semiconductor discharge tube, wherein the groove and the first diffusion region are on the same side of the semiconductor substrate; and arranging a third diffusion region of the first conductivity type extending into the semiconductor substrate along the groove, the diffusion depth of the third diffusion region can be increased, the thickness of the body region can be reduced, and the resistance of the body region can be reduced, that is, the series resistance inside the chip can be reduced, thereby reducing the residual voltage of the semiconductor discharge tube during lightning surges.
[0088] The semiconductor discharge tube provided by the embodiment of the present invention is fabricated by the manufacturing method of the semiconductor discharge tube provided by any embodiment of the present invention. Therefore, the semiconductor discharge tube provided by the embodiment of the present invention also has the beneficial effects described in the above - mentioned embodiments, which will not be elaborated here.
[0089] Optionally, on the basis of the above - mentioned embodiment, continue to refer to Figure 7 , the depth of the groove 106 is greater than or equal to the depth of the first diffusion region 101, wherein the depth direction of the groove 106 is parallel to the thickness direction Z of the semiconductor substrate 10, and the depth direction of the first diffusion region 101 is parallel to the thickness direction Z of the semiconductor substrate 10.
[0090] Optionally, on the basis of the above - mentioned embodiment, continue to refer to Figure 7 The third diffusion region 103 is disposed around the groove 106, the first diffusion region 101 is disposed around the third diffusion region 103, and a plurality of spaced - apart short - circuit points 1011 are provided within the fourth diffusion region 105, and the plurality of short - circuit points 1011 are located around the third diffusion region 103.
[0091] Optionally, on the basis of the above - mentioned embodiment, continue to refer to Figure 7, in any device unit region 11, the first diffusion region 101 and the second diffusion region 102 are located on opposite sides of the semiconductor substrate 10; the first diffusion region 101 and the second diffusion region 102 face each other along the thickness direction Z of the semiconductor substrate 10.
[0092] Optionally, based on the above embodiment, continue to refer to Figure 10 , there are at least two device unit regions 11.
[0093] Optionally, based on the above embodiment, continue to refer to Figure 10 , at least two device unit regions 11 include a first device unit region 11-1 and a second device unit region 11-2 arranged adjacent to each other; the first diffusion region 101 of the first device unit region 11-1 and the second diffusion region 102 of the second device unit region 11-2 are located on the same side of the semiconductor substrate 10.
[0094] Optionally, based on the above embodiment, continue to refer to Figure 10 , in the adjacent first device unit region 11-1 and second device unit region 11-2, the first diffusion region 101 and the second diffusion region 102 located on the same side of the semiconductor substrate 10 are connected and communicated as the same diffusion region.
[0095] Optionally, based on the above embodiment, the doping concentration of the third diffusion region 103 is greater than the doping concentration of the body region 104; the third diffusion region 103 and the second diffusion region 102 are arranged at intervals.
[0096] Optionally, based on the above embodiment, in any device unit region 11, the depth of the fourth diffusion region 105 is less than the depth of the first diffusion region 101; the depth direction of the fourth diffusion region 105 is parallel to the thickness direction Z of the semiconductor substrate 10.
[0097] Optionally, the first conduction type is electron type and the second conduction type is hole type; or, the first conduction type is hole type and the second conduction type is electron type.
[0098] Optionally, based on the above embodiment, continue to refer to Figure 9 , the semiconductor discharge tube 100 further includes a corresponding second conductive block 50 in any device unit region 11. The second conductive block 50 is located on one side of the semiconductor substrate 10, and the second conductive block 50 covers the second diffusion region 102. The second conductive block 50 is electrically connected to the second diffusion region 102. The side of the second conductive block 50 away from the second diffusion region 102 is electrically connected to the corresponding electrode, so as to realize the electrical connection between the second diffusion region 102 and the corresponding electrode.
[0099] Optionally, based on the above embodiment, continue to refer to Figure 9, in the first device unit region 11-1 and the second device unit region 11-2 which are adjacently arranged, the first conductive block 20 and the second conductive block on the same side of the semiconductor substrate 10 can be connected and communicated as the same conductive block. Optionally, on the basis of the above embodiment, the semiconductor discharge tube further includes an insulating layer, the insulating layer covers the side of the semiconductor substrate where the first diffusion region is provided, and exposes the first conductive block. The insulating layer can cover grooves and the like. The material of the insulating layer can include at least one of the following: silicon oxide, silicon nitride, etc.
[0100] An embodiment of the present invention provides an overvoltage protection device. Figure 12 It is a schematic structural diagram of an overvoltage protection device provided by an embodiment of the present invention. On the basis of the above embodiment, the overvoltage protection device includes the semiconductor discharge tube provided by any embodiment of the present invention.
[0101] Among them, as Figure 12 shown, the two output terminals of the power supply 200 are respectively electrically connected to the two input terminals of the circuit to be protected 300, and the two electrodes of the semiconductor discharge tube 100 are respectively electrically connected to the two input terminals of the circuit to be protected 300. The power supply 200 can be an AC power supply or a DC power supply. During normal operation, the semiconductor discharge tube 100 is cut off, and the power supply 200 can supply power to the circuit to be protected 300 normally. When overvoltage such as lightning strike and surge interference occurs on the two output terminals of the power supply 200, the semiconductor discharge tube 100 will conduct to discharge the surge current and surge voltage, and avoid damage to the circuit to be protected by overvoltage.
[0102] The overvoltage protection device provided by the embodiment of the present invention includes the semiconductor discharge tube in the above embodiment. Therefore, the overvoltage protection device provided by the embodiment of the present invention also has the beneficial effects described in the above embodiment, which will not be repeated here.
[0103] Note that the above is only the preferred embodiment of the present invention and the applied technical principle. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described here, and various obvious changes, re-adjustments, combinations with each other and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.
Claims
1. A manufacturing method of a semiconductor discharge tube, characterized in that, Comprising: Providing a semiconductor substrate of a first conductivity type, the semiconductor substrate including at least one device unit region; In any one of the device unit regions, forming a first diffusion region and a second diffusion region of a second conductivity type on the semiconductor substrate, the first diffusion region and the second diffusion region being separated by a body region of the first conductivity type of the semiconductor substrate; wherein, the first conductivity type and the second conductivity type are different; In any one of the device unit regions, forming a groove on one side of the semiconductor substrate, wherein, the groove and the first diffusion region are on the same side of the semiconductor substrate; Forming a third diffusion region of the first conductivity type extending into the semiconductor substrate along the groove, wherein, the third diffusion region is in contact with both the first diffusion region and the body region of the semiconductor substrate; In any one of the device unit regions, forming a fourth diffusion region of the first conductivity type in the first diffusion region, wherein, the third diffusion region and the fourth diffusion region are spaced apart; In any one of the device unit regions, forming a corresponding first conductive block, wherein, the first conductive block is electrically connected to the first diffusion region and the fourth diffusion region, and on the shortest current flow path from the third diffusion region through the first diffusion region to the nearest short circuit point, passing through that part of the first diffusion region in contact with the fourth diffusion region; wherein, the short circuit point is the contact part between the first diffusion region and the first conductive block; Electrically connecting the first conductive block and the second diffusion region in any one of the device unit regions to different electrodes.
2. The manufacturing method of the semiconductor discharge tube according to claim 1, wherein, The depth of the groove is greater than or equal to the depth of the first diffusion region, wherein, the depth direction of the groove is parallel to the thickness direction of the semiconductor substrate, and the depth direction of the first diffusion region is parallel to the thickness direction of the semiconductor substrate.
3. The manufacturing method of the semiconductor discharge tube according to claim 2, characterized in that, The third diffusion region surrounds the groove, the first diffusion region surrounds the third diffusion region, and a plurality of spaced short circuit points are provided in the fourth diffusion region, and the plurality of short circuit points are located around the third diffusion region.
4. The manufacturing method of the semiconductor discharge tube according to claim 1, characterized in that, In any one of the device unit regions, the first diffusion region and the second diffusion region are on opposite sides of the semiconductor substrate; the first diffusion region and the second diffusion region are opposite to each other along the thickness direction of the semiconductor substrate; There are at least two device unit regions, and the at least two device unit regions include an adjacent first device unit region and a second device unit region; the first diffusion region of the first device unit region and the second diffusion region of the second device unit region are on the same side of the semiconductor substrate; In the adjacent first device unit region and second device unit region, the first diffusion region and the second diffusion region on the same side of the semiconductor substrate are connected and communicated as the same diffusion region.
5. The manufacturing method of the semiconductor discharge tube according to claim 1, characterized in that, The doping concentration of the third diffusion region is greater than the doping concentration of the body region; the third diffusion region and the second diffusion region are spaced apart; In any one of the device unit regions, the depth of the fourth diffusion region is less than the depth of the first diffusion region; the depth direction of the fourth diffusion region is parallel to the thickness direction of the semiconductor substrate; The first conductivity type is electron type, and the second conductivity type is hole type; or, the first conductivity type is hole type, and the second conductivity type is electron type.
6. A semiconductor discharge tube, characterized in that, Comprising: A semiconductor substrate of the first conductivity type, the semiconductor substrate including at least one device unit region; In any one of the device unit regions, a first diffusion region and a second diffusion region of the second conductivity type are provided on the semiconductor substrate, and the first diffusion region and the second diffusion region are separated by a body region of the first conductivity type of the semiconductor substrate; wherein, the first conductivity type and the second conductivity type are different; a groove is provided on one side of the semiconductor substrate, wherein the groove and the first diffusion region are on the same side of the semiconductor substrate; a third diffusion region of the first conductivity type extending into the semiconductor substrate along the groove, wherein the third diffusion region is in contact with both the first diffusion region and the body region of the semiconductor substrate; a fourth diffusion region of the first conductivity type is provided in the first diffusion region, wherein the third diffusion region and the fourth diffusion region are spaced apart; In any one of the device unit regions, a corresponding first conductive block is provided, wherein the first conductive block is electrically connected to the first diffusion region and the fourth diffusion region, and on the shortest current flow path from the third diffusion region through the first diffusion region to the nearest short-circuit point, it passes through that part of the first diffusion region in contact with the fourth diffusion region; wherein, the short-circuit point is the contact part between the first diffusion region and the first conductive block; Two electrodes, in any one of the device unit regions, the first conductive block and the second diffusion region are electrically connected to different electrodes.
7. The semiconductor discharge tube according to claim 6, wherein The depth of the groove is greater than or equal to the depth of the first diffusion region, wherein the depth direction of the groove is parallel to the thickness direction of the semiconductor substrate, and the depth direction of the first diffusion region is parallel to the thickness direction of the semiconductor substrate.
8. The semiconductor discharge tube according to claim 6, wherein, The third diffusion region surrounds the groove, the first diffusion region surrounds the third diffusion region, and a plurality of spaced short-circuit points are provided in the fourth diffusion region, and the plurality of short-circuit points are located around the third diffusion region.
9. The semiconductor discharge tube according to claim 6, wherein In any one of the device unit regions, the first diffusion region and the second diffusion region are on opposite sides of the semiconductor substrate; the first diffusion region and the second diffusion region are opposite to each other along the thickness direction of the semiconductor substrate; There are at least two device unit regions, and the at least two device unit regions include an adjacent first device unit region and a second device unit region; the first diffusion region of the first device unit region and the second diffusion region of the second device unit region are on the same side of the semiconductor substrate; In the adjacent first device unit region and second device unit region, the first diffusion region and the second diffusion region on the same side of the semiconductor substrate are connected and communicated as the same diffusion region; The doping concentration of the third diffusion region is greater than the doping concentration of the body region; the third diffusion region and the second diffusion region are spaced apart; In any of the device unit regions, the depth of the fourth diffusion region is less than the depth of the first diffusion region; the depth direction of the fourth diffusion region is parallel to the thickness direction of the semiconductor substrate; The first conduction type is electron type and the second conduction type is hole type; or the first conduction type is hole type and the second conduction type is electron type.
10. An overvoltage protection device, characterized in that, It includes the semiconductor discharge tube according to any one of claims 6-9.
Citation Information
Patent Citations
Semiconductor discharge tube and overvoltage protection device
CN215955287U