RF semiconductor device and method for manufacturing the same

Abstract

The present disclosure relates to a radio frequency (RF) device comprising a molded device die and a multi-layer redistribution structure located below the molded device die. The molded device die comprises a device region and a first molding compound, wherein the device region has a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion located above the BEOL portion. The FEOL portion comprises an active layer formed of a strained silicon epitaxial layer having a lattice constant greater than 5.461 at a temperature of 300K. The first molding compound is located above the active layer. In this context, no silicon crystals are present between the first molding compound and the active layer. The multi-layer redistribution structure comprises a plurality of bump structures located at a bottom of the multi-layer redistribution structure and electrically coupled to the FEOL portion of the molded device die.

Description

Technical Field

[0001] The present disclosure relates to a radio frequency (RF) device and a process for manufacturing the same, and more particularly to an RF device having enhanced thermal performance and enhanced electrical performance, and a wafer-level manufacturing and packaging process for providing the RF device having enhanced performance. Background Art

[0002] The widespread use of cellular and wireless devices has driven the rapid development of radio frequency (RF) technology. The substrate on which RF devices are manufactured plays an important role in achieving high levels of performance in RF technology. Manufacturing RF devices on conventional silicon substrates can benefit from low-cost silicon materials, large-scale wafer production capabilities, well-established semiconductor design tools, and well-established semiconductor manufacturing technology. Although the use of conventional silicon substrates is beneficial for RF device manufacturing, it is well known in the industry that conventional silicon substrates may have two undesirable properties for RF devices: harmonic distortion and low resistivity values. Harmonic distortion is a key obstacle to achieving high levels of linearity in RF devices built on silicon substrates.

[0003] Furthermore, high-speed, high-performance transistors are increasingly being integrated into RF devices. Consequently, due to the large number of transistors integrated into the RF device, the large amount of power passing through the transistors, and / or the high operating speeds of the transistors, the heat generated by the RF device can significantly increase. Therefore, it is desirable to package the RF device in a configuration that achieves improved heat dissipation.

[0004] Wafer-level fan-out (WLFO) and embedded wafer-level ball grid array (eWLB) technologies are currently attracting widespread attention in portable RF applications. WLFO and eWLB technologies are designed to provide high-density input / output (I / O) ports without increasing package size. This capability allows for dense packaging of RF devices within a single wafer.

[0005] To improve the operating speed and performance of RF devices, accommodate increased heat generation, reduce harmful harmonic distortion in RF devices, and leverage the advantages of WLFO / eWLB technology, the present disclosure aims to provide an improved wafer-level manufacturing and packaging process for RF devices. Furthermore, it is desirable to enhance the performance of RF devices without increasing device size. Summary of the Invention

[0006] The present disclosure relates to a radio frequency (RF) device with enhanced performance and a process for manufacturing the same. The disclosed RF device includes a molded device die and a multi-layer redistribution structure. The molded device die includes a first molding compound and a device region having a front-end-of-line (FEOL) portion and a back-end-of-line (BEOL) portion located below the FEOL portion. Here, the FEOL portion includes an isolation section and an active layer, the active layer being surrounded by the isolation section and not extending vertically beyond the isolation section. The active layer is formed from a strained silicon epitaxial layer having a lattice constant greater than 5.461 at a temperature of 300K. The first molding compound is located above the active layer in the FEOL portion. No silicon crystals without germanium, nitrogen, or oxygen content are present between the first molding compound and the active layer. The multi-layer redistribution structure, including a plurality of bump structures, is formed below the BEOL portion of the molded device die. The bump structure is located on a bottom surface of the multi-layer redistribution structure and is electrically coupled to the FEOL portion of the molded device die.

[0007] In one embodiment of the RF device, the FEOL portion further includes a contact layer, the active layer and the isolation section being located above the contact layer. The BEOL portion includes a connection layer located below the contact layer of the FEOL portion. The multi-layer redistribution structure further includes a redistribution interconnect within the multi-layer redistribution structure. In this context, the bump structure is electrically coupled to the FEOL portion of the molded device die via the redistribution interconnect within the multi-layer redistribution structure and the connection layer within the BEOL portion.

[0008] In one embodiment of the RF device, a portion of the first molding compound is located over the isolation segment.

[0009] In one embodiment of the RF device, the isolation section vertically extends beyond a top surface of the active layer to define an opening within the isolation section and above the active layer. In this context, the first molding compound fills the opening.

[0010] According to another embodiment, the RF device further includes a passivation layer located above the top surface of the active layer and within the opening. In this context, the passivation layer is formed of silicon dioxide, silicon nitride, or a combination thereof; and the first molding compound is in contact with the passivation layer.

[0011] In one embodiment of the RF device, the first molding compound is in contact with the top surface of the active layer.

[0012] In one embodiment of the RF device, a top surface of each isolation segment is coplanar with the top surface of the active layer.Herein, the first molding compound is located over both the active layer and the isolation segment.

[0013] In one embodiment of the RF device, the thermal conductivity of the first molding compound is greater than 1 W / m·K.

[0014] In one embodiment of the RF device, the dielectric constant of the first molding compound is less than 8.

[0015] In one embodiment of the RF device, the dielectric constant of the first molding compound is between 3 and 5.

[0016] In an embodiment of the RF device, the FEOL portion is configured to provide at least one of a switching field effect transistor (FET), a diode, a capacitor, a resistor, or an inductor.

[0017] According to another embodiment, an alternative RF device includes a molded device die and a multi-layer redistribution structure. The molded device die includes a first molding compound and a device region having a FEOL portion and a BEOL portion located below the FEOL portion. Here, the FEOL portion includes an isolation section and an active layer, the active layer being surrounded by the isolation section and not extending vertically beyond the isolation section. The active layer is formed from a strained silicon epitaxial layer having a lattice constant greater than 5.461 at a temperature of 300K. The first molding compound is located above the active layer of the FEOL portion. No silicon crystals without germanium content are present between the first molding compound and the active layer. The multi-layer redistribution structure, including a plurality of bump structures, is formed below the BEOL portion of the molded device die. The bump structures are located on a bottom surface of the multi-layer redistribution structure and are electrically coupled to the FEOL portion of the molded device die. The multi-layer redistribution structure extends horizontally beyond the molded device die. The alternative RF device further includes a second molding compound over the multi-layer redistribution structure to encapsulate the molded device die.

[0018] In one embodiment of the alternative RF device, the first molding compound is formed of the same material as the second molding compound.

[0019] In one embodiment of the alternative RF device, the first molding compound and the second molding compound are formed of different materials.

[0020] According to an exemplary process, a precursor wafer is first provided, comprising a plurality of device regions, a plurality of separate interfacial layers, and a silicon handle substrate. Each device region comprises a back-end (BEOL) portion and a front-end (FEOL) portion located above the BEOL portion. The FEOL portion comprises an isolation section and an active layer, the active layer being surrounded by the isolation section and not extending vertically beyond the isolation section. Here, each active layer is formed from a separate strained silicon epitaxial layer having a lattice constant greater than 5.461 at a temperature of 300K. Furthermore, each separate interfacial layer is located above the active layer in the corresponding device region, and the silicon handle substrate is located above each separate interfacial layer. Each separate interfacial layer is formed from SiGe having a germanium concentration greater than 15%, and having a lattice constant greater than 5.461 at a temperature of 300K. Each separate interfacial layer is unstrained by the silicon handle substrate. Next, the silicon handle substrate is completely removed. A first molding compound is then applied to provide a molded device wafer comprising a plurality of molded device dies. Here, the first molding compound is applied over the active layer of each device region at a location where the silicon handle substrate is removed. No silicon crystals without germanium, nitrogen, or oxygen content are present between the active layer of each device region and the first molding compound. Each molded device die includes a corresponding device region and a portion of the first molding compound located over the active layer of the corresponding device region.

[0021] According to another embodiment, the exemplary process further includes, before removing the silicon handle substrate, bonding the precursor wafer to a temporary carrier via a bonding layer; and after applying the first molding compound, debonding the temporary carrier from the molding device wafer and clearing the bonding layer from the molding device wafer.

[0022] According to another embodiment, the exemplary process further includes forming a multi-layer redistribution structure beneath the molded device wafer. Here, the multi-layer redistribution structure includes a plurality of bump structures on a bottom surface of the multi-layer redistribution structure and redistribution interconnects within the multi-layer redistribution structure. Each bump structure is electrically coupled to an active layer of a corresponding molded device die via the redistribution interconnects within the multi-layer redistribution structure and a connection layer within the BEOL portion of the corresponding molded device die.

[0023] According to another embodiment, the exemplary process further includes singulating the molded device wafer into a plurality of individual molded device dies. A second molding compound is then applied around and over the individual molded device dies to provide a dual-molded device wafer. In this context, the second molding compound encapsulates the top and side surfaces of each individual molded device die, while the bottom surface of each individual molded device die is exposed. The bottom surface of the dual-molded device wafer is a combination of the bottom surface of each individual molded device die and the bottom surface of the second molding compound. Next, a multi-layer redistribution structure is formed under the dual-molded device wafer. The multi-layer redistribution structure includes a plurality of bump structures on the bottom surface of the multi-layer redistribution structure and redistribution interconnects within the multi-layer redistribution structure. Each bump structure is electrically coupled to an active layer of the corresponding individual molded device die via the redistribution interconnects within the multi-layer redistribution structure and a connection layer within the BEOL portion of the corresponding individual molded device die.

[0024] In one embodiment of the exemplary process, the precursor wafer further comprises a plurality of individual buffer structures. Herein, the germanium concentration within each individual interface layer is uniform. Each individual buffer structure is positioned between the silicon handle substrate and the corresponding individual interface layer. Each individual buffer structure is formed of SiGe having a vertically graded germanium concentration. The vertically graded germanium concentration within each individual buffer structure increases from the silicon handle substrate to the corresponding individual interface layer.

[0025] According to another embodiment, the exemplary process further includes removing each individual buffer structure and each interface layer before applying the first mold compound, such that after applying the first mold compound, the active layer of each device region is in contact with the first mold compound.

[0026] According to another embodiment, the exemplary process further comprises removing each individual buffer structure and each individual interface layer, and applying a passivation layer directly over the active layer in each device region before applying the first molding compound, wherein the passivation layer is formed of silicon dioxide, silicon nitride, or a combination thereof, and after applying the first molding compound, the passivation layer is in contact with the first molding compound.

[0027] In one embodiment of the exemplary process, providing the precursor wafer begins by providing a starting wafer comprising a common strained silicon epitaxial layer, a common interface layer located above the common strained silicon epitaxial layer, and a silicon handle substrate located above the common interface layer. At a temperature of 300K, the common strained silicon epitaxial layer has a lattice constant greater than 5.461. The common interface layer is formed of SiGe having a germanium concentration greater than 15%, and the lattice constant of the common interface layer is greater than 5.461 at a temperature of 300K. The common interface layer is not strained by the silicon handle substrate. A complementary metal oxide semiconductor (CMOS) process is then performed to provide the precursor wafer. In this context, the isolation region extends through the common strained silicon epitaxial layer and the common interface layer and into the silicon handle substrate, such that the common interface layer is separated into a plurality of separate interface layers, and the common strained silicon epitaxial layer is separated into a plurality of separate strained silicon epitaxial layers. Each active layer of the device region is formed from a corresponding separate strained silicon epitaxial layer. Each individual interface layer is located over a top surface of a corresponding active layer, and the silicon handle substrate is located over the individual interface layers.

[0028] In one embodiment of the exemplary process, the starting wafer further comprises a common buffer structure positioned between the silicon handle substrate and the common interface layer. Herein, the germanium concentration within the common interface layer is uniform. The common buffer structure is formed of SiGe having a vertically graded germanium concentration. The vertically graded germanium concentration within the common buffer structure increases from the silicon handle substrate to the common interface layer.

[0029] In one embodiment of the exemplary process, the isolation segment extends through the common strained silicon epitaxial layer, the common interface layer, the common buffer structure, and into the silicon handle substrate, such that the common buffer structure is separated into a plurality of individual buffer structures, the common interface layer is separated into the plurality of individual interface layers, and the common strained silicon epitaxial layer is separated into the individual strained silicon epitaxial layers. Each individual buffer structure is located above a corresponding interface layer, and the silicon handle substrate is located above each individual buffer structure.

[0030] Those skilled in the art will understand the scope of the present disclosure and recognize additional aspects of the present disclosure after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure and together with the description serve to explain the principles of the disclosure.

[0032] Figure 1A typical silicon-silicon-germanium-silicon (Si-SiGe-Si) structure is shown.

[0033] Figure 2 Relaxed silicon and relaxed silicon germanium are shown.

[0034] Figure 3 Shown is strained silicon grown on relaxed silicon germanium.

[0035] Figure 4 An exemplary radio frequency (RF) device with enhanced performance according to one embodiment of the present disclosure is shown.

[0036] Figure 5 An alternative RF device having enhanced thermal performance and enhanced electrical performance according to one embodiment of the present disclosure is shown.

[0037] Figure 6-17 Shown is provided Figure 4 The steps of an exemplary wafer-level fabrication and packaging process for an exemplary RF device are shown.

[0038] Figure 18-23 Shown is provided Figure 5 The steps of an alternative RF device are shown in an alternative wafer-level manufacturing and packaging process.

[0039] It should be understood that for the sake of clarity, Figure 1-23 Drawings may not be to scale. DETAILED DESCRIPTION

[0040] The embodiments described below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. When reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will recognize applications of these concepts not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0041] It should be understood that although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of this disclosure, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated enumerated items.

[0042] It should be understood that when an element such as a layer, region or substrate is referred to as being "on another element" or extending "onto another element", it can be directly on the other element or directly extended onto the other element, or there can also be an intermediate element. In contrast, when an element is referred to as being "directly on another element" or "extending directly onto another element", there are no intermediate elements. Similarly, it should be understood that when an element such as a layer, region or substrate is referred to as being "on another element" or extending "onto another element", it can be directly on another element or directly extended onto another element, or there can also be an intermediate element. In contrast, when an element is referred to as being "directly on another element" or "extending directly onto another element", there are no intermediate elements. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be an intermediate element. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0043] Relative terms, such as "below," "above," "upper," "lower," "horizontal," or "vertical," may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0044] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that when used herein, the terms "comprises," "comprising," "includes," and / or "including" specify the presence of stated features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or combinations thereof.

[0045] Unless otherwise defined, all terms used herein (including technical terms and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It should be further understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0046] With the expected shortage of conventional radio frequency silicon-on-insulator (RFSOI) wafers in the next few years, alternative technologies are being designed to use silicon wafers, trap-rich layer formation, and smart-cut SOI wafer processes to meet the high resistivity requirements. One alternative technology is based on using a silicon-germanium (SiGe) interface layer between the silicon substrate and the silicon epitaxial layer instead of a buried oxide layer (BOX), which forms a silicon-silicon-germanium-silicon (Si-SiGe-Si) structure, such as Figure 1 However, this technology will still suffer from detrimental distortion effects caused by the silicon substrate, similar to those observed in RFSOI technology.

[0047] At a fixed temperature, such as 300K, the lattice constant of relaxed silicon is And relaxation Si 1-x Ge x The lattice constant depends on the germanium concentration, as Larger than the lattice constant of relaxed silicon, such as Figure 2 If silicon is grown on top of relaxed SiGe, the lattice constant of the silicon will be strained (stretched) to match the lattice constant of the underlying relaxed SiGe, as shown in Figure 3 as shown. It is clear to those skilled in the art that electrons in strained silicon (with an increased lattice constant) will have enhanced mobility compared to original / relaxed silicon because the silicon atoms move farther away from each other, which reduces the atomic forces that interfere with the movement of electrons. However, in a conventional Si-SiGe-Si structure, the SiGe interface layer is grown on top of the silicon substrate so that the lattice constant of the SiGe interface layer can be strained (reduced) due to the silicon substrate, and the lattice constant in the silicon epitaxial layer can remain in the original relaxed form (approximately the same as the lattice constant in the silicon substrate). Therefore, the electron mobility of the silicon epitaxial layer in a conventional Si-SiGe-Si structure may not be enhanced. The present disclosure relates to a radio frequency (RF) device and a wafer-level manufacturing and packaging process for manufacturing the RF device, which benefits from the strained silicon layer with enhanced electron mobility without the deleterious deformation effects from the silicon substrate.

[0048] Figure 4 An exemplary RF device 10 having enhanced performance according to one embodiment of the present disclosure is shown. For purposes of this illustration, the exemplary RF device 10 includes a molded device die 12 having a device region 14 and a first mold compound 16, and a multi-layer redistribution structure 18 formed beneath the molded device die 12.

[0049] Specifically, the device region 14 includes a front-end of the line (FEOL) portion 20 and a back-end of the line (BEOL) portion 22 located below the FEOL portion 20. In one embodiment, the FEOL portion 20 can be configured to provide a switching field effect transistor (FET) and includes an active layer 24 and a contact layer 26. The active layer 24 is formed of a strained silicon epitaxial layer and includes a source 28, a drain 30, and a channel 32 between the source 28 and the drain 30. As used herein, a strained silicon epitaxial layer refers to a silicon epitaxial layer in which the lattice constant of the silicon is greater than the lattice constant of relaxed silicon. At a temperature of 300K, the lattice constant within the strained silicon epitaxial layer can be greater than 5.461, or greater than 5.482, or greater than 5.493, or greater than 5.515. As such, the mobility of electrons in the strained silicon epitaxial layer can be enhanced compared to a relaxed silicon layer. Therefore, the switching speed of the FET based on the active layer 24 formed from the strained silicon epitaxial layer can be faster than that of the FET formed from the relaxed silicon layer.

[0050] Contact layer 26 is formed beneath active layer 24 and includes gate structure 34, source contact 36, drain contact 38, and gate contact 40. Gate structure 34 may be formed of silicon oxide and extends horizontally beneath channel 32 (e.g., from beneath source 28 to beneath drain 30). Source contact 36 is connected to and beneath source 28, drain contact 38 is connected to and beneath drain 30, and gate contact 40 is connected to and beneath gate structure 34. Insulating material 42 may be formed around source contact 36, drain contact 38, gate structure 34, and gate contact 40 to electrically isolate source 28, drain 30, and gate structure 34. In different applications, FEOL portion 20 may have different FET configurations or provide different device components, such as diodes, capacitors, resistors, and / or inductors.

[0051] In addition, the FEOL portion 20 further includes an isolation region 44 located above the insulating material 42 of the contact layer 26 and surrounding the active layer 24. The isolation region 44 is configured to electrically isolate the RF device 10, and in particular the active layer 24, from other devices formed in a common wafer (not shown). Herein, the isolation region 44 may extend from the top surface of the contact layer 26 and vertically extend beyond the top surface of the active layer 24 to define an opening 46 within the isolation region 44 and above the active layer 24. The isolation region 44 may be formed of silicon dioxide, which is resistant to etching chemistries such as tetramethylammonium hydroxide (TMAH), xenon difluoride (XeF2), potassium hydroxide (KOH), sodium hydroxide (NaOH), or acetylcholine (ACH), and is resistant to dry etching systems such as reactive ion etching (RIE) systems with chlorine-based gas chemistries. The first mold compound 16 may be formed of a thermoplastic or thermosetting polymer material such as polyphenylene sulfide (PPS), an overmolded epoxy doped with boron nitride, aluminum oxide, carbon nanotubes, or diamond-like thermal additives.

[0052] In some applications, the RF device 10 may further include a passivation layer 48, which may be formed of silicon dioxide, silicon nitride, or a combination thereof, located above the top surface of the active layer 24 and within the opening 46. In this way, the first molding compound 16 is directly located above the passivation layer 48. The passivation layer 48 is configured to terminate the surface bonding of the active layer 24, which may be the cause of unwanted leakage. The passivation layer 48 may also act as a barrier and is configured to protect the active layer 24 from moisture or ion contamination. In some applications, the RF device 10 may further include an interface layer and / or a buffer structure (not shown) formed of SiGe located above the top surface of the active layer 24 (described in the following paragraphs and not shown in this document). If the passivation layer 48, the buffer structure, and the interface layer are present, the interface layer and the buffer structure are vertically located between the active layer 24 and the passivation layer 48, and the first molding compound 16 is located above the passivation layer 48. If passivation layer 48 is omitted and the buffer structure and / or interfacial layer are present, the interfacial layer and / or buffer structure are vertically positioned between active layer 24 and first mold compound 16. If passivation layer 48, the buffer structure, and the interfacial layer are omitted, first mold compound 16 may be in contact with the top surface of active layer 24. It should be noted that regardless of the presence of passivation layer 48 or the interfacial layer, no silicon crystals without germanium, nitrogen, or oxygen content are present between first mold compound 16 and the top surface of active layer 24. Both passivation layer 48 and the interfacial layer are silicon composites.

[0053] Further, in some applications, the top surface of each isolation segment 44 and the top surface of the active layer 24 can be coplanar (not shown), and the opening 46 is omitted. The first mold compound 16 is located over both the active layer 24 and the isolation segments 44 of the FEOL portion 20. It should be noted that the active layer 24 never extends vertically beyond the isolation segments 44, otherwise the isolation segments 44 may not completely separate the active layer 24 from other devices formed from the same wafer.

[0054] The BEOL portion 22 is located below the FEOL portion 20 and includes a plurality of connection layers 50 formed within a dielectric layer 52. Some of the connection layers 50 (for internal connections) are encapsulated (not shown) by the dielectric layer 52, while some of the connection layers 50 have bottom portions that are not covered by the dielectric layer 52. Some of the connection layers 50 are electrically connected to the FEOL portion 20. For purposes of this illustration, one of the connection layers 50 is connected to the source contact 36, and another connection layer 50 is connected to the drain contact 38.

[0055] The multilayer redistribution structure 18, formed beneath the BEOL portion 22 of the molded device die 12, includes a plurality of redistribution interconnects 54, a dielectric pattern 56, and a plurality of bump structures 58. Here, each redistribution interconnect 54 is connected to a corresponding connection layer 50 within the BEOL portion 22 and extends above the bottom surface of the BEOL portion 22. The connection between the redistribution interconnect 54 and the connection layer 50 is solderless. A dielectric pattern 56 is formed around and beneath each redistribution interconnect 54. Some of the redistribution interconnects 54, which connect the molded device die 12 to other device components formed from the same wafer, may be encapsulated by the dielectric pattern 56 (not shown), while some of the redistribution interconnects 54 have bottom portions exposed through the dielectric pattern 56. Each bump structure 58 is formed at the bottom surface of the multilayer redistribution structure 18 and is electrically coupled to a corresponding redistribution interconnect 54 through the dielectric pattern 56. As such, the redistribution interconnects 54 are configured to connect the bump structures 58 to certain connection layers in the connection layers 50 in the BEOL portion 22 that are electrically connected to the FEOL portion 20. Therefore, the bump structures 58 are electrically connected to the FEOL portion 20 through the corresponding redistribution interconnects 54 and the corresponding connection layers 50. Furthermore, the bump structures 58 are separated from one another and protrude from the dielectric pattern 56.

[0056] In some applications, there may be additional redistribution interconnects (not shown) electrically coupled to the redistribution interconnects 54 via the dielectric pattern 56, as well as additional dielectric patterns (not shown) formed beneath the dielectric pattern 56 so that the bottom portions of some additional redistribution interconnects may be exposed. Thus, each bump structure 58 is coupled to a corresponding additional redistribution interconnect via an additional dielectric pattern (not shown). Regardless of the number of layers of redistribution interconnects and / or dielectric patterns, the multilayer redistribution structure 18 may be glass-free or glass-free. In this document, glass fiber refers to individual glass strands twisted into larger groups. These glass strands can then be woven into a fabric. The redistribution interconnects 54 may be formed of copper or other suitable metals. The dielectric pattern 56 may be formed of benzocyclobutene (BCB), polyimide, or other dielectric materials. The bump structures 58 may be solder balls or copper pillars. The thickness of the multilayer redistribution structure 18 is between 2 μm and 300 μm.

[0057] Heat generated in the device region 14 can travel upward to the bottom portion of the first mold compound 16 above the active layer 24 and then downward through the device region 14 toward the multilayer redistribution structure 18, which dissipates the heat. Therefore, it is highly desirable for the first mold compound 16 to have a high thermal conductivity, especially for the portion near the active layer 24. The thermal conductivity of the first mold compound 16 can be between 1 W / m·K and 100 W / m·K, or between 7 W / m·K and 20 W / m·K. Additionally, the first mold compound 16 can have a low dielectric constant, such as less than 8 or between 3 and 5, to produce low RF coupling. The thickness of the first mold compound 16 depends on the desired thermal performance of the RF device 10, the device layout, the distance from the multilayer redistribution structure 18, and the details of the package and assembly. The thickness of the first mold compound 16 can be between 200 μm and 500 μm.

[0058] Figure 5 Shown with Figure 4 Compared to the RF device 10 shown in FIG. 1 , an alternative RF device 10A further includes a second mold compound 60. Here, the multi-layer redistribution structure 18 can extend horizontally beyond the molded device die 12, and the second mold compound 60 is positioned above the multi-layer redistribution structure 18 to encapsulate the molded device die 12. In this embodiment, the redistribution interconnects 54 of the multi-layer redistribution structure 18 can extend horizontally beyond the molded device die 12, and the bump structures 58 of the multi-layer redistribution structure 18 can be not confined within the periphery of the molded device die 12. The second mold compound 60 can be formed of the same or different material as the first mold compound 16. Unlike the first mold compound 16, the second mold compound 60 may not have thermal conductivity or dielectric constant requirements.

[0059] Figure 6-17 Provides a demonstration of manufacturing Figure 4 1. The exemplary wafer-level manufacturing and packaging process of the exemplary RF device 10 shown in FIG. 1 is a schematic diagram illustrating an exemplary wafer-level manufacturing and packaging process of the exemplary RF device 10. Although the exemplary steps are shown in series, the exemplary steps are not necessarily dependent on the order. Some steps may be performed in a different order than presented. Further, the process within the scope of the present disclosure may include more than Figure 6-17 Fewer or more steps may be shown.

[0060] First, if Figure 6 As shown, a starting wafer 62 is provided. The starting wafer 62 includes a common strained silicon epitaxial layer 64, a common interface layer 66 located on the common strained silicon epitaxial layer 64, and a silicon handle substrate 68 located on the common interface layer 66. In this context, the silicon handle substrate 68 can be composed of conventional low-cost, low-resistivity and high-dielectric-constant silicon having a lattice constant of about 5.431 at a temperature of 300K. The common interface layer 66 is formed of SiGe. For the relaxed Si 1-x Ge x , whose lattice constant depends on the germanium concentration, such as at a temperature of 300K and is therefore larger than the lattice constant in the silicon handle substrate 68 .

[0061] In one embodiment, a common buffer structure 70 can be formed between the silicon handle substrate 68 and the common interface layer 66, which allows for a lattice constant transition from the silicon handle substrate 68 to the common interface layer 66. The common buffer structure 70 can include multiple layers and can be formed of SiGe with a vertically graded germanium concentration. The germanium concentration within the common buffer structure 70 can increase from 0% at the top side (near the silicon handle substrate 68) to X% at the bottom side (near the common interface layer 66). The X% can depend on the germanium concentration within the common interface layer 66, such as 15%, 25%, 30%, 40%, etc. In this context, the common interface layer 66 grown on the common buffer structure 70 can maintain its lattice constant in a relaxed form and can not be strained (reduced) to match the lattice constant of the silicon handle substrate 68. The germanium concentration can be uniform throughout the common interface layer 66 and greater than 15%, 25%, 30% or 40% so that at a temperature of 300K, the lattice constant of the relaxed SiGe in the common interface layer 66 is greater than 5.461, or greater than 5.482, or greater than 5.493 or greater than 5.515.

[0062] The common strained silicon epitaxial layer 64 can be formed of a device-grade silicon material having silicon epitaxial properties desired for forming electronic devices. In this article, the common strained silicon epitaxial layer 64 is grown directly on the common interface layer 66 so that the lattice constant of the common strained silicon epitaxial layer 64 matches (stretches to) the lattice constant in the common interface layer 66 (relaxed SiGe) below. Therefore, at a temperature of 300K, the lattice constant in the common strained silicon epitaxial layer 64 can be greater than 5.461, or greater than 5.482, or greater than 5.493 or greater than 5.515, and therefore greater than the lattice constant in the relaxed silicon epitaxial layer (for example, 5.431 at a temperature of 300K). The common strained silicon epitaxial layer 64 can have a significantly higher electron mobility than the relaxed silicon epitaxial layer. The thickness of the common strained silicon epitaxial layer 64 can be between 700nm and 2000nm, and the thickness of the common interface layer 66 can be between and The thickness of the common buffer structure 70 can be between and and the thickness of the silicon handle substrate 68 may be between 200 μm and 700 μm.

[0063] In another embodiment, the common interface layer 66 can be formed directly on the silicon handle substrate 68, and the common buffer structure 70 can be formed between the common interface layer 66 and the common strained silicon epitaxial layer 64 (not shown). In this embodiment, the lattice constant of the common interface layer 66 can be strained (reduced) by the silicon handle substrate 68. The common buffer structure 70 can still be formed of SiGe with a vertically graded germanium concentration. The germanium concentration within the common buffer structure 70 can increase from 0% at the top side (near the common interface layer 66) to X% at the bottom side (near the common strained silicon epitaxial layer 64). X% can be 15%, 25%, 30%, or 40%. The lattice constant at the bottom side of the common buffer structure 70 is greater than the lattice constant at the top side of the common buffer structure 70. In this embodiment, the lattice constant of the common strained silicon epitaxial layer 64 grown on the common buffer structure 70 matches (is stretched to) the lattice constant at the bottom side of the common buffer structure 70. Therefore, the lattice constant in the common strained silicon epitaxial layer 64 is greater than the lattice constant in the relaxed silicon epitaxial layer (eg, 5.431 at a temperature of 300K).

[0064] Next, a complementary metal oxide semiconductor (CMOS) process is performed on the starting wafer 62 to provide a precursor wafer 72 having a plurality of device regions 14, such as Figure 7AFor purposes of this description, the FEOL portion 20 of each device region 14 is configured to provide a switching FET. In different applications, the FEOL portion 20 may have different FET configurations or provide different device components, such as diodes, capacitors, resistors, and / or inductors.

[0065] In one embodiment, the isolation region 44 of each device region 14 extends through the common strained silicon epitaxial layer 64, the common interface layer 66, and the common buffer structure 70, and extends into the silicon handle substrate 68. In this way, the common buffer structure 70 is separated into a plurality of separate buffer structures 70I, the common interface layer 66 is separated into a plurality of separate interface layers 66I, and the common strained silicon epitaxial layer 64 is separated into a plurality of separate strained silicon epitaxial layers 64I. Each separate strained silicon epitaxial layer 64I is used to form a corresponding active layer 24 in one device region 14. The isolation region 44 can be formed by shallow trench isolation (STI). In this context, since the active layer 24 is formed by a separate strained silicon epitaxial layer 64I, in which the lattice constant is greater than the lattice constant in the relaxed silicon epitaxial layer, the FET based on the active layer 24 can have a faster switching speed (lower on-resistance) than the FET based on the relaxed / conventional silicon epitaxial layer.

[0066] The top surface of the active layer 24 contacts the corresponding interface layer 66I located below the corresponding buffer structure 70I. A silicon handle substrate 68 is located above each individual buffer structure 70I, and a portion of the silicon handle substrate 68 may be located above the isolation segment 44. The BEOL portion 22 of the device region 14, including at least the plurality of connection layers 50 and the dielectric layer 52, is formed below the contact layer 26 of the FEOL portion 20. The bottom portions of some of the connection layers 50 are exposed through the dielectric layer 52 located at the bottom surface of the BEOL portion 22.

[0067] In another embodiment, the isolation regions 44 may not extend into the silicon handle substrate 68. Instead, the isolation regions 44 may extend only through the common strained silicon epitaxial layer 64 and into the common interface layer 66, as shown in FIG. Figure 7BAs shown. Herein, the common interface layer 66 remains continuous and is located above the top surface of each active layer 24 and the top surface of each isolation segment 44. The common buffer structure 70 and the silicon handling substrate 68 remain intact. In addition, the isolation segment 44 can extend through the common strained silicon epitaxial layer 64 and the common interface layer 66 and extend into the common buffer structure 70 (now shown). The common buffer structure 70 remains continuous and is located above each individual interface layer 66I and each isolation segment 44. The silicon handling substrate 68 is still located above the common buffer structure 70. Further, the isolation segment 44 can extend through the common strained silicon epitaxial layer 64, but does not extend into the common interface layer 66 (not shown). The top surface of each isolation segment 44 and the top surface of each active layer 24 can be coplanar (not shown). The common interface layer 66, the common buffer structure 70 and the silicon handling substrate 68 remain intact. A common interface layer 66 is located over each isolation segment 44 and each active layer 24 , a common buffer structure 70 is still located over the common interface layer 66 , and a silicon handle substrate 68 is still located over the common buffer structure 70 .

[0068] After the precursor wafer 72 is completed, the precursor wafer 72 is then bonded to a temporary carrier 74, such as Figure 8 As shown, the precursor wafer 72 can be bonded to the temporary carrier 74 via a bonding layer 76 that provides a planarized surface for the temporary carrier 74. From a cost and thermal expansion perspective, the temporary carrier 74 can be a thick silicon wafer, but can also be constructed of glass, sapphire, or any other suitable carrier material. The bonding layer 76 can be a span-on polymeric adhesive film, such as Brewer Science's WaferBOND temporary adhesive material series.

[0069] The silicon handle substrate 68 is then selectively removed to provide an etched wafer 78, as shown. Figure 9As shown. Selective removal is stopped at each individual buffer structure 70I or each interface layer 66I (not shown). If the isolation segment 44 extends vertically beyond each individual buffer structure 70I, the removal of the silicon handle substrate 68 will provide an opening 46 above each active layer 24 and within the isolation segment 44. Removal of the silicon handle substrate 68 can be provided by a mechanical grinding process and an etching process, or by the etching process itself. As an example, the silicon handle substrate 68 can be ground to a thinner thickness to reduce the subsequent etching time. The etching process is then performed to at least completely remove the remaining silicon handle substrate 68. Because the silicon handle substrate 68, the individual buffer structures 70I and the individual interface layers 66I have different germanium concentrations, they may react differently to the same etching technique (for example: have different etching rates under the same etchant). Therefore, the etching system can be able to identify the presence of the individual buffer structures 70I or the individual interface layers 66I (the presence of germanium) and can indicate when to stop the etching process. Generally, the higher the germanium concentration, the better the etch selectivity between the silicon handle substrate 68 and the individual buffer structures 70I (or between the silicon handle substrate 68 and the individual interface layers 66I). The etching process can be provided by a wet etching system having an etching chemistry that is at least one of TMAH, KOH, NaOH, ACH, and XeF2, or by a dry etching system such as a reactive ion etching system having a chlorine-based gas chemistry.

[0070] During the removal process, the isolation segments 44 are not removed and the sides of each FEOL portion 20 are protected. The bonding layer 76 and the temporary carrier 74 protect the bottom surface of each BEOL portion 22. In this context, after the removal step, the top surface of each isolation segment 44 and the top surface of each individual buffer structure 70I (or each individual interface layer 66I) are exposed. If the isolation segments 44 extend only into the common buffer structure 70, or only into the common interface layer 66, or the top surface of each isolation segment 44 and the top surface of each active layer 24 are coplanar, only the top surface of the common buffer structure 70 or the common interface layer 66 may be exposed (not shown).

[0071] Due to the narrow gap nature of SiGe material, the buffer structure 70I and / or the interface layer 66I alone may be conductive (for certain types of devices). The buffer structure 70I and / or the interface layer 66I alone may cause significant leakage between the source 28 and the drain 30 of the active layer 24. Therefore, in some applications such as FET switch applications, it is also desirable to remove the buffer structure 70I and the interface layer 66I alone. Figure 10As shown. If there is an opening 46 above each active layer 24, each active layer 24 is exposed at the bottom of the corresponding opening 46. The separate buffer structure 70I and the separate interface layer 66I can be removed by the same etching process used to remove the silicon handle substrate 68, or can be removed by another etching process such as a chlorine-based dry etching system. In this context, if each separate interface layer 66I is thin enough, it may not cause any significant leakage between the source 28 and the drain 30 of the FEOL portion 20. In this case, the separate interface layer 66I (not shown) can be left. Similarly, if both the separate interface layer 66I and the separate buffer structure 70I are thin enough, they may not cause any significant leakage between the source 28 and the drain 30 of the FEOL portion 20. So that the separate interface layer 66I and the separate buffer structure 70I (not shown) can be left.

[0072] In some applications, after removing the silicon handle substrate 68, the separate buffer structure 70I, and the separate interface layer 66I, the active layer 24 may be passivated to achieve a suitably low level of current leakage in the device. The passivation layer 48 may be formed directly on each active layer 24 of each FEOL portion 20, such as Figure 11 As shown. Passivation layer 48 can be formed of silicon dioxide, silicon nitride, or a combination of both by chemical vapor deposition (CVD) dielectric film or passivation plasma. If openings 46 are present above each active layer 24 and within isolation segments 44, passivation layer 48 is formed within openings 46. Passivation layer 48 is configured to terminate surface bonding at the top surface of active layer 24, which may be a cause of unwanted leakage.

[0073] Next, a first molding compound 16 is applied over the etched wafer 78 to provide a molded device wafer 80, such as Figure 12As shown. The molded device wafer 80 includes a plurality of molded device dies 12, each of which includes a device region 14 and a portion of a first mold compound 16. Herein, the first mold compound 16 fills each opening 46 and contacts the passivation layer 48 within the opening 46. In addition, a portion of the first mold compound 16 may extend over the isolation segment 44. If the passivation layer 48 is not formed in each opening 46, the first mold compound 16 may contact the top surface of each active layer 24 (not shown). If each individual interface layer 66I is still located above the top surface of each active layer 24, the first mold compound 16 may contact the individual interface layer 66I (not shown). If both the individual interface layer 66I and the individual buffer structure 70I are located above the top surface of each active layer 24, the first mold compound 16 may contact the individual buffer structure 70I (not shown). The first mold compound 16 is always located above each active layer 24. It should be noted that regardless of the presence of passivation layer 48 or separate interfacial layer 661, no silicon crystals without germanium, nitrogen, or oxygen content exist between first mold compound 16 and the top surface of each active layer 24. Both passivation layer 48 and separate interfacial layer 661 are silicon composites.

[0074] The first molding compound 16 can be applied by various procedures, such as compression molding, sheet molding, overmolding, transfer molding, dam and fill encapsulation, and screen printing encapsulation. The thermal conductivity of the first molding compound 16 can be between 1 W / m·K and 100 W / m·K or between 7 W / m·K and 20 W / m·K. The dielectric constant of the first molding compound 16 can be less than 8 or between 3 and 5. During the molding process of the first molding compound 16, the temporary carrier 74 provides mechanical strength and rigidity to the etched wafer 78. A curing process (not shown) is then performed to harden the first molding compound 16. The curing temperature is between 100°C and 320°C, depending on which material is used as the first molding compound 16. After the curing process, the first molding compound 16 can be thinned and / or planarized (not shown).

[0075] The temporary carrier 74 is then debonded from the molded device wafer 80 and the bonding layer 76 is removed from the molded device wafer 80, as shown. Figure 13As shown. Depending on the properties of the temporary carrier 74 and bonding layer 76 selected in the previous steps, a variety of debonding and cleaning processes can be applied. For example, the temporary carrier 74 can be mechanically debonded using a lateral blade process when the stack is heated to a suitable temperature. If the temporary carrier 74 is formed of a transparent material, other suitable processes involve UV light exposure through the temporary carrier, or chemical debonding using a suitable solvent. The bonding layer 76 can be removed by a wet or dry etching process such as a proprietary solvent and plasma cleaning. After the debonding and cleaning processes, the bottom portions of some of the connection layers 50 that can serve as input / output (I / O) ports for the molded device die 12 are exposed through the dielectric layer 52 at the bottom surface of each BEOL portion 22. As such, each molded device die 12 in the molded device wafer 80 can now be electrically verified to determine that the molded device die is functioning properly.

[0076] Reference Figures 14 to 16 According to one embodiment of the present disclosure, a multi-layer redistribution structure 18 is formed under the molded device wafer 80. Although the redistribution steps are shown in series, the redistribution steps are not necessarily dependent on the order. Some steps may be performed in a different order than presented. Further, the redistribution steps within the scope of the present disclosure may include more than Figure 14-16 Fewer or more steps may be shown.

[0077] First, a plurality of redistribution interconnects 54 are formed under each BEOL portion 22, such as Figure 14 As shown. Each redistribution interconnect 54 is electrically coupled to an exposed bottom portion of a corresponding connection layer 50 within the BEOL portion 22 and may extend above the bottom surface of the BEOL portion 22. The connection between the redistribution interconnect 54 and the connection layer 50 is solderless. A dielectric pattern 56 is then formed under each BEOL portion 22 to partially encapsulate each redistribution interconnect 54, as shown. Figure 15 As shown, the bottom portion of each redistribution interconnect 54 is exposed through the dielectric pattern 56. In different applications, there may be additional redistribution interconnects (not shown) electrically coupled to the redistribution interconnect 54 through the dielectric pattern 56, and additional dielectric patterns (not shown) formed under the dielectric pattern 56, such that the bottom portion of each additional redistribution interconnect is exposed.

[0078] Next, a plurality of bump structures 58 are formed to complete the multi-layer redistribution structure 18 and provide a wafer level fan-out (WLFO) package 82, such as Figure 16Each bump structure 58 is formed at the bottom of the multi-layer redistribution structure 18 and is electrically coupled to the exposed bottom portion of the corresponding redistribution interconnect 54 through the dielectric pattern 56. Therefore, the redistribution interconnect 54 is configured to connect the bump structure 58 to certain connection layers in the connection layers 50 in the BEOL portion 22 that are electrically connected to the FEOL portion 20. In this way, the bump structure 58 is electrically connected to the FEOL portion 20 through the corresponding redistribution interconnect 54 and the corresponding connection layer 50. In addition, the bump structures 58 are separated from each other and vertically protrude from the dielectric pattern 56.

[0079] The multilayer redistribution structure 18 may be free of glass fibers or glass. In this context, glass fibers refer to individual glass strands twisted into larger groups. These glass strands can then be woven into a fabric. The redistribution interconnects 54 may be formed from copper or other suitable metals, the dielectric pattern 56 may be formed from BCB, polyimide, or other dielectric materials, and the bump structures 58 may be solder balls or copper pillars. The thickness of the multilayer redistribution structure 18 is between 2 μm and 300 μm. Figure 17 The final step of singulating the WLFO package 82 into individual RF devices 10 is shown. The singulation step may be provided by performing a probing and separation process at certain isolation sections 44.

[0080] In another embodiment, Figure 18-23 Provides a demonstration of manufacturing Figure 5 Although the exemplary steps are shown in a series, the exemplary steps are not necessarily dependent on the order. Some steps may be performed in a different order than presented. Further, the process within the scope of the present disclosure may include more steps than presented. Figure 18-23 Fewer or more steps may be shown.

[0081] like Figure 13 As shown, after the debonding process and the cleaning process to provide a clean molded device wafer 80, a singulation step is performed to singulate the molded device wafer 80 into individual device dies 12, as shown in FIG. Figure 18 This singulation step may be provided by performing a probing and separation process at certain isolation sections 44. Herein, each molded device die 12 may have the same height and include a device region 14 having a FEOL portion 20 and a BEOL portion 22, and a first molding compound 16.

[0082] Next, a second molding compound 60 is applied around and over the molded device die 12 to provide a double molded device wafer 84, as shown. Figure 19As shown. The second molding compound 60 encapsulates the top and side surfaces of each molded device die 12, while the bottom surface of each molded device die 12, i.e., the bottom surface of the BEOL portion 22, is exposed. The bottom surface of the dual-molded device wafer 84 is a combination of the bottom surface of each molded device die 12 and the bottom surface of the second molding compound 60. Herein, the bottom portion of some of the connection layers 50 remains exposed at the bottom surface of each molded device die 12. The second molding compound 60 can be applied by various procedures, such as sheet molding, overmolding, compression molding, transfer molding, dam and fill encapsulation, or screen printing encapsulation. The second molding compound 60 can be formed of the same or different material as the first molding compound 16. However, unlike the first molding compound 16, the second molding compound 60 has no thermal conductivity or resistivity requirements. The second molding compound 60 can be an organic epoxy resin system, etc. A curing process (not shown) is then used to harden the second molding compound 60. The curing temperature is between 100° C. and 320° C., depending on which material is used as the second mold compound 60 . A grinding process (not shown) may be performed to provide a planarized top surface of the second mold compound 60 .

[0083] refer to Figures 20 to 22 , forming a multi-layer redistribution structure 18 according to one embodiment of the present disclosure. Although the redistribution steps are shown in series, the redistribution steps are not necessarily dependent on the order. Some steps may be performed in a different order than presented. Further, the redistribution steps within the scope of the present disclosure may include more than Figure 20-22 Fewer or more steps may be shown.

[0084] First, a plurality of redistribution interconnects 54 are formed under the double molded device wafer 84, such as Figure 20 Each redistribution interconnect 54 is electrically coupled to a corresponding connection layer 50 within the BEOL portion 22 and may extend horizontally beyond the corresponding molded device die 12 and horizontally beneath the second mold compound 60. The connection between the redistribution interconnect 54 and the connection layer 50 is solderless. A dielectric pattern 56 is then formed beneath the dual molded device wafer 84 to partially encapsulate each redistribution interconnect 54, as shown. Figure 21 As shown, the bottom portion of each redistribution interconnect 54 is exposed through the dielectric pattern 56. In different applications, there may be additional redistribution interconnects (not shown) electrically coupled to the redistribution interconnect 54 through the dielectric pattern 56, and additional dielectric patterns (not shown) formed under the dielectric pattern 56, such that the bottom portion of each additional redistribution interconnect is exposed.

[0085] Next, a plurality of bump structures 58 are formed to complete the multi-layer redistribution structure 18 and provide an alternative WLFO package 82A, such as Figure 22 As shown, each bump structure 58 is formed at the bottom of the multi-layer redistribution structure 18 and is electrically coupled to the exposed bottom portion of the corresponding redistribution interconnect 54 through the dielectric pattern 56. Therefore, the redistribution interconnect 54 is configured to connect the bump structure 58 to certain connection layers in the connection layers 50 in the BEOL portion 22 that are electrically connected to the FEOL portion 20. In this manner, the bump structure 58 is electrically connected to the FEOL portion 20 through the corresponding redistribution interconnect 54 and the corresponding connection layer 50. In this context, the bump structures 58 may not be confined within the periphery of the corresponding molded device die 12. In addition, the bump structures 58 are separated from each other and protrude vertically from the dielectric pattern 56.

[0086] Figure 23 The final step of singulating the alternative WLFO package 82A into individual alternative RF devices 10A is shown. The singulation step may be provided by performing a probing and singulation process at portions of the second mold compound 60 that are horizontally located between adjacent molded device dies 12.

[0087] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the appended claims.

Claims

1. A radio frequency device, comprising: a molded device die comprising a device region and a first molding compound, wherein: The device region includes a front-end-of-the-line (FOL) portion and a back-end-of-the-line (BOL) portion located below the FOL portion, wherein the FOL portion includes an active layer and an isolation region, the isolation region being composed of silicon dioxide, surrounding the active layer and vertically extending beyond a top surface of the active layer to define an opening within the isolation region and above the active layer; The active layer is formed of a strained silicon epitaxial layer, wherein at a temperature of 300 K, the lattice constant of silicon in the strained silicon is greater than 5.461; a passivation layer located above the top surface of the active layer and within the opening, wherein the passivation layer is formed of silicon dioxide, silicon nitride, or a combination thereof; and the first mold compound fills the opening and contacts the passivation layer, wherein no silicon crystals without germanium, nitrogen, or oxygen content exist between the first mold compound and the active layer; and a multi-layer redistribution structure formed below a back-end-of-the-line (BEOL) portion of the molded device die, wherein the multi-layer redistribution structure includes a plurality of bump structures on a bottom surface of the multi-layer redistribution structure and electrically coupled to the front-end-of-the-line (FEOL) portion of the molded device die.

2. The radio frequency device according to claim 1, wherein: The back-end process part includes a connection layer; The front-end-of-the-line (FOL) portion further includes a contact layer, wherein the active layer and the isolation region are located above the contact layer, and the back-end-of-the-line (BOL) portion is located below the contact layer; and The multi-layer redistribution structure further includes redistribution interconnects, wherein the plurality of bump structures are electrically coupled to the front-end-of-the-line (FOL) portion of the molded device die through the redistribution interconnects within the multi-layer redistribution structure and the connection layer within the back-end-of-the-line (BOL) portion. The radio frequency device of claim 1 , wherein a portion of the first molding compound is located over the isolation section. The radio frequency device according to claim 1 , wherein a thermal conductivity of the first molding compound is greater than 1 W / m·K. The radio frequency device of claim 1 , wherein a dielectric constant of the first molding compound is less than 8. The radio frequency device of claim 1 , wherein a dielectric constant of the first molding compound is between 3 and 5. 7 . The radio frequency device according to claim 1 , wherein the front-end process section is configured to provide at least one of a switching field effect transistor (FET), a diode, a capacitor, a resistor, or an inductor.

8. A radio frequency device comprising: a molded device die comprising a device region and a first molding compound, wherein: The device region includes a front-end-of-the-line (FOL) portion and a back-end-of-the-line (BOL) portion located below the FOL portion, wherein the FOL portion includes an active layer and an isolation region, the isolation region being composed of silicon dioxide, surrounding the active layer and vertically extending beyond a top surface of the active layer to define an opening within the isolation region and above the active layer; The active layer is formed of a strained silicon epitaxial layer, wherein at a temperature of 300 K, the lattice constant of silicon in the strained silicon is greater than 5.461; a passivation layer located above the top surface of the active layer and within the opening, wherein the passivation layer is formed of silicon dioxide, silicon nitride, or a combination thereof; and the first molding compound filling the opening and contacting the passivation layer, wherein no silicon crystals without germanium, nitrogen, or oxygen content are present between the first molding compound and the active layer; a multi-layer redistribution structure formed beneath a back-end-of-line portion of the molded device die, wherein: The multi-layer redistribution structure extends horizontally beyond the molded device die; and The multi-layer redistribution structure includes a plurality of bump structures on a bottom surface of the multi-layer redistribution structure and electrically coupled to the front-end-of-line portion of the molded device die; and A second molding compound is over the multi-layer redistribution structure to encapsulate the molded device die. 9 . The radio frequency device of claim 8 , wherein the first molding compound is formed of the same material as the second molding compound. 10 . The radio frequency device of claim 8 , wherein the first molding compound and the second molding compound are formed of different materials.

11. The radio frequency device according to claim 8, wherein: The back-end process includes a connection layer; The front-end-of-the-line (FOL) portion further includes a contact layer, wherein the active layer and the isolation region are located above the contact layer, and the back-end-of-the-line (BOL) portion is located below the contact layer; and The multi-layer redistribution structure further includes redistribution interconnects, wherein the plurality of bump structures are electrically coupled to the front-end-of-the-line (FOL) portion of the molded device die through the redistribution interconnects within the multi-layer redistribution structure and the connection layer within the back-end-of-the-line (BOL) portion. 12 . The radio frequency device of claim 8 , wherein a portion of the first molding compound is located over the isolation section. The radio frequency device of claim 8 , wherein a thermal conductivity of the first molding compound is greater than 1 W / m·K. The radio frequency device of claim 8 , wherein the dielectric constant of the first molding compound is less than 8. The radio frequency device of claim 8 , wherein a dielectric constant of the first molding compound is between 3 and 5. 16 . The radio frequency device according to claim 8 , wherein the front-end process section is configured to provide at least one of a switching field effect transistor (FET), a diode, a capacitor, a resistor, or an inductor.

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