Estimating bit error rates of data stored by a memory subsystem using machine learning

Abstract

This disclosure describes techniques for estimating raw bit error rates of data stored in a set of memory cells. Encoded data is read from a set of memory cells. A first population value is obtained based on a first number of memory cells in the set of memory cells having a read voltage within a first range of read voltages, each read voltage representing one or more bits of the encoded data. It is determined that an estimated raw bit error rate of the data satisfies a first threshold. The determination is made using a first trained machine learning model and based in part on the first population value. In response to the determination that the estimated raw bit error rate satisfies the first threshold, a first media management operation is initiated.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to memory subsystems, and more particularly to estimating bit error rates of data stored by the memory subsystems using machine learning. BACKGROUND

[0002] A memory subsystem can be a storage system, such as a solid state drive (SSD) or a hard disk drive (HDD). A memory subsystem can be a memory module, such as a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile dual in-line memory module memory module (NVDIMM). A memory subsystem can include one or more memory components that store data. The memory components can be, for example, non-volatile memory components and volatile memory components. Generally, a host system can utilize a memory subsystem to store data at and retrieve data from the memory components. BRIEF DESCRIPTION OF DRAWINGS

[0003] The present disclosure will become more fully understood from the detailed description given herein and the accompanying drawings, which are given by way of illustration only and thus are not intended to limit the present disclosure to a specific embodiment. It is contemplated that the present disclosure can be practiced with the specific embodiments.

[0004] Figure 1 An example computing environment including a memory subsystem is illustrated in accordance with some embodiments of the present disclosure.

[0005] Figure 2 An example of data population features that can be used to predict bit error rates is illustrated in accordance with some embodiments of the present disclosure.

[0006] Figure 3 Another example of data population features that can be used to predict bit error rates is illustrated in accordance with some embodiments of the present disclosure.

[0007] Figure 4 An example technique for training a machine learning model to predict bit error rates is illustrated in accordance with some embodiments of the present disclosure.

[0008] Figure 5 Another example technique for training a machine learning model to predict bit error rates is illustrated in accordance with some embodiments of the present disclosure.

[0009] Figure 6 An example implementation of training a model is illustrated in accordance with some embodiments of the present disclosure.

[0010] Figure 7 A flowchart of an example method to train and use a bit error rate estimation model in accordance with some embodiments of the present disclosure.

[0011] Figure 8Block diagram of an example computer system in which embodiments of the present disclosure are operable. DETAILED DESCRIPTION

[0012] Aspects of the present disclosure relate to raw bit error rate (RBER) estimators in memory subsystems. Memory subsystems are also referred to as“memory devices” hereinafter. An example of a memory subsystem is a memory module that is connected to a central processing unit (CPU) via a memory bus. Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), non-volatile dual in-line memory modules (NVDIMMs), and the like. Another example of a memory subsystem is a storage device that is connected to a central processing unit (CPU) via a peripheral interconnect (e.g., an input / output bus, a storage area network, and the like). Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, and hard disk drives (HDDs). In some embodiments, the memory subsystem is a hybrid memory / storage subsystem. Generally, a host system can utilize a memory subsystem that includes one or more memory components. The host system can provide data to be stored at the memory subsystem and can request data to be retrieved from the memory subsystem.

[0013] A memory subsystem stores data on a medium, which can be modeled as a noisy communication channel. That is, data read from the medium can not match the data written to the medium due to noise associated with read and write operations, changes in the physical characteristics of the medium due to time and / or usage, media retention limitations, and the like. To account for changes in data between a write operation and a read operation, a memory subsystem typically employs an error-correcting code (ECC). When data is written to the medium, the memory subsystem encodes (e.g., with an ECC encoder) the data to be stored to include some redundancy and writes the encoded data to the medium. It should be noted that the encoded data is sometimes referred to as a codeword. When data is read from the medium, the memory subsystem decodes (e.g., with an ECC decoder) the read codeword to obtain the stored data, using the redundancy of the codeword to correct any changes related to the data intended to be stored. The number of bit changes is commonly referred to as the raw bit error rate (RBER). For example, if a codeword includes 512 bytes of data and 12 bits are changed during a decoding operation, the RBER would be 12 / 4,096 or approximately 0.00293.

[0014] Many media management operations, such as those described herein, condition on RBER. Traditionally, obtaining RBER for a given codeword or group of codewords requires decoding the codeword to identify the number of changed bits. ECC decode operations are costly in both latency and power: ECC decode operations introduce a delay between reading data from the media and obtaining RBER, and often involve many computations that result in increased power usage. If a read is performed to determine whether to trigger a media management operation and the obtained RBER is not worth the performance of the media management operation, the read still occupies the ECC decoder (whether it is a software process or a hardware component) for a period of time, which can block other ECC decode operations (e.g., those initiated by the host system) and result in increased power usage of the memory subsystem.

[0015] Aspects of the present disclosure address the above and other deficiencies by introducing techniques for estimating RBER without incurring the costs associated with ECC decode operations. In particular, a memory subsystem includes an RBER estimator that employs one or more models trained using machine learning techniques to predict RBER from one or more features available to or generated by the memory subsystem. Example features include overall data related to a number of memory cells storing certain values, locations of the memory cells on the media, and so on. The prediction can be based on a regression model that estimates the predicted RBER or a classification model that predicts whether the predicted RBER is above or below a threshold or within one or more threshold ranges. The memory subsystem can utilize the predictions of the RBER estimator to defer the more costly ECC decode operations to obtain actual RBER and / or various media management operations.

[0016] Figure 1 An example computing environment 100 including a memory subsystem 110 is illustrated in accordance with some embodiments of the present disclosure. The memory subsystem 110 can include media, such as memory components 112A-112N. The memory components 112A-112N can be volatile memory components, non-volatile memory components, or such combinations. In some embodiments, the memory subsystem is a storage system. An example of a storage system is an SSD. In some embodiments, the memory subsystem 110 is a hybrid memory / storage subsystem. Generally, the computing environment 100 can include a host system 120 that uses the memory subsystem 110. For example, the host system 120 can write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0017] The host system 120 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing device including a memory and a processing device. The host system 120 can include or be coupled to the memory sub-system 110, such that the host system 120 can read data from or write data to the memory sub-system 110. The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. As used herein, “coupled to” generally refers to a connection between components, which can be an indirect communicative connection or direct communicative connection (e.g., without intermediate components), whether wired or wireless, including connections such as electrical, optical, magnetic, and the like. Examples of physical host interfaces include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect (PCIe) interface, a universal serial bus (USB) interface, Fibre Channel, serial connected SCSI (SAS), and the like. The physical host interface can be used to transmit data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a PCIe interface, the host system 120 can further utilize a Non-Volatile Memory express (NVMe) interface to access the memory components 112A to 112N. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120.

[0018] The memory components 112A-112N can include any combination of different types of non-volatile memory components and / or volatile memory components. Examples of non-volatile memory components include NAND-type flash memory. Each of the memory components 112A-112N can include one or more arrays of memory cells, such as single-level cell (SLC) or multi-level cell (MLC) (e.g., triple-level cell (TLC) or quad-level cell (QLC)). In some embodiments, a particular memory component can include both SLC and MLC portions of memory cells. Each of the memory cells can store data (e.g., a block of data) of one or more bits used by the host system 120. Although non-volatile memory components such as NAND-type flash memory are described, the memory components 112A-112N can be based on any other type of memory such as volatile memory. In some embodiments, the memory components 112A-112N can be, but are not limited to, random access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), negative or (NOR) flash memory, electrically erasable programmable read only memory (EEPROM), and cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-gridded data access array. Further, in contrast to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where a non-volatile memory cell can be programmed without first erasing the non-volatile memory cell. Further, the memory cells of the memory components 112A-112N can be grouped into memory pages or blocks, which can refer to units of the memory components for storing data.

[0019] As illustrated, the example media hierarchy includes a plurality of memory components 112A-112N. The memory cells of the plurality of memory components can be physically and / or logically grouped based on how the cells are accessed. For example, different groups of memory cells can be accessed in parallel (e.g., for read, write, and / or erase operations) due to the parallel access circuitry structure. In this example media hierarchy, each memory component 112 includes a single die or a plurality of dies 130A-130R. Each die 130 includes one or more blocks 132A-132Q of memory cells. Each block 132 includes one or more pages 134A-134P of memory cells. Each page 134 stores one or more codewords 136A-136M. The codewords 136 are ECC encoded to allow correction of any changes to the stored data due to noise sources.

[0020] The memory system controller 115 (hereinafter referred to as “controller”) can communicate with the memory components 112A to 112N to perform operations such as reading data, writing data, or erasing data at the memory components 112A to 112N, among other such operations. The controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor. The controller 115 can include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120. In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetch data, and the like. The local memory 119 can also include read-only memory (ROM) for storing microcode. While the example memory sub-system 110 has been illustrated as including the controller 115, in another embodiment of the present disclosure, the memory sub-system 110 can not include the controller 115 and instead can rely upon external control (e.g., by an external host, or provided by a processor or controller separate from the memory sub-system). Figure 1

[0021] Generally, the controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 112A to 112N. The controller 115 can be responsible for other media management operations in association with the memory components 112A to 112N, such as wear leveling operations, garbage collection operations, error detection and ECC operations, encryption operations, caching operations, and address translations between a logical block address and a physical block address. The controller 115 can be responsible for other media management operations such as calibrating voltage thresholds to distinguish between multiple values represented by voltages stored by memory cells, checking the health of a valley of a distribution of cell voltages, managing data retention by checking whether data written recently has an elevated RBER worth decoding and re-writing to the media, and the like. The controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert commands received from the host system into command instructions to access the memory components 112A to 112N, as well as convert responses associated with the memory components 112A to 112N into information for the host system 120.

[0022] ​Memory sub-system 110 can also include additional circuitry or components not shown. In some embodiments, memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row and column decoders) that can receive an address from controller 115 and decode the address to access memory components 112A to 112N.

[0023] Memory sub-system 110 includes an RBER estimator 113 that can predict RBER with relatively low power and latency relative to conventional ECC operations. In some embodiments, controller 115 includes at least a portion of RBER estimator 113. For example, controller 115 can include a processor 117 (processing device) configured to execute instructions stored in local memory 119 to perform the operations described herein. In other embodiments, RBER estimator 113 is part of host system 120, an application, or an operating system. In other embodiments, RBER estimator 113 is incorporated into the logic or local controller of memory components 112 (not shown). For example, each memory component 112 can have access logic or a local controller to which controller 115 can issue operations to read data from or write data to memory components 112. RBER estimator 113 of a particular memory component 112 can provide RBER predictions to controller 115 as part of the metadata provided with read operations or in response to separate operations to obtain RBER predictions.

[0024] RBER estimator 113 predicts RBER for logical groups of data stored on the media based on one or more features that are available to the memory sub-system or generated by the memory sub-system without performing an ECC decode operation. Further details regarding the various features, training of RBER estimator 113, and operation of RBER estimator 113 are described below.

[0025] Figure 2Examples of data population characteristics that can be used to predict bit error rates are illustrated according to some embodiments of the disclosure. When a controller 115 reads a set of memory cells from a medium, the controller obtains population data related to the read or sensed voltages as the cells are accessed. The population data obtained can be accumulated by the controller 115 or obtained directly from another controller associated with a memory component 112 (not shown). The set of memory cells is a set of cells that can be read as a unit (e.g., a codeword 136, a page 134, a block 132, etc.) and the population data indicates, relative to one or more read thresholds, which sensed voltages should be interpreted as which values. For example, in a NAND-based SLC, a single threshold distinguishes between 0 and 1 (e.g., a read voltage above the threshold is interpreted as 0 and a read voltage below the threshold is interpreted as 1). If the controller 115 reads a set of 1,000 memory cells, the population data can indicate that the read voltages indicate that 700 memory cells store 0 and 300 memory cells store 1. It should be noted that the population data can be normalized based on the total number of cells (e.g., 0.7 and 0.3 for 0 and 1, respectively).

[0026] As illustrated in the example idealized voltage distribution 220, a distribution of read voltages from a set of NAND-based MLCs that store two bits per cell is plotted. In this example, three read thresholds 222, VTH1, VTH2, and VTH3, distinguish between the two-bit values 00, 01, 10, and 11. Specifically, read voltages less than VTH1 correspond to the value 11, read voltages between VTH1 and VTH2 correspond to the value 10, read voltages between VTH2 and VTH3 correspond to the value 00, and read voltages at or above VTH3 correspond to the value 01. It is worth noting that in this idealized example, the curve representing the 11 value does not extend beyond VTH1, the curve representing 10 does not extend below VTH1 or above VTH2, and so on. Other types of MLC media have different numbers of read thresholds (e.g., SLC has at least one read threshold; MLC with 2 bits per cell has at least three read thresholds; TLC with 3 bits per cell has at least 7 read thresholds, QLC with 4 bits per cell has at least 15 read thresholds, and so on).

[0027] In practice, as illustrated in example actual voltage distribution 240, the distribution curves are continuous and the read threshold 222 causes some cells storing one two-bit value to be interpreted as storing a different two-bit value - a source of RBER. As illustrated in the blow-up across the valley of VTH1, the tail of the 11 distribution extends above VTH1 and the tail of the 10 distribution extends below VTH1. Thus, cells falling into a read voltage region 242 that should be interpreted as storing value 10 are interpreted as storing value 11, and cells falling into a read voltage region 244 that should be interpreted as storing value 11 are interpreted as storing value 10. Without incurring the cost of performing an ECC decode operation, the controller does not know which cells have read voltages falling within regions 242, 244.

[0028] To avoid or reduce the frequency of using ECC decode operations, the controller 115 obtains aggregate data 250, as described above and illustrated here as PI, P2, P3, and P4, where PI corresponds to the number of memory cells having a read voltage less than VTH1, P2 corresponds to the number of memory cells having a read voltage between VTH1 and less than VTH2, P3 corresponds to the number of memory cells having a read voltage between VTH2 and less than VTH3, and P4 corresponds to the number of memory cells having a read voltage at or above VTH3. The aggregate data can be raw count data related to the number of cells, or normalized based on the number of cells read in a group.

[0029] The controller 115 provides one or more of the values from the aggregate data 250 as features 282 to the RBER estimator 113, which in turn provides a prediction 286 of RBER for the group of memory cells. In some embodiments, the controller 115 also provides the RBER threshold 284 to the RBER estimator 113 in the case that the RBER estimator 113 performs a classification to indicate whether the RBER is above or below the threshold 254. See below for additional details. Figure 4 and 5 Additional details are provided regarding these features.

[0030] Figure 3 Another example of data aggregate features that can be used to predict bit error rates is illustrated in accordance with some embodiments of the disclosure. In particular, Figure 3The population data can be sampled in different ways than illustrated in the example actual voltage distribution 240. In the example actual voltage distribution 390, the population data 350 is based on a subset of all populations bounded by read thresholds that define the bookends of the expected valley positions of the distribution. For example, PI corresponds to the number of memory cells with a read voltage less than VTHI, P2 corresponds to the number of memory cells with a read voltage between VTH2 and VTH3, P3 corresponds to the number of memory cells with a read voltage between VTH4 and VTH5, P4 corresponds to the number of memory cells with a read voltage between VTH6 and VTH7, and P5 corresponds to the number of memory cells with a read voltage greater than VTH8. The population data can be based on other portions of the distribution than those illustrated in Figure 2 and 3 those illustrated in FIGS. 1-3, such as the peaks, combinations of peaks and valleys, other estimated features such as the gradient between the peaks and valleys of a curve fitting the distribution, and so on.

[0031] Figure 4 and 5 An example technique for training a machine learning model to predict bit error rate is illustrated in accordance with some embodiments of the present disclosure. At a high level, machine learning techniques fit a model to data. The data can be split into a training data set to train a machine learning model, which can be refined using a validation data set, and its performance measured using a test data set. The learned model can then be deployed to make relevant predictions based on new data. To increase the benefit of using the RBER estimator 113 over performing the expensive ECC decode operation, the RBER estimator 113 is preferably computationally inexpensive (in terms of speed and / or latency and / or power consumption) compared to the ECC decode operation. One inexpensive model that can be implemented by the RBER estimator 113 is a decision tree classifier, which can provide an indication of whether the estimated RBER is above or below a threshold (in the case of a binary decision tree) or above one of many RBER thresholds (in the case of a multi-class decision tree). Such a decision tree can be implemented in hardware using cascading logic gates or in software using conditional statements. For example, Figure 4 A training technique that can be used to generate the decision tree model 407 is illustrated. As illustrated, the model 407 is trained from the training data set 401 using a machine learning algorithm 405. A computer system (not shown) can perform the model training.

[0032] The training data set 401 contains a number of samples, each containing features 282 associated with a given read operation of a set of memory cells, where the actual RBER is known (e.g., based on ECC decoding). Generally, the higher the number of samples in the training data set 401, the more robust the resulting model, provided that the model does not overfit. Example features 282 include overall data associated with a set of memory cells (e.g., overall data 250 or 350) and can include other features 413, such as PEC features (program-erase counts associated with the set of cells), WL features (word lines; in some architectures, certain word lines can exhibit higher RBER), features indicative of a block 132 or some other logical or physical grouping in a memory hierarchy containing a set of cells, features indicative of a host (e.g., if the memory sub-system is incorporated into a multi-core or multi-processor system, where different cores or processors have different host identifiers), and so on. Of course, features 282 that can be used for model training can include more, fewer, or different features than illustrated.

[0033] The machine learning algorithm 405 looks at the features 282 and known RBER and attempts to iteratively generate decisions that maximize information gain as characterized by a cost function. For example, if the model 407 being trained is a binary decision tree classifier to estimate whether the RBER for a given set of features is above or below a threshold 284, and the cost function is set to the total number of errors (or error rate) that the machine learning algorithm attempts to minimize. For example, a first decision can partition the samples in the training data set 401 into two subsets based on at least one feature and a decision threshold, such that one subset has a high ratio of samples exceeding the threshold RBER to samples not exceeding the threshold RBER, and the other subset has a low ratio of samples exceeding the threshold RBER to samples not exceeding the threshold.

[0034] Example decision tree machine learning algorithms 405 include ID3 (Iterative Dichotomiser 3), C4.5 (an extension of ID3), CART (Classification and Regression Tree), CHAID (Chi-squared Automatic Interaction Detection), and others known to those of ordinary skill in the art. At a high level, the machine learning algorithm 405 gradually learns a decision tree model 407 by splitting / partitioning the training data set 401 into subsets based on one or more input features that lead to the lowest cost. The splitting process is repeated on each derived subset in a recursive manner, subject to various parameters that limit the size of the tree. Example parameters include a minimum leaf size (i.e., a minimum subset that is no longer subdivided), a number of decisions (e.g., a total number of decisions in the tree), a depth of the tree (e.g., a maximum number of decisions between the first decision or root of the tree and the decision that provides the prediction), and so on.

[0035] The cost function can be specified depending on how model 407 should be optimized. For example, a cost function can be defined to limit the total error rate, the number of false positives, and the number of false negatives. The decision of which error rate to use can be based on the sensitivity of a given memory subsystem to the aforementioned types of errors. Due to the number of subsequent operations triggered (e.g., ECC decoding operations, media management operations), some memory subsystems may be more sensitive to false positive errors (e.g., incorrectly estimating RBER greater than the input threshold) than to false negative errors (e.g., incorrectly estimating RBER less than the input threshold), while other memory subsystems may be more sensitive to false negatives (e.g., risking data loss). Other cost functions can be defined as a combination of a certain error (false positive, false negative, or total error rate) with one or more non-error parameters (e.g., the number of decisions in the tree) to optimize both the error and the implementation complexity of the tree.

[0036] Figure 5 Another model training technique is described. Compared to decision tree machine learning algorithms that evaluate the entire population or a subset of samples in the training dataset 401 as a whole to identify each decision, other machine learning techniques iteratively evaluate individual samples 401 of the training dataset to refine the model. As illustrated, model 507 is trained from training dataset 401. A computer system (not shown) can perform model training. The instance model trained using the illustrated technique is a logistic regression model. For example, logistic regression model 507 can predict RBER according to the following equation:

[0037] The estimated RBER is: w0·f0 + ... + w n ·fn+b

[0038] Among them, f0 to f n Corresponding to feature 282 as described in this paper, w0 to w n Corresponding to the learning weights, and b corresponds to the offset. Another example model trained using the illustrated technique is a neural network model. The neural network model 507 may contain one or more hidden layers that operate on the input layer corresponding to feature 282 and output the estimated RBER, a prediction vector indicating the likelihood of the RBER within a certain range, a classification, etc.

[0039] During training, model 507 processes samples and generates prediction 586. Cost function 511 compares prediction 586 with the actual RBER associated with samples from training dataset 401. Model optimizer 513 evaluates the output of the cost function—sometimes referred to as the error—and updates the parameters of model 507. Instance-specific cost function 511 calculates the difference between the estimated RBER and the actual RBER associated with samples from training dataset 401. Instance-specific model optimizer 513 may employ a stochastic gradient descent algorithm to iteratively reduce the error.

[0040] Once trained, the model (e.g., model 407, 507) can be implemented as part of the RBER estimator 113. Note that the trained model can depend on fewer features 282 than the features available in the training dataset 401. That is, the trained model can be sensitive to a certain subset of the example features 282 described in Figure 4 and 5

[0041] Figure 6 An example implementation of training a model is described according to some embodiments of the disclosure. As described, the RBER estimator 113 can implement one or more models 607A-S (e.g., such as the model 407, 507). In an RBER estimator 113 with multiple models, different models 607 can be used for different purposes. For example, some media management operations can be triggered in response to different estimated RBER thresholds 284. The RBER estimator 113 can use one model 607 for one RBER threshold 284 and another model 607 for a different RBER threshold 284. Further, different models 607 can generate different types of predictions. As a classifier, one model 607 can generate a prediction of whether the estimated RBER is above a threshold 284 or within a certain range. In a regression context, another model 607 can generate an estimated value of the RBER. Additionally, different models 607 can depend on different input features 682 (e.g., a decision tree classifier model can be sensitive to a different set of features than a logistic regression model).

[0042] As described, the model 607A is a binary decision tree classifier (e.g., model 407) that determines whether the RBER is above or below a threshold 284. The described model 607A includes several levels of decision nodes 602 that lead to a leaf 604 that indicates whether the RBER is above or below a threshold 284. Each condition can evaluate one or more features. For example, if “Feature A” is greater than 0.1 and “Feature B” is greater than 0.3, then the estimated RBER exceeds the threshold 284. As another example, if “Feature A” is less than 0.1 and “Feature G” is less than 1.2, then the estimated RBER does not exceed the threshold 284. Such binary decision tree classifiers can be implemented in hardware, for example, using a cascade of comparators.

[0043] Figure 7 ​This is a flowchart of an example method 700 for training and using a bit error rate estimation model according to some embodiments of the present disclosure. Method 700 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, one or more of the processes in method 700 are performed by… Figure 1 The RBER estimator 113 is executed. Although shown in a specific order or sequence, the order of the procedures may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated procedures may be executed in different orders, and some procedures may be executed in parallel. In addition, one or more procedures may be omitted in various embodiments. Therefore, not all procedures are required in every embodiment. Other process flows are also possible.

[0044] At operation 705, a first processing device, such as a processor in a computer system, uses a training dataset to train a machine learning model. As described herein, the trained model can be used to generate predictions of the Relative Bit Rate (RBER) associated with data stored in a set of memory cells in a memory subsystem, based on one or more features contained in the training dataset. Such features may include aggregate data representing the read voltages of multiple sets of memory cells that can be normalized. Additional features include the PEC and various identifiers related to the location of a given set of memory cells, such as its block, page, word line, and / or the host system that initiated the stored data. Various machine learning techniques can be used to train the model, including those referenced above. Figure 4 and 5 Those described.

[0045] At operation 710, a second processing device, such as the logic or local controller of controller 115 or memory component 112, reads encoded data from a set of memory cells in the memory subsystem. This set of memory cells may store one or more codewords representing encoded data or ECC-protected data. The electrical characteristics of each cell, such as the read voltage, represent one or more bits (1s and 0s) of the stored encoded data. It should be noted that in some embodiments, the second processing device may be the first processing device, for example, in a system where the host system processor acts as the controller of the memory subsystem.

[0046] At operation 715, the second processing device obtains a first overall value based on the fact that a first number of memory cells in the group of memory cells have read voltages within a first read voltage range, wherein each read voltage represents one or more bits of encoded data. As described herein, the overall data can be used to represent the count or frequency of cells within a group of cells that encompass a range of electrical characteristics. For example, as described above for... Figure 2 and3 The overall data 250 and 350 described and illustrated include values representing counts or frequencies of cells between various read voltage thresholds.

[0047] At operation 720, the second processing device determines, using the first trained machine learning model, that an estimated raw bit error rate of the data exceeds a first threshold based in part on the first overall value. The machine learning model trained at operation 705 can be loaded into a controller 115 of the memory sub-system and implemented using a combination of software and / or firmware. In one embodiment, the machine learning model is implemented as an RBER estimator component 113 of the controller 115. The machine learning model accepts as input one or more features associated with a set of memory cells and generates an RBER prediction. For a model that estimates an RBER value, the controller 115 can compare the estimated RBER value to one or more thresholds. For a model that classifies RBER based on input thresholds, the controller 115 obtains from the RBER estimator component 113 an indication of whether the model predicts that the RBER of the set of memory cells exceeds an input threshold. In either case, when the predicted RBER does not exceed the threshold, the second processing can refrain from performing an ECC decode operation.

[0048] It should be noted that in various embodiments, a parameter representing a raw bit error rate can be used and different thresholds evaluated accordingly. For example, some machine learning models can generate a parameter that is inversely related to RBER (e.g., the parameter decreases as RBER increases). In such scenarios, the second processing device can determine that the parameter has fallen below a threshold (rather than the RBER exceeding a threshold). In general, the second processing device determines using the first trained machine learning model that the RBER or some parameter indicative of the RBER has met a threshold.

[0049] At operation 725, the second processing device initiates a first media management operation in response to determining that the estimated raw bit error rate exceeds the first threshold. As described above, mechanisms to implement a prediction of RBER without performing an expensive ECC decode operation can reduce power consumption and improve performance of a memory subsystem. Various media management operations can be triggered in response to an elevated RBER, such as read voltage threshold calibration and data retention algorithms can be performed to improve read threshold locations and avoid data loss, as described herein. ECC decode operations that would typically trigger such media management operations can be deferred until the predicted RBER exceeds the threshold determined at operation 720. For example, if the RBER prediction indicates an elevated RBER, the controller 115 can use an ECC decoder to decode the encoded data to correct any errors, re-encode the decoded data, and re-write the newly encoded data to the media. As another example, the controller 115 can obtain a plurality of RBER predictions while adjusting read voltage thresholds to optimize the read voltage thresholds toward the minimum RBER prediction without invoking ECC decoding. The controller 115 can read data from the media with a first set of one or more read voltage thresholds and obtain an associated RBER prediction. The controller 115 can then read the same data from the media with a second set of one or more read voltage thresholds, adjusting at least one read voltage threshold of the second set relative to a corresponding read voltage threshold in the first set. With reference to Figure 2 , the controller 115 can read data using VTHI, VTH2, and VTH3 as a first set of read threshold voltages and VTHI + n, VTH2, and VTH3 as a second set of read threshold voltages, where n is an offset. Repeating the process, the controller 115 can iteratively adjust the read threshold voltages until a minimum RBER prediction is reached and use the set of read threshold voltages when reading data from the media.

[0050] It is noted that while the present disclosure refers to using a machine learning model to estimate RBER, the machine learning model can be trained to make predictions related to other media data quality metrics. Such metrics can be related to or a function of RBER. For example, a high reliability error rate (HRER) can be predicted using a machine learning model, which represents a number of bits with a high magnitude of log likelihood ratio (LLR) errors.

[0051] Figure 8 An example machine, the computer system 800, is illustrated in which sets of instructions for causing the machine to perform any one or more of the methodologies discussed herein can be executed. In some embodiments, the computer system 800 can correspond to a host system (e.g., the host system 120) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system 110). Figure 1 An example machine, the computer system 800, is illustrated in which sets of instructions for causing the machine to perform any one or more of the methodologies discussed herein can be executed. In some embodiments, the computer system 800 can correspond to a host system (e.g., the host system 120) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system 110). Figure 1memory subsystem 110), or that can be used to perform operations of a controller (e.g., executing an operating system to perform operations corresponding to Figure 1 The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a

[0052] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a

[0053] Example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 818, which communicate with each other via a bus 830.

[0054] Processing device 802 represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or

[0055] Data storage system 818 can include a machine-readable storage medium 824 (also known as a computer-readable medium) on which is stored one or more sets of instructions 826 or software embodying any one or more of the methodologies or functions described herein. The instructions 826 can also reside completely, or at least partially, within the main memory 804 and / or within the processing device 802 during execution thereof by the computer system 800, the main memory 804 and the processing device 802 also constituting machine-readable storage media. The machine-readable storage medium 824, data storage system 818, and / or main memory 804 can correspond to the memory subsystem 110 of FIG. 1. Figure 1

[0056] In one embodiment, the instructions 826 include instructions to implement functionality corresponding to a RBER estimator (e.g., RBER estimator 113) of FIG. 1. While the machine-readable storage medium 824 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media. Figure 1

[0057] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. A

[0058] It is also important to note that the machine-readable storage medium 824 can correspond to a single physical memory device or multiple physical memory devices, such as a central processing unit (CPU) of the computer system 800, a chipset of the computer system 800, or any other memory device(s) of the computer system 800. Thus, the machine-readable storage medium 824 can correspond to RAM, ROM, a hard disk, a solid state drive, a floppy disk, a magnetic tape, a USB drive, an optical storage, a flash memory, or other storage medium.

[0059] ​​The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the required purposes, or it can comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. For example, a computer system or other data processing system, such as controller 115, can implement portions of the computer-implemented method 700 in response to its processor executing a computer program (e.g., a series of instructions) contained in a memory or other non-transitory machine-readable storage medium. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0060] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as follows from the description. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the present disclosure as described herein.

[0061] The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions, which can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form accessible by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium, such as a read only memory (“ROM”), a random access memory (“RAM”), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0062] In the various embodiments described above and in the following claims, unless specifically stated otherwise, e.g., by the phrase "A, B, or C" or the like, disjunctive language such as the phrase "at least one of A, B, or C" is intended to mean that A, B, or C, or any combination thereof (e.g., A, B, and / or C) is possible. Thus, the disjunctive language is not intended to imply that at least one of A, at least one of B, or at least one of C each must be present in the given embodiment.

[0063] In the foregoing specification, embodiments of the disclosure have been described with reference to specific example embodiments thereof. It is evident that various modifications can be made thereto without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The Specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method comprising: Read encoded data from a set of memory cells in the memory subsystem; Obtain overall data for a number of memory cells in the group of memory cells having read voltages within a read voltage range, the overall data including: A first number of memory cells having a read voltage less than a first threshold voltage; and A second number of memory cells having a read voltage greater than the first threshold voltage and less than a second threshold voltage; Using a first trained machine learning model, the estimated raw bit error rate of the encoded data is predicted to satisfy a first threshold using the overall data; and In response to determining that the estimated raw bit error rate meets the first threshold, a first media management operation is initiated.

2. The method according to claim 1, further comprising: Additional total data is obtained by using an additional number of memory cells in the group of memory cells having read voltages within different read voltage ranges, the additional total data including at least one of the following: A third number of memory cells having read voltages greater than the second threshold voltage and less than a third threshold voltage; and A fourth number of memory cells having a read voltage greater than the third threshold voltage and less than a fourth threshold voltage; and in: The estimated raw bit error rate of the data is further based on the additional overall data; and The reading voltage range does not overlap with the different reading voltage ranges.

3. The method of claim 1, wherein the estimated raw bit error rate is further based on: Programming erase count of the group memory cells A block of memory cells containing the group of memory cells. Including an indication of one or more word lines in the group of memory cells, or Instructions are provided to the host to provide unencoded data, which is then encoded and stored as the encoded data in the group memory unit.

4. The method of claim 1, further comprising: The first trained machine learning model is selected based on the first media management operation.

5. The method according to claim 1, wherein the first media management operation is: Calibration is used to interpret the threshold voltage of the read voltage stored in the memory cell. Data retention checks are used to determine whether the encoded data should be decoded, re-encoded, and rewritten to the memory subsystem, or Error correction code decoding operation.

6. The method of claim 1, wherein the first trained machine learning model is a decision tree model, a neural network model, or a logistic regression model.

7. The method of claim 1, further comprising: Using a second trained machine learning model, the estimated raw bit error rate of the data is determined to meet a second threshold based on the total data; and In response to determining that the estimated raw bit error rate meets the second threshold, a second media management operation is initiated, wherein the second media management operation is an operation of a different type from the first media management operation.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means, cause the processing means to: Read encoded data from a set of memory cells in the memory subsystem; Obtain overall data for a number of memory cells in the group of memory cells having read voltages within a read voltage range, the overall data including at least one of the following: A first number of memory cells having a read voltage less than a first threshold voltage; and A second number of memory cells having a read voltage greater than the first threshold voltage and less than a second threshold voltage; Using a first trained machine learning model, the estimated raw bit error rate of the encoded data is predicted to satisfy a first threshold using the overall data; and In response to determining that the estimated raw bit error rate meets the first threshold, a first media management operation is initiated.

9. The non-transitory computer-readable storage medium of claim 8, wherein the processing apparatus further comprises: Additional total data is obtained by using an additional number of memory cells in the group of memory cells having read voltages within different read voltage ranges, the additional total data including at least one of the following: A third number of memory cells having read voltages greater than the second threshold voltage and less than a third threshold voltage; and A fourth number of memory cells having a read voltage greater than the third threshold voltage and less than a fourth threshold voltage; and in: The estimated raw bit error rate of the data is further based on the additional overall data; and The reading voltage range does not overlap with the different reading voltage ranges.

10. The non-transitory computer-readable storage medium of claim 8, wherein the estimated raw bit error rate is further based on: Programming erase count of the group memory cells A block of memory cells containing the group of memory cells. Including an indication of one or more word lines in the group of memory cells, or Instructions are provided to the host to provide unencoded data, which is then encoded and stored as the encoded data in the group memory unit.

11. The non-transitory computer-readable storage medium of claim 8, wherein the processing means further selects the first trained machine learning model based on the first media management operation.

12. The non-transitory computer-readable storage medium of claim 8, wherein the first media management operation is: Calibration is used to interpret the threshold voltage of the read voltage stored in the memory cell. Data retention checks are used to determine whether the encoded data should be decoded, re-encoded, and rewritten to the memory subsystem, or Error correction code decoding operation.

13. The non-transitory computer-readable storage medium of claim 8, wherein the first trained machine learning model is a decision tree model, a neural network model, or a logistic regression model.

14. The non-transitory computer-readable storage medium of claim 8, wherein the processing apparatus further comprises: Using a second trained machine learning model, based on the overall data, determine whether the estimated raw bit error rate of the data satisfies a second threshold; and In response to determining that the estimated raw bit error rate meets the second threshold, a second media management operation is initiated, wherein the second media management operation is an operation of a different type from the first media management operation.

15. A system comprising: Memory components; and Processing device, which is operatively coupled to the memory component, to: Encoded data is read from a set of memory cells of the memory component; Obtain overall data for a number of memory cells in the group of memory cells having read voltages within a read voltage range, the overall data including at least one of the following: A first number of memory cells having a read voltage less than a first threshold voltage; and A second number of memory cells having a read voltage greater than the first threshold voltage and less than a second threshold voltage; Additional total data is obtained by using an additional number of memory cells in the group of memory cells having read voltages in different read voltage ranges, wherein the read voltage ranges do not overlap with the different read voltage ranges; Using a first trained machine learning model, the estimated raw bit error rate of the encoded data is predicted to satisfy a first threshold using the total data and the additional total data; and In response to determining that the estimated raw bit error rate meets the first threshold, a first media management operation is initiated.

16. The system of claim 15, wherein the estimated raw bit error rate is further based on: Programming erase count of the group memory cells A block of memory cells containing the group of memory cells. Including an indication of one or more word lines in the group of memory cells, or Instructions are provided to the host to provide unencoded data, which is then encoded and stored as the encoded data in the group memory unit.

17. The system of claim 15, wherein the processing device further selects the first trained machine learning model based on the first media management operation.

18. The system of claim 15, wherein the first media management operation is: Calibration is used to interpret the threshold voltage of the read voltage stored in the memory cell. A data retention check is performed to determine whether the encoded data should be decoded, re-encoded, and rewritten to the memory component, or Error correction code decoding operation.

19. The system of claim 15, wherein the first trained machine learning model is a decision tree model, a neural network model, or a logistic regression model.

20. The system of claim 15, wherein the processing device further comprises: Using a second trained machine learning model, based on the overall data, determine whether the estimated raw bit error rate of the data satisfies a second threshold; and In response to determining that the estimated raw bit error rate meets the second threshold, a second media management operation is initiated, wherein the second media management operation is an operation of a different type from the first media management operation.

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