A clock data recovery circuit, processing chip and display device

Abstract

The present invention discloses a clock data recovery circuit, processing chip, and display device, wherein a phase detector compares a reference clock signal and a data signal to generate an initial pulse signal; a pulse width adjustment circuit performs shift register processing on the initial pulse signal to generate a shift pulse signal, and generates a target pulse signal based on a current operating mode selection signal, the shift pulse signal, and a reference clock signal; a charge pump circuit charges and discharges according to the target pulse signal to output a voltage signal; and a voltage-controlled oscillator outputs a reference clock signal based on the voltage signal. Because the clock data recovery circuit includes a pulse width adjustment circuit capable of adjusting the initial pulse signal, and because the circuit adjusts the initial pulse signal based on the reference clock signal, the pulse width of the pulse signal can be adjusted as needed without using additional signals, thereby improving the flexibility of the clock data recovery circuit.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a clock data recovery circuit, a processing chip and a display device. Background Art

[0002] In recent years, with the rapid development of communication systems, the requirements for data transmission capacity and quality have continued to increase. The ever-increasing data transmission speed has also placed higher demands on the speed, accuracy, and supported frequency range of the receiving end.

[0003] As a crucial component of data receiving circuits, the design of the clock and data recovery (CDR) circuit is crucial. The CDR circuit generates a clock synchronized with the received data, providing digital signal and clock reproduction at the receiving stage. The CDR circuit typically consists of a phase detector (PD), a charge pump (CP), and a voltage-controlled oscillator (VCO). The PD is a crucial module, as its performance directly limits the operating frequency and accuracy of the CDR circuit.

[0004] A typical CDR circuit uses a bang-bang PD circuit for phase detection. After phase detection, it directly outputs UP / DOWN pulses to control the charge and discharge of the charge pump. The pulse width is fixed at one UI. Therefore, the charge and discharge time is directly related to the operating frequency. At low operating frequencies, the output frequency increases or decreases significantly with each pulse control, which can easily cause overflow. At high operating frequencies, the pulse width is too narrow, preventing the CP from properly charging and discharging, and the frequency cannot be effectively adjusted. Both of these situations ultimately lead to CDR failure, which limits the CDR's operating frequency.

[0005] In summary, the operating frequency of the existing CDR circuit is relatively fixed, and there is a problem that the CDR cannot work normally. How to improve the flexibility of the CDR circuit is an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0006] The present invention provides a clock data recovery circuit, a processing chip and a display device, which are used to solve the problem of poor flexibility of the clock data recovery circuit in the prior art.

[0007] In a first aspect, an embodiment of the present invention provides a clock data recovery circuit, the circuit comprising:

[0008] A phase detector is used to compare the reference clock signal and the data signal to obtain an initial pulse signal;

[0009] a pulse width adjustment circuit, configured to perform shift registration processing on the initial pulse signal to generate a shift pulse signal, and generate a target pulse signal based on the working mode selection signal, the shift pulse signal, and the reference clock signal, wherein the pulse width of the target pulse signal is the same as or different from the pulse width of the initial pulse signal;

[0010] a charge pump circuit, configured to charge and discharge according to the target pulse signal and output a voltage signal;

[0011] A voltage-controlled oscillator is configured to output the reference clock signal according to the voltage signal.

[0012] In a possible implementation, the initial pulse signal includes an initial pull-up signal and an initial pull-down signal, and the shift pulse signal includes a shift pull-up signal and a shift pull-down signal;

[0013] The pulse width adjustment circuit includes a control signal generating module and an output logic module;

[0014] The control signal generating module is configured to shift and register the consecutive m initial pull-up signals and the consecutive m initial pull-down signals to generate m shifted pull-up signals and m shifted pull-down signals; and generate a target operating mode selection signal based on the current operating mode selection signal, the m shifted pull-up signals, and the m shifted pull-down signals;

[0015] The output logic module is configured to generate a target pulse signal according to the m shift pull-up signals, the m shift pull-down signals and the reference clock signal under the control of the target working mode selection signal.

[0016] In a possible implementation, the control signal generating module includes a shift register, a voting logic unit, and a timing logic unit;

[0017] The shift register is used to shift and register the continuous m initial pull-up signals and the continuous m initial pull-down signals to generate m shifted pull-up signals and m shifted pull-down signals;

[0018] The voting logic unit is used to perform logic calculation on the m shift pull-up signals and the m shift pull-down signals to generate a voting completion signal and a mode switching control signal;

[0019] The sequential logic unit is used to perform logic calculation on the voting completion signal and the mode switching control signal to generate the target working mode selection signal.

[0020] In one possible implementation, the first voting logic unit includes (m-1) first AND gates, (m-1) first OR gates, a second AND gate, a second OR gate, a first buffer, a second buffer, a first NOT gate, a second NOT gate, a first flip-flop, and a second flip-flop, wherein:

[0021] The input end of each first AND gate is used to input (m-1) shifted pull-up signals or (m-1) shifted pull-down signals, and the output end is connected to the input end of the second OR gate;

[0022] The input end of each first OR gate is used to input (m-1) shifted pull-up signals or (m-1) shifted pull-down signals, and the output end is connected to the input end of the second AND gate;

[0023] The output ends of the second OR gate and the second AND gate are used to output a mode switching control signal;

[0024] The input end of the first buffer is used to input a reference pulse signal, and the output end of the first buffer is connected to the CK end of the first trigger;

[0025] The Q terminal of the first trigger is connected to the D terminal of the second trigger and the input terminal of the first NOT gate, and the D terminal of the first trigger is connected to the output terminal of the first NOT gate;

[0026] The CK terminal of the second flip-flop is connected to the output terminal of the second NOT gate, the Q terminal of the second flip-flop is connected to the input terminal of the second NOT gate and the input terminal of the second buffer, and the second buffer is used to output the voting completion signal.

[0027] In a possible implementation, the sequential logic unit includes a logic circuit, a third trigger, a fourth trigger, an adder, a subtractor, a first selector, and a second selector;

[0028] The first input terminal of the logic circuit is used to input the voting completion signal, the second input terminal of the logic circuit is used to input the mode switching control signal, the first output terminal of the logic circuit is connected to the first input terminal of the adder, the second output terminal of the logic circuit is connected to the first terminal of the third flip-flop and the first terminal of the fourth flip-flop, the third output terminal of the logic circuit is connected to the first input terminal of the subtractor, and the fourth output terminal of the logic circuit is connected to the selection control terminal of the first selector;

[0029] The second end of the third trigger is connected to the second end of the fourth trigger and the output end of the second selector, and the output end of the third trigger is connected to the second input end of the adder;

[0030] The output terminal of the fourth trigger is connected to the second input terminal of the subtractor;

[0031] The first input terminal of the first selector is connected to the output terminal of the adder, the second input terminal of the first selector is connected to the output terminal of the subtractor, and the output terminal of the first selector is connected to the first input terminal of the second selector;

[0032] The second input terminal of the second selector is used to input up_sel<1:0>, the selection control terminal of the second selector is used to input a selection signal, and the output terminal of the second selector is used to output the target working mode selection signal.

[0033] In a possible implementation, the output logic module includes a voting logic unit, a narrow pulse generating unit, and a sampling output logic unit;

[0034] The voting logic unit is configured to output a first signal according to the m shift pull-up signals and the m shift pull-down signals under the control of the target working mode selection signal;

[0035] The narrow pulse generating unit is configured to generate a second signal according to the reference clock signal under the control of the target operating mode selection signal;

[0036] The sampling output logic unit is used to generate the target pulse signal according to the m shifted pull-up signals or the reference clock signal.

[0037] In a possible implementation, the second voting logic unit includes a fifth OR gate;

[0038] The input end of the fifth OR gate is used to input the shift pull-up signal or the shift pull-down signal, and the output end of the fifth OR gate is used to output the pulse width widening voting signal;

[0039] The narrow pulse generating unit includes a first NAND gate and a plurality of second NAND gates;

[0040] The input end of each second NAND gate is used to input the reference clock signal, and the output end is connected to the first NAND gate;

[0041] The output terminal of the second NAND gate is used to output a narrow pulse signal.

[0042] In a possible implementation, the sampling output logic circuit includes a third selector, a fourth selector, a fifth selector, a third buffer, a sixth OR gate, a third NOT gate, and a fifth trigger, wherein:

[0043] A first input terminal of the third selector is connected to the power supply terminal, a second input terminal of the third selector is used to input a shift pull-up signal or a shift pull-down signal, and an output terminal of the third selector is connected to the first input terminal of the fifth selector;

[0044] A first input terminal of the fourth selector is connected to the D terminal of the fifth flip-flop for inputting a pulse width widening voting signal, a second input terminal of the fourth selector is connected to the Q terminal of the fifth flip-flop, a control terminal of the fourth selector is connected to the output terminal of the third NOT gate, and the output terminal of the fourth selector is connected to the second input terminal of the fifth selector;

[0045] The CK terminal of the fifth trigger is connected to the output terminal of the third buffer 4 and the input terminal of the third NOT gate;

[0046] The input terminal of the third buffer is used for inputting a reference clock signal;

[0047] The input end of the sixth OR gate is used to input the working mode selection signal, and the output end is connected to the control end of the fifth selector.

[0048] In a second aspect, an embodiment of the present invention further provides a processing chip, comprising any one of the clock data recovery circuits in the first aspect.

[0049] In a third aspect, an embodiment of the present invention further provides a display device, comprising the processing chip in the second aspect.

[0050] The beneficial effects of the present invention are as follows:

[0051] The present invention discloses a clock data recovery circuit, processing chip, and display device, wherein the clock data recovery circuit includes a phase detector, a pulse width adjustment circuit, a charge pump circuit, and a voltage-controlled oscillator. The phase detector compares a reference clock signal with a data signal to generate an initial pulse signal; the pulse width adjustment circuit performs shift register processing on the initial pulse signal to generate a shift pulse signal, and generates a target pulse signal based on a current operating mode selection signal, the shift pulse signal, and a reference clock signal; the charge pump circuit charges and discharges according to the target pulse signal to output a voltage signal; and the voltage-controlled oscillator outputs a reference clock signal based on the voltage signal. Because the clock data recovery circuit includes a pulse width adjustment circuit that can adjust the initial pulse signal, and because the circuit adjusts the initial pulse signal based on the reference clock signal, the pulse width of the pulse signal can be adjusted as needed without using additional signals, thereby improving the flexibility of the clock data recovery circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0053] Figure 1 A schematic diagram of a clock data signal recovery circuit provided by an embodiment of the present invention;

[0054] Figure 2 A schematic diagram of a pulse width modulation circuit provided by an embodiment of the present invention;

[0055] Figure 3a and Figure 3b A circuit diagram of a first voting logic unit provided by an embodiment of the present invention;

[0056] Figure 4 A circuit diagram of a sequential logic unit provided by an embodiment of the present invention;

[0057] Figure 5 A schematic diagram of a logic circuit provided by an embodiment of the present invention;

[0058] Figure 6 A circuit diagram of a second voting logic unit provided by an embodiment of the present invention;

[0059] Figure 7 A circuit diagram of a narrow pulse generating unit provided by an embodiment of the present invention;

[0060] Figure 8 A circuit diagram of a sampling output logic unit provided by an embodiment of the present invention;

[0061] Figure 9 A timing diagram of halving the pulse width of an output pulse signal provided by an embodiment of the present invention;

[0062] Figure 10 A timing diagram of pulse width widening of an output pulse signal provided by an embodiment of the present invention;

[0063] Figure 11 A timing diagram of adaptively adjusting pulse width provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0064] To make the objectives, technical solutions, and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the embodiments described herein are merely some, rather than all, of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort are intended to fall within the scope of protection of the present invention.

[0065] A typical CDR circuit uses a bang-bang PD circuit for phase detection. After phase detection is complete, it directly outputs the UP / DOWN (pull-up / pull-down) pulses that control the charge pump's charge and discharge. These pulses have a fixed width of one UI. Therefore, the charge and discharge time is directly related to the operating frequency. Lower operating frequencies result in longer charge and discharge times, higher gain, and greater VCO frequency gain; vice versa. Consequently, at lower operating frequencies, the output frequency increases or decreases significantly with each pulse control, easily causing overflow. At higher operating frequencies, the narrow pulse width prevents the CP from properly charging and discharging, and the frequency cannot be effectively adjusted. Both of these situations ultimately lead to CDR failure, limiting the CDR's operating frequency.

[0066] Existing pulse width adjustment circuits are commonly used in phase detectors, analog-to-digital converters, etc. Most of them reduce the pulse width and require an additional clock signal to generate narrow pulses. The structure is complex. Therefore, designing a circuit that can adjust the pulse width output by the PD circuit to make the output pulse width more suitable for the current operating frequency, make the pulse width adjustment more flexible, simplify the structure, minimize the delay, and reduce the impact on feedback speed and system stability is a problem that needs to be solved.

[0067] Based on the above problems, an embodiment of the present invention provides a clock data signal recovery circuit, such as Figure 1 As shown, the clock data signal recovery circuit includes a phase detector (PD) 10, a pulse width adjustment circuit 20, a charge pump (CP) 30 and a voltage controlled oscillator (VCO) 40;

[0068] The phase detector 10 is used to compare the reference clock signal ck<2x-1:0> (x is a positive integer) with the data signal data to generate initial pulse signals up_bbpd and dn_bbpd;

[0069] The pulse width adjustment circuit 20 is used to perform shift register processing on the initial pulse signals up_bbpd and dn_bbpd to generate a shift pulse signal and select the signal mode_sel based on the initial working mode. <w:0>Or the current working mode selection signal bnd_sel <w:0> n , the shift pulse signal and the reference clock signal to generate a target pulse signal, wherein a pulse width of the target pulse signal is the same as or different from a pulse width of the initial pulse signal;

[0070] a charge pump circuit, configured to charge and discharge according to the target pulse signal and output a voltage signal;

[0071] A voltage-controlled oscillator is configured to output the reference clock signal according to the voltage signal.

[0072] The reference clock signal is a clock signal with a fixed frequency.

[0073] The clock data recovery circuit in an embodiment of the present invention includes a phase detector, a pulse width adjustment circuit, a charge pump circuit, and a voltage-controlled oscillator. The phase detector compares a reference clock signal with a data signal to generate an initial pulse signal. The pulse width adjustment circuit performs shift register processing on the initial pulse signal to generate a shift pulse signal, and generates a target pulse signal based on a current operating mode selection signal, a shift pulse signal, and a reference clock signal. The charge pump circuit charges and discharges according to the target pulse signal to output a voltage signal. The voltage-controlled oscillator outputs a reference clock signal based on the voltage signal. Because the clock data recovery circuit includes a pulse width adjustment circuit that can adjust the initial pulse signal, and the circuit adjusts the initial pulse signal based on the reference clock signal, the pulse width of the pulse signal can be adjusted according to actual needs without using additional signals, thereby improving the flexibility of the clock data recovery circuit.

[0074] It should be noted that mode_sel in the embodiment of the present invention <w:0>The w in the function is determined by the number of working modes. For example, if w is 1, there are two working modes, mode_sel <1> and mode_sel <0> .

[0075] The initial pulse signal in the embodiment of the present invention may include an initial pull-up signal up_bbpd and an initial pull-down signal dn_bbpd, and the shift pulse signal may include a shift pull-up signal up_bbpd <m-1:0>and shift pull-down signal dn_bbpd <m-1:0>;

[0076] like Figure 2 As shown, the pulse width adjustment circuit 20 provided by the embodiment of the present invention may include a control signal generating module 101 and an output logic module 102;

[0077] The control signal generating module 101 is used to shift and register the continuous m initial pull-up signals up_bbpd and the continuous m initial pull-down signals dn_bbpd to generate m shift pull-up signals up_bbpd <m-1:0>and m shift pull-down signals dn_bbpd <m-1:0>; Based on the current working mode selection signal, m shift pull-up signals up_bbpd <m-1:0>and m shift pull-down signals dn_bbpd <m-1:0>, generate the target working mode selection signal bnd_sel <w:0>;

[0078] Output logic module 102, used to select signal bnd_sel in target working mode <w:0>Under the control of m shift pull-up signals up_bbpd <m-1:0>and m shift pull-down signals dn_bbpd <m-1:0>The target pulse signals up_out and dn_out are generated by the reference clock signal ck<2x-1:0>.

[0079] In a specific implementation, the control signal generating module 101 may include a shift register 1011 , a voting logic unit 1012 , and a timing logic unit 1013 ;

[0080] The shift register 1011 is used to shift and register the continuous m initial pull-up signals and the continuous m initial pull-down signals to generate m shift pull-up signals up_bbpd <m-1:0>and m shift pull-down signals dn_bbpd <m-1:0>;

[0081] The first voting logic unit 1012 is used to select m shift pull-up signals up_bbpd <m-1:0>and m shift pull-down signals dn_bbpd <m-1:0>Perform logical calculations to generate the voting completion signal mode_fin and the mode switching control signal mode<1:0>;

[0082] The timing logic unit 1013 is used to perform logic calculation on the voting completion signal mode_fin and the mode switching control signal mode<1:0> to generate the target working mode selection signal bnd_sel<w:0> .

[0083] Specifically, the first voting logic unit 1012 may include (m-1) first AND gates, (m-1) first OR gates, a second AND gate, a second OR gate, a first buffer, a second buffer, a first NOT gate, a second NOT gate, a first flip-flop, and a second flip-flop, wherein:

[0084] The input end of each first AND gate is used to input (m-1) shifted pull-up signals or (m-1) shifted pull-down signals, and the output end is connected to the input end of the second OR gate;

[0085] The input end of each first OR gate is used to input (m-1) shifted pull-up signals or (m-1) shifted pull-down signals, and the output end is connected to the input end of the second AND gate;

[0086] The output terminals of the second OR gate and the second AND gate are used to output the mode switching control signal mode<1:0>;

[0087] The input end of the first buffer is used to input a reference pulse signal, and the output end of the first buffer is connected to the CK end of the first trigger;

[0088] The Q terminal of the first trigger is connected to the D terminal of the second trigger and the input terminal of the first NOT gate, and the D terminal of the first trigger is connected to the output terminal of the first NOT gate;

[0089] The CK terminal of the second flip-flop is connected to the output terminal of the second NOT gate, the Q terminal of the second flip-flop is connected to the input terminal of the second NOT gate and the input terminal of the second buffer, and the second buffer is used to output the voting completion signal mode_fin.

[0090] The first voting logic unit is described below with reference to a specific embodiment.

[0091] like Figure 3a and Figure 3b As shown, the following description is made by taking four pull-up signals (UP pulses) for judgment once as an example.

[0092] Figure 3a and Figure 3b In the example, the voting logic unit includes four first AND gates (31, 32, 33, 34), four first OR gates (35, 36, 37, 38), a second AND gate 39, a second OR gate 40, a first buffer 41, a second buffer 42, a first NOT gate 43, a second NOT gate 44, a first flip-flop DFF1, and a second flip-flop DFF2, wherein:

[0093] The first AND gate and the second AND gate are three-input AND gates, and the first OR gate and the second OR gate are four-input OR gates. The types of the AND gates and the OR gates can be selected according to actual needs, and the embodiment of the present invention does not limit this.

[0094] The first input terminal of the first AND gate 31 is used to input the shift pull-up signal up_bbpd <0> The second input is used to input the shift pull-up signal up_bbpd <1> The third input terminal is used to input the shift pull-up signal up_bbpd <2> ;

[0095] The first input terminal of the second AND gate 32 is used to input the shift pull-up signal up_bbpd <0> The second input is used to input the shift pull-up signal up_bbpd <1> The third input terminal is used to input the shift pull-up signal up_bbpd <3> ;

[0096] The first input terminal of the third AND gate 33 is used to input the shift pull-up signal up_bbpd <0> The second input is used to input the shift pull-up signal up_bbpd <2> The third input terminal is used to input the shift pull-up signal up_bbpd <3> ;

[0097] The first input terminal of the fourth AND gate 34 is used to input the shift pull-up signal up_bbpd <1> The second input is used to input the shift pull-up signal up_bbpd <2> The third input terminal is used to input the shift pull-up signal up_bbpd <3> ;

[0098] The second OR gate 40 is used to output a mode switching control signal mode <0> ;

[0099] The first input terminal of the first OR gate 35 is used to input the shift pull-up signal up_bbpd <0> The second input is used to input the shift pull-up signal up_bbpd <1> The third input terminal is used to input the shift pull-up signal up_bbpd <2> ;

[0100] The first input terminal of the second OR gate 36 is used to input the shift pull-up signal up_bbpd <0> The second input is used to input the shift pull-up signal up_bbpd <1> The third input terminal is used to input the shift pull-up signal up_bbpd <3> ;

[0101] The first input terminal of the third OR gate 37 is used to input the shift pull-up signal up_bbpd <0> The second input is used to input the shift pull-up signal up_bbpd <2> The third input terminal is used to input the shift pull-up signal up_bbpd <3> ;

[0102] The first input terminal of the fourth OR gate 38 is used to input the shift pull-up signal up_bbpd <1> The second input is used to input the shift pull-up signal up_bbpd <2> The third input terminal is used to input the shift pull-up signal up_bbpd <3> ;

[0103] The output terminal of the second AND gate 39 is used to output a mode switching control signal mode <1> ;

[0104] Figure 3b In the embodiment, the input terminal of the first buffer 41 is used to input the reference pulse signal, and the output terminal of the first buffer 41 is connected to the CK terminal of the first flip-flop DFF1;

[0105] The Q terminal of the first flip-flop DFF1 is connected to the CK terminal of the second flip-flop DFF2 and the input terminal of the first NOT gate 43 , and the D terminal of the first flip-flop DFF1 is connected to the output terminal of the first NOT gate 43 ;

[0106] The D terminal of the second flip-flop DFF2 is connected to the output terminal of the second NOT gate 44 , and the Q terminal of the second flip-flop DFF2 is connected to the input terminal of the second NOT gate 44 and the input terminal of the second buffer 42 . The second buffer 42 is used to output the voting completion signal mode_fin.

[0107] like Figure 4 As shown, the sequential logic unit 1013 may include a logic circuit 10131, a third flip-flop DFF3, a fourth flip-flop DFF4, an adder 10132, a subtractor 10133, a first selector 10134 and a second selector 10135;

[0108] A first input terminal of the logic circuit 10131 is used to input a voting completion signal mode_fin. A second input terminal of the logic circuit 10131 is used to input a mode switching control signal mode<1:0>. A first output terminal of the logic circuit 10131 is connected to a first input terminal of the adder 10132. A second output terminal of the logic circuit 10131 is connected to a first terminal of a third flip-flop DFF3 and a first terminal of a fourth flip-flop DFF4 for outputting a done signal. A third output terminal of the logic circuit 10131 is connected to a first input terminal of a subtractor 10133. A fourth output terminal of the logic circuit 10131 is connected to a selection control terminal of a first selector 10134.

[0109] A second end of the third flip-flop DFF3 is connected to the second end of the fourth flip-flop DFF4 and the output end of the second selector 10135 , and the output end of the third flip-flop DFF3 is connected to the second input end of the adder 10132 ;

[0110] An output terminal of the fourth flip-flop DFF4 is connected to a second input terminal of the subtractor 10133;

[0111] A first input terminal of the first selector 10134 is connected to the output terminal of the adder 10132, a second input terminal of the first selector 10134 is connected to the output terminal of the subtractor 10133, and the output terminal of the first selector 10134 is connected to a first input terminal of the second selector 10135;

[0112] The second input terminal of the second selector 10135 is used to input the initial working mode signal mode_sel <w:0>The selection control terminal of the second selector 10135 is used to input the selection signal set (the set signal is an external input and can be set according to actual needs), and the output terminal of the second selector 10135 is used to output the target working mode selection signal bnd_sel <w:0>.

[0113] Specifically, such as Figure 5 As shown, the logic circuit 10131 may include a sixth flip-flop DFF6, a seventh flip-flop DFF7, a fourth buffer 101316, and a fifth buffer 101317;

[0114] The D terminal of the sixth flip-flop DFF6 is used to input mode <0> The CK terminal of the sixth flip-flop DFF6 is connected to the CK terminal of the seventh flip-flop DFF7 and the input terminal of the fourth buffer 101316 for inputting mode_fin, and the Q terminal of the sixth flip-flop DFF6 is used to output the add signal;

[0115] The D terminal of the seventh flip-flop DFF7 is used to input mode <1> , a Q terminal of the seventh flip-flop DFF7 is connected to the input terminal of the fifth buffer 101317 for outputting the sub signal;

[0116] The output terminal of the fourth buffer 101316 is used to output a done signal;

[0117] The output end of the fifth buffer 101317 is used to output the add_sub-sel signal.

[0118] The control signal generation module consists of a voting logic unit, a timing logic unit and a shift register. The input signals are the UP / DOWN signal up_bbpd / dn_bbpd output by the PD and the initial working mode selection signal mode_sel <w:0>, the output is the working mode control signal bnd_sel <w:0>(w is determined by the number of working modes.) The shift register is used to shift and store m consecutive pulses of the UP / DOWN signal to obtain up_bbpd / dn_bbpd <m-1:0>. It is input into the voting logic unit, which makes a judgment: among the m pulses, if there are more than m / 2 high levels, the next moment switches to a working mode wider than the current output pulse width; if there are m / 2 high levels, it remains unchanged; if there are less than m / 2 high levels, the next moment switches to a working mode narrower than the current output pulse width. Based on the judgment result, the voting completion signal mode_fin and the mode switching control signal mode<1:0> are output, and the timing logic unit controls the working mode control signal bnd_sel according to the current working mode. <w:0> n Or initial working mode mode_sel <w:0>, generate a new mode selection control signal bnd_sel <w:0> n+1 , thereby adjusting the degree of increase or decrease of the pulse.

[0119] One possible implementation method is to use the voting result to control the adder or subtractor to convert the current control signal bnd_sel <w:0> n Add 1 or subtract 1, that is, switch to a working mode with a wider or narrower pulse width, and output it through the selector to obtain a new control signal bnd_sel <w:0> n+1 .

[0120] In one embodiment, the output logic module 102 may include a second voting logic unit 1021 , a narrow pulse generating unit 1022 , and a sampling output logic unit 1023 ;

[0121] The second voting logic unit 1021 is configured to output a pulse width widening voting signal according to a plurality of shift pull-up signals and a plurality of shift pull-down signals under the control of a target working mode selection signal;

[0122] a narrow pulse generating unit 1022 for generating a narrow pulse signal according to a reference clock signal under the control of a target operating mode selection signal;

[0123] The sampling output logic unit 1023 is configured to generate a target pulse signal according to a plurality of shifted pull-up signals or a reference clock signal.

[0124] Specifically, the second voting logic unit 1021 may include a fifth OR gate, an input end of the fifth OR gate is used to input the shift pull-up signal or the shift pull-down signal, and an output end of the fifth OR gate is used to output the pulse width widening voting signal.

[0125] like Figure 6 As shown, it is a circuit schematic diagram in which the number of shift pull-up signals is 2. Figure 6 In the example, the first input terminal of the fifth OR gate 10211 inputs up_bbpd <0> , the second input terminal inputs up_bbpd <1> , the output end outputs the pulse width widening voting signal vote_up.

[0126] The above description is based on the pull-up signal as an example. The same is true for the pull-down signal, so no further examples are given here.

[0127] The narrow pulse generating unit 1022 in the embodiment of the present invention may include a first NAND gate and multiple second NAND gates, the input end of each second NAND gate is used to output a reference clock signal, the output end is connected to the first NAND gate, and the output end of the second NAND gate is used to output a narrow pulse signal.

[0128] like Figure 7 As shown, the example of reducing the original pulse width to 1 / 4 is used for illustration. Figure 7 In the embodiment, a first NAND gate 10221, a second NAND gate 10222 and a second NAND gate 10223 are included, wherein the first input terminal of 10222 inputs clk <1> , the second input terminal inputs clk <7> , the output terminal is connected to the first input terminal of 10221; the first input terminal of 10223 inputs clk <3> , the second input terminal inputs clk <5> , the output end is connected to the second input end of 10221; the output end of 10221 outputs a narrow pulse signal pulse_narrow.

[0129] The sampling output logic unit 1023 in the embodiment of the present invention is as follows: Figure 8 As shown, the first embodiment may include a third selector 10231, a fourth selector 10232, a fifth selector 10233, a third buffer 10234, a sixth OR gate 10235, a third NOT gate 10236, and a fifth flip-flop DFF5, wherein:

[0130] A first input terminal of the third selector 10231 is connected to the power supply terminal (vdd) for providing a high-level signal. A second input terminal of the third selector 10231 is used to input a shift pull-up signal or a shift pull-down signal. An output terminal of the third selector 10231 is connected to a first input terminal of the fifth selector 10233.

[0131] A first input terminal of the fourth selector 10232 is connected to the D terminal of the fifth flip-flop DFF5 for inputting vote_up. A second input terminal of the fourth selector 10232 is connected to the Q terminal of the fifth flip-flop DFF5. A control terminal of the fourth selector 10232 is connected to the output terminal of the third NOT gate 10235. The output terminal of the fourth selector 10232 is connected to the second input terminal of the fifth selector 10233.

[0132] The CK terminal of the fifth flip-flop DFF5 is connected to the output terminal of the third buffer 10234 and the input terminal of the third NOT gate 10235;

[0133] The input terminal of the third buffer 10234 is used to input the reference clock signal ck;

[0134] The input terminal of the sixth OR gate 10235 is used to input bnd_sel <m:0>, such as bnd_sel <0> and bnd_sel <1> , the output end is connected to the control end of the fifth selector 10233.

[0135] In the embodiment of the present invention, the second voting logic unit is used for pulse voting and works when the pulse width needs to be widened. It is implemented by a logic circuit and its input is the shifted up_bbpd <m-1:0> / dn_bbpd <m-1:0>The second voting logic unit can use the up_bbpd / dn_bbpd obtained in the control signal generation module to generate the control signal. <m-1:0>Voting is performed according to the control signal. When the working mode is to widen the pulse width to several times of the original pulse width, voting is performed on several consecutive pulses. When there is a high level among them, the output is high.

[0136] The narrow pulse generation unit generates narrow pulse signals and operates when the pulse width needs to be reduced. It is implemented using logic gates and takes as input the PD's UP / DOWN signals up_bbpd / dn_bbpd, the reference clock signal ck<2x-1:0>, and the mode selection control signal. The sampling clock is the multiphase clock used by the bang-bang PD in the CDR to sample data. Based on the operating mode corresponding to the control signal, the logic circuit uses ck<2x-1:0> to generate a narrow pulse with a rising edge width of 1 / 2x UI.

[0137] The sampling and output unit, implemented with logic gates, selectors, and flip-flops, samples up_bbpd / dn_bbpd using narrow pulses or the voting module output signal, outputting pulse width-adjusted pulse signals up_out / dn_out. Depending on the operating mode control signal, when the pulse width is reduced, narrow pulses are used to sample up_bbpd / dn_bbpd, resulting in an output pulse signal up_out / dn_out with a pulse width 1 / 2x the original width. When the pulse width is increased, the voting module output signal is used for sampling, resulting in an output pulse signal with a pulse width of 1 to m UI.

[0138] Traditional CDR circuits often directly output UP / DOWN signals (up_bbpd and dn_bbpd) with a pulse width of one UI to control the charge pump's charging and discharging, thus limiting the frequency range of normal operation. The present invention incorporates a pulse-width adjustment circuit into the CDR circuit. This circuit processes the UP / DOWN signals through a logic unit, depending on the operating frequency, and outputs UP / DOWN control signals with narrower or wider pulse widths, thereby varying the VCO's adjustment frequency. During low-frequency operation, reducing the pulse width shortens the charge pump's on-time, preventing overcharging and discharging and reducing gain. During high-frequency operation, widening the pulse width reduces the speed, ensuring normal charge and discharge of the charge pump.

[0139] Furthermore, compared to conventional pulse-width adjustment modules, this module adds adaptive adjustment functionality. Through the logic unit, it adjusts the operating mode and the degree of pulse widening or reduction based on changes in the UP / DOWN signal, enabling it to automatically adapt to the current operating frequency. Thus, by controlling the operating mode of the output logic module through the control signal generation module, the pulse width of the PD's UP / DOWN signal can be adjusted to meet the needs of higher and lower operating frequencies, expanding the operating frequency range of the CDR circuit.

[0140] For ease of understanding, the present invention is described below with reference to specific embodiments.

[0141] Example 1: The pulse width of the output pulse signal is halved.

[0142] Circuit timing is as follows Figure 9 The control signal generation module outputs a fixed control signal. After shift registering the UP / DOWN pulse signals up_bbpd and dn_bbpd, they are input to the output logic module. The logic unit processes the multi-phase clock signal ck<7:0> to generate a narrow pulse signal ck_sel with a duty cycle of 1 / 4, that is, a rising edge width of 1 / 4 UI. The ck_sel signal is used to sample the UP / DOWN pulse signal: when the ck_bbpd signal and the output UP / DOWN pulse width are both high, the output signal is high; otherwise, the output signal is low, completing the pulse width reduction.

[0143] Example 2: The pulse width of the output pulse signal is widened to 2 UI.

[0144] Circuit timing is as follows Figure 10 The UP / DOWN pulse signals up_bbpd and dn_bbpd, derived from comparing the data and the clock, are shift-registered and then input into the second voting logic unit. The second voting logic unit votes on two consecutive UP signals. If both are non-zero, a pulse signal with a width of 2 UI is output; otherwise, a 0 is output, thus widening the pulse width.

[0145] Embodiment 3: The pulse width is adaptively adjusted in an adjustment range of -1 / 4 to 2 UI.

[0146] First, a voting circuit of a control signal generating module is used to vote on four consecutive pulse signals, and the control signal obtained by voting is input into a timing logic unit for generating a control signal. Figure 11 This paper provides an implementation method for a sequential logic circuit. Taking the UP pulse signal up_bbpd as an example, the sequential logic unit performs a logical operation on the voting result signals mode_fin and mode<1:0> and then outputs a control signal to control the operation of the trigger, adder, subtractor, and selector.

[0147] Set the current working mode control signal n up_sel<1:0> n Input adder or subtractor, after completing addition or subtraction, output new working mode control signal up_sel<1:0> n+1 (When set is valid, the output working mode signal is set to the setting mode up_sel<1:0>) to control the output logic module to complete the pulse width adjustment. The same applies to the DOWN signal dn_bbpd.

[0148] The adjustment process sequence is as follows Figure 11 As shown in the figure, when the operating mode control signals up_sel<1:0> and dn_sel<1:0> are 0 to 3 (binary 00 to 11), they correspond to operating modes with output pulse widths of 1 / 4 UI, 1 / 2 UI, 1 UI, and 2 UI, respectively. Initially, the UP pulse output width is 1 / 4 UI. First, the four pulses in block 1 are voted on, and three of the up_bbdp pulses are high. Therefore, the control signals up_sel<1:0> are incremented by 1, switching to the 1 / 2 UI pulse width operating mode. At this point, the duty cycle of the narrow pulse signal ck_sel is 1 / 2, and the output up_out pulse width is 1 / 2 UI. Second, the four pulses in block 2 are voted on, and two of them are high. Therefore, the operating mode remains unchanged for the next moment. Third, the four pulses in block 3 are voted on, and one of them is high. Therefore, the control signals up_sel<1:0> are decremented by 1, switching to the 1 / 4 UI pulse width operating mode for the next moment. The initial output pulse width of the DWON pulse charge is 2 UI. For the first time, when voting on the four pulses in block 4, one of the dn_bbdp signals is high. Therefore, the control signal dn_sel<1:0> is decremented by 1, switching to a 1 UI pulse width operation mode. The output up_out pulse width is 1 UI. The second and third voting processes are similar to those for the UP pulse.

[0149] Based on the same inventive concept, an embodiment of the present invention further provides a processing chip, including any one of the above-mentioned clock data recovery circuits. The specific implementation method can refer to the clock data recovery circuit, and the repeated parts will not be repeated.

[0150] Based on the same inventive concept, an embodiment of the present invention further provides a display device, including the above-mentioned processing chip. The specific implementation method can refer to the clock data recovery circuit, and the repeated parts will not be repeated.

[0151] Those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include these modifications and variations.

Claims

1. A clock data recovery circuit, characterized in that: The circuit includes: A phase detector is used to compare the reference clock signal and the data signal to obtain an initial pulse signal; a pulse width adjustment circuit, configured to perform shift registration processing on the initial pulse signal to generate a shift pulse signal, and generate a target pulse signal based on the working mode selection signal, the shift pulse signal, and the reference clock signal, wherein the pulse width of the target pulse signal is the same as or different from the pulse width of the initial pulse signal; a charge pump circuit, configured to charge and discharge according to the target pulse signal and output a voltage signal; a voltage-controlled oscillator, configured to output the reference clock signal according to the voltage signal; Wherein, the pulse width adjustment circuit includes a control signal generating module and an output logic module; The control signal generating module is configured to shift and register the continuous m initial pull-up signals and the continuous m initial pull-down signals to generate m shifted pull-up signals and m shifted pull-down signals; and generate a target working mode selection signal based on a current working mode selection signal, the m shifted pull-up signals, and the m shifted pull-down signals; The output logic module is configured to generate a target pulse signal according to the m shift pull-up signals, the m shift pull-down signals, and the reference clock signal under the control of the target working mode selection signal, where m is a positive integer greater than 1; The control signal generating module includes a shift register, a first voting logic unit and a timing logic unit; The shift register is used to shift and register the continuous m initial pull-up signals and the continuous m initial pull-down signals to generate m shifted pull-up signals and m shifted pull-down signals; The first voting logic unit is configured to perform logic calculations on the m shift pull-up signals and the m shift pull-down signals to generate a voting completion signal and a mode switching control signal; The sequential logic unit is used to perform logic calculation on the voting completion signal and the mode switching control signal to generate the target working mode selection signal.

2. The circuit according to claim 1, wherein The initial pulse signal includes the initial pull-up signal and the initial pull-down signal, and the shift pulse signal includes the shift pull-up signal and the shift pull-down signal.

3. The circuit according to claim 1, wherein The first voting logic unit includes (m-1) first AND gates, (m-1) first OR gates, a second AND gate, a second OR gate, a first buffer, a second buffer, a first NOT gate, a second NOT gate, a first flip-flop, and a second flip-flop, wherein: The input end of each first AND gate is used to input (m-1) shifted pull-up signals or (m-1) shifted pull-down signals, and the output end is connected to the input end of the second OR gate; The input end of each first OR gate is used to input (m-1) shifted pull-up signals or (m-1) shifted pull-down signals, and the output end is connected to the input end of the second AND gate; The output ends of the second OR gate and the second AND gate are used to output a mode switching control signal; The input end of the first buffer is used to input a reference pulse signal, and the output end of the first buffer is connected to the CK end of the first trigger; The Q terminal of the first trigger is connected to the D terminal of the second trigger and the input terminal of the first NOT gate, and the D terminal of the first trigger is connected to the output terminal of the first NOT gate; The CK terminal of the second flip-flop is connected to the output terminal of the second NOT gate, the Q terminal of the second flip-flop is connected to the input terminal of the second NOT gate and the input terminal of the second buffer, and the second buffer is used to output the voting completion signal.

4. The circuit according to claim 1, wherein The sequential logic unit includes a logic circuit, a third trigger, a fourth trigger, an adder, a subtractor, a first selector and a second selector; The first input terminal of the logic circuit is used to input the voting completion signal, the second input terminal of the logic circuit is used to input the mode switching control signal, the first output terminal of the logic circuit is connected to the first input terminal of the adder, the second output terminal of the logic circuit is connected to the first terminal of the third flip-flop and the first terminal of the fourth flip-flop, the third output terminal of the logic circuit is connected to the first input terminal of the subtractor, and the fourth output terminal of the logic circuit is connected to the selection control terminal of the first selector; The second end of the third trigger is connected to the second end of the fourth trigger and the output end of the second selector, and the output end of the third trigger is connected to the second input end of the adder; The output terminal of the fourth trigger is connected to the second input terminal of the subtractor; The first input terminal of the first selector is connected to the output terminal of the adder, the second input terminal of the first selector is connected to the output terminal of the subtractor, and the output terminal of the first selector is connected to the first input terminal of the second selector; The second input terminal of the second selector is used to input up_sel<1:0>, the selection control terminal of the second selector is used to input a selection signal, and the output terminal of the second selector is used to output the target working mode selection signal.

5. The circuit according to claim 1, wherein The output logic module includes a second voting logic unit, a narrow pulse generating unit and a sampling output logic unit; The second voting logic unit is configured to output a first signal according to the m shift pull-up signals and the m shift pull-down signals under the control of the target working mode selection signal; The narrow pulse generating unit is configured to generate a second signal according to the reference clock signal under the control of the target operating mode selection signal; The sampling output logic unit is used to generate the target pulse signal according to the m shifted pull-up signals or the reference clock signal.

6. The circuit according to claim 5, wherein: The second voting logic unit includes a fifth OR gate; The input end of the fifth OR gate is used to input the shift pull-up signal or the shift pull-down signal, and the output end of the fifth OR gate is used to output the pulse width widening voting signal; The narrow pulse generating unit includes a first NAND gate and a plurality of second NAND gates; The input end of each second NAND gate is used to input the reference clock signal, and the output end is connected to the first NAND gate; The output terminal of the second NAND gate is used to output a narrow pulse signal.

7. The circuit according to claim 5, wherein: The sampling output logic unit includes a third selector, a fourth selector, a fifth selector, a third buffer, a sixth OR gate, a third NOT gate and a fifth trigger, wherein: A first input terminal of the third selector is connected to the power supply terminal, a second input terminal of the third selector is used to input a shift pull-up signal or a shift pull-down signal, and an output terminal of the third selector is connected to the first input terminal of the fifth selector; A first input terminal of the fourth selector is connected to the D terminal of the fifth flip-flop for inputting a pulse width widening voting signal, a second input terminal of the fourth selector is connected to the Q terminal of the fifth flip-flop, a control terminal of the fourth selector is connected to the output terminal of the third NOT gate, and the output terminal of the fourth selector is connected to the second input terminal of the fifth selector; The CK terminal of the fifth trigger is connected to the output terminal of the third buffer and the input terminal of the third NOT gate; The input terminal of the third buffer is used for inputting a reference clock signal; The input end of the sixth OR gate is used to input the working mode selection signal, and the output end is connected to the control end of the fifth selector.

8. A processing chip, characterized in that: The method comprises the clock data recovery circuit according to any one of claims 1 to 7.

9. A display device, characterized in that: Comprising the processing chip as claimed in claim 8.

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