Reliable health prediction through high-stress aging of memory devices

Abstract

The present application relates to reliability health prediction through high-stress burn-in of a memory device. An accelerated burn-in cycle criterion is associated with a memory die among a plurality of memory dies. The memory die undergoes one or more accelerated burn-in conditions during the accelerated burn-in cycle. In response to determining that the accelerated burn-in cycle criterion has been met, a defect scan is performed on the memory die. Based on a result of the defect scan, the memory die is associated with a corresponding reliability partition among a plurality of reliability partitions, wherein the result of the defect scan meets one or more predetermined threshold reliability criteria corresponding to the corresponding reliability partition.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to a memory subsystem, and more particularly to predicting expected reliability of memory devices in a memory subsystem. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally speaking, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, the present application provides a method comprising: associating accelerated burn-in processing cycle criteria with a memory die among a plurality of memory dies; subjecting the memory die to one or more accelerated burn-in processing conditions during the accelerated burn-in processing cycle; performing a defect scan on the memory die in response to a determination by a processing device that the accelerated burn-in processing cycle criteria have been met; and associating, by the processing device, the memory die with a corresponding reliability partition among a plurality of reliability partitions based on a result of the defect scan, wherein the result of the defect scan meets one or more predetermined threshold reliability criteria corresponding to the corresponding reliability partition.

[0004] In another aspect, the present application provides a system comprising: a test setup comprising a plurality of memory dies; and a processing device operatively coupled to the plurality of memory dies to perform a screening operation for each of the plurality of memory dies, the screening operation comprising: predetermining a plurality of checkpoints during an accelerated burn-in test, wherein each of the plurality of checkpoints corresponds to a cycle threshold criterion; determining whether the number of accelerated burn-in cycles performed on the memory die satisfies the cycle threshold criterion for a first checkpoint; in response to determining that the number of accelerated burn-in cycles satisfies the cycle threshold criterion for the first checkpoint, determining an error rate associated with the memory die; determining whether the error rate satisfies an error threshold criterion specifically for a predetermined reliability rating; and in response to determining that the error rate satisfies the error threshold criterion, repeating the screening operation until the cycle threshold criterion for a next checkpoint is met.

[0005] In another aspect, the present application provides a non-transitory computer-readable medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations including: associating accelerated burn-in processing cycle criteria with a memory die among a plurality of memory dies; subjecting the memory die to one or more accelerated burn-in processing conditions during an accelerated burn-in processing cycle; performing a defect scan on the memory die in response to a determination by the processing device that the accelerated burn-in processing cycle criteria have been met; and associating, by the processing device, the memory die with a corresponding reliability partition among a plurality of reliability partitions based on a result of the defect scan, wherein the result of the defect scan satisfies one or more predetermined threshold reliability criteria corresponding to the corresponding reliability partition. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing system including a host system coupled with a memory subsystem is shown, according to some embodiments of the present disclosure.

[0008] Figure 2 The voltage levels of a memory cell in set and reset conditions and the corresponding set and reset tolerances relative to a reference voltage are shown according to some embodiments of the present disclosure.

[0009] Figure 3 Die-level variations showing degradation of set and reset margins with increasing numbers of write cycles under normal operating conditions according to some embodiments of the present disclosure are shown.

[0010] Figure 4 A flow chart illustrating an example method for die screening based on accelerated burn-in cycles according to some embodiments of the present disclosure.

[0011] Figure 5A Voltage pulse configurations are shown for accelerated weathering cycles according to some embodiments of the present disclosure.

[0012] Figure 5B The corresponding relationship between the number of write cycles under normal operating conditions and accelerated aging conditions according to some embodiments of the present disclosure is shown.

[0013] Figure 6 A flow chart illustrating an example method of die sorting based on high and low temperature testing for error data collection according to some embodiments of the present disclosure.

[0014] Figure 7 It is shown that error threshold criteria are set to define reliability partitions according to some embodiments of the present disclosure.

[0015] Figure 8 A graph showing device-level reliability zoning classifications is shown, according to some embodiments of the present disclosure.

[0016] Figure 9 A block diagram illustrating an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0017] Aspects of the present disclosure are directed to pre-screening memory dies before they are assembled in a memory device in a memory subsystem based on reliability checks of the memory dies after applying a high stress aging process, also known as an accelerated aging process. The memory subsystem may be a memory device, a memory module, or a mixture of a memory device and a memory module. Figure 1 Describes examples of storage devices and memory modules. In general, a host system can utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory subsystem and can request data to be retrieved from the memory subsystem.

[0018] The memory subsystem may include a high-density nonvolatile memory device where data retention is required when no power is supplied to the memory device. One example of a nonvolatile memory device is a NAND memory device. Another example is a three-dimensional cross-point ("3D cross-point") memory device that includes an array of nonvolatile memory cells. A 3D cross-point memory device may be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die can be composed of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a collection of physical blocks. Each block is composed of a collection of pages. Each page is composed of a collection of memory cells ("cells"). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information and have various logical states related to the number of bits being stored. The logical states can be represented by binary values ​​(e.g., "0" and "1") or combinations of these values.

[0019] A memory device can be composed of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines (BL)) and rows (hereinafter also referred to as word lines (WL)). A word line can refer to one or more rows of memory cells of a memory device that are used together with one or more bit lines to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes the address of the memory cell. Hereinafter, a block refers to a cell of a memory device used to store data and can include a group of memory cells, a word line group, a word line, or an individual memory cell. One or more blocks can be grouped together to form a plane of a memory device to allow concurrent operations on each plane. A 3D crosspoint-based memory device can be referred to as a "driver" that has multiple dies layered in multiple "stacks." A segment of a 3D crosspoint memory device can encompass one or more stacks, one or more dies, or one or more cells that are not necessarily physically adjacent but have some common characteristics, such as having the same electrical distance (ED) between word lines (WL) and / or bit lines (BL).

[0020] In conventional memory subsystems, temperature variations and / or process drift can adversely affect the reliability of memory devices. For example, excessively high temperatures used during the heating process in the assembly flow can cause crystallization of regions of the memory device over a period of time (e.g., resetting the amorphous phase of the memory in the memory cell). This crystallization can reduce the resistivity of the memory cell, which in turn reduces the threshold voltage of the memory cell. This reduced resistivity can adversely affect reliability because high voltage levels can cause voltage level instability, leading to higher error rates in the memory device over the operational life of the memory subsystem.

[0021] For example, during the operational life of a memory device, the set state (e.g., a lower voltage level associated with a bit value of '1') and the reset state (e.g., a higher voltage level associated with a bit value of '0') of a memory cell may vary relative to a predefined threshold voltage (V t ) read level registers a higher-than-expected voltage level. Thus, a memory cell of a memory device programmed to the set state may be interpreted by a read operation as indicating a higher voltage level, indicating a reset state. This incorrect interpretation, in turn, may lead to a higher error rate due to the observed voltage level drift, which may affect the representative voltage state of the affected memory cell. Although a write operation is performed to program the memory cell to the set state, the voltage state of the memory cell may be indicated differently in response to a read operation due to the voltage level drift.

[0022] Conventional memory subsystems configured in this manner typically address the resulting reliability issues by performing repeated cycles of specialized read or write operations on the memory device to stabilize the voltage levels of the memory cells. During these "burn-in" cycles, voltage pulses are applied to the memory device to stabilize the voltage levels of the memory cells to predetermined set and reset voltage states.

[0023] In conventional memory subsystems, the intensity and duration of the burn-in voltage pulses and the number of burn-in cycles applied to the memory devices are selected based on the conditions that the memory devices are expected to experience during their lifetime. For example, in conventional memory subsystems, it is believed that the wear level of a memory device is directly dependent on the number of read / write cycles under normal operating conditions. However, conventional memory subsystems do not employ schemes for pre-screening memory dies before they are assembled into corresponding memory devices. Some memory dies may be defective from the outset and may wear out faster than other memory dies. As a result, die-level performance may vary between memory devices, and there is a risk that overall device performance may be compromised due to several suboptimal dies in a memory device that is expected to meet specific reliability criteria.

[0024] Aspects of the present disclosure address the above and other deficiencies by pre-screening suboptimal die at the outset before assembling a memory device comprised of multiple dies. Each memory device is associated with an expected performance and reliability level. The present disclosure describes a pre-assembly test setup that simulates a memory subsystem. The test setup applies accelerated stress test parameters, collectively referred to as "accelerated burn-in" or "high stress burn-in" conditions, to the die, and based on the results of the stress test, each die is associated with one of a plurality of predefined reliability categories ("reliability partitions"). This classification, in turn, determines whether the die should be assembled into a low-end memory device product with low to medium reliability expectations or a high-end memory device product with high reliability expectations. After a preset number of accelerated burn-in cycles are applied to the die, if the determined bit error rate does not meet an acceptable bit error rate associated with a stable voltage level for a memory device with a specific performance expectation, the die is not assembled into the memory device. The suboptimal die can be discarded altogether or included in a memory device with low reliability requirements. It should be noted that under normal operating conditions, a read cycle involves transferring data from the memory device to the host, and a write cycle involves transferring data from the host to the memory device. The high stress aging-based die screening scheme disclosed herein can be modified to be used for periodic calibration during the operating life of the memory device as well as during normal read / write cycling.

[0025] Advantages of the present disclosure include, but are not limited to, the ability to screen for suboptimal dies that could cause reliability issues in memory devices and compromise data integrity. This screening effectively improves yield by reducing defect metrics such as defective parts per million (DPPM). The disclosed aging process can be used to predict the wear of individual dies before they are assembled into corresponding memory devices. Furthermore, embodiments of the present disclosure can estimate data loss, guide preventative system management decisions, and enable dynamic adjustment of various performance parameters of a memory device over its lifetime. Overall, the present disclosure enables improved memory management to ensure data integrity.

[0026] Figure 1 An example computing system 100 is shown that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such devices. It should be noted that in this disclosure, the reliability test setup simulates memory subsystem 110.

[0027] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0028] The computing system 100 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or networked commercial device), or such a computing device that includes a memory and a processing device.

[0029] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1An example of a host system 120 coupled to one memory subsystem 110 is shown. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0030] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0031] The host system 120 can be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket supporting Double Data Rate (DDR)), and the like. The physical host interface can be used to transmit data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a physical host interface (e.g., a PCIe bus), the host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface can provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is shown as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0032] Memory devices 130 and 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0033] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, in which non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0034] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), and penta-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, PLC, or any combination of these. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0035] Although nonvolatile memory components such as a 3D cross-point array of nonvolatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), selectable memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0036] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0037] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in a local memory 119. In the example shown, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0038] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been shown as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0039] Typically, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block address (LBA) namespace) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0040] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0041] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) to perform media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0042] The memory subsystem 110 may further include a die screening component 113 that can be used to facilitate operations on the memory device 130. The operations include transferring data from the host to the memory device during a write cycle, and transferring data from the memory device to the host during a read cycle. Specifically, Figure 1 The die screening component 113 shown in FIG. 1 can be part of a test setup that pre-screens and sorts specific dies for assembly into memory devices with appropriate reliability ratings. In some embodiments, the die screening component 113 can be part of a memory subsystem 110 having one or more assembled memory devices 130. In those embodiments, the die screening component 113 can dynamically change memory management parameters for the memory devices 130 based on wear levels during the operational life of the memory devices. In some embodiments, the memory subsystem controller 115 includes at least a portion of the die screening component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the die screening component 113 is part of the host system 120, an application, or an operating system. In other embodiments, the local media controller 135 includes at least a portion of the die screening component 113 and is configured to perform the functionality described herein. Additional details regarding the operation of the die screening component 113 are described below.

[0043] Figure 2The voltage levels of memory cells in set and reset conditions according to some embodiments of the present disclosure and their corresponding set and reset tolerances relative to a reference voltage are shown. The reference voltage may be a sensing voltage set for a read operation. As part of a die screening process, a processing device may determine an error parameter associated with the memory cells of a memory device (e.g., a bit error rate (BER) or a codeword error rate (CWER), where a codeword is a combination of the original data plus corrected bits). In some embodiments, memory cells having a voltage state associated with a set state and memory cells having a voltage state associated with a reset state may have different error rates. The set state error rate and the reset state error rate may be determined based on the voltage distributions associated with the set state and the reset state, respectively. The set state voltage distribution 220 may have a high edge "E2," and the reset state voltage distribution 225 may have a lower edge "E3." In these examples, the set state error rate may be determined based on the tolerance of the high edge (E2) of the set state relative to the reference voltage 210. This tolerance is referred to as the "set state tolerance" or E2 tolerance. Similarly, the reset state error rate can be determined based on the tolerance of the lower edge (E3) of the reset state relative to the reference voltage 210. This tolerance is referred to as the "reset state tolerance" or E3 tolerance. The processing device can select a set of memory cells that provides a representation of the voltage levels and E2 / E3 tolerances of the entire memory device.

[0044] Figure 3 Die-level variations showing degradation of set and reset margins for several memory dies with an increasing number of write cycles under normal operating conditions according to some embodiments of the present disclosure. Normal operating conditions may include using standard voltage pulses for write cycles and / or read cycles at room temperature. Figure 3 , the E2 and E3 tolerances of several memory dies are plotted against a logarithmic number of write cycles under normal operating conditions. Each line in cluster 310 indicates the E2 tolerance of a particular die plotted against a logarithmic number of write cycles. Each line in cluster 320 indicates the E3 tolerance of a particular die plotted against a logarithmic number of write cycles. As described above, for the same error rate, the E2 tolerance and E3 tolerance can be different for the same die. Figure 3 In the example of FIG. 3 , the E3 tolerance is lower than the E2 tolerance. In this case, dies in area 370 whose E3 tolerance degrades below a threshold E3 tolerance 360 ​​after a specified number of write cycles may be pre-screened. The pre-screened dies may not be assembled into a memory device that needs to meet a specific error threshold because an E3 tolerance below the threshold 360 indicates an unacceptably high error rate. Similarly, dies whose E2 tolerance degrades below the threshold E2 tolerance 350 after a specified number of write cycles may also be pre-screened.

[0045] Figure 4is a flow chart of an example method 400 for screening and sorting memory dies into different reliability partitions according to some embodiments of the present disclosure. The method 400 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 may be performed by Figure 1 The die screening component 113 performs the following steps. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0046] At operation 420, the die screening component may associate an accelerated burn-in cycle criterion with a memory die in the plurality of memory dies. An example of associating an accelerated burn-in cycle criterion may be setting a threshold number of accelerated burn-in cycles for the memory die. Because accelerated burn-in involves high stress conditions such as temperatures significantly above room temperature and / or voltage pulses that are more aggressive than normal operating voltages, the memory die experiences substantially the same level of wear much faster during accelerated burn-in than under normal read / write operations. The number of accelerated burn-in cycles is set based on this wear equivalence. For example, for accelerated burn-in, Figure 5A The voltage pulse pattern 500 shown in FIG may have a higher intensity and a longer duration than the voltage pulse pattern for a normal write operation. Also, as an illustrative example, if the room temperature for a normal write operation is assumed to be 40° C., the temperature for the accelerated aging process may be 85° C. Figure 5BAs shown, the median threshold voltage (Vt) degrades much faster for accelerated aging than during normal operation. As a non-limiting illustrative example, 100 cycles of accelerated aging at 85°C can produce a wear level equivalent to 200,000 cycles of normal operation at 40°C, as shown along the line indicating the reset state median Vt level 525. Curve 520 shows the Vt degradation for accelerated aging, and curve 510 shows the Vt degradation for normal operation. Circle 530, where curve 520 intersects Vt level 525, indicates 100 cycles, and circle 540, where curve 510 intersects Vt level 525, indicates 200,000 cycles. Similarly, circles 550 and 560, along Vt level 545, indicate that 300 cycles of accelerated aging at 85°C are equivalent to 1 million cycles of normal operation at 40°C. It should be noted that the median voltage level for the set state is generally lower than the median voltage for the reset state, but the same pattern of accelerated degradation of the Vt level is also observed in the set state between curve 570 depicting accelerated aging and curve 580 depicting normal operation. Typically, test settings that apply accelerated aging attempt to simulate similar device wear levels during the device's operating life. This is referred to as simulating "end-of-life" (EOL) cycles.

[0047] At operation 430, the die screening assembly subjects the memory die to accelerated burn-in conditions during an accelerated burn-in cycle. For example, a voltage pulse such as 500 may be applied to the memory die at a temperature significantly above room temperature (eg, 85°C).

[0048] At operation 440, the die screening component determines that the accelerated burn-in cycle criteria have been met. For example, the die screening component may determine that a threshold number of accelerated burn-in cycles have been completed. The operation then proceeds to a defect scan. The purpose of a defect scan is to monitor reliability at specific checkpoints. The defect scan may involve various tests to collect error data that represents the current wear level of the memory die. One possible test is to vary the write-to-read (W2R) delay time at high temperature and collect data that represents E2 tolerance degradation. For example, the short W2R delay time may be set to 25 μs and the long W2R delay time may be 100 ms. Along the Vt distribution curve (e.g. Figure 2 The median value Vt at the static important point (such as the curve 220 in Figure 5B is a good indicator of E2 margin degradation, which can predict die failure, such as Figure 3 Defect scanning may involve more than one test for determining both E2 and E3 degradation. Figure 6This concept is described in more detail. For example, a fast read test may indicate E3 margin degradation. Die failure criteria may be defined by the user by configuring or training the die screening component 113.

[0049] At operation 450, the defect screening component associates the memory dies with corresponding reliability partitions in view of the results of the defect scan. Several reliability partitions may be predefined based on various reliability criteria to classify the plurality of memory dies. For example, partition 1 may be assigned to memory dies that can withstand less than 200,000 cycles. Similarly, partition 2 may be assigned to memory dies that can withstand less than 200,000-500,000 cycles, partition 3 may be assigned to memory dies that can withstand 500,000-1 million cycles, and so on. It should be noted that the number of partitions and the number of cycles associated with each partition may be defined by the user. Memory dies in different partitions may be reserved for different products. For example, memory dies in partition 1 may be reserved for lower-end memory devices with low reliability expectations, and memory dies in partition 3 may be reserved for higher-end memory devices with high reliability expectations. The die screening component may associate one or more predetermined threshold reliability criteria for each of several reliability partitions. Examples of reliability partitions are described in Figure 8 Examples of reliability criteria may include, but are not limited to, the number of failed bits at a particular threshold error rate, referred to as a failed bit count (FBC). The error rate may be a raw bit error rate (RBER) or a codeword error rate (CWER), i.e., the error rate obtained after an error correction algorithm has been applied. The CWER is a good indicator of a suboptimal die because, even after error correction, the die fails to meet the reliability criteria. Pre-screening these types of suboptimal die using a test setup at the outset prevents the inclusion of defective die in assembled memory devices associated with a specified reliability rating.

[0050] Figure 6 is a flow chart detailing an example method 600 for performing a die classification process based on error data collection as mentioned in operation 440 of method 400, according to some embodiments of the present disclosure. Method 600 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 600 may be performed by a processor coupled to Figure 1The steps are performed by a processing device in the firmware of the memory subsystem of the die screening component 113. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible. This operation may be performed periodically for each memory segment in the memory device.

[0051] At operation 610, a die screening component in a test setup subjects the memory die to accelerated burn-in conditions as described in method 400. The die screening component predetermines a plurality of checkpoints during the accelerated burn-in test. Each checkpoint corresponds to a cycle threshold criterion. The cycle threshold criterion may be a number of accelerated burn-in cycles equivalent to a number of operating cycles required to produce equivalent device wear, as discussed above with respect to method 400. Each checkpoint may be associated with a corresponding reliability partition. For example, the first checkpoint may be set at a number of accelerated burn-in cycles equivalent to 200k normal operating cycles.

[0052] At operation 620, the die screening component determines whether the number of accelerated burn-in cycles performed on the memory die satisfies the cycle threshold criteria for the first checkpoint.The operation at 610 is repeated until the threshold criteria is met.

[0053] At operation 625, in response to determining that the number of accelerated burn-in processing cycles satisfies the cycle threshold criteria for the first checkpoint, the die screening component determines an error rate associated with the memory die. A processing device coupled to the die screening component may determine the error rate based on one or more tests used to collect error data. In some embodiments, both operations 630 and 640 may be used to determine the error rate. In some other embodiments, one of operations 630 and 640 may be omitted. In some other embodiments, alternative error collection operations other than operations 630 and 640 may be selected.

[0054] At operation 630, the die screening component performs a high temperature defect scan for error data collection. For example, the high temperature may be 85° C. The error data collected from the defect scan may indicate E2 margin degradation data that may be associated with a specific predetermined error rate for a specific W2R delay (e.g., a W2R delay of 100 ms) at a specific checkpoint.

[0055] At operation 640, fast read error data is collected at a low temperature (e.g., 0°C), which can be correlated with E3 tolerance degradation. A fast read indicates a read operation that follows a write operation (with a typical delay in the microsecond range). For example, the W2R delay time can be set at 25 μs. The number of fast read operations can be 100, but other numbers can be selected. Either or both of E2 and E3 tolerance degradation can be associated with error threshold criteria.

[0056] At operation 650 , the die screening component determines whether error threshold criteria are met. Figure 7 One such example is shown of error threshold criteria set by the user or automatically selected by the die screening component based on historical data. Figure 7 Each line 710, 720, 730, 740, 750, 760, and 770 in FIG. 1 indicates the change in the codeword error rate (CWER) of the corresponding memory die. The error threshold criteria can be set to use a combination of FBC and CWER. For example, a criterion can be selected such that at a cycle threshold of 200k with a W2R delay time of 100ms, the FBC should be less than or equal to 8 (shown by 780). For the same cycle threshold and W2R delay time, the CWER should be less than 1e -5 (Shown by 790).

[0057] At operation 660, the dies that did not meet the error threshold criteria at operation 650 are placed in a first reliability partition (e.g., Figure 8 On the other hand, dies that do meet the error threshold criteria are not immediately placed in the reliability partition, but instead undergo additional accelerated burn-in cycles until the next cycle threshold is met. This process is repeated until the maximum number of accelerated burn-in cycles simulates the end-of-life (EOL) cycles of the memory die in terms of normal operating cycle equivalents, as shown in FIG. Figure 5B shown.

[0058] Figure 8 Multiple reliability partitions corresponding to various threshold cycles are shown. Each line 810, 820, 830, 840, 850, and 860 corresponds to a respective die undergoing accelerated aging. The error threshold criteria is set to less than or equal to 8 at FBC and 1e at CWER. -5(Indicated by line 805). The die corresponding to line 810 belongs to partition 1 because it crosses the error threshold at the first checkpoint of 200k cycles. However, the die corresponding to line 820 has an FBC below the error threshold at the first checkpoint of 200k cycles, so the cycle count is increased to the next cycle threshold of 500k cycles. This die is placed in partition 2 because it crosses the error threshold at the next checkpoint of 500k cycles. Following a similar process, the die corresponding to lines 830 and 840 are placed in partition 3 because they can withstand up to 1 million cycles before crossing the error threshold.

[0059] Figure 9 900 is an example machine in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. For example, the computer system 900 may correspond to a host system (e.g., Figure 1 120) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 memory subsystem 110) or can be used to perform operations of the controller (for example, execute an operating system to perform operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or as a server or a client machine in a peer-to-peer (or distributed) network environment.

[0060] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0061] The example computer system 900 includes a processing device 902, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 906 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 918, which communicate with each other via a bus 930.

[0062] Processing device 902 represents one or more general-purpose processing devices, such as microprocessors, central processing units, and the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing another instruction set, or a processor implementing a combination of instruction sets. Processing device 902 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, and the like. Processing device 902 is configured to execute instructions 926 for performing the operations and steps discussed herein. Computer system 900 may further include a network interface device 908 for communicating over a network 920. Data storage device 918 may include a machine-readable storage medium 924 (also referred to as a computer-readable medium) having stored thereon one or more instruction sets or software embodying any one or more of the methods or functions described herein. The instructions 926 may also reside, completely or at least partially, within the main memory 904 and / or within the processing device 902 during execution thereof by the computer system 900, the main memory 904 and the processing device 902 also constituting machine-readable storage media. The machine-readable storage media 924, the data storage device 918, and / or the main memory 904 may correspond to Figure 1 Memory subsystem 110.

[0063] In one embodiment, instructions 926 include instructions for implementing instructions corresponding to a particular component (e.g., Figure 1 13) of the die screening component 113). Although the machine-readable storage medium 924 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store the one or more instruction sets. The term "machine-readable storage medium" should also be considered to include any medium that can store or encode an instruction set for execution by a machine and cause the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should accordingly be understood to include (but not be limited to) solid-state memory, optical media, and magnetic media.

[0064] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the data processing arts most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. An operation is one requiring physical manipulation of physical quantities. These quantities are often, but not necessarily, in the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Primarily for reasons of common usage, it has proven convenient at times to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0065] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless expressly stated otherwise as is apparent from the above discussion, it should be understood that throughout the description, discussions utilizing terms such as "receive" or "serve" or "publish" refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage devices.

[0066] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0067] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with the programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of a variety of these systems will be presented as set forth in the description below. Additionally, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure described herein.

[0068] The present disclosure can be provided as a computer program product or software, which can include a machine-readable medium having instructions stored thereon, and the instructions can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0069] In the foregoing description, the embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method for memory die screening, comprising: associating accelerated aging cycle criteria with a memory die in the plurality of memory dies; subjecting the memory die to one or more accelerated burn-in conditions during an accelerated burn-in cycle; In response to a determination by a processing device that the accelerated burn-in processing cycle criteria have been met, performing a defect scan on the memory die; as well as The memory die is associated, by the processing device, with a respective reliability partition of a plurality of reliability partitions in view of a result of the defect scan, wherein the result of the defect scan satisfies one or more predetermined threshold reliability criteria corresponding to the respective reliability partition.

2. The method according to claim 1, further comprising: One or more memory dies are selected from the respective reliability partitions to assemble a memory device having a predetermined reliability rating.

3. The method of claim 1 , wherein subjecting the memory die to one or more accelerated burn-in conditions comprises subjecting the memory die to temperatures significantly above room temperature during the accelerated burn-in cycles.

4. The method of claim 3, wherein performing a defect scan further comprises: collecting error data corresponding to one or more predetermined write-read delay times; as well as A degradation of a set margin of the memory die relative to a reference voltage is determined in view of the erroneous data.

5. The method of claim 4, wherein performing a defect scan further comprises: subjecting the memory die to a temperature substantially below room temperature; performing a predetermined number of fast read operations on the memory die; collecting error data corresponding to the fast read operation; as well as A degradation of a reset margin of the memory die relative to the reference voltage is determined in view of the erroneous data corresponding to the fast read operation.

6. The method according to claim 1, further comprising: In response to determining that the results of the defect scan satisfy the one or more predetermined threshold reliability criteria corresponding to a first reliability partition after a first threshold number of accelerated burn-in cycles, increasing the number of accelerated burn-in cycles to a next higher threshold number.

7. The method of claim 6, wherein the maximum number of accelerated aging cycles corresponds to a total number of operating cycles that the memory die is expected to experience during its operational lifetime after being assembled into a memory device.

8. A system for memory die screening, comprising: a test setup including a plurality of memory dies; as well as a processing device operatively coupled to the plurality of memory dies to perform a screening operation for each of the plurality of memory dies, the screening operation comprising: predetermining a plurality of checkpoints during the accelerated weathering test, wherein each checkpoint in the plurality of checkpoints corresponds to a cycle threshold criterion; determining whether a number of accelerated seasoning cycles performed on the memory die satisfies a cycle threshold criterion for a first checkpoint; responsive to determining that the number of accelerated burn-in processing cycles satisfies the cycle threshold criteria for the first checkpoint, determining an error rate associated with the memory die; determining whether the error rate satisfies an error threshold criterion corresponding to a predetermined reliability rating; and In response to determining that the error rate satisfies the error threshold criterion, the screening operation is repeated until a cycle threshold criterion for a next checkpoint is satisfied.

9. The system of claim 8, wherein the operations further comprise: Responsive to determining that the error rate does not satisfy the error threshold criteria, the memory die is classified as being associated with a respective reliability partition of a plurality of reliability partitions without proceeding to the next checkpoint.

10. The system of claim 9, wherein a memory device having a predetermined reliability rating is assembled using one or more memory dies selected from the respective reliability partitions.

11. The system of claim 10, wherein the cycle threshold criterion is based on a correspondence between a number of accelerated aging cycles at high temperature and a number of normal operating cycles performed on the memory device during an operating life.

12. The system of claim 11, wherein the error threshold criterion is set based on reset margin degradation at high temperatures.

13. The system of claim 12, wherein the error threshold criterion is based on settling margin degradation at low temperatures.

14. The system of claim 10, wherein a dynamic aging process is periodically performed on the memory die after being assembled into a memory device during a normal operating life of the memory device.

15. A non-transitory computer-readable medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: associating an accelerated seasoning cycle criterion with a memory die of the plurality of memory dies; subjecting the memory die to one or more accelerated burn-in conditions during an accelerated burn-in cycle; In response to a determination by a processing device that the accelerated burn-in processing cycle criteria have been met, performing a defect scan on the memory die; as well as The memory die is associated, by the processing device, with a respective reliability partition of a plurality of reliability partitions in view of a result of the defect scan, wherein the result of the defect scan satisfies one or more predetermined threshold reliability criteria corresponding to the respective reliability partition.

16. The non-transitory computer-readable medium of claim 15, the operations further comprising: One or more memory dies are selected from the respective reliability partitions to assemble a memory device having a predetermined reliability rating.

17. The non-transitory computer-readable medium of claim 15, wherein the subjecting the memory die to one or more accelerated aging conditions comprises: The memory die is subjected to temperatures significantly above room temperature during the accelerated aging cycle.

18. The non-transitory computer-readable medium of claim 17, wherein the operation of performing a defect scan further comprises: collecting error data corresponding to one or more predetermined write-read delay times; as well as Degradation of a set margin relative to a reference voltage is determined in view of the erroneous data.

19. The non-transitory computer-readable medium of claim 15, the operations further comprising: In response to determining that the results of the defect scan satisfy the one or more predetermined threshold reliability criteria corresponding to a first reliability partition after a first threshold number of burn-in cycles, the number of accelerated burn-in cycles is increased to a next higher threshold number.

20. The non-transitory computer-readable medium of claim 19, wherein the maximum number of accelerated aging cycles corresponds to a total number of normal operating cycles that the memory die is expected to experience during an operational lifetime after being assembled into a memory device.

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