Memory with optimized resistive layer

Abstract

This application relates to a memory with optimized resistance layers. A memory system can include a separate amount or type of resistive material deposited over a memory cell and a conductive via using a separate resistance layer in an access line. A first resistive material layer can be deposited over the memory cell prior to performing an array termination etch for depositing the array of conductive vias. The array termination etch can remove the first resistive material over portions of the array for depositing the conductive vias. A second resistive material layer can be deposited after the etch has occurred and the conductive vias have been formed. The second resistive material layer can be deposited over the conductive vias.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 16 / 941,885, titled “MEMORY WITH OPTIMIZED RESISTIVE LAYERS” and filed on July 29, 2020, by Wei, et al., assigned to the assignee hereof, and expressly incorporated herein in its entirety by reference thereto. TECHNICAL FIELD

[0003] The technical field relates to a memory with optimized resistive layers. BACKGROUND

[0004] The following relates generally to one or more systems for memory, and more specifically, to a memory with optimized resistive layers.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, often denoted by a logic 1 or a logic 0. In some examples, an individual memory cell can support more than two states, any of which can be stored. To access stored information, a component can read or sense at least one stored state in a memory device. To store information, a component can write or program a state in a memory device.

[0006] There are a variety of types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self- selective memory, sulfide memory technology, and the like. Memory cells can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain their stored logic state for a long period of time even in the absence of an external power source. Volatile memory devices, such as DRAM, can lose their stored state when disconnected from an external power source. SUMMARY

[0007] A method is described. The method can include depositing a first resistive material on a plurality of memory stacks. Each of the memory stacks can include a layered assembly of electrode material and memory material. The method can further include depositing a first conductive material on the plurality of memory stacks over the first resistive material; removing regions of the plurality of memory stacks to form gaps in the first resistive material, the first conductive material, and one or more of the plurality of memory stacks; depositing a conductive material to form a conductive via in the gaps; depositing a second resistive material over the first conductive material and the conductive via; and depositing a second conductive material on the plurality of memory stacks over the second resistive material and over the via on the second resistive material.

[0008] A memory device is described. The memory device can include a substrate and a plurality of memory stacks positioned on the substrate. Each memory stack can include a layered assembly of electrode material and memory material. The memory device can further include a first resistive material positioned on the plurality of memory stacks, a first conductive material positioned on the plurality of memory stacks over the first resistive material, and a via positioned on the substrate. The via can include a conductive material. The memory device can further include a second resistive material positioned on the first conductive material and the via, and a second conductive material positioned on the second resistive material.

[0009] Another memory device is described. The memory device can include a plurality of first access lines extending in a first direction. A respective plurality of memory stacks can be positioned on the plurality of first access lines. The memory device can further include a plurality of vias each including a conductive material and aligned with a group of memory stacks in a second direction. Each group of memory stacks can include a memory stack from each of the plurality of first access lines aligned with the via in the second direction. The memory device can further include a plurality of second access lines extending in the second direction. Each second access line can extend over a via of the plurality of vias and a group of memory stacks aligned with the via. Each second access line can include a first resistive material positioned on each memory stack of the respective plurality of memory stacks, a first conductive material positioned on the first resistive material, a second resistive material positioned on the via and the first conductive material, and a second conductive material positioned on the second resistive material. BRIEF DESCRIPTION OF DRAWINGS

[0010] In the drawings, like reference numerals can designate similar components or features. Also, various components can be differentiated by following a reference numeral with a dash and a second numeral that distinguishes among like components (e.g., “100-a”). If only the first reference numeral is used in the specification (e.g., “100”), the description can apply to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0011] Figure 1 Examples of systems supporting memory with optimized resistance layers are described in accordance with examples as disclosed herein.

[0012] Figure 2 Examples of memory arrays supporting memory with optimized resistance layers are described in accordance with examples as disclosed herein.

[0013] Figures 3A to 5F Examples of operations performed as part of a manufacturing process supporting memory with optimized resistance layers are described in accordance with examples as disclosed herein.

[0014] Figure 6 Examples of memory devices supporting memory with optimized resistance layers are described in accordance with examples as disclosed herein.

[0015] Figure 7 Flowcharts illustrating examples of methods supporting memory with optimized resistance layers are shown in accordance with examples as disclosed herein. DETAILED DESCRIPTION

[0016] In some cases, resistive material can be used to control current stress to memory cells. For example, resistive material can be present between an access line driver for an access line and a memory stack containing memory cells coupled with the access line to prevent high current stress and spikes. In some cases, depositing resistive material between the access line and the memory stack can also deposit resistive material between the access line driver and the access line (e.g., over a via of the access line). However, too much resistive material can reduce efficiency or performance of the access line or memory cells. Thus, each access line or memory cell can require a different amount of resistive material. But the optimal amount of resistive material for an access line can be different than the optimal amount of resistive material for a memory cell.

[0017] To allow independent optimization of the resistive material provided for memory cells and access lines, a separate amount or type of resistive material can be deposited over the memory cells and conductive vias using a separate resistive layer in the access line. This can allow an optimized amount of resistive material for memory cells and access lines, even when those amounts can be different for each memory cell and access line.

[0018] A first resistive material layer can be deposited prior to performing an array termination etch for depositing an array of conductive vias. By doing so, the array termination etch can remove the first resistive material over portions of the array for depositing the array of conductive vias. A second resistive material layer can be deposited after the etching has occurred and the conductive vias have been formed. This allows the second resistive material layer to be deposited over the conductive vias. Thus, in a finished memory device, the first resistive material layer can be positioned between the memory cells and the conductive material in the access lines, and the second resistive material layer can be positioned between the conductive vias and the conductive material in the access lines. As a result, the first resistive material layer can be designed to provide an optimized or desired amount of resistive material for the memory cells, and the second resistive material layer can be designed to provide an optimized or desired amount of resistive material for the conductive vias, even when those amounts can not be the same as one another.

[0019] Features of the disclosure are first described in the context of a memory device as described with reference to Figure 1 and 2 Features of the disclosure are described in the context of a manufacturing process as described with reference to FIGS. 3-5. Features of the disclosure are described in the context of a memory array as described with reference to Figure 6 Features of the disclosure are described in the context of a manufacturing process as described with reference to FIGS. 3-5. Features of the disclosure are described in the context of a memory array as described with reference to Figure 7 Features of the disclosure are described in the context of a manufacturing process as described with reference to FIGS. 3-5. Features of the disclosure are described in the context of a memory array as described with reference to

[0020] Figure 1 An example memory device 100 as disclosed herein is illustrated. The memory device 100 can also be referred to as an electronic memory apparatus. Figure 1 is an illustrative representation of various components and features of the memory device 100. Thus, it should be appreciated that the components and features of the memory device 100 are shown to illustrate functional interrelationships, rather than their actual physical locations within the memory device 100. In Figure 1 In an illustrative example, the memory device 100 includes a 3D memory array 102. The memory array 102 includes memory cells 105 that are programmable to store different states. In some examples, each memory cell 105 can be programmable to store two states, denoted as a logical 0 and a logical 1. In some examples, the memory cells 105 can be configured to store more than two logical states. Although Figure 1 Some of the elements included in the various figures can be labeled with a

[0021] The memory array 102 can include two or more two-dimensional (2D) memory arrays 103 formed on top of each other. This can increase the number of memory cells that can be placed or produced on a single die or substrate as compared to 2D arrays, which in turn can reduce production costs (e.g., cost per bit), or increase performance of the memory device, or both. The memory array 102 can include two tiers of memory cells 105, and can thus be considered a 3D memory array; however, the number of tiers is not limited to two. Each tier can be aligned or positioned such that the memory cells 105 can be in alignment (precisely, overlapping, or approximately) with each other on each tier, forming a memory cell stack 145. In some cases, the memory cell stack 145 can include multiple memory cells that are on top of each other and that share a word line or bit line for both, as set forth below. In some cases, the memory cells can be multi-tier memory cells configured to store more than one data bit using multi-tier storage techniques.

[0022] In some examples, each row of memory cells 105 is connected to a word line 110, and each column of memory cells 105 is connected to a bit line 115. The term access line can refer to a word line 110, a bit line 115, or a combination thereof. The word lines 110 and bit lines 115 can be perpendicular (or nearly so) to each other and can produce a memory cell array. As shown in the example of FIG. 1, the memory array 102 includes a plurality of memory cells 105 arranged in rows and columns. Each memory cell 105 can be a multi-level memory cell configured to store more than one data bit using multi-level storage techniques. Figure 1 As shown in the example of FIG. 1, two memory cells 105 in the memory cell stack 145 can share a common conductive line, such as a bit line 115. That is, the bit line 115 can be in electronic communication with a bottom electrode of an upper memory cell 105 and a top electrode of a lower memory cell 105. Other configurations can be possible, such as a third tier sharing a word line 110 with a lower tier. In general, one memory cell 105 can be located at the intersection of two conductive lines, such as a word line 110 and a bit line 115. This intersection can be referred to as the address of the memory cell. A target memory cell 105 can be the memory cell 105 located at the intersection of an energized access line 110 and bit line 115; that is, the access line 110 and bit line 115 can be energized (can have a voltage potential or a current flow) to read or write the memory cell 105 at their intersection. Other memory cells 105 in electronic communication with (e.g., connected to) the same access line 110 or bit line 115 can be referred to as non-target memory cells 105.

[0023] The electrodes can be coupled with the memory cells 105 and word lines 110 or bit lines 115. The term electrode can refer to an electrical conductor and in some cases can function as an electrical contact to the memory cells 105. The electrodes can include traces, wires, conductive lines, conductive layers, etc. that provide an electrically conductive path between elements or components of the memory device 100. In some examples, the memory cells 105 can include a chalcogenide material positioned between a first electrode and a second electrode. One side of the first electrode can be coupled to a word line 110 and the other side of the first electrode can be coupled to the chalcogenide material. Additionally, one side of the second electrode can be coupled to a bit line 115 and the other side of the second electrode can be coupled to the chalcogenide material. The first electrode and the second electrode can be the same material (e.g., carbon) or different materials.

[0024] Operations such as reads and writes can be performed on the memory cells 105 by activating or selecting the access lines 110 and the bit lines 115. In some examples, the bit lines 115 can also be known as digit lines 115. References to access lines, word lines, and bit lines, etc. can be interchanged without affecting understanding or operation. Activating or selecting a word line 110 or a bit line 115 can include applying a voltage to the respective line. The word lines 110 and the bit lines 115 can be made of an electrically conductive material such as a metal (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), a metal alloy, carbon, an electrically conductive doped semiconductor (e.g., polysilicon), or other electrically conductive materials, alloys, compounds, etc.

[0025] Access to the memory cells 105 can be controlled by a row decoder 120 and a column decoder 130. For example, the row decoder 120 can receive a row address from a memory controller 140 and activate an appropriate word line 110 based on the received row address. Similarly, the column decoder 130 can receive a column address from the memory controller 140 and activate an appropriate bit line 115. For example, the memory array 102 can include a plurality of word lines 110 labeled WL_T1 through WL_TM for a top array, a plurality of word lines 110 labeled WL_B1 through WL_BM for a bottom array, and a plurality of digit lines 115 labeled BL_1 through BL_N, where M and N depend on the array size. Thus, by activating a word line 110 and a bit line 115, such as WL_T2 and BL_3, a memory cell 105 at their intersection can be accessed. As discussed in more detail below, access to the memory cells 105 can be controlled by the row decoder 120 and the column decoder 130, which can include one or more doped materials (e.g., forming transistors) within or on a substrate coupled to the memory array 102.

[0026] After access, the memory cell 105 can be read or sensed by the sensing component 125 to determine the stored state of the memory cell 105. For example, a voltage can be applied to the memory cell 105 (using the corresponding word line 110 and bit line 115), and the presence of a resulting current can depend on the applied voltage and threshold voltage of the memory cell 105. In some cases, more than one voltage can be applied. Additionally, if the applied voltage does not cause current to flow, other voltages can be applied until the sensing component 125 detects current. By evaluating the voltage that causes current to flow, the stored logic state of the memory cell 105 can be determined. In some cases, the magnitude of the voltage can be ramped until current flow is detected. In other cases, predetermined voltages can be applied sequentially until current is detected or a threshold or limit voltage is applied. Likewise, a current can be applied to the memory cell 105, and the magnitude of the voltage used to generate the current can depend on the resistance or threshold voltage of the memory cell 105.

[0027] In some examples, a memory cell can be programmed by providing an electrical pulse to the cell, which can include a memory storage element. The pulse can be provided via a first access line (e.g., word line 110) or a second access line (e.g., bit line 115), or a combination thereof. In some cases, after the pulse is provided, ions can migrate within the memory storage element depending on the polarity of the memory cell 105. Thus, the concentration of ions relative to a first side or a second side of the memory storage element can be based at least in part on the polarity of the voltage between the first access line and the second access line. In some cases, an asymmetrically shaped memory storage element can cause ions to be more crowded at the portion of the element having more area. Certain portions of the memory storage element can have a higher resistivity, and thus can generate a higher threshold voltage than the threshold voltage of other portions of the memory storage element. This description of ion migration represents an example of a mechanism of a memory cell for achieving the results described herein. This example of a mechanism should not be considered limiting. The present disclosure also includes other examples of mechanisms of a memory cell for achieving the results described herein.

[0028] The sensing component 125 can include various transistors or amplifiers to detect and amplify signal differences, which can be referred to as sensing or latching. The detected logic state of the memory cell 105 can then be output as an output 135 by the column decoder 130. In some cases, the sensing component 125 can be part of the column decoder 130 or the row decoder 120. Alternatively, the sensing component 125 can be connected to or in electronic communication with the column decoder 130 or the row decoder 120. The sensing component 125 can be associated with the column decoder 130 and the row decoder 120.

[0029] A memory cell 105 can be set or written to by activating an associated word line 110 and bit line 115, and at least one logic value can be stored in the memory cell 105. A column decoder 130 or a row decoder 120 can accept data to be written to the memory cell 105, such as input / output 135. In the case of a memory cell including a chalcogenide material, the memory cell 105 can be written to store a logic state in the memory cell 105 by applying a first voltage to the memory cell 105 as part of an access operation based on coupling a first conductive line of a decoder (e.g., row decoder 120 or column decoder 130) with an access line (e.g., word line 110 or bit line 115).

[0030] A memory controller 140 can control the operation of memory cells 105 (e.g., read, write, rewrite, refresh, discharge) through various components, such as row decoder 120, column decoder 130, and sense component 125. In some cases, one or more of row decoder 120, column decoder 130, and sense component 125 can be collocated with memory controller 140. Memory controller 140 can generate row and column address signals to activate desired word lines 110 and bit lines 115. Memory controller 140 can also generate and control various voltages or currents used during operation of memory device 100.

[0031] Memory controller 140 can be configured to select a memory cell 105 by applying a first voltage to a first conductive line of a decoder (e.g., row decoder 120 or column decoder 130). In some cases, memory controller 140 can be configured to couple the first conductive line of the decoder with a word line (e.g., word line 110 or bit line 115) associated with the memory cell 105 based on selecting the memory cell 105. Memory controller 140 can be configured to apply the first voltage to the memory cell 105 based at least in part on coupling the first conductive line of the decoder with an access line.

[0032] In some examples, memory controller 140 can be configured to apply a second voltage to a second conductive line of the decoder as part of an access operation. In some cases, the second voltage can cause a doped material to selectively couple the first conductive line of the decoder with an access line associated with the memory cell 105. Applying the first voltage to the memory cell 105 can be based on applying the second voltage to the second conductive line. For example, memory controller 140 can select the memory cell 105 based on an intersection of the first voltage and the second voltage. In some cases, a signal applied to a memory cell 105 as part of an access operation can have a positive or negative polarity.

[0033] In some examples, the memory controller 140 can receive a command including an instruction to perform an access operation to the memory cell 105 and identify an address of the memory cell 105 based on receiving the command. In some cases, applying the second voltage to the second conductive line can be based on identifying the address. If the access operation is a read operation, the memory controller 140 can be configured to output a logic state stored in the memory cell 105 based on applying the first voltage to the memory cell 105. If the access operation is a write operation, the memory controller 140 can be configured to store a logic state in the memory cell 105 based on applying the first voltage to the memory cell 105. While discussed as being applied using the first voltage and the second voltage, it should be understood that in some cases, a current can be applied between the first conductive line and the second conductive line to perform the access operation.

[0034] In some examples, each word line 110 and / or each bit line 115 can be coupled with a conductive via that couples the word line 110 and / or the bit line 115 with a substrate on which the memory device 100 is disposed. In general, a conductive via can be formed by etching out portions of the memory array 102 to form a gap and depositing a conductive via material in the gap. However, the method of etching out portions of the memory array 102 can damage memory cells 105 outside of the intended coverage of the gap, which can be referred to as tile or block damage. Methods of preventing tile or block damage can be described herein. Additionally, methods of processing a memory array and a conductive via to manage resistance of a word line and / or a bit line are described herein.

[0035] Figure 2 Examples of a memory device 200 that supports memory with an optimized resistance layer according to examples as disclosed herein are illustrated. The memory device 200 can be an example of the memory array 102 described with reference to Figure 1 The memory device 200 can include a first array or stack 205 of memory cells positioned over a substrate 204 and a second array or stack 210 of memory cells positioned on top of the first array or stack 205. The memory device 200 can also include word lines 110-a, 110-b and bit lines 115-a, which can be examples of the word lines 110 and the bit lines 115 as described with reference to Figure 1 The first stack 205 and the second stack 210 can each have one or more memory cells (e.g., memory cells 220-a and 220-b, respectively). While Figure 2 Some elements included in the figures can be labeled with a numerical designator, while other corresponding elements are not labeled with a numerical designator, but are instead referred to by their respective label. This is done for the sake of clarity and to increase the ease of understanding of the figures. It should be understood, however, that the use of a numerical designator in the figures is not intended to limit the scope of the disclosure in any way.

[0036] The memory cells of the first deck 205 can each include a first electrode 215-a, a memory cell 220-a (e.g., including a chalcogenide material), and a second electrode 225-a. The memory cells of the second deck 210 can each include a first electrode 215-b, a memory cell 220-b (e.g., including a chalcogenide material), and a second electrode 225-b. The first electrode 215-a, the memory cell 220-a, and the second electrode 225-a can form a first memory stack 230-a, and the first electrode 215-b, the memory cell 220-b, and the second electrode 225-b can form a second memory stack 230-b. The memory stacks can also include other layers and materials. In some examples, the memory cells of the first deck 205 and the second deck 210 can have a common conductive line, such that corresponding memory cells of each deck 205 and 210 can share a bit line 115 or a word line 110, as described with reference to Figure 1 For example, the first electrode 215-b of the second deck 210 and the second electrode 225-a of the first deck 205 can be coupled to a bit line 115-a, such that the bit line 115-a is shared by vertically adjacent memory cells. In accordance with the teachings herein, if the memory device 200 includes more than one deck, a decoder can be coupled with each deck. For example, a decoder can be coupled with the first deck 205 and the second deck 210. In some cases, the memory cells 220 can be examples of phase change memory cells or self-selecting memory cells.

[0037] The architecture of the memory device 200 can be referred to as a cross-point architecture, where memory cells are formed at topological cross-points between word lines and bit lines as illustrated in Figure 2 Such cross-point architectures can provide relatively high density data storage at lower production costs than other memory architectures. For example, a cross-point architecture can have memory cells with a reduced area and thus an increased memory cell density compared to other architectures. For example, the architecture can have a 4F2memory cell area compared to other architectures (e.g., those with three-terminal selection components) that have a 6F2memory cell area, where F is a minimum feature size. For example, DRAMs can use transistors that are three-terminal devices as selection components for each memory cell, and can have a larger memory cell area compared to cross-point architectures. In some cases, a cross-point architecture can be formed by two successive etches or cuts with a pattern along orthogonal directions.

[0038] While Figure 2Examples illustrate two memory decks, but other configurations are possible. In some examples, a single memory deck of memory cells can be constructed over the substrate 204, which can be referred to as two-dimensional memory. In some examples, three or four memory decks of memory cells can be configured in a three-dimensional cross-point architecture in a similar manner.

[0039] In some examples, one or more of the memory decks can include memory cells 220 including a chalcogenide material. The memory cells 220 may, for example, include a chalcogenide glass, such as an alloy of selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), and silicon (Si). In some examples, a chalcogenide material having primarily Se, As, and Ge can be referred to as a SAG alloy. In some examples, a SAG alloy can include Si, and such a chalcogenide material can be referred to as a SiSAG alloy. In some examples, a chalcogenide glass can include additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (CI), or fluorine (F), each of which can be in atomic or molecular form.

[0040] In some examples, a memory cell 220 including a chalcogenide material can be programmed to a logic state by applying a first voltage or a first current. By way of example, when a particular memory cell 220 is programmed, elements within the cell can separate, causing ions to migrate. Depending on the polarity of the voltage applied to the memory cell, the ions can migrate toward a particular electrode. For example, in a memory cell 220, the ions can migrate toward a negative electrode. The memory cell can then be read to sense by applying a voltage across the cell. The threshold voltage seen during a read operation can be based on the distribution of ions in the memory cell and the polarity of the read pulse.

[0041] For example, if a memory cell has a given distribution of ions, the threshold voltage detected during a read operation can be different for a first read voltage having a first polarity than for a second read voltage having a second polarity. Depending on the polarity of the memory cell, this concentration of migrated ions can represent a logic "1" or a logic "0" state. This description of ion migration represents an example of a mechanism of a memory cell for achieving the results described herein. This example of a mechanism should not be considered limiting. The present disclosure can also be applicable to other examples of mechanisms of memory cells for achieving the results described herein.

[0042] In some cases, a first voltage can be applied to the first conductive line of the decoder as part of an access operation of the memory cell 220. After the first voltage is applied, the first conductive line can be coupled with an access line (e.g., word line 110-a, word line 110-b, or bit line 115-a) associated with the memory cell 220. For example, the first conductive line can be coupled with the access line based on a doped material of the decoder extending between the first conductive line and the access line in a first direction.

[0043] In some examples, the first voltage can be applied to the memory cell 220 based on coupling the first conductive line of the decoder with the access line. The decoder can include one or more transistors selectively coupling the first conductive line and the access line of the memory device 200. In some cases, the decoder can be formed in the substrate 204.

[0044] In some examples, a resistive material can be present between the electrode and the access line. For example, a resistive barrier can be present between the electrode 215-a and the word line 110-a; the electrode 225-a and the bit line 115-a; the electrode 215-b and the bit line 115-a; the electrode 225-b and the word line 110-b; or a combination of these locations. The resistive material can be configured to prevent or reduce current surges or heat diffusion between the memory cell 220 and the word line 110 or the bit line 115.

[0045] In some examples, the word line 110 and / or the bit line 115 can be coupled with a conductive via coupling the word line 110 and / or the bit line 115 with the substrate 204. In some cases, the conductive via can be coupled with a word line 110 or a bit line 115 from a different stack. For example, in the present example, the conductive via can be coupled with the word line 110-a in the stack 205 and the word line 110-b in the stack 210. According to the art described herein, a resistive material can be formed between the electrode material and the word line or the bit line, rather than also between the conductive via and the word line or the bit line.

[0046] Figures 3A to 5F A fabrication process is described that includes performing a series of operations on a layered assembly of materials to form a memory array including conductive vias that can allow for optimized or desired amounts of resistive material for memory cells and access lines, even when those amounts can not be the same as one another.

[0047] The figures describe examples of intermediate structures that can be formed by performing operations of a fabrication process on a layered assembly of materials. Figures 3A to 3C The structures described in the left column can represent initial or partial processing steps on the layered assembly. Figures 4A to 4D The structures described in the middle column can represent a first set of processing steps performed after the initial processing steps, and the structures described in the right column can represent a second set of processing steps performed after the first set of processing steps.Figures 5A to 5F The structures illustrated in FIGS. 4A-4D can represent a second set of processing steps performed after the initial processing steps. Together, Figures 3A to 3C And 4A-4D can represent a first manufacturing process and Figures 3A to 3C And 5A-5F can represent a second manufacturing process. In some cases, the first or second manufacturing processes can include combining various operations, altering a sequence of operations, eliminating one or more steps of these operations, or any combination thereof.

[0048] Figures 3A to 3C Cross-sectional views of layered assemblies of materials 300-a-300-c supporting memory with optimized resistive layers, in accordance with examples as disclosed herein, are respectively illustrated.

[0049] In Figure 3A , the memory stacks 305 can be separated from one another by dielectric material 310. The memory stacks 305 can be composed of electrode material (e.g., electrodes 215 and 225 as described with reference to Figure 2 ) and memory material (e.g., memory cells 220 as described with reference to Figure 2 ). The dielectric material 310 can be configured to provide structure while limiting the amount of charge that can be transferred between the memory stacks 305.

[0050] In some cases, the arrangement of materials on each memory stack 305 can be the same for each memory stack 305. For example, if a first memory stack 305 has a bottom electrode material, a memory material above the bottom electrode material, and a top electrode material above the memory material, a second, adjacent memory stack can have a corresponding bottom electrode material, a corresponding memory material, and a corresponding top electrode material. The sets of materials that correspond to one another among the memory stacks 305 can be considered patterned layers. For example, the set of bottom electrodes can be considered a first patterned layer; the set of memory materials can be considered a second patterned layer; and the set of top electrodes can be considered a third patterned layer. For clarity, the individual materials of the memory stacks 305 are not illustrated in Figures 3A to 5F . Additionally, the memory stacks 305 can be in contact with a bottom conductor, which can be, for example, the word lines 110 and / or the bit lines 115 as shown in Figure 2 .

[0051] Additionally, a hard mask (HM) 315 can be used to pattern at least portions of the memory stacks 305, and can be approximately at the level of the dielectric material 310 between the memory stacks 305 after a first planarization step (e.g., via chemical mechanical planarization (CMP)). In some cases, the HM 315 can be composed of nitride material.

[0052] In Figure 3BIn some cases, the manufacturing system can perform another processing step to etch away the HM 315 (e.g., a second CMP step) and at least portions of the dielectric material 310, which can expose a top of the memory stack 305. The dielectric material 310 can have a higher material removal rate than the material removal rate of the HM 315 and the material of the memory stack 305, and can have a smaller height than the height of the memory stack 305 after the processing step to etch the HM 315. In some cases, the termination process to remove the HM 315 can be a wet process that does not cause substantial plug dishing.

[0053] In some cases, Figure 3C In some cases, the manufacturing system can deposit a resistive material 320 onto the memory stack 305 and the dielectric material 310. The resistive material 320 can also be referred to as a thermal barrier material. The manufacturing system can deposit the resistive material 320 such that the exposed top and exposed sides of the memory stack 305 are completely covered. In some cases, the resistive material 320 can be composed of tungsten silicon nitride (WSiN) or silicon carbide (SiC) or a combination thereof. In some cases, the resistive material 320 can be composed of aluminum oxide (AlOx) or tungsten oxide (WOx) or a combination thereof. Other materials are also possible.

[0054] The manufacturing system can then deposit a conductive material 325 on top of the resistive material 320. The manufacturing system can deposit the conductive material 325 such that the conductive material 325 has a relatively uniform surface on top, or can perform a process (e.g., CMP) to produce a relatively uniform surface. In such cases, the thickness of the conductive material 325 can vary depending on whether the conductive material is over the memory stack 305 or over the dielectric material 310. In some cases, the conductive material 325 can be composed of tungsten.

[0055] Figures 4A to 4D Cross-sectional views of layered assemblies supporting memory with optimized resistive layers are illustrated in accordance with examples as disclosed herein. In some cases, Figures 4A to 4D Steps that can occur after the steps illustrated in Figures 3A to 3C are illustrated.

[0056] In some cases, Figure 4A In some cases, the manufacturing system can etch away at least some of the memory stack 305 and the dielectric material 310 at the first region of the layered assembly to form a gap 405. In the same processing step, the manufacturing system can etch at least portions of the resistive material 320 and the conductive material 325. In some cases, the manufacturing system can etch one or more decks of the memory stack (e.g., the manufacturing system can etch one or more decks or all the way to the substrate). Figure 4A Steps that can occur after the steps illustrated in Figure 3CThe result of the subsequent processing steps including deposition and patterning of a mask layer and etching with the patterned mask layer to remove material from the gap 405.

[0057] The presence of the conductive material 325 can assist in preventing slotting recess at the interface between the array 425 and the gap 405. For example, in the absence of the conductive material 325 when performing etching, etching can occur faster at the interface between the array 425 and the gap 405 due to increased CMP loading. As a result, the manufacturing process can slot into the memory stack 305 beyond the pre-gap 405, which can be referred to as slotting recess. However, the planarization step to remove the mask above the conductive material 325 can result in less slotting recess due to the different mask material and increased tolerance of planarization (e.g., due to the thickness of the conductive material 325). Reduced slotting recess can reduce the likelihood of damage affecting the operation of the array or increasing the number of layers that can be formed.

[0058] In Figure 4B The manufacturing system can deposit an insulator material 410 (e.g., tetraethyl orthosilicate (TEOS) or a dielectric material) in the gap 405. For example, from the assembly shown in Figure 4A The deposition of the insulator material 410 can be followed by a planarization step (e.g., CMP) to remove the insulator material 410 above the array 425. The insulator material 410 can be configured to provide a structure and insulate the memory stack 305. After planarization, the insulator material 410 can have a top surface that is coplanar or substantially coplanar with the conductive material 325. In some cases, the conductive material 325 can be used to increase the tolerance of the planarization step, where the resistive material 320 is deposited to create the gap 405 before the etching is terminated. For example, the conductive material 325 can be substantially thicker than the resistive material 320. Without the conductive material 325 above the resistive material, it can be challenging to stop planarization at the resistive material 320 or to stop planarization partially into the resistive material 320. For example, if the planarization step does not remove all of the insulator material 410 above the array 425, the conductivity through the resistive material can be compromised. At the same time, if the planarization step removes too much of the resistive material, the performance of the memory cell can be compromised. However, performing planarization with the conductive material 325 can allow for a larger tolerance for stopping the planarization within the thickness of the conductive material 325.

[0059] In Figure 4CIn this process, the fabrication system can etch the insulating material 410 to form gaps or holes (e.g., using one or more masking steps). The gaps can extend through the insulating material 410 to, for example, a substrate beneath the insulating material 410. The fabrication system can deposit conductive via material 415 in the gaps, such that the via material 415 extends through the insulating material 410. The conductive via material 415 can have a surface aligned with the insulating material 410. In some cases, the conductive via material 415 can extend above the height of the resistive material 320 within the layered assembly.

[0060] After the via material has been deposited, the manufacturing system can deposit a resistive material 418 on the conductive material 325, the insulating material 410, and the conductive via material 415. In some cases, the resistive material 418 may be in direct contact with the conductive via material 415. The resistive material 418 may be composed of any of the materials discussed above with respect to the resistive material 320. The resistivity of the resistive material layer 418 may be the same as or different from that of the resistive material layer 320. As a result, the resistive material layer 418 may be designed to provide an optimized or desired amount of resistive material for the conductive via, regardless of whether said amount may differ from that used for the memory stack 305. In some cases, the resistivity of the resistive material 320 may be greater than that of the resistive material 418. The resistive material 418 may have the same thickness as or a different thickness than the resistive material 320. The resistive materials 320 and 418 may be composed of the same material or may be composed of different materials. In either case, resistive material 320 may be considered as a first resistive material layer or a first resistive material, and resistive material 418 may be considered as a second resistive material layer or a second resistive material. In some cases, the manufacturing system may polish the conductive material 325 before depositing the resistive material 418. Polishing may involve smoothing the surface of the conductive material 325 and may assist in the adhesion of the resistive material 418.

[0061] exist Figure 4D In this process, the manufacturing system can deposit conductive material 420 on resistive material 418 to produce memory device 400-d. Conductive materials 325 and 420 may be made of the same material or different materials. In either case, conductive material 325 may be considered a first conductive material layer or a first conductive material, and conductive material 420 may be considered a second conductive material layer or a second conductive material. In some cases, conductive material 420 may be made of tungsten. In some cases, the manufacturing system may polish the resistive material 418 before depositing the conductive material 420. Polishing may involve smoothing the surface of the resistive material 418 and may assist in the adhesion of the conductive material.

[0062] While the thickness of the resistive material 418 over the via 415 can be substantially the same as the thickness over the memory array 425, the surface area of the portion of the resistive material 418 positioned over the memory array 425 (portion 418-a) can be relatively larger and in some cases substantially larger than the surface area of the portion of the resistive material 418 positioned over the via 415 (portion 418-b). Because of this, the resistance provided by the resistive material 418 can correspond to the many equivalent resistances of the portions 418-b in parallel. As a result, the total resistance provided by the resistive material 418 between the substrate (e.g., an access line driver) and the memory stack 305 can be dominated by the portion positioned over the via 415 (e.g., portion 418-b).

[0063] Together, the first resistive material 320, the first conductive material 325, the second resistive material 418, and the second conductive material 420 can together form an access line (e.g., a word line 110 or a bit line 115). As shown, the first resistive material 320 can be positioned between the memory stack 305 and the conductive materials 325 and 420 in the access line, and the second resistive material 418 can be positioned between the conductive via 415 and the conductive material 420 in the access line. Using the memory device 400-d, independent optimization of resistive materials can be provided for the memory cells and the access line. Separate amounts or types of resistive materials can be deposited over the memory cells and the conductive via using separate resistive layers in the access line. This can allow optimized or desired amounts of resistive materials to be used for the memory cells and the access line, even when those amounts can be different from each other.

[0064] Figures 5A to 5F Cross-sectional views of layered assemblies of materials 500-a through 500-f supporting memory with optimized resistive layers are illustrated in accordance with examples as disclosed herein. In some cases, Figures 5A to 5F Steps performed after the steps represented by Figures 3A to 3C are represented.

[0065] In Figure 5A , the manufacturing system can deposit an encapsulation material 505 over the conductive material 325. The encapsulation material 505 can protect the resistive material 320, the conductive material 325, and the memory stack 305 during processing. In some cases, the manufacturing system can polish the conductive material 325 prior to depositing the encapsulation material 505. Polishing can flatten the surface morphology of the conductive material 325, and can enable the manufacturing system to deposit the encapsulation material 505 on a uniform surface.

[0066] In Figure 5BIn this process, the manufacturing system may etch away at least some of the memory stack 305 and dielectric material 310 at a first region of the layered assembly to form a gap 530. In the same processing step, the manufacturing system may etch at least a portion of the resistive material 320, conductive material 325, and end-capping material 505. Additionally, the manufacturing system may deposit a liner material 510 over the end-capping material 505 and within the gap 530. The liner material 510 may be deposited over the exposed portion of the gap 530, including a bottom (e.g., a substrate) and sides (e.g., sidewalls of the array 525). Therefore, the liner material 510 may have a first horizontal portion over the end-capping material 505, a second horizontal portion over the gap 530, and a vertical portion contacting the ends of the end-capping material 505, conductive material 325, and resistive material 320, as well as one side of the memory stack 305 or dielectric 310. The vertical portions of the liner material 510 can protect adjacent memory stack 305, end cap material 505, conductive material 325, resistive material 320, or combinations thereof during additional processing or operation (e.g., through additional insulating properties). The liner material 510 may, for example, have a higher dielectric constant than the dielectric material used to fill gap 530.

[0067] The vertical portion of the liner material 510 may contact the memory stack 305. In some cases, the vertical portion may abut the first and second horizontal portions. The liner material 510 may be made of the same material as the end cap material 505, or it may be made of a different material. For example, both the end cap material 505 and the liner material 510 may be made of a nitride-based material. Alternatively, the end cap material 505 may be made of a nitride-based material, and the liner material 510 may be made of a nitride-based material different from that of the end cap material 505.

[0068] exist Figure 5C In this process, the manufacturing system can fill gaps 530 with an insulating material 515 (e.g., TEOS or a dielectric material). A two-step planarization or removal process can be used to fill gaps 530 and planarize the assembly after depositing the insulating material 515. First, the insulating material 515 can be deposited over both array 525 and gaps 530 (not shown). A first planarization step can then be used to remove the dielectric material over array 525. The first planarization step can be designed to stop on end cap material 505. The first planarization step can use a first abrasive slurry (e.g., an oxide abrasive slurry). The first planarization step can produce Figure 5Cthe array and dielectric assembly shown in FIG. 5. Thus, insulator material 515 is shown over the second horizontal portion of liner material 510, and gap fill to the height of the capping material 505 (or the portion of capping material 505 that remains after stopping at capping material 505 in a planarization step). Liner material 510 can form a barrier between insulator material 515 and resistive material 320 and between insulator material 515 and conductive material 325.

[0069] After depositing insulator material 515 and performing the first planarization process, the manufacturing system can etch insulator material 515 and portions of liner material 510 to form gap or hole 540. The manufacturing system can deposit conductive via material 520 in gap or hole 540 such that via material 520 extends through insulator material 515. In some cases, the top surface of conductive via material 520 can be in line with insulator material 515. In some cases, conductive via material 520 can extend to a height within the layered assembly that is higher than the resistive material.

[0070] After Figure 5D In some cases, the manufacturing system can use a second planarization step to remove capping material 505 to produce a layered assembly of material 500-d. The second planarization step can use different processing characteristics than the first planarization step (e.g., a second polishing slurry that is different than the first polishing slurry). The second planarization process can be formulated to stop on conductive material 325.

[0071] After completing the second planarization process, the top surface of conductive material 325, the top surface of the vertical portion of liner material 510, the top surface of insulator material 515, and the top surface of conductive via material 520 can be approximately coplanar with one another.

[0072] After Figure 5EIn some cases, the manufacturing system can deposit a resistive material 550 on top of the conductive material 325, the vertical portion of the liner material 510, the insulator material 515, and the conductive via material 520. In some cases, the resistive material 550 can be in direct contact with the conductive via material 520. The resistive material 550 can be composed of any of the materials discussed above with respect to the resistive material 320. The resistivity of the resistive material layer 550 can be the same or different than the resistivity of the resistive material layer 320. As a result, the resistive material layer 550 can be designed to provide an optimized or desired amount of resistive material for the conductive via, regardless of whether that amount can be different than the amount used for the memory stack 305. In some cases, the resistivity of the resistive material 320 can be greater than the resistivity of the resistive material 550. The resistive material 550 can be the same thickness or a different thickness than the thickness of the resistive material 320. The resistive materials 320 and 550 can be composed of the same material or can be composed of different materials. In either case, the resistive material 320 can be considered a first resistive material layer or a first resistive material, and the resistive material 550 can be considered a second resistive material layer or a second resistive material. In some cases, the manufacturing system can polish the conductive material 325 prior to depositing the resistive material 550. Polishing can involve smoothing the surface of the conductive material 325 and can assist with adhesion of the resistive material 550.

[0073] In Figure 5F In some cases, the manufacturing system can deposit a conductive material 555 on the resistive material 550 to produce the memory device 500-f. The conductive materials 325 and 555 can be composed of the same material or can be composed of different materials. In either case, the conductive material 325 can be considered a first conductive material layer or a first conductive material, and the conductive material 555 can be considered a second conductive material layer or a second conductive material. In some cases, the conductive material 555 can be composed of tungsten. In some cases, the manufacturing system can polish the resistive material 550 prior to depositing the conductive material 555. Polishing can involve smoothing the surface of the resistive material 550 and can assist with adhesion of the conductive material 555.

[0074] While the thickness of the resistive material 550 over the via 520 can be generally the same as the thickness over the memory array 525, the surface area of the portion of the resistive material 550 positioned over the memory array 525 (portion 550-a) can be relatively greater and in some cases generally greater than the surface area of the portion of the resistive material 550 positioned over the via 520 (portion 550-b). Because of this, the resistance provided by the resistive material 550 can correspond to the many equivalent resistances of the portion 550-b in parallel. As a result, the total resistance provided by the resistive material 550 between the substrate (e.g., an access line driver) and the memory stack 305 can be dominated by the portion positioned over the via 520 (e.g., portion 550-b).

[0075] Together, the first resistive material 320, the first conductive material 325, the second resistive material 550, and the second conductive material 555 can together form an access line (e.g., a word line 110 or a bit line 115). As shown, the first resistive material 320 can be positioned between the memory stack 305 and the conductive materials 325 and 555 in the access line, and the second resistive material 550 can be positioned between the conductive via 520 and the conductive material 555 in the access line. Using the memory device 500-f, independent optimization of resistive materials can be provided for the memory cell and the access line. Separate amounts or types of resistive materials can be deposited over the memory cell and the conductive via using separate resistive layers in the access line. This can allow optimized or desired amounts of resistive materials for the memory cell and the access line, even when those amounts can be different from each other.

[0076] In general, the processes as described herein can enable smaller die sizes because the processes described herein can limit tile damage that occurs at smaller scales. Additionally or alternatively, the processes described herein can reduce the size of a slot or can completely prevent the formation of a slot, which can reduce the likelihood that tile damage will occur. Additionally or alternatively, the processes described herein can provide fewer dummy line opportunities.

[0077] Figure 6 An example of a memory device 600 that supports memory with optimized resistive layers is described in accordance with examples as disclosed herein. The memory device 600 can be an example of the memory device 200 described with reference to Figure 1 the memory array 102 described with reference to Figure 2 the memory device 200 described with reference to Figure 1 and 2 .

[0078] The memory device 600 can also include an array of memory stacks 635 positioned on the word lines 610. Each word line 610 can have a respective plurality of memory stacks 635 positioned thereon (e.g., memory stacks 635-a and 635-c on word line 610-a and memory stacks 635-b and 635-d on word line 610-b). The memory stacks 635 can be composed of memory cells 620 and electrodes 625 and 630. The memory stacks 635 can also include other layers and materials. The memory stacks 635 can be examples of the memory stacks 230 described with reference to Figure 2 the memory array 102 described with reference to Figure 6 the memory device 200 described with reference to

[0079] The memory device 600 can also include a plurality of conductive vias 640 that can be aligned with one another in the first direction z. The vias 640 can be examples of the conductive vias 415 and 520 as described with reference to Figure 4C and 5C Each via 640 can include a conductive material and extend through the insulator material 650 deposited in the gap, similar to those embodiments. Each via 640 can also extend through a liner material 655 that lines the gap discussed above, similar to the via 520. Each via 640 can be aligned with a group of memory stacks 635 in the second direction x. Each group of memory stacks can include memory stacks 635 positioned on each word line 610 (e.g., the group aligned with the via 640-a can include memory stacks 635-a and 635-b).

[0080] The memory device 600 can include a plurality of second access lines 615 (e.g., bit lines) that extend in the second direction x. The bit lines 615 can be examples of the bit lines 115 as described with reference to Figure 1 and 2 Each bit line 615 can extend over the vias 640 and the corresponding group of memory stacks 635 in the vias (e.g., the bit line 615-a can extend over the vias 640-a and the memory stacks 635-a and 635-b).

[0081] Each bit line 615, and the vias 640 and memory stacks 635 that extend thereover, can be formed in the same manner as the memory device 400-d shown in Figure 4D or the memory device 500-f shown in Figure 5F For example, the memory device 600 is depicted as incorporating the memory device 500-f shown in Figure 5F

[0082] ​As in memory device 500-f, in order from bottom to top, bit line 615-a can include first resistive material 642, first conductive material 644, second resistive material 646, and second conductive material 648. First resistive material 642 and first conductive material 644 can extend over all memory stacks 635 (e.g., memory stacks 635-a through 635-b) in a group. Second resistive material 646 and second conductive material 648 can also extend over memory stacks 635-a and 635-b, but can further extend over corresponding via 640-a. As a result, memory device 600 can be designed to provide an optimized or desired amount of second resistive material 646 for the conductive via, regardless of whether that amount can be different than the amount for memory stacks 635. Additionally, first resistive material 642 can directly contact memory stacks 635-a and 635-b, and second resistive material 646 can directly contact via 640-a. One end of first resistive material 642 and first conductive material 644 can end at liner material 655. Thus, liner material 655 can form a barrier between insulator material 650 and first resistive material 642 and between insulator material 650 and first conductive material 644.

[0083] In some embodiments, word lines 610 and bit lines 615 can be interchangeable. In those embodiments, each via 640 and corresponding group of memory stacks 635 can be associated with a word line instead of a bit line. For example, word lines 610 can instead be bit lines and bit lines 615 can instead be word lines.

[0084] With memory device 600, independent optimization of resistive material can be provided for memory cells and access lines. Separate amounts or types of resistive material can be deposited over memory cells and conductive vias using separate resistive layers in access lines. This can allow optimized or desired amounts of resistive material for memory cells and access lines, even when those amounts can be different for each memory cell and access line.

[0085] Figure 7 A flow diagram illustrating a method 700 of supporting memory with optimized resistive layers in accordance with aspects of the present disclosure is shown. The operations of method 700 can be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, one or more controllers can execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, one or more controllers can use special-purpose hardware to perform aspects of the described functions.

[0086] At 705, the method 700 can include depositing a first resistive material on a set of memory stacks. Each of the memory stacks can include a layered assembly of electrode material and memory material. The operations of 705 can be performed according to the methods described herein.

[0087] At 710, the method 700 can include depositing a first conductive material on the memory stacks over the first resistive material. The operations of 710 can be performed according to the methods described herein.

[0088] At 715, the method 700 can include removing a region of the set of memory stacks to form a gap in the first resistive material, the first conductive material, and one or more memory stacks of the set of memory stacks. In some cases, the gap can be formed by etching. The operations of 715 can be performed according to the methods described herein.

[0089] At 720, the method 700 can include depositing a conductive material to form a conductive via in the gap. In some cases, a dielectric material can be deposited in the gap, and the conductive via can extend through the dielectric material. In some cases, a liner material can be deposited over the first conductive material and the gap prior to formation of the conductive via. The liner material can form a barrier between the gap and the first resistive material and between the gap and the first conductive material. In some cases, a first portion of the liner material can be removed prior to depositing a second resistive material. The operations of 720 can be performed according to the methods described herein.

[0090] At 725, the method 700 can include depositing a second resistive material over the first conductive material and the conductive via. In some cases, a resistivity of the first resistive material is greater than a resistivity of the second resistive material. In some cases, the first resistive material and the second resistive material are composed of the same material. The operations of 725 can be performed according to the methods described herein.

[0091] At 730, the method 700 can include depositing a second conductive material on the set of memory stacks over the second resistive material and on the via over the second resistive material. The operations of 730 can be performed according to the methods described herein.

[0092] It should be noted that the methods described above describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more of the methods can be combined.

[0093] A memory device is described. The memory device can include a substrate and a plurality of memory stacks positioned on the substrate. Each memory stack can include a layered assembly of electrode materials and a memory material. The memory device can further include a first resistive material positioned on the plurality of memory stacks, a first conductive material positioned on the plurality of memory stacks above the first resistive material, and a via positioned on the substrate. The via can include a conductive material. The memory device can further include a second resistive material positioned on the first conductive material and the via, and a second conductive material positioned on the second resistive material.

[0094] In some examples, the first resistive material can cover the plurality of memory stacks and fail to cover the via. In some examples, a resistivity of the first resistive material can be greater than a resistivity of the second resistive material.

[0095] In some examples, the memory device can include a dielectric material positioned in a gap of the memory device, and the via can extend through the dielectric material. In some examples, the memory device can include a liner material positioned in the gap so as to form a barrier between the dielectric material and the first resistive material and between the dielectric material and the first conductive material.

[0096] In some examples, the second conductive material of the via can be in direct contact with the second resistive material. In some examples, the first resistive material and the second resistive material can be the same material. In some examples, the first resistive material can include WSiN or SiC.

[0097] Another memory device is described. The memory device can include a plurality of first access lines extending in a first direction. A respective plurality of memory stacks can be positioned on the plurality of first access lines. The memory device can further include a plurality of vias each including a conductive material and aligned with a group of memory stacks in a second direction. Each group of memory stacks can include a memory stack from each of the plurality of first access lines that is aligned with a via in the second direction. The memory device can further include a plurality of second access lines extending in the second direction. Each second access line can extend over a via of the plurality of vias and a group of memory stacks aligned with the via. Each second access line can include a first resistive material positioned on each memory stack of the respective plurality of memory stacks, a first conductive material positioned on the first resistive material, a second resistive material positioned on the via and the first conductive material, and a second conductive material positioned on the second resistive material.

[0098] In some examples, the first resistive material can not cover the plurality of vias. In some examples, a resistivity of the first resistive material can be greater than a resistivity of the second resistive material.

[0099] In some examples, each via can extend through the dielectric material and a liner material that forms a barrier between the dielectric material and the first resistive material and between the dielectric material and the first conductive material. In some examples, the second conductive material of each via can be in direct contact with the second resistive material.

[0100] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, it will be understood by those skilled in the art that the signals can represent a bus of signals, where buses can have a variety of bit widths.

[0101] The terms "in electronic communication," "in conductive contact," "connected," and "coupled" can refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with one another (or in conductive contact with one another, or connected to one another, or coupled to one another) if there exists any conductive path between the components that can support the flow of signals between the components at any time. The conductive path between components that are in electronic communication with one another (or in conductive contact with one another, or connected to one another, or coupled to one another) can be an open circuit or a closed circuit at any given time, based on the operation of the device that includes the connected components. The conductive path between connected components can be a direct conductive path between the components, or the conductive path between connected components can be an indirect conductive path that can include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between connected components can be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0102] The term "coupled" refers to the condition of components moving from an open circuit relationship between the components, in which signals cannot currently be conveyed between the components through a conductive path, to a closed circuit relationship between the components, in which signals can be conveyed between the components through a conductive path. When a component such as a controller couples other components together, the component initiates a change that allows signals to flow between the other components through a conductive path in which signals were not previously permitted to flow.

[0103] The term "isolated" refers to a relationship between components in which signals cannot currently flow between the components. Components are isolated from one another if there is an open circuit between the components. For example, components that are separated by a switch positioned between the two components are isolated from one another when the switch is open. When a controller isolates two components, the controller implements a change that prevents signals from flowing between the components using a conductive path in which signals were previously permitted to flow.

[0104] As used herein, the term "layer" or "level" refers to a layer or sheet of a geometry (e.g., relative to a substrate). Each layer or level can have three dimensions (e.g., height, width, and depth), and can cover at least a portion of a surface. For example, a layer or level can be a three-dimensional structure in which two dimensions are greater than a third dimension, such as a thin film. A layer or level can include different elements, components, and / or materials. In some examples, a layer or level can be composed of two or more sub-layers or sub-levels.

[0105] As used herein, the term "electrode" can refer to an electrical conductor, and in some examples, can serve as an electrical contact to a memory cell or other component of a memory array. An electrode can include a trace, wire, conductive line, conductive layer, etc. that provides an electrically conductive path between elements or components of a memory array.

[0106] Devices discussed herein that include a memory array can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as a silicon-on-glass (SOG) or a silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate, or sub-regions of the substrate, can be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0107] Switching components or transistors discussed herein can represent field effect transistors (FETs), and include a three-terminal device that includes a source, a drain, and a gate. The terminals can be connected to other electronic elements by conductive materials, such as metals. The source and drain can be electrically conductive, and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority of carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority of carriers are holes), the FET can be referred to as a p-type FET. The channel can be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, can cause the channel to become conductive. A transistor can be "on" or "activated" when a voltage greater than or equal to the threshold voltage of the transistor is applied to the gate of the transistor. A transistor can be "off' or "deactivated" when a voltage less than the threshold voltage of the transistor is applied to the gate of the transistor.

[0108] The description set forth herein describes example configurations and does not represent all configurations in which the excitation system can be practiced. The term "exemplary" is used herein to mean "serving as an example, instance, or illustration," and not "preferred over other examples." The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts described in the example.

[0109] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0110] The various illustrative blocks and modules described in connection with the present disclosure herein can be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0111] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations. Also, as used herein, including in the claims, "or" as used in a list of items (for example, a list of items prefaced by a phrase such as "at least one of" or "one or more of") indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as "based on condition A" can be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" shall be construed in the same manner as the phrase "based at least in part on."

[0112] The description in this document is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for manufacturing a memory device, the method comprising: A first resistive material is deposited on multiple memory stacks, each of the multiple memory stacks comprising a layered assembly of electrode material and memory material; A first conductive material is deposited on the plurality of memory stacks over the first resistive material; Remove regions of the plurality of memory stacks to form gaps in the first resistive material, the first conductive material, and one or more of the plurality of memory stacks; Deposit conductive material to form conductive vias in the gaps; A second resistive material is deposited over the first conductive material and the conductive via; as well as A second conductive material is deposited on the plurality of memory stacks above the second resistive material, wherein the second conductive material is in contact with a portion of the second resistive material, and the second resistive material is directly above the conductive via.

2. The method according to claim 1, wherein the resistivity of the first resistive material is greater than the resistivity of the second resistive material.

3. The method according to claim 1, further comprising: Dielectric material is deposited in the gap, wherein the conductive via extends through the dielectric material.

4. The method of claim 3, further comprising: A lining material is deposited over the first conductive material and the gap before the conductive via is formed, wherein the lining material forms a barrier between the gap and the first resistive material and between the gap and the first conductive material.

5. The method of claim 4, further comprising: The first portion of the lining material is removed before the second resistive material is deposited.

6. The method according to claim 1, wherein the first resistive material and the second resistive material are made of the same material.

7. The method of claim 1, wherein the regions of the plurality of memory stacks are removed by etching.

8. A memory device comprising: Substrate: Multiple memory stacks are positioned on the substrate, each memory stack comprising a layered assembly of electrode material and memory material; A first resistive material is positioned on the plurality of memory stacks; A first conductive material is positioned on the plurality of memory stacks above the first resistive material; A via is positioned on the substrate, the via comprising a conductive material; A second resistive material is positioned on the first conductive material and the through hole; as well as A second conductive material is positioned on the second resistive material, wherein the second conductive material is in contact with a portion of the second resistive material, and the second resistive material is directly above the through-hole.

9. The memory device of claim 8, wherein the first resistive material covers the plurality of memory stacks but fails to cover the via.

10. The memory device of claim 8, wherein the resistivity of the first resistive material is greater than the resistivity of the second resistive material.

11. The memory device of claim 8, further comprising a dielectric material positioned in a gap of the memory device, the via extending through the dielectric material.

12. The memory device of claim 11, further comprising a lining material positioned in the gap to form a barrier between the dielectric material and the first resistive material and between the dielectric material and the first conductive material.

13. The memory device of claim 8, wherein the first resistive material and the second resistive material are the same material.

14. The memory device of claim 8, wherein the first resistive material comprises WSiN or SiC.

15. A memory device comprising: Multiple first access lines extend in a first direction; The corresponding multiple memory stacks on the multiple first access lines; Multiple vias, each aligned in a second direction with a group of memory stacks, each group of memory stacks comprising memory stacks from each of the multiple first access lines aligned in the second direction with the multiple vias, each via comprising a conductive material; as well as A plurality of second access lines extending in the second direction, each second access line extending over the vias in the plurality of vias and the group of memory stacks aligned with the vias. Each of the second access lines includes: A first resistive material is positioned on each of the respective plurality of memory stacks; A first conductive material is positioned on the first resistive material; A second resistive material is positioned on the through-hole and the first conductive material; and A second conductive material is positioned on the second resistive material, wherein the second conductive material is in contact with a portion of the second resistive material, and the second resistive material is directly above the through-hole.

16. The memory device of claim 15, wherein the first resistive material does not cover the plurality of vias.

17. The memory device of claim 15, wherein the resistivity of the first resistive material is greater than the resistivity of the second resistive material.

18. The memory device of claim 15, wherein each via extends through a dielectric material and a liner material, the liner material forming a barrier between the dielectric material and the first resistive material and between the dielectric material and the first conductive material.

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