Reverse current detection circuit and dc-dc converter

Abstract

A reverse current detection circuit and a DC-DC converter. The reverse current detection circuit is coupled to a synchronous rectification transistor and detects a reverse current based on a voltage across the coupled synchronous rectification transistor, wherein the reverse current detection circuit includes a first stage differential input circuit having a first transistor, a first resistor, a second transistor, and a second resistor, and a second stage differential input circuit having a third transistor and a fourth transistor, the first stage differential input circuit further having a fifth transistor including a drain connected to an opposite end of the first resistor relative to an end connected to the first transistor and being of a same conductivity type as the synchronous rectification transistor.

Description

Technical Field

[0001] This invention relates to a reverse current detection circuit and a DC-DC converter. Background Technology

[0002] A DC-DC converter is a device that converts a DC input voltage into different DC output voltages. For example, in a synchronous rectification type DC-DC converter, the efficiency of power conversion can be improved by disconnecting the synchronous rectification transistor, which acts as a synchronous rectifier, during light load conditions such as standby (see Japanese Patent Application Publication No. 2019-103199).

[0003] Regarding the timing of turning off the synchronous rectifier transistor, the closer the coil current is to 0 (zero) amperes, the more advantageous it is from the viewpoint of obtaining high efficiency. Therefore, in a synchronous rectifier converter, a reverse current detection circuit detects the voltage across the synchronous rectifier transistor and turns it off when the coil current reaches 0 amperes.

[0004] [Existing Technical Documents]

[0005] [Patent Literature]

[0006] Patent Document 1: Japanese Patent Application Publication No. 2019-103199 Summary of the Invention

[0007] [The problem the invention aims to solve]

[0008] However, the on-resistance of a synchronous rectifier transistor can vary due to the so-called process-voltage-temperature (PVT) deviation. This variation in the on-resistance causes a change in the detected coil current. For example, if the on-resistance of the synchronous rectifier transistor varies significantly from its design value, the timing of its disconnection will be delayed. This delay in disconnection leads to discharge of the output capacitor, resulting in a decrease in power conversion efficiency.

[0009] In view of the aforementioned situation, the present invention aims to provide a reverse current detection circuit and a DC-DC converter that can suppress the decrease in power conversion efficiency even when the resistance value of the on-resistance of the synchronous rectifier transistor changes.

[0010] [Technical means to solve the problem]

[0011] The reverse current detection circuit of this invention is coupled to a synchronous rectifier transistor and detects reverse current based on the voltage across the coupled synchronous rectifier transistor. The reverse current detection circuit includes: a first-stage differential input circuit having a first transistor having a gate connected to a first input terminal, a first resistor connected in series with the first transistor, a second transistor having a gate connected to a second input terminal, and a second resistor connected in series with the second transistor; and a second-stage differential input circuit having a third transistor having a gate connected to a node of the first transistor and the first resistor, and a fourth transistor having a gate connected to a node of the second transistor and the second resistor. The first-stage differential input circuit also includes a fifth transistor having a drain connected to the other end of the first resistor opposite to the end connected to the first transistor, and having the same conductivity type as the synchronous rectifier transistor.

[0012] According to another embodiment of the present invention, the reverse current detection circuit includes a fifth transistor comprising a gate connected to a bias circuit that supplies a predetermined bias voltage.

[0013] According to another embodiment of the present invention, the reverse current detection circuit includes a fifth transistor comprising a gate connected to a power supply terminal supplying a power supply voltage.

[0014] According to another embodiment of the reverse current detection circuit of the present invention, the fifth transistor is an N-channel metal-oxide-semiconductor transistor including a gate connected to a power supply terminal, wherein the power supply terminal supplies a voltage higher than the ground voltage as the power supply voltage.

[0015] According to another embodiment of the reverse current detection circuit of the present invention, the fifth transistor is a P-channel metal-oxide-semiconductor transistor including a gate connected to a ground terminal, the ground terminal supplying a ground voltage as the power supply voltage.

[0016] The DC-DC converter of the present invention includes a synchronous rectifier transistor, and the reverse current detection circuit detects the reverse current based on the voltage across the synchronous rectifier transistor.

[0017] [The effects of the invention]

[0018] According to the present invention, even when the resistance value of the on-resistance of the synchronous rectifier transistor changes, the decrease in power conversion efficiency can be suppressed. Attached Figure Description

[0019] Figure 1 This is a circuit diagram of a DC-DC converter according to the first embodiment of the present invention.

[0020] Figure 2This is a circuit diagram showing a structural example (first structural example) of the reverse current detection circuit in the DC-DC converter of the first embodiment.

[0021] Figure 3 This is an explanatory diagram that schematically shows the operating waveform of the DC-DC converter according to the first embodiment.

[0022] Figure 4 This is an explanatory diagram illustrating the offset voltage generated within the reverse current detection circuit.

[0023] Figure 5 This is an explanatory diagram illustrating the relationship between the detection voltage, offset voltage, voltage at the non-inverting input terminal, voltage at the first and second input terminals of the second-stage differential input circuit within the reverse current detection circuit, and the voltage at the output terminal relative to time.

[0024] Figure 6 (a) is a graph showing the relationship between the on-resistance of the synchronous rectifier transistor and the offset voltage in the reverse current detection circuit of the first structural example and temperature. Figure 6 (b) is a graph showing the relationship between the on-resistance of the synchronous rectifier transistor and the offset voltage relative to the input voltage in the reverse current detection circuit of the first structural example.

[0025] Figure 7 This is a circuit diagram illustrating a structural example (second structural example) of the reverse current detection circuit in the DC-DC converter of the second embodiment.

[0026] Figure 8 (a) is a graph showing the relationship between the on-resistance of the synchronous rectifier transistor and the offset voltage in the reverse current detection circuit of the second structural example and temperature. Figure 8 (b) is a graph showing the relationship between the on-resistance of the synchronous rectifier transistor and the offset voltage relative to the input voltage in the reverse current detection circuit of the second structural example.

[0027] Figure 9 This is a circuit diagram of a DC-DC converter according to the third embodiment of the present invention.

[0028] Figure 10 This is a circuit diagram showing a structural example (third structural example) of the reverse current detection circuit in the DC-DC converter of the third embodiment.

[0029] Figure 11 This is a circuit diagram showing a structural example (fourth structural example) of the reverse current detection circuit in the DC-DC converter of the fourth embodiment.

[0030] [Explanation of Symbols]

[0031] 1A~1D: DC-DC converter

[0032] 3: Power supply terminals (power supply terminals)

[0033] 4: Grounding terminal (power supply terminal)

[0034] 12: NMOS transistor (Synchronous Rectifier Transistor)

[0035] 30A~30D: Reverse current detection circuit

[0036] 310A, 310B, 410C, 410D: 1-segment differential input circuit

[0037] 311: PMOS transistor (first transistor)

[0038] 312: PMOS transistor (second transistor)

[0039] 313, 314: NMOS transistors (fifth transistors)

[0040] 411: NMOS transistor (first transistor)

[0041] 412: NMOS transistor (second transistor)

[0042] 413, 414: PMOS transistors (fifth transistors)

[0043] 320, 420: Second-stage differential input circuit

[0044] 321: PMOS transistor (third transistor)

[0045] 322: PMOS transistor (fourth transistor)

[0046] 421: NMOS transistor (third transistor)

[0047] 422: NMOS transistor (fourth transistor)

[0048] 340, 440: Bias circuit

[0049] 62: PMOS transistor (synchronous rectifier transistor)

[0050] VDD: Voltage (Power Supply Voltage)

[0051] GND: Ground voltage (power supply voltage)

[0052] V BIAS Bias voltage

[0053] N1, N11: Nodes (first input terminals)

[0054] N3, N13: Nodes (Second Input Terminal)

[0055] N4, N5, N14, N15: Nodes Detailed Implementation

[0056] Hereinafter, the reverse current detection circuit and DC-DC converter according to embodiments of the present invention will be described with reference to the accompanying drawings.

[0057] [First Implementation Method]

[0058] Figure 1 This is a circuit diagram of DC-DC converter 1A, which is an example of a DC-DC converter according to the first embodiment.

[0059] DC-DC converter 1A is a so-called synchronous rectification type buck DC-DC converter. DC-DC converter 1A includes: a P-channel metal-oxide-semiconductor (PMOS) transistor 11, an NMOS transistor 12, an inductor 21, an output capacitor 22, a reverse current detection circuit 30A, and an inverter 41 and a not-and-not-interchange (NAND) circuit 42 constituting the control circuit. The reverse current detection circuit 30A includes a comparator 31 with an offset voltage.

[0060] PMOS transistor 11 includes: a gate connected to control terminal Tc; a source connected to input terminal Ti; and a drain connected to the drain of NMOS transistor 12 and node N1 at the first end of inductor 21.

[0061] The NMOS transistor 12, which is a synchronous rectifier transistor, includes: a gate connected to the output of the NAND circuit 42; a drain connected to node N1; and a source connected to ground terminal 4.

[0062] Inductor 21 includes: a first terminal connected to the drain of NMOS transistor 12; and a second terminal connected to output terminal To. Output capacitor 22 is connected between the second terminal of inductor 21 and node N2 of output terminal To and ground terminal 4. Output voltage Vout is output from output terminal To to an external circuit (not shown) connected to output terminal To.

[0063] The reverse current detection circuit 30A equivalently includes a comparator 31 and an offset voltage source 32 that generates an offset voltage value Vos. The comparator 31 includes a non-inverting input (+) connected to node N1; and an inverting input (-) connected via the offset voltage source 32 to the source of the NMOS transistor 12 and node N3 of the ground terminal 4. The offset voltage source 32 includes a positive terminal connected to node N3 and a negative terminal connected to the inverting input (-).

[0064] The positive power supply terminal of comparator 31 is connected to power supply terminal 3, and the negative power supply terminal is connected to ground terminal 4. Power supply terminal 3, which serves as the power supply terminal, supplies the power supply voltage VDD. Ground terminal 4, which also serves as the power supply terminal, supplies the ground voltage GND, which serves as the power supply voltage. Voltage VDD is a voltage higher than the ground voltage GND.

[0065] Figure 2 This is a circuit diagram showing a first structural example of a reverse current detection circuit 30A in a DC-DC converter as a first embodiment.

[0066] The reverse current detection circuit 30A includes, for example, a first-stage differential input circuit 310A and a second-stage differential input circuit 320 constituting a two-stage or multi-stage differential input circuit, an NMOS transistor 331, an inverter 332, and a constant current source 339 that supplies constant current to the NMOS transistor 331.

[0067] The first-stage differential input circuit 310A includes a PMOS transistor 311 as a first transistor, a PMOS transistor 312 as a second transistor, a resistor 315 as a first resistor, and a resistor 316 as a second resistor. A constant current source 319, which supplies constant current to each PMOS transistor 311 and PMOS transistor 312, is connected between the source of each PMOS transistor 311 and PMOS transistor 312 and the power supply terminal 3. Furthermore, the first-stage differential input circuit 310A also includes an n-type NMOS transistor 313, which is the fifth transistor and has the same conductivity type as NMOS transistor 12.

[0068] PMOS transistor 311 includes a gate connected to node N3, which serves as a first input terminal. PMOS transistor 312 includes a gate connected to node N1, which serves as a second input terminal.

[0069] Resistors 315 and 316 are the load resistors in the first-stage differential input circuit 310A. Resistors 315 and 316 are each connected in series with PMOS transistors 311 and 312, respectively. Here, the connection point between resistor 315 and the drain of PMOS transistor 311 is called node N4, and the connection point between resistor 316 and the drain of PMOS transistor 312 is called node N5.

[0070] Resistor 315 includes: a first terminal connected to the drain of PMOS transistor 311; and a second terminal, the opposite terminal to the first terminal, connected to the drain of NMOS transistor 313. Resistor 316 includes a first terminal connected to the drain of PMOS transistor 312 and a second terminal connected to ground terminal 4. The resistance values ​​of resistors 315 and 316 can be the same or different.

[0071] The NMOS transistor 313 includes: a gate, and a supply bias voltage V. BIAS The bias circuit 340 is connected; the drain is connected to the second end of the resistor 315; and the source is connected to the ground terminal 4.

[0072] The second-stage differential input circuit 320 includes a PMOS transistor 321 as a third transistor and a PMOS transistor 322 as a fourth transistor. The drain of an NMOS transistor 323 is connected to the drain of the PMOS transistor 321. The drain of an NMOS transistor 324 is connected to the drain of the PMOS transistor 322. A constant current source 329, supplying constant current to each PMOS transistor 321 and PMOS transistor 322, is connected between the source of each PMOS transistor 321 and PMOS transistor 322 and the power supply terminal 3.

[0073] PMOS transistor 321 includes a gate connected to node N4. PMOS transistor 322 includes a gate connected to node N5.

[0074] NMOS transistor 323 includes: a drain connected to the drain of PMOS transistor 321, a gate connected to its own drain (short-circuited), and a source connected to ground terminal 4. NMOS transistor 324 includes: a gate connected to the gate and drain of NMOS transistor 323, a drain connected to the drain of PMOS transistor 322, and a source connected to ground terminal 4. NMOS transistors 323 and 324 constitute a current mirror circuit 325.

[0075] The NMOS transistor 331, serving as the output transistor, includes: a gate connected to the node of the PMOS transistor 322 and the NMOS transistor 324; a drain connected to the power supply terminal 3 via a constant current source 339; and a source connected to the ground terminal 4. The inverter 332 includes: an input terminal connected to the node of the constant current source 339 and the NMOS transistor 331; and an output terminal connected to the output terminal 31o.

[0076] Next, the function of DC-DC converter 1A will be explained.

[0077] Figure 3 This is the operating waveform of DC-DC converter 1A, and roughly represents the voltage Vc at control terminal Tc and the voltage V at output terminal 31o. CMP The voltage Vsw at node N1 and the coil current I flowing through inductor 21 L The explanatory diagram. Additionally... Figure 3In this simplified diagram, the dead time period during which PMOS transistor 11 and NMOS transistor 12 are simultaneously off is omitted. Furthermore, Figure 3 The underlined PWM shown indicates that the voltage Vc turns on PMOS transistor 11 at a low (L) level.

[0078] Voltage Vc, Voltage V CMP Voltage Vsw and coil current I L All change periodically with a period T. The voltage Vc remains at level L from time 0 until time t1, transitions to a high (H) level at time t1, remains at level H from time t1 until time t3, and transitions back to level L at time t3. Therefore, PMOS transistor 11 is in the on state from time 0 until time t1, is off at time t1, remains off from time t1 until time t3, and is on at time t3.

[0079] Voltage V CMP The NMOS transistor 12 is in the off state from time 0 until time t1, turns on at time t1, remains at the L level from time t1 to time t2, turns on at time t2, and remains at the H level from time t2 to time t3. Therefore, the NMOS transistor 12 is in the off state from time 0 until time t1, turns on at time t1, remains on, and then turns off at time t3.

[0080] Coil current I L The current increases at a fixed rate after time 0 until time t1. When time t1 is reached, with the PMOS transistor 11 turning off and the NMOS transistor 12 turning on, the coil current I... L It decreases by a fixed percentage. When time t2 is reached, the coil current I... L It becomes 0 amperes and remains at 0 amperes until time t3 (I L =0).

[0081] The voltage Vsw decreases at a fixed rate from the input voltage Vin after time 0 and before time t1. At time t1, with the PMOS transistor 11 turning off and the NMOS transistor 12 turning on, it drops to a negative voltage, and then increases at a fixed rate toward 0 volts. At time t2, the coil current I... L When the current reaches 0 amperes, the coil current I LThe change ceases. Therefore, the voltage difference between the two ends of inductor 21 becomes 0 volts, the voltages at nodes N1 and N2 are balanced, and the voltage rises to a predetermined positive voltage lower than the input voltage Vin. This positive voltage is maintained after time t2 and before time t3. At time t3, with the turn-on of PMOS transistor 11 and the turn-off of NMOS transistor 12, the voltage Vsw rises to a voltage equal to the input voltage Vin.

[0082] Figure 4 This is an explanatory diagram illustrating the offset voltage generated within the 30A reverse current detection circuit. The solid line L1 represents the characteristics of the voltage Vsw generated at node N1, and the dashed line L2 represents the characteristics of the voltage Vsw after the on-resistance value Ron12 of the NMOS transistor 12 increases due to some reason.

[0083] The reverse current detection circuit 30A imparts an offset voltage to the detection voltage Vd. That is, for the reverse current detection circuit 30A, an offset voltage value Vos is set that takes into account the delay time td1 of the comparator 31's response. The offset voltage value Vos can be expressed as a function of the on-resistance value Ron12 and the coil current I of the inductor 21. L It is expressed as the product of Ron12 and I. That is, the offset voltage value Vos(=Ron12·I L The voltage value is equal to the detection voltage Vd. The offset voltage value Vos is set such that the detection voltage Vd is negative (Vd < 0) (point P1).

[0084] The voltage Vsw generated at node N1 is represented by the solid line L1. Solid line L1 is a straight line passing through points P1 and P0, and is derived from the on-resistance value Ron12 and the coil current I of inductor 21. L The product is used to calculate the voltage. Therefore, the voltage value of voltage Vsw is equal to the offset voltage value Vos and the detection voltage value Vd. The timing for the reverse current detection circuit 30A to detect the voltage is at the intersection of the solid line L1 and the detection voltage Vd, i.e., point P1. When the reverse current detection circuit 30A detects the voltage, at the point P0, which is the intersection with 0 volts, after the delay time td1 of the comparator 31's response, the voltage V... CMP Reversing the current causes NMOS transistor 12 to turn off, thus preventing coil current I. L The countercurrent.

[0085] Next, the case where the on-resistance value Ron12 increases for some reason (dashed line L2) will be explained. Here, it is assumed that the offset voltage value Vos and the delay time td2 do not change with the change in the on-resistance value Ron12. That is, regarding the delay time of the comparator 31's response, it is assumed that the delay time td2 is equal to the delay time td1.

[0086] The voltage Vsw when the on-resistance Ron12 increases is represented by the dashed line L2. The dashed line L2 is a straight line passing through points P3 and P0. Although the coil current I... L The same, but due to the on-resistance of NMOS transistor 12 and the coil current I... L The absolute value of the generated voltage Vsw, |Vsw|, increases. Therefore, if the offset voltage value Vos is the same, the detected coil current I... L The current value decreases. The coil current I L The slope of the decrease in current value is expressed as the product of the output voltage Vout and the reciprocal of the inductance L of inductor 21, i.e., Vout / L. Even when the on-resistance Ron12F changes, the coil current I... L The slope of Vout / L remains roughly unchanged, but the absolute value of the voltage Vsw, |Vsw|, increases.

[0087] Here, even if the detected voltage Vd remains the same when the offset voltage Vos does not change, the voltage Vsw changes sharply. Therefore, at point P4, after a delay time td2 from the detected voltage point P3, the voltage Vsw changes by ΔI. L Generate coil current I L The reverse current, that is, the current flowing from node N2 towards node N1, is the reverse current. ΔI L This is due to the discharge action of the output capacitor 22, thus reducing the efficiency of the power conversion. Conversely, when the on-resistance value Ron12 decreases, the voltage Vsw will decrease before reaching 0 volts. CMP The reversed direction makes it easy to deviate from the ideal operation, and the efficiency of power conversion is likely to decrease.

[0088] Therefore, in the reverse current detection circuit 30A, the NMOS transistor 12 (which is used as a synchronous rectifier transistor) is utilized. Figure 1 (Refer to) The on-resistance of NMOS transistor 313 of the same conductivity type is used to generate comparator 31 (refer to) Figure 1 The offset voltage.

[0089] Since NMOS transistor 12 and NMOS transistor 313 have the same conductivity type, even if the on-resistance value Ron12 changes due to temperature, input voltage, or manufacturing deviations (Pilot-run Verification Test, PVT) deviations, the on-resistance value Ron313 of NMOS transistor 313 will change in the same way. This means that if using Figure 4The example shown illustrates this conceptually: when the on-resistance value Ron12 changes, the offset voltage value Vos automatically shifts from point P1 to point P2. Therefore, the offset voltage value Vos automatically changes in the direction that minimizes the decrease in power conversion efficiency, corresponding to the change in the on-resistance value Ron12, thus ensuring that the power conversion efficiency does not decrease.

[0090] Figure 5 This describes the detection voltage Vd, the offset voltage Vos, the voltage Vsw at the non-inverting input terminal (+), the first input voltage and the second input voltage of the second-stage differential input circuit 320, i.e., voltage V. N4 and voltage V N5 The voltage V at the output terminal 31o CMP A diagram illustrating the relationship with time.

[0091] The voltage Vsw is the sum of the on-resistance value Ron12 and the coil current I of inductor 21. L The product of the detected voltage Vd, offset voltage Vos, point P0, point P1, and delay time. Figure 3 The same applies. As the voltage Vsw approaches point P0 from point P1, that is, from a negative voltage (Vsw < 0) to 0 volts, the first input voltage of the second-stage differential input circuit 320, i.e., voltage V... N4 The voltage gradually increases, and the second input voltage of the second-stage differential input circuit 320, i.e., voltage V, is... N5 Gradually decreasing.

[0092] In the reverse current detection circuit 30A, the on-resistance value Ron313 of the NMOS transistor 313 is added to the resistor 315, therefore the voltage V N4 The increase generates an offset voltage value Vos. The generated offset voltage value Vos is determined not only by the on-resistance value Ron313, but also by the gate-source voltages of PMOS transistors 311 and 312, as well as the threshold voltages and the resistance values ​​of resistors 315 and 316. The voltage V at the output terminal 31o... CMP The voltage V before it reaches 0 volts from voltage Vsw N4 =Voltage V N5 The timing is such that after a delay of td1, the level reverses from L to H.

[0093] Figure 6 (a) represents NMOS transistor 12 (refer to) Figure 1 The graph shows the relationship between the on-resistance of the comparator 31 and the offset voltage in the reverse current detection circuit 30A, and temperature. Here, the solid line L3 represents the on-resistance value Ron12. The dashed line L4 represents the comparator 31 (see reference). Figure 1 The offset voltage value Vos.

[0094] Both solid line L3 and dashed line L4 are straight lines sloping upwards to the right with the same slope. This indicates that both the on-resistance value Ron12 and the offset voltage value Vos are proportional to temperature. Specifically, if the temperature rises, the offset voltage value Vos rises along with the on-resistance value Ron12. That is, the offset voltage value Vos automatically adjusts in a direction that minimizes efficiency loss relative to the temperature change of the on-resistance value Ron12. After a delay time td1, the coil current I can be detected. L =Near 0 amperes.

[0095] Figure 6 (b) represents NMOS transistor 12 (refer to) Figure 1 The graph shows the relationship between the on-resistance of the comparator 31 and the offset voltage in the reverse current detection circuit 30A relative to the input voltage Vin. Here, the solid line L5 represents the on-resistance value Ron12. The dashed line L6 represents the comparator 31 (see reference). Figure 1 The offset voltage value Vos.

[0096] Both solid line L5 and dashed line L6 are straight lines that are fixed (with zero slope) relative to the input voltage Vin. This means that the on-resistance value Ron12 and the offset voltage value Vos do not change relative to the input voltage Vin; that is, they remain fixed values. This is because the voltage applied to the gate of the NMOS transistor 313 is fixed as the bias voltage V. BIAS .

[0097] According to the DC-DC converter 1A configured in this way, the offset voltage value Vos is automatically adjusted in a direction that minimizes efficiency degradation in response to environmental changes such as temperature or power supply voltage. Furthermore, the offset voltage value Vos is also automatically adjusted in a direction that minimizes efficiency degradation in response to manufacturing process deviations. Therefore, in the DC-DC converter 1A, the timing for turning off the NMOS transistor 12 is precisely controlled, for example, by adjusting the coil current I... L Set at a coil current I that yields high efficiency L When the current is near 0 Amperes, the efficiency decrease of DC-DC converter 1A caused by the change in the on-resistance value Ron12 can be suppressed.

[0098] Furthermore, according to the DC-DC converter 1A, the current consumption will not increase, so the power consumption will not increase, and the efficiency of power conversion can be stabilized relative to the change of the on-resistance value Ron12.

[0099] Furthermore, according to the DC-DC converter 1A, the voltage applied to the gate of the NMOS transistor 313 that generates the offset voltage is fixed as the bias voltage V. BIAS Therefore, it does not depend on the input voltage Vin.

[0100] [Second Implementation]

[0101] Figure 7 This is a circuit diagram of a reverse current detection circuit 30B in DC-DC converter 1B, which is an example of a DC-DC converter according to a second embodiment (second structural example).

[0102] The difference between DC-DC converter 1B and DC-DC converter 1A is that DC-DC converter 1B includes a reverse current detection circuit 30B instead of a reverse current detection circuit 30A; otherwise, they are substantially the same. Therefore, in this embodiment, the description will focus on the reverse current detection circuit 30B, and descriptions that are repeated in the first embodiment will be omitted.

[0103] The difference between the reverse current detection circuit 30B and the reverse current detection circuit 30A is that the first-stage differential input circuit 310B includes an NMOS transistor 314 instead of an NMOS transistor 313 in the first-stage differential input circuit 310A. Otherwise, they are essentially the same.

[0104] The NMOS transistor 314, as the fifth transistor, differs from the NMOS transistor 313 in that its gate has a different connection target, but otherwise they are substantially the same. The NMOS transistor 314 includes a gate connected to a power supply terminal 3, which serves as a power supply terminal and supplies a voltage VDD.

[0105] Figure 8 (a) represents NMOS transistor 12 (refer to) Figure 1 The graph shows the relationship between the on-resistance of the comparator 31 and the offset voltage in the reverse current detection circuit 30B relative to temperature. Here, the solid line L7 represents the on-resistance value Ron12. The dashed line L8 represents the comparator 31 (see reference). Figure 1 The offset voltage value Vos.

[0106] Both solid line L7 and dashed line L8 are straight lines sloping upwards to the right with the same gradient. This indicates that both the on-resistance value Ron12 and the offset voltage value Vos are proportional to temperature. Specifically, if the temperature rises, the offset voltage value Vos rises along with the on-resistance value Ron12. That is, the offset voltage value Vos automatically adjusts in a direction that minimizes efficiency loss relative to the temperature change of the on-resistance value Ron12, and the coil current I can be detected after a delay time td1. L =Near 0 amperes.

[0107] Figure 8 (b) represents NMOS transistor 12 (refer to) Figure 1The graph shows the relationship between the on-resistance value Ron12 of the comparator 31 and the offset voltage in the reverse current detection circuit 30B relative to the input voltage Vin. Here, the solid line C1 represents the on-resistance value Ron12. The dashed line C2 represents the comparator 31 (see reference). Figure 1 The offset voltage value Vos.

[0108] The solid line C1 and the dashed line C2 are inversely proportional curves. The voltage applied to the gate of the NMOS transistor 314 is voltage VDD. The offset voltage value Vos is inversely proportional to voltage VDD. When the input voltage Vin is VDD, the change in offset voltage Vos relative to the input voltage Vin changes synchronously with the change in on-resistance Ron12. That is, the offset voltage value Vos automatically adjusts synchronously with the change in on-resistance Ron12 relative to the change in input voltage Vin.

[0109] The DC-DC converter 1B configured in this way can achieve the same function and effect as the DC-DC converter 1A. That is, with the DC-DC converter 1B, the offset voltage value Vos is automatically adjusted in a direction that minimizes efficiency degradation in response to environmental changes such as temperature or power supply voltage. Moreover, the offset voltage value Vos is also automatically adjusted in a direction that minimizes efficiency degradation in response to deviations in the manufacturing process.

[0110] Therefore, in the DC-DC converter 1B, the timing for turning off the NMOS transistor 12 is, for example, whenever the coil current I... L Set at a coil current I that yields high efficiency L When the current is near 0 Amperes, the decrease in power conversion efficiency caused by changes in the on-resistance Ron12 can be suppressed.

[0111] Furthermore, according to the DC-DC converter 1B, the current consumption does not increase, thus preventing an increase in power consumption, and the efficiency of power conversion can be stabilized relative to the change in the on-resistance value Ron12.

[0112] Furthermore, according to DC-DC converter 1B, the voltage applied to the gate of NMOS transistor 314, which generates the offset voltage value Vos, is voltage VDD. Therefore, the offset voltage value Vos changes synchronously with the on-resistance value Ron12 relative to the input voltage Vin. Consequently, DC-DC converter 1B has the advantage that it is less affected by changes in the input voltage Vin than DC-DC converter 1A.

[0113] [Third Implementation Method]

[0114] Figure 9 This is a circuit diagram of DC-DC converter 1C, which is an example of a DC-DC converter according to a third embodiment.

[0115] The DC-DC converter 1C differs from the DC-DC converter 1A in that it replaces the PMOS transistor 11, NMOS transistor 12, reverse current detection circuit 30A, inverter 41, and NAND circuit 42 with an NMOS transistor 61, a PMOS transistor 62, a reverse current detection circuit 30C, an OR circuit 81, and an inductor 21. Otherwise, they are substantially the same. Therefore, in this embodiment, descriptions that are repeated in the first and second embodiments are omitted.

[0116] DC-DC converter 1C is a so-called synchronous rectification type boost DC-DC converter. DC-DC converter 1C includes an NMOS transistor 61, a PMOS transistor 62, an inductor 21, an output capacitor 22, a reverse current detection circuit 30C, and an OR circuit 81 constituting the control circuit. The reverse current detection circuit 30C includes a comparator 31 with an offset voltage.

[0117] In the DC-DC converter 1C, the inductor 21 includes a first terminal connected to the input terminal Ti, an NMOS transistor 61, a PMOS transistor 62, and a second terminal connected to node N11 of the reverse current detection circuit 30C.

[0118] The NMOS transistor 61 includes a gate connected to the control terminal Tc, a drain connected to node N11, and a source connected to the ground terminal 4.

[0119] The PMOS transistor 62, which is a synchronous rectifier transistor, includes: a gate connected to the output terminal of the OR circuit 81, a drain connected to node N11, and a source connected to the output terminal To.

[0120] OR circuit 81 is connected to: a first input terminal connected to control terminal Tc and the gate of NMOS transistor 61, a second input terminal connected to output terminal 31o, and the gate of PMOS transistor 62.

[0121] The reverse current detection circuit 30C equivalently includes: a comparator 31 and an offset voltage source 32 that generates an offset voltage value Vos. The comparator 31 includes: an inverting input terminal (-) connected to node N11, and a non-inverting input terminal (+) connected to node N13 via the offset voltage source 32. The offset voltage source 32 includes: a positive terminal connected to the non-inverting input terminal (+), and a negative terminal connected to node N13.

[0122] The positive power supply terminal of comparator 31 is connected to power supply terminal 3, and the negative power supply terminal is connected to ground terminal 4. Power supply terminal 3, which serves as the power supply terminal, supplies the power supply voltage VDD. Ground terminal 4, which also serves as the power supply terminal, supplies the ground voltage GND, which serves as the power supply voltage. Voltage VDD is a voltage higher than the ground voltage GND.

[0123] Figure 10 This is a circuit diagram showing a third structural example of a reverse current detection circuit 30C in a DC-DC converter as a third embodiment.

[0124] The reverse current detection circuit 30C includes, for example, a first-stage differential input circuit 410C and a second-stage differential input circuit 420 constituting a two-stage or multi-stage differential input circuit, a PMOS transistor 431, an inverter 432, and a constant current source 439 that sinks a constant current from the PMOS transistor 431 to the ground terminal 4.

[0125] The first-stage differential input circuit 410C includes: an NMOS transistor 411 as a first transistor, an NMOS transistor 412 as a second transistor, a resistor 415 as a first resistor, and a resistor 416 as a second resistor. A constant current source 419, which sinks a constant current to the ground terminal 4, is connected between the source of each of the NMOS transistors 411 and 412 and the ground terminal 4. Furthermore, the first-stage differential input circuit 410C also includes a p-type PMOS transistor 413 as a fifth transistor, having the same conductivity type as the PMOS transistor 62.

[0126] NMOS transistor 411 includes a gate connected to node N11, which serves as a first input terminal. NMOS transistor 412 includes a gate connected to node N13, which serves as a second input terminal.

[0127] Resistors 415 and 416 are the load resistors in the first-stage differential input circuit 410C. Resistors 415 and 416 are each connected in series with NMOS transistors 411 and 412, respectively. Here, the connection point between resistor 415 and the drain of NMOS transistor 411 is called node N14, and the connection point between resistor 416 and the drain of NMOS transistor 412 is called node N15.

[0128] Resistor 415 includes a first terminal connected to the drain of NMOS transistor 411 and a second terminal connected to power supply terminal 3. Resistor 416 includes a first terminal connected to the drain of NMOS transistor 412 and a second terminal connected to the drain of PMOS transistor 413. Furthermore, the resistance values ​​of resistors 415 and 416 can be the same or different.

[0129] PMOS transistor 413 includes: a supply bias voltage V BIAS The bias circuit 440 is connected to the gate, the drain connected to the second end of the resistor 416, and the source connected to the power supply terminal 3.

[0130] The second-stage differential input circuit 420 includes an NMOS transistor 421 as a third transistor and an NMOS transistor 422 as a fourth transistor. A constant current source 429 is connected between the source of each of the NMOS transistors 421 and 422 and the ground terminal 4 to sink a constant current to the ground terminal 4.

[0131] The drain of PMOS transistor 423 is connected to the drain of NMOS transistor 421. The drain of PMOS transistor 424 is connected to the drain of NMOS transistor 422. A constant current source 429 is connected between the source of NMOS transistor 421 and NMOS transistor 422 and the ground terminal 4 to inject constant current into the ground terminal 4.

[0132] NMOS transistor 421 includes a gate connected to node N14. NMOS transistor 422 includes a gate connected to node N15.

[0133] PMOS transistor 423 includes: a drain connected to the drain of NMOS transistor 421, a gate connected to its own drain (short-circuited), and a source connected to power supply terminal 3. PMOS transistor 424 includes: a gate connected to the gate and drain of PMOS transistor 423, a drain connected to the drain of NMOS transistor 422, and a source connected to power supply terminal 3. PMOS transistors 423 and 424 constitute a current mirror circuit 425.

[0134] The PMOS transistor 431, serving as the output transistor, includes: a gate connected to the node of the NMOS transistor 422 and the PMOS transistor 424, a source connected to the power supply terminal 3, and a drain connected to the ground terminal 4 via the constant current source 439. The inverter 432 includes: an input terminal connected to the node of the constant current source 439 and the PMOS transistor 431, and an output terminal connected to the output terminal 31o.

[0135] The DC-DC converter 1C configured in this way achieves the same function and effect as the DC-DC converter 1A. That is, an offset voltage is generated using the on-resistance of a PMOS transistor 413, which has the same conductivity type as the PMOS transistor 62 used as a synchronous rectifier. Since PMOS transistors 62 and 413 have the same conductivity type, even if the on-resistance value Ron62 of PMOS transistor 62 changes due to temperature, input voltage, or manufacturing deviation (PVT deviation), the on-resistance value Ron413 of PMOS transistor 413 will change accordingly. Therefore, the offset voltage value Vos automatically changes in a direction that minimizes the decrease in power conversion efficiency, corresponding to the change in the on-resistance value Ron62, thus preventing a decrease in power conversion efficiency.

[0136] As described above, according to the DC-DC converter 1C, for a boost DC-DC converter, the offset voltage value Vos is automatically adjusted in a direction that minimizes efficiency degradation in response to environmental changes such as temperature or power supply voltage. Furthermore, the offset voltage value Vos is also automatically adjusted in a direction that minimizes power conversion efficiency degradation in response to manufacturing process variations. Therefore, in the DC-DC converter 1C, the timing for turning off the PMOS transistor 62 is, for example, simply by reducing the coil current I... L Set at a coil current I that yields high efficiency L When the current is near 0 Amperes, the efficiency decrease of DC-DC converter 1C caused by the change in the on-resistance of PMOS transistor 62 can be suppressed.

[0137] Moreover, according to the DC-DC converter 1C, the current consumption will not increase, so the power consumption will not increase, and the efficiency of power conversion can be stabilized relative to the change of the on-resistance value Ron62.

[0138] Furthermore, according to the DC-DC converter 1C, the voltage applied to the gate of the PMOS transistor 413 that generates the offset voltage is fixed as the bias voltage V. BIAS Therefore, it does not depend on the input voltage Vin.

[0139] [Fourth Implementation Method]

[0140] Figure 11 This is a circuit diagram showing a structural example (fourth structural example) of the reverse current detection circuit 30D in a DC-DC converter 1D, which is an example of a DC-DC converter according to the fourth embodiment.

[0141] The difference between DC-DC converter 1D and DC-DC converter 1C is that DC-DC converter 1D includes a reverse current detection circuit 30D, which replaces the reverse current detection circuit 30C; otherwise, they are substantially the same. Therefore, in this embodiment, the description will focus on the reverse current detection circuit 30D, and descriptions that are repeated in the first to third embodiments will be omitted.

[0142] The difference between the reverse current detection circuit 30D and the reverse current detection circuit 30C is that the first-stage differential input circuit 410D includes a PMOS transistor 414 replacing the PMOS transistor 413 in the first-stage differential input circuit 410C. Otherwise, they are essentially the same.

[0143] The PMOS transistor 414, as the fifth transistor, differs from the PMOS transistor 413 in that its gate has a different connection target, but otherwise they are substantially the same. The PMOS transistor 414 includes a gate connected to a ground terminal 4, which serves as a power supply terminal and supplies a ground voltage GND.

[0144] The DC-DC converter 1D, configured in this way, can achieve the same function and effect as the DC-DC converter 1B. Therefore, the timing for turning off the PMOS transistor 62 can be achieved, for example, simply by reducing the coil current I... L Set at a coil current I that yields high efficiency L When the current is near 0 Amperes, the power conversion efficiency of DC-DC converter 1D can be suppressed due to the change in the on-resistance of PMOS transistor 62.

[0145] Furthermore, according to the DC-DC converter 1D, the current consumption does not increase, thus preventing an increase in power consumption, and the power conversion efficiency can be stabilized relative to changes in the on-resistance of the PMOS transistor 62. Moreover, according to the DC-DC converter 1D, the voltage applied to the gate of the PMOS transistor 414 that generates the offset voltage is the ground voltage GND, so the offset voltage value Vos changes synchronously with the on-resistance value Ron62 relative to the input voltage Vin. Therefore, the DC-DC converter 1D has the advantage that it is less affected by fluctuations in the input voltage than the DC-DC converter 1C.

[0146] As described above, according to any of the embodiments of this invention, even if the resistance value of the on-resistance of the synchronous rectifier transistor changes, the current consumption will not increase and the power conversion efficiency can be suppressed.

[0147] Furthermore, the present invention is not limited to the described embodiments. In practice, it can be implemented in various ways besides the examples described, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and their equivalents.

Claims

1. A reverse current detection circuit, characterized in that it is coupled to a synchronous rectifier transistor and detects reverse current based on the voltage across the coupled synchronous rectifier transistor. The reverse current detection circuit includes: The first-stage differential input circuit includes a first transistor with a gate connected to one end of the synchronous rectifier transistor as a first input terminal, a first resistor connected in series with the first transistor, a second transistor with a gate connected to the other end of the synchronous rectifier transistor as a second input terminal, and a second resistor connected in series with the second transistor. as well as The second-stage differential input circuit includes a third transistor with a gate connected to the node of the first transistor and the first resistor, and a fourth transistor with a gate connected to the node of the second transistor and the second resistor. The first-stage differential input circuit also has a fifth transistor, which includes a drain connected to the other end of the first resistor relative to the end connected to the first transistor, and has the same conductivity type as the synchronous rectifier transistor.

2. The reverse current detection circuit according to claim 1, wherein... The fifth transistor includes a gate connected to a bias circuit that supplies a specified bias voltage.

3. The reverse current detection circuit according to claim 1, wherein... The fifth transistor includes a gate connected to a terminal supplying the power supply voltage.

4. The reverse current detection circuit according to claim 3, wherein... The fifth transistor is an N-channel metal-oxide-semiconductor transistor containing a gate connected to a power supply terminal, which supplies a voltage higher than the ground voltage as the power supply voltage.

5. The reverse current detection circuit according to claim 3, wherein... The fifth transistor is a P-channel metal-oxide-semiconductor transistor containing a gate connected to a ground terminal, which supplies a ground voltage as the power supply voltage.

6. A DC-DC converter, comprising: Synchronous rectifier transistor; as well as The reverse current detection circuit according to any one of claims 1 to 5, wherein the reverse current detection circuit detects the reverse current based on the voltage across the synchronous rectifier transistor.

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