Shielded gate trench field effect transistor with trench source and preparation method thereof

Abstract

The present application relates to a shielded-gate trench field-effect transistor with a trench source, comprising: a substrate region, a drift region, a body region, an N-type source region, a shield gate, a control gate, an insulating layer, a trench source, a drain, and a metal gate. The drift region is connected to the substrate region, and the body region and the N-type source region are sequentially arranged above the drift region. The control gate and the shield gate are sequentially arranged on the sides of the drift region from top to bottom and are respectively connected to the drift region, the body region, and the N-type source region through the insulating layer. The trench source includes a horizontal source portion and a vertical source portion, the vertical source portion being connected to one end of the horizontal source portion to form a source with an L-shaped longitudinal cross-section. The horizontal source portion is arranged above the N-type source region, and the vertical source portion is connected to the side surfaces of the N-type source region and the body region, so that the corners of the N-type source region align with the corners of the trench source. The drain is arranged below the substrate region, and the metal gate is arranged above the control gate. The solution provided by this application can improve the avalanche capability of the device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a shielded gate trench field effect transistor with a trench source and a preparation method thereof. Background Art

[0002] Shielded-gate trench field-effect transistors (SGTs) have been widely used in important low-voltage applications such as power management. This is due to their high channel density and excellent charge compensation. Furthermore, their shielded gate structure effectively isolates the coupling between the metal gate and the drain, significantly reducing transfer capacitance. This results in lower specific on-resistance, reduced conduction and switching losses, and higher operating frequencies.

[0003] In related technologies, in order to suppress the floating effect of the substrate region, a heavily doped P-type source region is required to short-circuit the base region and the N-type source region connecting the channel. In the traditional structure, both the P-type source region and the N-type source region are fabricated on the surface of the silicon wafer in the transistor. This structure has two problems:

[0004] First, this structure consumes a certain amount of silicon wafer area. In order to ensure that the P-type source region has sufficient area for short-circuiting, the area of ​​the P-type source region must be introduced; or in order to ensure the area of ​​the P-type source region and the N-type source region, the required silicon wafer area is larger, and the device cost increases accordingly; second, under this structure, when the transistor is in forward high-voltage blocking or forward high-voltage conduction, holes are generated due to the avalanche effect. The holes will flow through the substrate channel to form a hole current sufficient to turn on the parasitic transistor, triggering the transistor to turn on, which limits the avalanche capability of the device. Summary of the Invention

[0005] In order to overcome the problems existing in the related art, the present application provides a shielded gate trench field effect transistor with a trench source, which can simplify the P-type source region structure and ensure the avalanche capability of the transistor.

[0006] In a first aspect, the present application provides a shielded gate trench field effect transistor with a trench source, comprising:

[0007] Substrate region 1, drift region 2, body region 3, N-type source region 4, shield gate 5, control gate 6, insulating layer 7, trench source 8, drain 9 and metal gate 10;

[0008] The drift region 2 is connected to the substrate region 1, with the direction from the substrate region 1 to the drift region 2 being the upper side. The base region 3 and the N-type source region 4 are sequentially arranged above the drift region 2. The control gate 6 and the shield gate 5 are sequentially arranged on the sides of the drift region 2 from top to bottom, and are respectively connected to the drift region 2, the base region 3 and the N-type source region 4 through the insulating layer 7.

[0009] The trench-type source electrode 8 includes a horizontal source portion and a vertical source portion. The vertical source portion is connected to one end of the horizontal source portion to form a source electrode with an L-shaped longitudinal cross-section. The horizontal source portion is arranged above the N-type source region 4. The vertical source portion is connected to the side surfaces of the N-type source region 4 and the base region 3, so that the corners of the N-type source region 4 are aligned with the corners of the trench-type source electrode 8.

[0010] The drain electrode 9 is disposed below the substrate region; and the metal gate 10 is disposed above the control gate.

[0011] In one embodiment, the shielded gate trench field effect transistor with a trench source further includes: an N-type compensation region 11;

[0012] The N-type compensation region 11 is arranged between the trench source 8 and the drift region 2, the top surface of the N-type compensation region 11 is connected to the vertical source portion, the bottom surface of the N-type compensation region 11 is connected to the drift region, and one side surface of the N-type compensation region 11 is connected to the base region 3.

[0013] In one embodiment, the doping concentration of the N-type compensation region 11 is a medium doping concentration.

[0014] In one embodiment, the doping concentration of the N-type source region 4 is a heavy doping concentration.

[0015] In one embodiment, the lateral width of the N-type source region 4 is greater than or equal to 0.2 μm.

[0016] In one embodiment, the doping type of the substrate region 1 is N-type doping, and the doping concentration of the substrate region 1 is a heavy doping concentration;

[0017] The doping type of the drift region 2 is N-type doping, and the doping concentration of the drift region 2 is a light doping concentration;

[0018] The doping type of the base region 3 is P-type doping, and the doping concentration of the base region 3 is medium doping concentration;

[0019] The doping type of the shielding gate 5 and the control gate 6 are both P-type doping; the doping concentration of the shielding gate 5 and the control gate 6 are both heavily doped.

[0020] A second aspect of the present application provides a method for preparing a shielded gate trench field effect transistor with a trench source, which is used to prepare the shielded gate trench field effect transistor with a trench source as described in any one of the above items, comprising:

[0021] preparing a substrate region with semiconductor material;

[0022] epitaxially forming a drift region on the substrate region;

[0023] forming a matrix region on the drift region by ion implantation or diffusion;

[0024] etching a trench on one side of the drift region;

[0025] Depositing oxide, polysilicon, oxide and polysilicon in sequence in the trench to form a shield gate, an insulating layer and a control gate;

[0026] forming an N-type source region on the base region using an N-type doped semiconductor material;

[0027] Etching part of the N-type source region and part of the substrate region to form a metal electrode trench;

[0028] Fabricating a metal source electrode above the N-type source region and in the metal electrode trench to form a trench-type source electrode;

[0029] forming a metal gate over the trench;

[0030] A drain is formed below the substrate region.

[0031] In one embodiment, after etching part of the N-type source region and part of the substrate region to form a metal electrode trench, the method includes:

[0032] An N-type doped semiconductor material is deposited in the metal electrode trench to form an N-type compensation region.

[0033] In one embodiment, in the N-type source region formed on the base region using an N-type doped semiconductor material, the N-type doped semiconductor material is an N-type heavily doped semiconductor material.

[0034] In one embodiment, oxide, polysilicon, oxide and polysilicon are sequentially deposited in the trench to form a shield gate, an insulating layer and a control gate, and the polysilicon is heavily doped polysilicon.

[0035] The technical solution provided by this application may have the following beneficial effects:

[0036] In the shielded gate trench field-effect transistor with a trench source provided by the present application, the P-type source region in the traditional source structure is removed, and a trench source having a horizontal source portion and a vertical source portion is combined with an N-type source region to form a trench Schottky source region structure. In this trench Schottky source region structure, the horizontal source portion is arranged above the N-type source region, and the vertical source portion is connected to the side surfaces of the N-type source region and the body region, so that the corners of the N-type source region are aligned with the corners of the trench source, thereby bringing the source region closer to the drift region, which in turn enables the source region to collect avalanche current more quickly. Since the original P-type source region is removed, the shielded gate trench field-effect transistor with a trench source provided by the present application can reduce the silicon wafer area while ensuring that the area occupied by the N-type source region is constant, thereby saving device cost; or, within a certain silicon wafer area, make the channel density as large as possible, thereby improving the conductivity of the device;

[0037] On the premise that the above-mentioned P-type source region structure is simplified, the groove-type source in the present application forms a P-type Schottky contact with the substrate region. When the device is in an avalanche state, the injected hole current must first reach the turn-on voltage of the P-type Schottky junction before the holes can be injected, so that the avalanche hole current is collected by the groove-type source in advance before reaching the substrate region. Therefore, the groove-type source of the present application suppresses the ability of the avalanche hole current to flow into the groove-type source through the substrate region, thereby improving the avalanche capability of the device, so that the device still maintains a high avalanche capability when the P-type source region structure is removed.

[0038] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The above and other objects, features and advantages of the present application will become more apparent through a more detailed description of exemplary embodiments of the present application in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the present application.

[0040] Figure 1 Schematic diagram of the structure of a shielded gate trench field effect transistor with a trench source shown in an embodiment of the present application;

[0041] Figure 2 1 is another structural schematic diagram of a shielded gate trench field effect transistor with a trench source shown in an embodiment of the present application;

[0042] Figure 3 1 is a flow chart of a method for manufacturing a shielded gate trench field effect transistor with a trench source shown in an embodiment of the present application;

[0043] Figure 4 This is another flow chart of a method for preparing a shielded gate trench field effect transistor with a trench source shown in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The preferred embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. Instead, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0045] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0046] It should be understood that although the terms "first", "second", "third", etc. may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0047] Example 1

[0048] In the traditional structure, both the P-type source region and the N-type source region are fabricated on the surface of the silicon wafer in the transistor. This structure has two problems:

[0049] First, this structure consumes a certain amount of silicon wafer area. In order to ensure that the P-type source region has sufficient area for short-circuiting, the area of ​​the N-type source region must be sacrificed; or in order to ensure the area of ​​the P-type source region and the N-type source region, the required silicon wafer area is larger, and the device cost increases accordingly; second, under this structure, when the transistor is in forward high-voltage blocking or forward high-voltage conduction, holes are generated due to the avalanche effect. The holes will flow through the substrate channel to form a hole current sufficient to turn on the parasitic transistor, triggering the transistor to turn on.

[0050] In response to the above problems, an embodiment of the present application provides a shielded gate trench field effect transistor with a trench source, which can simplify the P-type source region without affecting the avalanche capability of the transistor.

[0051] The technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0052] Figure 1 Schematic diagram of the structure of a shielded gate trench field effect transistor with a trench source shown in an embodiment of the present application.

[0053] See also Figure 1 , the shielded gate trench field effect transistor with a trench source comprises:

[0054] Substrate region 1, drift region 2, body region 3, N-type source region 4, shield gate 5, control gate 6, insulating layer 7, trench source 8, drain 9 and metal gate 10;

[0055] The drift region 2 is connected to the substrate region 1, with the direction from the substrate region 1 to the drift region 2 being the upper side. The base region 3 and the N-type source region 4 are sequentially arranged above the drift region 2. The control gate 6 and the shield gate 5 are sequentially arranged on the sides of the drift region 2 from top to bottom, and are respectively connected to the drift region 2, the base region 3 and the N-type source region 4 through the insulating layer 7.

[0056] The drain electrode 9 is arranged below the substrate region 1; the metal gate 10 is arranged above the control gate 6;

[0057] The trench-type source electrode 8 includes a horizontal source portion and a vertical source portion. The vertical source portion is connected to one end of the horizontal source portion to form a source electrode with an L-shaped longitudinal cross-section. The horizontal source portion is arranged above the N-type source region 4. The vertical source portion is connected to the side surfaces of the N-type source region 4 and the base region 3, so that the corners of the N-type source region 4 are aligned with the corners of the trench-type source electrode 8.

[0058] In the embodiment of the present application, with the direction from the drift region 2 to the substrate region 1 as the longitudinal direction, the vertical source portion is connected to the end of the horizontal source portion away from the control gate, so that the longitudinal cross-section of the trench source 8 is L-shaped, wherein the inner side surface of the vertical source portion is attached to the side of the transistor, connected to the N-type source region and the base region, and the horizontal source portion is attached to the top surface of the N-type source region.

[0059] Compared with the traditional shielded gate trench field effect transistor with a heavily doped P-type source region, the embodiment of the present application uses a trench source to replace the P-type source region, freeing up a considerable portion of the silicon wafer area, which not only provides sufficient silicon wafer area for the N-type source region, but also saves the material cost of the transistor.

[0060] By utilizing the vertical source portion of the trench source, the trench source is closer to the drift region, which can not only collect the avalanche current faster, but also enable the body diode of the transistor to conduct with majority current when turned on, shortening the reverse recovery time, thereby improving the fast switching capability of the transistor.

[0061] In the embodiment of the present application, the doping concentration of the N-type source region 4 is a heavy doping concentration; and the lateral width of the N-type source region 4 is greater than or equal to 0.2 μm.

[0062] Furthermore, the doping type of the substrate region 1 is N-type doping, and the doping concentration of the substrate region 1 is a heavy doping concentration; the doping type of the drift region 2 is N-type doping, and the doping concentration of the drift region 2 is a light doping concentration; the doping type of the base region 3 is P-type doping, and the doping concentration of the base region 3 is a medium doping concentration; the doping type of the shielding gate 5 and the control gate 6 are both P-type doping; the doping concentration of the shielding gate 5 and the control gate 6 are both heavy doping concentrations.

[0063] In practical applications, the shielding gate 5 and the control gate 6 may also be doped with N-type doping.

[0064] Among them, the value range of light doping concentration is 1×10 15 cm -3 to 5×10 16 cm -3 The doping concentration range is 1×10 17 cm -3 to 5×10 18 cm -3 The range of heavy doping concentration is 1×10 19 cm -3 to 5×10 20 cm -3 .

[0065] In the shielded gate trench field effect transistor with a trench source provided in an embodiment of the present application, the P-type source region in the traditional source structure is removed, and a trench source having a horizontal source portion and a vertical source portion is combined with an N-type source region to form a trench Schottky source region structure. In this trench Schottky source region structure, the horizontal source portion is arranged above the N-type source region, and the vertical source portion is connected to the side surfaces of the N-type source region and the body region, so that the corners of the N-type source region are aligned with the corners of the trench source, thereby bringing the source region closer to the drift region, and thus enabling the source region to collect avalanche current more quickly. Since the original P-type source region is removed, the shielded gate trench field effect transistor with a trench source provided in the present application can reduce the silicon wafer area while ensuring that the area occupied by the N-type source region is constant, thereby saving device cost; or, within a certain silicon wafer area, make the channel density as large as possible, thereby improving the conductivity of the device.

[0066] On the premise that the above-mentioned P-type source region structure is simplified, the groove-type source in the present application forms a P-type Schottky contact with the substrate region. When the device is in an avalanche state, the injected hole current must first reach the turn-on voltage of the P-type Schottky junction before the holes can be injected, so that the avalanche hole current is collected by the groove-type source in advance before reaching the substrate region. Therefore, the groove-type source of the present application suppresses the ability of the avalanche hole current to flow into the groove-type source through the substrate region, thereby improving the avalanche capability of the device, so that the device still maintains a high avalanche capability when the P-type source region structure is removed.

[0067] Example 2

[0068] Based on the shielded gate trench field effect transistor with a trench source shown in the first embodiment above, the embodiment of the present application provides another structure of a shielded gate trench field effect transistor with a trench source, which can perform impurity compensation with the base region to improve the avalanche capability of the transistor.

[0069] The technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0070] Figure 2 This is another structural schematic diagram of the shielded gate trench field effect transistor with a trench source shown in an embodiment of the present application.

[0071] See also Figure 2 , the shielded gate trench field effect transistor with a trench source comprises:

[0072] Substrate region 1, drift region 2, body region 3, N-type source region 4, shield gate 5, control gate 6, insulating layer 7, trench source 8, drain 9, metal gate 10 and N-type compensation region 11;

[0073] The N-type compensation region 11 is disposed between the trench source 8 and the drift region 2 , wherein the top surface of the N-type compensation region 11 is in contact with the vertical source portion, the bottom surface of the N-type compensation region 11 is in contact with the drift region 2 , and one side surface of the N-type compensation region 11 is in contact with the base region 3 ;

[0074] Furthermore, the doping concentration of the N-type compensation region 11 is a medium doping concentration.

[0075] In an embodiment of the present application, grooves are etched on the sides of the N-type source region 4 and the base region 3 by an etching process, and then an N-type doped semiconductor material with a medium doping concentration is injected to form an N-type compensation region 11. Since the doping concentration of the N-type compensation region 11 is similar to that of the base region 3 and the doping type is opposite, the N-type compensation region 11 can compensate for the impurities in the base region 3. The grooved source 8 formed after metal deposition forms a P-type Schottky contact with the base region 3. When the transistor is in an avalanche state, the injected hole current must first reach the turn-on voltage of the P-type Schottky junction before the holes can be injected, which is equivalent to raising the threshold for the hole current to flow into the source. Therefore, the ability of the avalanche hole current to flow into the source is suppressed, thereby improving the avalanche capability of the transistor.

[0076] In practical applications, preferably, the doping concentration of the N-type compensation region and the base region can be set to the same doping concentration, for example: 5×10 17 cm -3 .

[0077] It should be noted that the above description of the doping concentration of the N-type compensation region is merely an example given in the embodiment of the present application and does not constitute the sole limitation of the present application.

[0078] The drift region 2 is connected to the substrate region 1, with the direction from the substrate region 1 to the drift region 2 being the upper side. The base region 3 and the N-type source region 4 are sequentially arranged above the drift region 2. The control gate 6 and the shield gate 5 are sequentially arranged on the sides of the drift region 2 from top to bottom, and are respectively connected to the drift region 2, the base region 3 and the N-type source region 4 through the insulating layer 7.

[0079] The trench-type source 8 includes a horizontal source portion and a vertical source portion, the vertical source portion is connected to one end of the horizontal source portion, forming a source with an L-shaped longitudinal cross-section; the horizontal source portion is arranged above the N-type source region 4, and the vertical source portion is connected to the side surfaces of the N-type source region 4 and the base region 3, so that the corners of the N-type source region 4 are aligned with the corners of the trench-type source 8; the drain 9 is arranged below the substrate region; and the metal gate 10 is arranged above the control gate.

[0080] An embodiment of the present application provides another shielded gate trench field effect transistor with a trench source, wherein an N-type compensation region is provided between the trench source and the drift region, and the N-type compensation region is connected to the base region. Impurity compensation is performed on the base region through the N-type compensation region, which is equivalent to forming an N-type drift region with a medium doping concentration, while the trench source forms a P-type Schottky contact with the base region. When the transistor is in an avalanche state, the injected hole current must first reach the turn-on voltage of the p-type Schottky junction before holes can be injected. Therefore, the ability of the avalanche hole current to flow into the trench source through the base region is suppressed, and the avalanche capability of the transistor is improved. On the other hand, when the transistor is in reverse conduction of the body diode, since the P-type Schottky diode is in a reverse biased state, the trench source and the above-mentioned N-type drift region form a forward-biased N-type Schottky junction. Therefore, the conduction of the body diode is mainly based on majority conduction, which reduces the reverse recovery time of the transistor and improves the switching speed of the transistor.

[0081] Example 3

[0082] Corresponding to the shielded gate trench field effect transistor with a trench source described in the first embodiment above, the present application also provides a method for preparing a shielded gate trench field effect transistor with a trench source and corresponding embodiments.

[0083] Figure 3 It is a flow chart of a method for preparing a shielded gate trench field effect transistor with a trench source shown in an embodiment of the present application.

[0084] See also Figure 3 The method for preparing the shielded gate trench field effect transistor with a trench source comprises:

[0085] 301. Prepare a substrate region using semiconductor material;

[0086] In the embodiment of the present application, the semiconductor material used is an N-type heavily doped semiconductor material.

[0087] 302. Epitaxially forming a drift region on the substrate region;

[0088] In the embodiments of the present application, different epitaxial processes may be used according to actual needs, including but not limited to: vapor phase epitaxy (VPE) or chemical vapor deposition (CVD).

[0089] 303. Forming a matrix region on the drift region by ion implantation or diffusion;

[0090] Ion implantation is the process of doping silicon materials. In practice, a power device is placed at one end of an ion implanter, with a doping ion source located at the other. At the doping ion source, the dopant atoms are ionized, becoming charged. The electric field propels them at high speeds, forcing them through the surface of the device. The momentum of the atoms propagates through the power device, forming a doped region.

[0091] The diffusion process is the process of doping pure impurity atoms into the surface of silicon materials. In actual applications, diborane or phosphine is usually used as an ion source, and intermittent diffusion or substitutional diffusion is used to dope pure impurity atoms into the surface of silicon materials.

[0092] It should be noted that the embodiments of the present application do not have strict restrictions on the preparation method used for the substrate region. In actual practice, the above-mentioned different processes can be selected according to actual needs to complete the preparation of the substrate region.

[0093] 304. Etching a groove on one side of the drift region;

[0094] In an embodiment of the present application, a groove is etched on one side of the drift region by a photolithography process, and the residual photoresist is removed by wet etching or dry etching.

[0095] 305. Depositing oxide, polysilicon, oxide and polysilicon in sequence in the trench to form a shield gate, an insulating layer and a control gate;

[0096] In the embodiment of the present application, the polysilicon is N-type or P-type heavily doped polysilicon.

[0097] Preferably, in actual application, oxide, P-type medium-doped polysilicon, oxide and P-type heavily-doped polysilicon may be deposited in sequence in the trench to form a shielding gate, an insulating layer and a control gate.

[0098] 306. Forming an N-type source region on the substrate region using an N-type doped semiconductor material;

[0099] In the embodiment of the present application, the N-type doped semiconductor material is an N-type heavily doped semiconductor material.

[0100] 307. Etching part of the N-type source region and part of the substrate region to form a metal electrode trench;

[0101] In the embodiment of the present application, the etching process used is the same as that in step 304 and will not be described again here.

[0102] 308. Fabricate a metal source electrode above the N-type source region and in the metal electrode trench to form a trench-type source electrode;

[0103] Specifically: after etching the metal electrode trench, metal deposition is performed in the metal electrode trench to form a vertical source portion of the trench-type source, and then a metal deposition process is used to deposit a horizontal source portion on the top surface of the remaining N-type source region that has not been etched away to obtain a trench-type source.

[0104] 309. Forming a metal gate above the trench;

[0105] 310. Fabricate a drain below the substrate region.

[0106] An embodiment of the present application provides a method for preparing a shielded gate trench field-effect transistor with a trench source. The shielded gate trench field-effect transistor with a trench source prepared using this method has a trench source structure. The trench source replaces the P-type source region in the traditional source structure, so that the source region is closer to the drift region, which enables the source region to collect avalanche current more quickly. Since the original P-type source region is removed, the shielded gate trench field-effect transistor with a trench source provided by the present application can reduce the silicon wafer area while ensuring that the area occupied by the N-type source region is constant, thereby saving device costs. Alternatively, within a certain silicon wafer area, the channel density can be maximized, thereby improving the conductivity of the device.

[0107] On the premise that the above-mentioned P-type source region structure is simplified, the groove-type source in the present application forms a P-type Schottky contact with the substrate region. When the device is in an avalanche state, the injected hole current must first reach the turn-on voltage of the P-type Schottky junction before the holes can be injected, so that the avalanche hole current is collected by the groove-type source in advance before reaching the substrate region. Therefore, the groove-type source of the present application suppresses the ability of the avalanche hole current to flow into the groove-type source through the substrate region, thereby improving the avalanche capability of the device, so that the device still maintains a high avalanche capability when the P-type source region structure is removed.

[0108] Example 4

[0109] Corresponding to the shielded gate trench field effect transistor with a trench source described in the second embodiment above, the present application also provides a method for preparing a shielded gate trench field effect transistor with a trench source and corresponding embodiments.

[0110] Figure 4 This is another flow chart of a method for preparing a shielded gate trench field effect transistor with a trench source shown in an embodiment of the present application.

[0111] See also Figure 4 The method for preparing the shielded gate trench field effect transistor with a trench source comprises:

[0112] 401. Prepare a substrate region using semiconductor material;

[0113] In the embodiment of the present application, step 401 is consistent with step 301 in the above-mentioned embodiment 3 and will not be repeated here.

[0114] 402. Epitaxially forming a drift region on the substrate region;

[0115] In the embodiment of the present application, step 402 is consistent with step 302 in the above-mentioned embodiment 3 and will not be repeated here.

[0116] 403. Forming a matrix region on the drift region by ion implantation or diffusion;

[0117] In the embodiment of the present application, step 403 is consistent with step 303 in the above-mentioned embodiment 3 and will not be repeated here.

[0118] 404. Etching a trench on one side of the drift region;

[0119] In the embodiment of the present application, step 404 is consistent with step 304 in the above-mentioned embodiment 3 and will not be repeated here.

[0120] 405. Depositing oxide, polysilicon, oxide, and polysilicon in sequence in the trench to form a shield gate, an insulating layer, and a control gate;

[0121] In the embodiment of the present application, step 405 is consistent with step 305 in the above-mentioned embodiment 3 and will not be repeated here.

[0122] 406. Forming an N-type source region on the substrate region using an N-type doped semiconductor material;

[0123] In the embodiment of the present application, step 406 is consistent with step 306 in the above-mentioned embodiment 3 and will not be repeated here.

[0124] 407. Etching part of the N-type source region and part of the substrate region to form a metal electrode trench;

[0125] In the embodiment of the present application, step 407 is consistent with step 307 in the above-mentioned embodiment 3 and will not be repeated here.

[0126] 408. Depositing an N-type doped semiconductor material in the metal electrode trench to form an N-type compensation region;

[0127] In an embodiment of the present application, an N-type medium-doped semiconductor material is deposited in the metal electrode trench to form an N-type compensation region, which is equivalent to adjusting the doping concentration of the area in the drift region that is connected to the source, that is, the area close to the substrate region, to a medium doping concentration, thereby forming impurity compensation and suppressing avalanche hole current.

[0128] 409. Fabricate a metal source electrode above the N-type source region and in the metal electrode trench to form a trench-type source electrode;

[0129] In the metal electrode trench, metal is deposited above the N-type compensation region to obtain a groove-type source, and a P-type Schottky contact is formed between the source and the substrate region. When the transistor is in an avalanche state, the injected hole current must first reach the turn-on voltage of the P-type Schottky junction before holes can be injected, thereby suppressing the ability of the avalanche hole current to flow into the groove-type source through the substrate region. In addition, when the device is in the body diode reverse conduction, since the P-type Schottky diode is in a reverse biased state, the groove-type source and the drift region of the N-type doping concentration below it, that is, the N-type compensation region in the above step 408, form a forward-biased N-type Schottky junction. Therefore, the conduction of the body diode is mainly based on majority conduction, which reduces the reverse recovery time of the transistor and improves the switching speed of the transistor.

[0130] 410. Forming a metal gate above the trench;

[0131] 411. Fabricate a drain below the substrate region.

[0132] An embodiment of the present application provides another method for preparing a shielded gate trench field effect transistor with a trench source. The shielded gate trench field effect transistor with a trench source prepared by this method has an N-type compensation region provided between the trench source and the drift region. The N-type compensation region is connected to the substrate region. Impurities in the substrate region are compensated by the N-type compensation region, which is equivalent to forming an N-type drift region with a medium doping concentration. The trench source forms a P-type Schottky contact with the substrate region. When the transistor is in an avalanche state, the injected hole current must first reach the turn-on voltage of the p-type Schottky junction before holes can be injected. The ability of the avalanche hole current to flow into the trench source through the substrate region is suppressed, and the avalanche capability of the transistor is improved. On the other hand, when the transistor is in reverse conduction of the body diode, since the P-type Schottky diode is in a reverse biased state, the trench source and the above-mentioned N-type drift region form a forward-biased N-type Schottky junction. Therefore, the conduction of the body diode is mainly based on majority conduction, which reduces the reverse recovery time of the transistor and improves the switching speed of the transistor.

[0133] The scheme of the present application has been described in detail above with reference to the accompanying drawings. In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Those skilled in the art should also be aware that the actions and modules involved in the description are not necessarily required for this application. In addition, it is understood that the steps in the method of the embodiment of the present application can be adjusted in sequence, merged and deleted according to actual needs, and the modules in the device of the embodiment of the present application can be merged, divided and deleted according to actual needs.

[0134] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems and methods according to multiple embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or code, and the part of the module, program segment or code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0135] The embodiments of the present application have been described above. The above description is illustrative and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to the technology in the market, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

Claims

1. A shielded gate trench field effect transistor with a trench source, characterized in that: include: A substrate region (1), a drift region (2), a base region (3), an N-type source region (4), a shielding gate (5), a control gate (6), an insulating layer (7), a trench source (8), a drain (9), and a metal gate (10); The drift region (2) is connected to the substrate region (1), with the direction from the substrate region (1) to the drift region (2) being the upper side, and the base region (3) and the N-type source region (4) being sequentially arranged above the drift region (2); the control gate (6) and the shield gate (5) are sequentially arranged on the side of the drift region (2) from top to bottom, and are respectively connected to the drift region (2), the base region (3) and the N-type source region (4) through the insulating layer (7); The trench-type source (8) comprises a horizontal source portion and a vertical source portion, wherein the vertical source portion is connected to one end of the horizontal source portion to form a source with an L-shaped longitudinal section; the horizontal source portion is arranged above the N-type source region (4), and the vertical source portion is connected to the side surfaces of the N-type source region (4) and the base region (3), so that the corner of the N-type source region (4) is aligned with the corner of the trench-type source (8); The drain (9) is arranged below the substrate region; The metal gate (10) is arranged above the control gate; It also includes: an N-type compensation area (11); The N-type compensation region (11) is arranged between the trench source (8) and the drift region (2), the top surface of the N-type compensation region (11) is in contact with the vertical source portion, the bottom surface of the N-type compensation region (11) is in contact with the drift region, and one side surface of the N-type compensation region (11) is in contact with the base region (3).

2. The shielded gate trench field effect transistor with a trench source according to claim 1, wherein: The doping concentration of the N-type compensation region (11) is a medium doping concentration.

3. The shielded gate trench field effect transistor with a trench source according to claim 1, wherein: The doping concentration of the N-type source region (4) is a heavy doping concentration.

4. The shielded gate trench field effect transistor with a trench source according to claim 1, wherein: The lateral width of the N-type source region (4) is greater than or equal to 0.2 μm.

5. The shielded gate trench field effect transistor with a trench source according to claim 1, wherein: The doping type of the substrate region (1) is N-type doping, and the doping concentration of the substrate region (1) is a heavy doping concentration; The doping type of the drift region (2) is N-type doping, and the doping concentration of the drift region (2) is a light doping concentration; The doping type of the matrix region (3) is P-type doping, and the doping concentration of the matrix region (3) is a medium doping concentration; The doping type of the shielding gate (5) and the control gate (6) are both P-type doping; and the doping concentration of the shielding gate (5) and the control gate (6) are both heavy doping concentrations.

6. A method for preparing a shielded gate trench field effect transistor with a trench source, characterized in that: A shielded gate trench field effect transistor for preparing a trench source according to any one of claims 1 to 5, comprising: preparing a substrate region with semiconductor material; epitaxially forming a drift region on the substrate region; forming a matrix region on the drift region by ion implantation or diffusion; etching a trench on one side of the drift region; Depositing oxide, polysilicon, oxide and polysilicon in sequence in the trench to form a shield gate, an insulating layer and a control gate; forming an N-type source region on the base region using an N-type doped semiconductor material; Etching part of the N-type source region and part of the substrate region to form a metal electrode trench; Fabricating a metal source electrode above the N-type source region and in the metal electrode trench to form a trench-type source electrode; forming a metal gate over the trench; forming a drain electrode below the substrate region; After etching part of the N-type source region and part of the substrate region to form a metal electrode trench, the method includes: An N-type doped semiconductor material is deposited in the metal electrode trench to form an N-type compensation region.

7. The method for preparing a shielded gate trench field effect transistor with a trench source according to claim 6, characterized in that: In the N-type source region formed on the base region by using an N-type doped semiconductor material, the N-type doped semiconductor material is an N-type heavily doped semiconductor material.

8. The method for preparing a shielded gate trench field effect transistor with a trench source according to claim 6, wherein: Oxide, polysilicon, oxide and polysilicon are sequentially deposited in the trench to form a shielding gate, an insulating layer and a control gate, and the polysilicon is heavily doped polysilicon.

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