Semiconductor structure and method for forming the same

Abstract

The present application provides a semiconductor structure and a method for forming the same. The semiconductor structure includes: a semiconductor substrate including a first region and a second region and an isolation structure isolating the first region from the second region; a gate structure located on the semiconductor substrate in the first region and the second region; a first spacer located on the sidewalls of the gate structure; a source and a drain located in the semiconductor substrate on both sides of the gate structure, wherein the first region also includes a lightly doped source extending below the first spacer on the source side of the first region; and a second spacer located on the sidewalls of the first spacer on the drain side of the first region and the sidewalls of the first spacer in the second region. The semiconductor structure and method for forming the same described in the present application can improve the bipolar effect of a TFET device, increase the tunneling current of the device, and improve device reliability.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] TFET (Tunneling Field Effect Transistor) devices with excellent subthreshold characteristics can be hybrid integrated with traditional CMOS devices to reduce the overall power consumption of the circuit. The high-frequency part of the circuit is completed by conventional CMOS devices, and the low-frequency part is completed by TFET devices.

[0003] While compatible with existing CMOS processes, the structure and performance of TFET devices remain unstable, leaving significant room for improvement. Conventional TFET devices have opposite source and drain doping types, resulting in a bipolar effect. When the channel length is short, leakage current deteriorates significantly, affecting the device's turn-off characteristics.

[0004] Therefore, it is necessary to provide more reliable and effective technical solutions. Summary of the Invention

[0005] The present application provides a semiconductor structure and a method for forming the same, which can improve the bipolar effect of a TFET device, increase the tunneling current of the device, and improve the reliability of the device.

[0006] One aspect of the present application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, the semiconductor substrate comprising a first region and a second region and an isolation structure isolating the first region from the second region, a gate structure being formed on the semiconductor substrate in the first region and the second region, the sidewalls of the gate structure being sequentially formed with a first sidewall and a second sidewall, a source and a drain being formed in the semiconductor substrate on both sides of the gate structure; removing the second sidewall on the source side of the first region to expose a portion of the semiconductor substrate; and forming a lightly doped source in the exposed semiconductor substrate.

[0007] In some embodiments of the present application, the method for removing the second sidewall on the source side of the first region includes: forming a blocking layer on the surface of the semiconductor substrate, the surface of the first sidewall, the surface of the second sidewall, the surface of the gate structure and the surface of the isolation structure; forming a third mask layer on the surface of the blocking layer, the third mask layer exposing the blocking layer on the second sidewall on the source side of the first region; etching and removing the exposed blocking layer using the third mask layer as a mask to expose the second sidewall on the source side of the first region; removing the third mask layer; etching and removing the exposed second sidewall; removing the blocking layer.

[0008] In some embodiments of the present application, the method for forming a lightly doped source in the exposed semiconductor substrate includes: forming a fourth mask layer on the semiconductor substrate, the fourth mask layer exposing the semiconductor substrate; and performing a light doping process on the exposed semiconductor substrate to form the lightly doped source.

[0009] In some embodiments of the present application, the doping concentration of the light doping process is 1E14 to 5E15 atom / cm 3 .

[0010] In some embodiments of the present application, the doping energy of the light doping process is 5-10 keV.

[0011] In some embodiments of the present application, the method for forming the semiconductor structure includes: forming a gate structure on the semiconductor substrate in the first region and the second region; forming a first sidewall on the sidewall of the gate structure; forming a second sidewall on the sidewall of the first sidewall; and forming a source and a drain in the semiconductor substrate on both sides of the gate structure in the first region and the second region, respectively.

[0012] In some embodiments of the present application, a method for forming a source and a drain in a semiconductor substrate on both sides of a gate structure in the first region includes: forming a first mask layer on the semiconductor substrate, the first mask layer exposing the semiconductor substrate on one side of the gate structure in the first region; forming a drain in the exposed semiconductor substrate; removing the first mask layer; forming a second mask layer on the semiconductor substrate, the second mask layer exposing the semiconductor substrate on the other side of the gate structure in the first region; forming a source in the exposed semiconductor substrate; and removing the second mask layer.

[0013] In some embodiments of the present application, the source of the second region includes a lightly doped source and a heavily doped source; the drain of the second region includes a lightly doped drain and a heavily doped drain.

[0014] In some embodiments of the present application, the method for forming the second sidewall and forming the source and drain in the semiconductor substrate of the second region includes: forming a fifth mask layer on the semiconductor substrate of the first region; performing a first ion implantation on the semiconductor substrate on both sides of the gate structure of the second region to form a lightly doped source and a lightly doped drain; removing the fifth mask layer; forming a second sidewall on the sidewall of the first sidewall; forming a sixth mask layer on the semiconductor substrate of the first region; performing a second ion implantation on the semiconductor substrate on both sides of the gate structure of the second region to form a heavily doped source and a heavily doped drain; and removing the sixth mask layer.

[0015] In some embodiments of the present application, the concentration of the first ion implantation is 2E13-2E15 atom / cm 3 The concentration of the second ion implantation is 2E13~2E16 atom / cm 3 .

[0016] In some embodiments of the present application, the energy of the first ion implantation is 2-5 keV; the energy of the second ion implantation is 5-25 keV.

[0017] In some embodiments of the present application, the first region is a TFET region; the second region includes a MOSFET region or a TFET region.

[0018] In some embodiments of the present application, the source and drain of the TFET region have opposite doping types.

[0019] In some embodiments of the present application, the gate structure includes a gate oxide layer located on the surface of the semiconductor substrate and a gate layer located on the gate oxide layer.

[0020] Another aspect of the present application also provides a semiconductor structure, including: a semiconductor substrate, the semiconductor substrate including a first region and a second region and an isolation structure isolating the first region and the second region; a gate structure, located on the semiconductor substrate in the first region and the second region; a first sidewall, located on the sidewall of the gate structure; a source and a drain, located in the semiconductor substrate on both sides of the gate structure, wherein the first region also includes a lightly doped source, the lightly doped source extends to below the first sidewall on the source side of the first region; a second sidewall, the sidewall of the first sidewall on the drain side of the first region and the sidewall of the first sidewall of the second region.

[0021] In some embodiments of the present application, the doping concentration of the lightly doped source is 1E14 to 5E15 atom / cm 3 .

[0022] In some embodiments of the present application, the doping energy of the lightly doped source is 5-10 keV.

[0023] In some embodiments of the present application, the source of the second region includes a lightly doped source and a heavily doped source; the drain of the second region includes a lightly doped drain and a heavily doped drain.

[0024] In some embodiments of the present application, the doping concentration of the lightly doped source is 2E13-2E15 atom / cm 3 The doping concentration of the lightly doped drain is 2E13 to 2E15 atom / cm 3The doping concentration of the heavily doped source is 2E13 to 2E16 atom / cm 3 The doping concentration of the heavily doped drain is 2E13 to 2E16 atom / cm 3 .

[0025] In some embodiments of the present application, the doping energy of the lightly doped source is 2-5 keV, and the doping depth of the lightly doped drain is 2-5 keV; the doping depth of the heavily doped source is 5-25 keV, and the doping depth of the heavily doped drain is 5-25 keV.

[0026] In some embodiments of the present application, the first region is a TFET region; and the second region includes a MOSFET region or a TFET region.

[0027] In some embodiments of the present application, the source and drain of the TFET region have opposite doping types.

[0028] In some embodiments of the present application, the gate structure includes a gate oxide layer located on the surface of the semiconductor substrate and a gate layer located on the gate oxide layer.

[0029] The semiconductor structure and formation method described in this application improve the structure of the TFET device, so that the source boundary is closer to the channel below the gate, while the drain is away from the channel, which can improve the bipolar effect of the TFET device, enhance the switching capability of the TFET device, and reduce the leakage current when the device is turned off. After the second gate on the source side is removed, the subsequent metal silicide generation process can increase the doping concentration gradient at the edge of the TFET device channel, increase the tunneling current of the device, and thus improve the device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The following figures describe in detail exemplary embodiments disclosed in this application. Identical reference numerals denote similar structures in several views of the drawings. Those skilled in the art will appreciate that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of this application. Other embodiments may also achieve the same inventive intent as described in this application. It should be understood that the drawings are not drawn to scale. Among them:

[0031] Figures 1 to 27 Schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content of this application. Various local modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but is intended to be of the widest scope consistent with the claims.

[0033] The technical solution of the present invention is described in detail below with reference to the embodiments and drawings.

[0034] Unlike CMOS devices, conventional TFETs have opposite source and drain doping types. This opposite doping type creates a bipolar effect, a phenomenon in which tunneling occurs at the drain junction of a TFET, increasing subthreshold leakage current and degrading transistor performance, significantly affecting the device's turn-off characteristics.

[0035] In response to the above problems, the present application provides a semiconductor structure and a method for forming the same, which improves the structure of the TFET device so that the source boundary is closer to the channel below the gate, while the drain is away from the channel. This can improve the bipolar effect of the TFET device, enhance the switching capability of the TFET device, and reduce the leakage current when the device is turned off.

[0036] Figures 1 to 27 The semiconductor structure and its forming method described in the present application are described in detail below with reference to the accompanying drawings.

[0037] An embodiment of the present application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, the semiconductor substrate comprising a first region and a second region and an isolation structure isolating the first region and the second region, a gate structure being formed on the semiconductor substrate in the first region and the second region, the sidewalls of the gate structure being sequentially formed with a first sidewall and a second sidewall, a source and a drain being formed in the semiconductor substrate on both sides of the gate structure; removing the second sidewall on the source side of the first region to expose a portion of the semiconductor substrate; and forming a lightly doped source in the exposed semiconductor substrate.

[0038] refer to Figure 1 , a semiconductor substrate 100 is provided, wherein the semiconductor substrate 100 includes a first region 101 and a second region 102 and an isolation structure 103 isolating the first region 101 from the second region 102 .

[0039] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.

[0040] In some embodiments of the present application, the isolation structure 103 is made of silicon oxide, silicon nitride, silicon oxynitride, etc. The isolation structure 103 is used to isolate active devices in the semiconductor substrate in the first region 101 and the second region 102 .

[0041] refer to Figure 2 The semiconductor substrates of the first region 101 and the second region 102 are doped separately. A deeper portion of the semiconductor substrate of the first region 101 is doped to form an isolation region 104, and a larger area of ​​the semiconductor substrate of the second region 102 is doped to form a well region 105. The isolation region 104 further isolates the second region 102.

[0042] In some embodiments of the present application, the first region 101 is a TFET region; the second region 102 includes a MOSFET region or a TFET region. It should be noted that in this embodiment, the second region 102 is only an MOS region as an exemplary embodiment, but this does not limit the technical solution of the present application. The doping type of the isolation region 104 and the well region 105 is not limited and can be P-type doping or N-type doping. The second region 102 can be a PMOSFET region or an NMOSFET region.

[0043] In some embodiments of the present application, the well region 105 can be a P-type well region doped with a P-type dopant (eg, boron, indium, aluminum, or gallium), or an N-type well region doped with an N-type dopant (eg, phosphorus or arsenic).

[0044] refer to Figure 3 and Figure 4 A gate structure 110 is formed on the semiconductor substrate 100 in the first region 101 and the second region 102. In some embodiments of the present application, the gate structure 110 includes a gate oxide layer 111 located on the surface of the semiconductor substrate 100 and a gate layer 112 located on the gate oxide layer 111.

[0045] refer to Figure 3 A gate oxide material layer 111 a and a gate material layer 112 a are sequentially formed on the semiconductor substrate 100 in the first region 101 and the second region 102 .

[0046] In some embodiments of the present application, a method of forming the gate oxide material layer 111 a and the gate material layer 112 a includes a chemical vapor deposition process or a high-temperature diffusion process.

[0047] In some embodiments of the present application, the gate oxide material layer 111 a is made of silicon oxide.

[0048] In some embodiments of the present application, the gate material layer 112 a is made of polysilicon.

[0049] refer to Figure 4 The gate oxide material layer 111 a and the gate material layer 112 a are etched to form a gate layer 112 and a gate oxide layer 111 . The gate structure 110 includes the gate oxide layer 111 and the gate layer 112 .

[0050] In some embodiments of the present application, a method of etching the gate oxide material layer 111 a and the gate material layer 112 a includes wet etching or dry etching.

[0051] refer to Figure 5 , a first spacer 120 is formed on the sidewall of the gate structure 110 . The first spacer 120 can protect the gate structure 110 .

[0052] In some embodiments of the present application, the method of forming the first sidewall spacer 120 includes: forming a first sidewall spacer material layer on the surface of the semiconductor substrate 100, the surface of the isolation structure 103 and the surface of the gate structure 110; and etching the first sidewall spacer material layer to form the first sidewall spacer 120.

[0053] refer to Figures 6 to 11 , forming the second spacer 123 and forming a source 130 and a drain 140 in the semiconductor substrate 100 in the second region 102 .

[0054] refer to Figure 6 A fifth mask layer 155 is formed on the semiconductor substrate in the first region 101 , and a first ion implantation is performed on the semiconductor substrate 100 on both sides of the gate structure 110 in the second region 102 to form a lightly doped source 131 and a lightly doped drain 141 .

[0055] In some embodiments of the present application, the concentration of the first ion implantation is 2E13-2E15 atom / cm 3 .

[0056] In some embodiments of the present application, the energy of the first ion implantation is 2-5 keV.

[0057] refer to Figure 7 , remove the fifth mask layer 155.

[0058] refer to Figure 8 A second spacer 123 is formed on the sidewall of the first spacer 120. The second spacer 123 can further protect the gate structure 110 and increase the distance between the subsequently formed heavily doped source and heavily doped drain and the channel.

[0059] In some embodiments of the present application, the second spacer 123 includes a portion of a silicon oxide layer 121 located on the sidewalls of the first spacer 120 and a silicon nitride layer 122 located on the sidewalls of the portion of the silicon oxide layer 121. The remaining silicon oxide layer 121 located on the surface of the semiconductor substrate 100, the surface of the gate structure 110, and the surface of the isolation structure 103 will be removed in subsequent processes.

[0060] refer to Figure 9 A sixth mask layer 156 is formed on the semiconductor substrate in the first region 101, and a second ion implantation is performed on the semiconductor substrate 100 on both sides of the gate structure 110 in the second region 102 to form a heavily doped source 132 and a heavily doped drain 142. During the second ion implantation, the silicon oxide layer 121 on the surface of the semiconductor substrate can also serve as a shielding layer to prevent the ion implantation process from damaging the surface of the semiconductor substrate.

[0061] The lightly doped source 131 and the heavily doped source 132 together serve as the source 130 of the device in the second region 102 ; the lightly doped drain 141 and the heavily doped drain 142 together serve as the source 140 of the device in the second region 102 .

[0062] In some embodiments of the present application, the concentration of the second ion implantation is 2E13-2E16 atom / cm 3 The doping concentrations of the heavily doped source 132 and the heavily doped drain 142 are higher than those of the lightly doped source 131 and the lightly doped drain 141 . Therefore, the concentration of the second ion implantation is higher than that of the first ion implantation.

[0063] In some embodiments of the present application, the energy of the second ion implantation is 5 to 25 keV. The doping depths of the heavily doped source 132 and the heavily doped drain 142 are greater than the doping depths of the lightly doped source 131 and the lightly doped drain 141. Therefore, the depth of the second ion implantation is greater than the depth of the first ion implantation.

[0064] In some embodiments of the present application, the source 130 of the second region 102 includes a lightly doped source 131 and a heavily doped source 132 ; the drain 140 of the second region 102 includes a lightly doped drain 141 and a heavily doped drain 142 .

[0065] refer to Figure 10 , remove the sixth mask layer 156.

[0066] refer to Figure 11 , the silicon oxide layer 121 on the surface of the semiconductor substrate 100 , the surface of the gate structure 110 and the surface of the isolation structure 103 is removed, and only a portion of the silicon oxide layer is retained as the second spacer 123 .

[0067] refer to Figures 12 to 15 , a source 160 and a drain 170 are formed in the semiconductor substrate 100 in the first region 101 .

[0068] refer to Figure 12 A first mask layer 151 is formed on the semiconductor substrate 100. The first mask layer 151 exposes the semiconductor substrate on one side of the gate structure 110 on the first region 101, and a drain 170 is formed in the exposed semiconductor substrate. The method for forming the drain 170 includes an ion implantation process, etc.

[0069] refer to Figure 13 , remove the first mask layer 151.

[0070] refer to Figure 14 A second mask layer 152 is formed on the semiconductor substrate 100. The second mask layer 152 exposes the semiconductor substrate on the other side of the gate structure 110 on the first region 101, and a source electrode 160 is formed in the exposed semiconductor substrate. The method for forming the source electrode 160 includes an ion implantation process, etc.

[0071] refer to Figure 15 , remove the second mask layer 152.

[0072] The step of forming the source 160 and the drain 170 in the first region 101 is placed after the second spacer process and the first spacer process with multiple high-temperature processes, which is beneficial to reducing the thermal budget.

[0073] In some embodiments of the present application, the source 160 and drain 170 of the first region 101 (in this embodiment, the TFET region) have opposite doping types. For example, the source 160 is P-type doped, and the drain 170 is N-type doped. The doping type of the isolation region 104 is opposite to the doping type of the lightly doped substrate 100.

[0074] In some embodiments of the present application, the order of forming the source electrode 160 and the drain electrode 170 is not limited. The drain electrode 170 may be formed first and then the source electrode 160 ; or the source electrode 160 may be formed first and then the drain electrode 170 .

[0075] In some embodiments of the present application, the doping concentration of the source electrode 160 is 2E14 to 5E15 atoms / cm 3 ; The doping energy of the source is 5 to 25 keV.

[0076] In some embodiments of the present application, the doping concentration of the drain electrode 170 is 2E14 to 5E15 atoms / cm 3 ; The doping energy of the drain 170 is 5 to 25 keV.

[0077] refer to Figures 16 to 21 , remove the second sidewall spacer 123 on the side of the source 160 on the first region 101. Since the second sidewall spacer 123 blocks the source 160 and the channel, the distance between the source 160 and the channel is increased. Therefore, removing the second sidewall spacer 123 prevents the second sidewall spacer 123 from blocking the subsequent formation of the lightly doped source.

[0078] refer to Figure 16 A barrier layer 106 is formed on the surface of the semiconductor substrate 100, the surface of the first spacer 120, the surface of the second spacer 123, the surface of the gate structure 110, and the surface of the isolation structure 103. The barrier layer 106 can protect structures at other locations on the semiconductor substrate from being damaged when the second spacer 123 on the side of the source 160 in the first region 101 is subsequently etched away.

[0079] In some embodiments of the present application, a method for forming the barrier layer 106 includes a chemical vapor deposition process or a high-temperature diffusion process.

[0080] In some embodiments of the present application, the material of the barrier layer 106 includes silicon oxide.

[0081] refer to Figure 17 A third mask layer 153 is formed on the surface of the barrier layer 106 , and the third mask layer 153 exposes the barrier layer 106 on the second sidewall spacer 123 on the side of the source 160 in the first region 101 .

[0082] It should be noted that, while theoretically the third mask layer 153 only needs to expose the barrier layer 106 on the second sidewall spacer 123 on the side of the source electrode 160 in the first region 101, in actual processing, due to the small width of the second sidewall spacer 123, it is difficult to accurately form the third mask layer 153. Therefore, the third mask layer 153 may also expose a portion of the gate structure 110 and the semiconductor substrate, etc., but the opening of the third mask layer 153 should be as small as possible. However, it should be understood that although in the embodiment of the present application, the third mask layer 153 not only exposes the barrier layer 106 on the second sidewall spacer 123 on the side of the source electrode 160 in the first region 101, but also exposes a portion of the gate structure 110 and the semiconductor substrate 100, etc., this should not be considered a limitation of the technical solution of the present application. This embodiment adopts this approach only to reduce process difficulty. If process difficulty is not a consideration, the third mask layer 153 may only expose the barrier layer 106 on the second sidewall spacer 123 on the side of the source electrode 160 in the first region 101.

[0083] refer to Figure 18 The exposed barrier layer 106 is removed by etching using the third mask layer 153 as a mask, thereby exposing the second sidewall spacer 123 on the side of the source 160 in the first region 101 .

[0084] In some embodiments of the present application, the etching includes wet etching or dry etching, etc.

[0085] refer to Figure 19 , remove the third mask layer 153.

[0086] refer to Figure 20 , the silicon nitride layer 122 in the exposed second sidewall spacer 123 is etched away. The etching selectivity of the silicon nitride layer 122 is significantly different from that of the semiconductor substrate 100 and the gate structure 110, so that the exposed small portion of the semiconductor substrate 100 and the gate structure 110 will not be significantly damaged. The remaining semiconductor substrate 100 and the gate structure 110 covered by the barrier layer 106 are protected by the barrier layer 106 and will not be damaged.

[0087] In some embodiments of the present application, a method of etching and removing the exposed silicon nitride layer 122 includes wet etching or dry etching.

[0088] refer to Figure 21 , remove the barrier layer 106 and the remaining silicon oxide layer 121 in the second sidewall spacer 123. The silicon oxide layer 121 and the barrier layer 106 are made of similar materials and can be removed simultaneously in one step, thus saving process steps.

[0089] In some embodiments of the present application, the method of removing the barrier layer 106 and the silicon oxide layer 121 includes wet etching or dry etching.

[0090] refer to Figures 22 to 24 A lightly doped source 161 is formed in the exposed semiconductor substrate 110. The lightly doped source 161 is closer to the channel, while the drain 170 is still some distance away from the channel. This structure can improve the bipolar effect of the TFET device, enhance its switching capability, and reduce leakage current when the device is turned off. Furthermore, the process of removing a portion of the second sidewall spacer and then forming the lightly doped source 161 is compatible with standard CMOS processes and does not affect the performance of the MOSFET region.

[0091] refer to Figure 22 , a fourth mask layer 154 is formed on the semiconductor substrate 100 , and the fourth mask layer 154 exposes the exposed semiconductor substrate 100 .

[0092] refer to Figure 23 , a lightly doped process is performed on the exposed semiconductor substrate 100 to form the lightly doped source 161 .

[0093] In some embodiments of the present application, the doping concentration of the light doping process is 1E14 to 5E15 atom / cm 3 .

[0094] In some embodiments of the present application, the doping depth of the light doping process is 5-10 keV.

[0095] refer to Figure 24 , remove the fourth mask layer 154.

[0096] refer to Figure 25 , forming a metal silicide 180 on the surface of the semiconductor substrate 100 and the surface of the gate structure 110 .

[0097] When the metal silicide 180 is formed, the impurity segregation between the metal silicide and silicon can help to increase the concentration gradient of doped ions at the edge of the channel, thereby improving the tunneling probability and driving current of the TFET region.

[0098] refer to Figure 26 An etch stop layer 190 is formed on the surface of the metal silicide 180, the surface of the first spacer 120, the surface of the second spacer 123, and the surface of the isolation structure 103. The etch stop layer 190 is used to protect the surface of the metal silicide 180, the surface of the first spacer 120, the surface of the second spacer 123, and the surface of the isolation structure 103 from being damaged by excessive etching when trenches are subsequently etched to form contact structures.

[0099] refer to Figure 27 , forming an interlayer dielectric layer 191 on the semiconductor substrate 100 ; and forming a contact structure 192 penetrating the interlayer dielectric layer 191 and the etch stop layer 190 and electrically connected to the metal silicide 180 .

[0100] In some embodiments of the present application, the material of the interlayer dielectric layer 191 includes silicon oxide.

[0101] In some embodiments of the present application, the material of the contact structure 192 includes tungsten, cobalt, copper, etc.

[0102] In the method for forming a semiconductor structure described in the present application, the structure of the TFET device is improved so that the source boundary is closer to the channel below the gate, while the drain remains unchanged. This can improve the bipolar effect of the TFET device, enhance the switching capability of the TFET device, and reduce the leakage current when the device is turned off. After the second gate on the source side is removed, the subsequent metal silicide generation process can increase the doping concentration gradient at the edge of the TFET device channel, increase the tunneling current of the device, and thus improve the device reliability.

[0103] An embodiment of the present application also provides a semiconductor structure, comprising: a semiconductor substrate, the semiconductor substrate comprising a first region and a second region and an isolation structure isolating the first region and the second region; a gate structure, located on the semiconductor substrate in the first region and the second region; a first sidewall, located on the sidewall of the gate structure; a source and a drain, located in the semiconductor substrate on both sides of the gate structure, wherein the first region also includes a lightly doped source, the lightly doped source extends to below the first sidewall on the source side of the first region; a second sidewall, a sidewall of the first sidewall on the drain side of the first region and a sidewall of the first sidewall of the second region.

[0104] refer to Figure 27 The semiconductor substrate 100 includes a first region 101 and a second region 102 and an isolation structure 103 isolating the first region 101 from the second region 102 .

[0105] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.

[0106] In some embodiments of the present application, the isolation structure 103 is made of silicon oxide, silicon nitride, silicon oxynitride, etc. The isolation structure 103 is used to isolate active devices in the semiconductor substrate in the first region 101 and the second region 102 .

[0107] Continue to refer Figure 27 The deeper portion of the semiconductor substrate in the first region 101 is doped to form an isolation region 104, and the larger area of ​​the semiconductor substrate in the second region 102 is doped to form a well region 105. The isolation region 104 further isolates the second region 102.

[0108] In some embodiments of the present application, the first region 101 is a TFET region; the second region 102 includes a MOSFET region or a TFET region. It should be noted that in this embodiment, the second region 102 is only an MOS region as an exemplary embodiment, but this does not limit the technical solution of the present application. The doping type of the isolation region 104 and the well region 105 is not limited and can be P-type doping or N-type doping. The second region 102 can be a PMOSFET region or an NMOSFET region.

[0109] In some embodiments of the present application, the well region 105 can be a P-type well region doped with a P-type dopant (eg, boron, indium, aluminum, or gallium), or an N-type well region doped with an N-type dopant (eg, phosphorus or arsenic).

[0110] Continue to refer Figure 27 A gate structure 110 is formed on the semiconductor substrate 100 in the first region 101 and the second region 102. In some embodiments of the present application, the gate structure 110 includes a gate oxide layer 111 located on the surface of the semiconductor substrate 100 and a gate layer 112 located on the gate oxide layer 111.

[0111] In some embodiments of the present application, the material of the gate oxide layer 111 includes silicon oxide.

[0112] In some embodiments of the present application, the gate layer 112 is made of polysilicon.

[0113] Continue to refer Figure 27 A first spacer 120 is formed on the sidewall of the gate structure 110 . The first spacer 120 can protect the gate structure 110 .

[0114] Continue to refer Figure 27 A source 130 and a drain 140 are formed in the semiconductor substrate 100 in the second region 102 .

[0115] In some embodiments of the present application, the source 130 of the second region 102 includes a lightly doped source 131 and a heavily doped source 132 ; the drain 140 of the second region 102 includes a lightly doped drain 141 and a heavily doped drain 142 .

[0116] In some embodiments of the present application, the doping concentration of the lightly doped source is 2E13-2E15 atom / cm 3 The doping concentration of the lightly doped drain is 2E13 to 2E15 atom / cm 3 The doping concentration of the heavily doped source is 2E13 to 2E16 atom / cm 3 The doping concentration of the heavily doped drain is 2E13 to 2E16 atom / cm 3 The doping concentrations of the heavily doped source 132 and the heavily doped drain 142 are higher than those of the lightly doped source 131 and the lightly doped drain 141 .

[0117] In some embodiments of the present application, the doping energy of the lightly doped source is 2-5 keV, the doping energy of the lightly doped drain is 2-5 keV, the doping energy of the heavily doped source is 5-25 keV, and the doping depth of the heavily doped drain is 5-25 keV. The doping depths of the heavily doped source 132 and the heavily doped drain 142 are greater than the doping depths of the lightly doped source 131 and the lightly doped drain 141.

[0118] Continue to refer Figure 27 A source 160 and a drain 170 are formed in the semiconductor substrate 100 in the first region 101 .

[0119] In some embodiments of the present application, the source 160 and drain 170 of the first region 101 (in this embodiment, the TFET region) have opposite doping types. For example, the source 160 is P-type doped. The isolation region 104 has an opposite doping type to that of the substrate 100.

[0120] In some embodiments of the present application, the doping concentration of the source electrode 160 is 2E14 to 5E15 atoms / cm 3 ; The doping energy of the source is 5 to 25 keV.

[0121] In some embodiments of the present application, the doping concentration of the drain electrode 170 is 2E14 to 5E15 atoms / cm 3 ; The doping energy of the drain 170 is 5 to 25 keV.

[0122] Continue to refer Figure 27The first region 101 further includes a lightly doped source 161 , which extends to below the first sidewall 120 on one side of the source 160 in the first region 101 .

[0123] The lightly doped source 161 is closer to the channel, while the drain 170 is still a certain distance away from the channel. Such a structure can improve the bipolar effect of the TFET device, enhance the switching capability of the TFET device, and reduce the leakage current when the device is turned off.

[0124] In some embodiments of the present application, the doping concentration of the lightly doped source 161 is 1E14 to 5E15 atom / cm 3 .

[0125] In some embodiments of the present application, the doping energy of the lightly doped source 161 is 5-10 keV.

[0126] Continue to refer Figure 27 The second spacer 123 is located on the sidewall of the first spacer 120 on the drain 170 side of the first region 101 and the sidewall of the first spacer 120 of the second region 102. The second spacer 123 can protect the audit structure 110.

[0127] In some embodiments of the present application, the second spacer 123 includes a silicon oxide layer 121 located on a sidewall of the first spacer 120 and a silicon nitride layer located on a sidewall of the silicon oxide layer 121 .

[0128] Continue to refer Figure 27 A metal silicide 180 is formed on the surface of the semiconductor substrate 100 and the surface of the gate structure 110 .

[0129] The impurity segregation effect between the metal silicide 180 and silicon can help to increase the concentration gradient of doped ions at the edge of the channel, thereby improving the tunneling probability and driving current of the TFET region.

[0130] Continue to refer Figure 27 An etch stop layer 190 is formed on the surface of the metal silicide 180, the surface of the first spacer 120, the surface of the second spacer 123, and the surface of the isolation structure 103. The etch stop layer 190 is used to protect the surface of the metal silicide 180, the surface of the first spacer 120, the surface of the second spacer 123, and the surface of the isolation structure 103 from being damaged by excessive etching when etching to form a trench to form a contact structure.

[0131] Continue to refer Figure 27An interlayer dielectric layer 191 is formed on the semiconductor substrate 100 ; a contact structure 192 is also formed in the interlayer dielectric layer 191 and the etch stop layer 190 , penetrating the interlayer dielectric layer 191 and the etch stop layer 190 and electrically connected to the metal silicide 180 .

[0132] In some embodiments of the present application, the material of the interlayer dielectric layer 191 includes silicon oxide.

[0133] In some embodiments of the present application, the material of the contact structure 192 includes tungsten, cobalt, copper, etc.

[0134] The semiconductor structure described in the present application improves the structure of the TFET device, so that the source boundary is closer to the channel below the gate and the drain is away from the channel, which can improve the bipolar effect of the TFET device, enhance the switching capability of the TFET device, and reduce the leakage current when the device is turned off. After the second gate on the source side is removed, the subsequent metal silicide generation process can increase the doping concentration gradient at the edge of the TFET device channel, increase the tunneling current of the device, and thus improve the device reliability.

[0135] In summary, after reading the contents of this application, those skilled in the art will understand that the foregoing contents are presented by way of example only and are not intended to be limiting. Although not expressly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0136] It should be understood that the term "and / or" used in this embodiment includes any and all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present.

[0137] Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means there are no intervening elements.

[0138] It should also be understood that the terms “comprise,” “comprising,” “include,” or “including,” when used in this application document, indicate the presence of the recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0139] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present application, the first element in some embodiments may be referred to as the second element in other embodiments. The same reference numerals or the same reference designators represent the same elements throughout the specification.

[0140] In addition, this specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: A semiconductor substrate is provided, the semiconductor substrate comprising a first region and a second region and an isolation structure isolating the first region from the second region, a gate structure is formed on the semiconductor substrate in the first region and the second region, sidewalls of the gate structure are sequentially formed with a first sidewall spacer and a second sidewall spacer, a source and a drain are formed in the semiconductor substrate on both sides of the gate structure, the first region is a TFET region, and the second region comprises a MOSFET region or a TFET region; removing the second sidewall spacer on the source side of the first region to expose a portion of the semiconductor substrate, while not removing the second sidewall spacer on the drain side of the first region; A lightly doped source is formed in the exposed semiconductor substrate.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method of removing the second sidewall spacer on the source side of the first region includes: forming a blocking layer on the surface of the semiconductor substrate, the surface of the first sidewall spacer, the surface of the second sidewall spacer, the surface of the gate structure, and the surface of the isolation structure; forming a third mask layer on the surface of the blocking layer, wherein the third mask layer exposes the blocking layer on the second sidewall of the source electrode on the first region; Using the third mask layer as a mask, etching to remove the exposed barrier layer, exposing the second sidewall spacer on the source side of the first region; removing the third mask layer; Etching and removing the exposed second sidewall spacer; The barrier layer is removed.

3. The method for forming a semiconductor structure according to claim 1, wherein: The method of forming a lightly doped source in the exposed semiconductor substrate includes: forming a fourth mask layer on the semiconductor substrate, wherein the fourth mask layer exposes the exposed semiconductor substrate; A lightly doped source is formed by performing a lightly doping process on the exposed semiconductor substrate.

4. The method for forming a semiconductor structure according to claim 3, wherein: The doping concentration of the light doping process is 1E14~5E15atom / cm 3 .

5. The method for forming a semiconductor structure according to claim 3, wherein: The doping energy of the light doping process is 5-10 keV.

6. The method for forming a semiconductor structure according to claim 1, wherein: include: forming a gate structure on the semiconductor substrate in the first region and the second region; forming a first spacer on a sidewall of the gate structure; forming a second sidewall on the sidewall of the first sidewall; A source electrode and a drain electrode are formed in the semiconductor substrate on both sides of the gate structure in the first region and the second region respectively.

7. The method for forming a semiconductor structure according to claim 6, wherein: The method of forming a source and a drain in the semiconductor substrate on both sides of the gate structure in the first region includes: forming a first mask layer on the semiconductor substrate, wherein the first mask layer exposes the semiconductor substrate on one side of the gate structure on the first region; forming a drain in the exposed semiconductor substrate; removing the first mask layer; forming a second mask layer on the semiconductor substrate, wherein the second mask layer exposes the semiconductor substrate on the other side of the gate structure on the first region; forming a source electrode in the exposed semiconductor substrate; The second mask layer is removed.

8. The method for forming a semiconductor structure according to claim 6, wherein: The source of the second region includes a lightly doped source and a heavily doped source; the drain of the second region includes a lightly doped drain and a heavily doped drain.

9. The method for forming a semiconductor structure according to claim 8, wherein: The method of forming the second spacer and forming a source and a drain in the semiconductor substrate in the second region includes: forming a fifth mask layer on the semiconductor substrate in the first region; Performing a first ion implantation on the semiconductor substrate at both sides of the gate structure in the second region to form a lightly doped source and a lightly doped drain; removing the fifth mask layer; forming a second sidewall on a sidewall of the first sidewall; forming a sixth mask layer on the semiconductor substrate in the first region; Performing a second ion implantation on the semiconductor substrate at both sides of the gate structure in the second region to form a heavily doped source and a heavily doped drain; The sixth mask layer is removed.

10. The method for forming a semiconductor structure according to claim 9, wherein: The concentration of the first ion implantation is 2E13-2E15 atom / cm 3 The concentration of the second ion implantation is 2E13~2E16atom / cm 3 .

11. The method for forming a semiconductor structure according to claim 9, wherein: The energy of the first ion implantation is 2-5 keV; the energy of the second ion implantation is 5-25 keV.

12. The method for forming a semiconductor structure according to claim 1, wherein: The source and drain of the TFET region have opposite doping types.

13. The method for forming a semiconductor structure according to claim 1, wherein: The gate structure includes a gate oxide layer located on the surface of the semiconductor substrate and a gate layer located on the gate oxide layer.

14. A semiconductor structure, characterized in that include: A semiconductor substrate comprising a first region and a second region and an isolation structure isolating the first region from the second region, wherein the first region is a TFET region; and the second region comprises a MOSFET region or a TFET region; a gate structure located on the semiconductor substrate in the first region and the second region; A first spacer, located on a sidewall of the gate structure; A source and a drain are located in the semiconductor substrate on both sides of the gate structure, wherein the first region further includes a lightly doped source, and the lightly doped source extends below the first sidewall spacer on the source side of the first region; The second sidewall spacer is located on the drain side of the first region and the first sidewall spacer of the second region. The source side of the first region does not include the second sidewall spacer.

15. The semiconductor structure according to claim 14, wherein: The doping concentration of the lightly doped source is 1E14-5E15 atom / cm 3 .

16. The semiconductor structure according to claim 14, wherein: The doping energy of the lightly doped source is 5-10 keV.

17. The semiconductor structure according to claim 14, wherein: The source of the second region includes a lightly doped source and a heavily doped source; the drain of the second region includes a lightly doped drain and a heavily doped drain.

18. The semiconductor structure according to claim 17, wherein: The doping concentration of the lightly doped source is 2E13-2E15 atom / cm 3 The doping concentration of the lightly doped drain is 2E13 to 2E15 atom / cm 3 The doping concentration of the heavily doped source is 2E13~2E16atom / cm 3 The doping concentration of the heavily doped drain is 2E13 to 2E16 atom / cm 3 .

19. The semiconductor structure according to claim 17, wherein: The doping energy of the lightly doped source is 2-5 keV, and the doping energy of the lightly doped drain is 2-5 keV; the doping energy of the heavily doped source is 5-25 keV, and the doping energy of the heavily doped drain is 5-25 keV.

20. The semiconductor structure according to claim 14, wherein The source and drain of the TFET region have opposite doping types.

21. The semiconductor structure according to claim 14, wherein The gate structure includes a gate oxide layer located on the surface of the semiconductor substrate and a gate layer located on the gate oxide layer.

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