Balanced memory access

Abstract

The present application relates to balancing memory portion access. Some memory structures are designed to accelerate memory access using a scheme that relies at least in part on memory access requests being roughly evenly distributed across multiple memory portions of the memory. Examples of such memory portions include cache groups of cache memory and memory banks of multi-bank memory. However, some codes may execute in a manner that concentrates memory accesses on subsets of the total memory portion, which may reduce memory responsiveness in these memory types. To illustrate such behavior, the described technology can shuffle memory addresses based on a shuffle map to produce shuffled memory addresses. The shuffle map can be determined based on a count of reference bit values ​​that appear at the bit positions of the memory address. Using shuffled memory addresses for memory requests can substantially balance accesses on memory portions.

Description

Technical Field

[0001] The present application relates to balancing memory portion accesses. Background Art

[0002] A computer may have a processor that runs faster than the computer's memory. Because of this speed difference, the faster processor waits to receive requested data from the slower memory. This waiting prevents the processor from providing services to the user, such as playing a video or updating the appearance of a document. The waiting may cause the computer to run so slowly that the computer appears to be frozen, which frustrates the user. In addition, this speed difference hinders the growth of computer features and applications because adding new applications and features would degrade the computer's performance, so software designers would not do so. Summary of the invention

[0003] In one aspect, the present application provides a device comprising: a memory address circuit system, the memory address circuit system being configured to provide a plurality of memory addresses; a bit counter array, the bit counter array being coupled to the memory address circuit system, the bit counter array being configured to track at least one bit count value corresponding to at least one bit position on the plurality of memory addresses; control logic, the control logic being coupled to the bit counter array, the control logic being configured to determine a shuffle map based on the at least one bit count value; and a shuffle circuit, the shuffle circuit being coupled to the memory address circuit system and the control logic, the shuffle circuit being configured to shuffle memory addresses using the shuffle map to generate shuffled memory addresses.

[0004] In another aspect, the present application provides a method comprising: tracking bit count values ​​of multiple bit positions at multiple memory addresses; determining a shuffle map based on the tracking; shuffling memory addresses using the shuffle map to generate shuffled memory addresses; and accessing a memory using the shuffled memory addresses.

[0005] In another aspect, the present application provides an apparatus comprising: a memory address circuit system configured to provide a plurality of memory addresses; a bit counter array coupled to the memory address circuit system, the bit counter array configured to track over time a plurality of bit count values ​​corresponding to a plurality of bit positions on the plurality of memory addresses, respectively; control logic coupled to the bit counter array, the control logic configured to determine a shuffle map based on the plurality of bit count values; and an interface coupled to the control logic, the interface configured to transmit a memory command to a memory device via an interconnect, the memory command including the shuffle map and instructing the memory device to generate a shuffled memory address using the shuffle map in response to a memory address. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Devices and techniques for balancing memory portion access are described with reference to the following drawings. In all drawings, the same numerals are used to refer to similar features and components:

[0007] Figure 1 An exemplary device that can implement balanced memory portion access is shown.

[0008] Figure 1-1 Another exemplary apparatus that can implement balanced memory portion access and includes a host device and a memory device is shown.

[0009] Figure 1-2 An exemplary "discrete" implementation of a memory portion balancer is shown, which may be included in different individual devices.

[0010] Figure 1-3 An exemplary "distributed" implementation including memory portion balancers on a host device and a memory device is shown.

[0011] Figure 2-1 An exemplary memory including a plurality of selected memory portions and an exemplary memory portion balancer including memory address circuitry and a bit counter array are shown.

[0012] Figure 2-2 Exemplary memory address circuitry and an exemplary bit counter array that can track bit count values ​​are shown.

[0013] Figure 2-3 An example of a distributed memory part balancer divided into two parts is shown.

[0014] Figure 3 An exemplary method of analyzing bit count values ​​from bit positions of a plurality of memory addresses to determine a plurality of bit ratios is shown.

[0015] Figure 4-1 An exemplary implementation of balancing memory portion access in a hierarchical memory structure with cache memory, wherein a plurality of selected memory portions are implemented as a plurality of cache sets, is shown.

[0016] Figure 4-2 An exemplary implementation of balancing memory portion access in a memory architecture having a multi-bank memory, wherein a plurality of selected memory portions are implemented as a plurality of banks, is shown.

[0017] Figure 5 An exemplary flow chart describing operations performed by a memory portion balancer to determine a shuffle map for shuffling memory addresses using a plurality of bit ratios is shown.

[0018] Figure 6 An exemplary method for a device to balance access to memory portions is shown. DETAILED DESCRIPTION

[0019] Overview

[0020] Computers use processors that are communicatively coupled to memory to provide services and features. Because the processor can use data faster than some memory can accommodate, many computers use one or more schemes to accelerate memory access. Therefore, these schemes to accelerate memory access can reduce the speed difference between the processor and the memory. A scheme to accelerate memory access involves using a hierarchical memory system. Hierarchical memory can be designed to effectively balance cost and speed. Relatively fast memory is usually more expensive than relatively slow memory, so computer hardware designers try to balance their relative costs and benefits. One method is to use a small amount of faster, more expensive memory while using a large amount of slower, cheaper memory. In a hierarchical memory system, faster memory is deployed at a higher level than slower memory, so that the faster memory is preferably accessed by the processor first. An example of relatively fast memory is called cache memory. Although a hierarchical memory system based on cache can accelerate memory access, such a scheme may not provide the expected results in some computing environments.

[0021] In general, schemes for accelerating memory access can involve hardware structures of various designs. As described above, one exemplary design involves a hierarchical memory system with a relatively fast cache memory and a relatively slow main memory. Another design involves dividing the main memory into multiple memory banks, each of which can be accessed in parallel, which is faster than sequential access to the memory banks. If the code (e.g., an application, program, or routine) executed by the processor runs in a certain way, then these designs can accelerate memory access. On the other hand, if the code does not run in the expected manner, then these schemes will not accelerate memory access to a great extent, or they may not even accelerate memory access.

[0022] To address these situations, this document describes devices and techniques that can compensate when code does not behave in an expected manner. By employing the described compensation techniques, various designed memory access schemes can be successfully applied to different types of executable code. As described in this article, accesses to various memory portions can be balanced by shuffling memory address bits. This balancing of memory portion accesses can promote memory access acceleration under different types of executable code.

[0023] This document describes various techniques, including those involving cache-based hierarchical memory schemes or banked-memory schemes. With a cache-based hierarchical memory scheme, a memory structure includes cache memory at a higher memory level and main memory at a lower level. A subset of data stored in the main memory is temporarily copied to the cache memory for faster access. If the data targeted by the memory access request exists in the cache memory, there is a cache hit, and the memory system can return the target data from the cache memory to the requesting processor more quickly. Conversely, if the data targeted by the memory access request does not yet appear in the cache memory, there is a cache miss. In the case of a cache miss, the memory system retrieves the target data from the main memory more slowly and then provides it to the requesting processor. Therefore, schemes for accelerating memory access using cache memory are more effective when more frequently requested data exists in the cache memory.

[0024] One way to increase the likelihood that the requested data is present in the cache memory is to increase the size of the cache memory. However, larger cache memory increases costs. Another way to increase cache hits is to improve the utilization of a given cache size. In other words, if parts of the cache are not being used due to some properties of the code currently being executed, then the cache cannot speed up memory accesses as much as it could for a given cache size. For example, if 30% of the cache is not being fully utilized, then memory accesses may be significantly slower, adversely affecting overall computing performance.

[0025] Typically, a "set associative" type of cache memory can be constructed in a grid pattern using a memory array that includes rows and columns. Rows are called "sets" with set associative cache memory, and columns are called "ways". For example, in a four-way set associative cache memory, the cache memory can have thousands of sets (1000 rows), with four ways (four columns) in each set. Using some set associative cache memory structures, the memory system can move any given data segment from the main memory to a specified cache set, but not to other cache sets. In other words, there may be a one-to-one correspondence between data and the groups that are allowed to cache the data. However, unlike the set, a given data segment can be cached in any of the four ways of the specified cache set. Therefore, relative to the flexibility provided by the multi-way of the cache memory, the set portion of the cache memory can cause a bottleneck in the utilization of the cache memory.

[0026] The memory system maps or indexes data from main memory into corresponding groups based on subsets of bits in the memory address that indicate the requested data. A code segment may be executed in a loop with an address step that happens to skip some memory address ranges. If the executing code happens to request data whose memory address does not map to 40% of the cache groups, then the code leaves 40% of the cache unused. This is equivalent to having a 40% smaller cache, reducing the frequency or amount of data that the cache memory can provide in response to data requests. As a result, the executing code may exhibit behavior that significantly affects the ability of the cache structure to accelerate memory accesses. In contrast, this document describes techniques and systems that can substantially balance the utilization of groups of cache memory to increase the percentage of cache available for memory accesses during code execution.

[0027] The structure or parallel memory scheme that divides the memory into memory banks can also be applied to accelerate memory access. Here, each memory bank of the memory can be accessed in parallel, which may be faster than sequential access to the memory banks. By accessing multiple memory banks in parallel, the memory system can execute multiple memory access requests at least partially simultaneously or overlappingly, rather than serially one at a time. For example, the memory controller can organize a set of memory access requests so that those requests targeting different memory banks are sent out together without the need for other intercepted memory requests. Therefore, multiple memory banks can respond to multiple memory requests in parallel. Even if the memory controller sends memory requests sequentially, the memory response can be returned faster due to the parallel access operation because it takes longer to generate a response than to transmit a memory request or a memory response.

[0028] If a multi-bank memory has, for example, four banks, four memory access requests can be processed in parallel. If a banked memory has eight banks, the banked memory can process up to eight memory access requests in parallel. Thus, a multi-bank memory structure speeds up memory accesses, at least to some extent, depending on how many banks are included in the memory. With a fixed bank supply, if the memory controller issues more memory requests to more banks, the multi-bank memory can process more memory requests in parallel. In other words, if a subset of banks of a multi-bank memory is not used due to some unexpected properties of the code currently being executed, the multi-bank memory may not be able to speed up memory accesses as much as it would with a fixed number of banks. For example, if 25% of the banks of a multi-bank memory are not fully utilized, memory accesses may be significantly slower relative to the potential of the memory, and this slowness can have an adverse effect on computing performance.

[0029] With a multi-bank memory, the memory system maps or routes memory access requests to corresponding memory banks based on a subset of bits in the memory address that indicate the requested data. If the executing code happens to request data at a memory address that does not map to 25% of the memory banks, then 25% of the memory is unused in terms of enabling faster parallel access. This is equivalent to using only 75% of the physically present memory banks in terms of processing the memory requests in an overlapping manner. By omitting 25% of the memory banks, the executing code reduces the speed or amount of data that the multi-bank memory can provide in response to parallel data requests. The effect is increased or amplified the longer the code executes or the longer it cycles through memory addresses that exclude 25% or other portions of the memory banks. As a result, the executing code may exhibit behavior that significantly affects the ability of the banked memory structure to accelerate memory access. In contrast, the techniques and systems described in this document can substantially balance the utilization of the memory banks of a multi-bank memory to increase the percentage of memory banks that are targeted for parallel memory access.

[0030] As described above, some cache memory structures include multiple cache groups, and multi-bank memory structures include multiple banks. The degree of memory access balance across multiple cache groups can affect the performance of cache memory. Similarly, the amount of memory access balance across multiple banks can affect the performance of banked memory. As used herein, cache groups and banks are examples of different types of memory portions of a given memory structure. The described devices and techniques can increase balanced memory access across multiple memory portions to speed up memory access, including using code with different execution behaviors.

[0031] In an exemplary embodiment, a memory portion balancer can increase the amount of balanced memory requests on multiple memory portions (such as cache groups or memory banks). To this end, control logic determines a shuffle map for shuffling memory addresses to generate shuffled memory addresses. Each memory address includes multiple memory address bits or bit positions, such as 32 bit positions or 64 bit positions. Individual memory address bits can be rearranged (e.g., reordered) to adjust which address bits map to which portions of memory. Shuffled memory addresses balance memory access requests on multiple memory portions by monitoring the behavior of the executed code as evidenced by the bit values ​​of the bit positions.

[0032] In an exemplary operation, a memory portion balancer uses a bit counter array to track bit values ​​as bit value counts of bit positions on a plurality of memory addresses. The bit counter array includes a bit counter for each bit position of at least a portion of a plurality of bit positions of a memory address. Each bit counter stores a bit count value that is incremented each time a corresponding bit position in a memory address has a reference bit value (e.g., "0" or "1"). In response to the expiration of a timer or reaching a certain number of memory transactions, the control logic analyzes the bit count values ​​stored in the bit counter array. The control logic calculates a bit ratio corresponding to each bit position of the memory address based on the corresponding bit count value from the bit counter. In some cases, the control logic calculates each corresponding bit ratio based on the corresponding bit count value and the transaction count value. In such cases, a bit ratio close to 0.5 (e.g., close to 50% of the transaction count value) indicates that the corresponding memory address bit position is approximately equally likely to take a binary value of 0 or 1. In other cases, the bit ratio can be calculated based on two bit count values ​​corresponding to 0 and 1, respectively. In such cases, a balanced 50% bit ratio or fifty-fifty corresponds to 1 / 1 or 1.0. For any computation, these balanced bit positions are relatively more likely to correspond to memory requests for memory access that are distributed across substantially all available memory portions to which these bit positions are mapped.

[0033] In other words, for the currently executing code segment, the bit ratio can be used as an indicator of the degree of balance of the corresponding bit positions of the memory address over time, even if different codes exhibit different behaviors. The shuffling circuit remaps those bit positions with bit ratios indicating that are closer to the fifty-fifty split in the memory address to different bit positions in the shuffled memory address, thereby addressing those memory portions of the memory that can benefit relatively more from the balance-based access. Therefore, the memory portion balancer can remap those bit positions with bit ratios closer to the fifty-fifty split to those bits that specify the selected memory portion to accelerate memory access. As described below, the selected memory portion can include cache groups, memory banks, memory channels, etc.

[0034] For cache memory, such selected memory portions may correspond to cache groups rather than cache ways or byte offset bits. Using cache memory, memory address bits may include group bits (also referred to as index bits or group index bits) corresponding to multiple cache groups and tag bits corresponding to multiple ways per cache group. As described above, cache memory operation may be enhanced if access to each cache group is balanced across multiple cache groups. Thus, the memory portion balancer may remap those bit positions that are closer to a fifty-fifty split to group bits to speed up memory access for different types of code execution behaviors.

[0035] For multi-bank memories, the selected memory portions that can benefit from being accessed in a balanced manner correspond to banks rather than memory rows or memory columns. Using banked memories, memory address bits can include bank select bits corresponding to multiple banks, row select bits corresponding to multiple rows, and column select bits corresponding to multiple columns. As described above, if access to each bank is balanced between multiple banks, the operation of the multi-bank memory can be enhanced. Therefore, the memory portion balancer can remap those bit positions that are closer to 50% to bank select bits to speed up memory access for different types of code execution behaviors. For memories with multiple channels, the memory portion balancer can additionally or alternatively remap those bit positions that are closer to 50% to channel select bits to speed up memory access.

[0036] Therefore, the design of certain memory structures (such as cache memory and multi-bank memory) can speed up memory access. Accelerated memory access can improve computing performance by reducing the average response time of memory requests issued by relatively fast processors. The effectiveness of these structures depends in part on certain assumptions about the behavior of the code currently executed on the processor. One such assumption is that the code will access certain memory portions of the memory in roughly equal amounts. However, without this behavior, the expected acceleration of memory access may fail and even reduce the performance of the memory.

[0037] To address these issues with some memory structures, the devices and techniques described in this document can increase the frequency or likelihood of generating approximately equal accesses on selected memory portions. Such balanced accesses to memory portions can be achieved even when code is not currently executing in a manner that automatically creates such balanced behavior. Thus, hardware applying the described principles can balance memory accesses while software exhibits various modes of operating behavior. The resulting memory access acceleration enables software to run faster, thereby providing a better user experience, providing more software features, and / or less performance degradation.

[0038] Exemplary operating environment for balancing memory portion accesses

[0039] Figure 1An exemplary apparatus 100 is shown that can implement balanced memory portion access. The apparatus 100 can be implemented as, for example, at least one electronic device. Exemplary electronic device implementations include an Internet of Things (IoT) device 100-1, a tablet device 100-2, a smartphone 100-3, a notebook computer 100-4, a desktop computer 100-5, a server computer 100-6, and a server cluster 100-7 that can be part of a cloud computing infrastructure or data center. Other device examples include wearable devices, such as smart watches or smart glasses; entertainment devices, such as set-top boxes, smart TVs, or gaming devices; motherboards or blade servers; home appliances; vehicles or electronic components thereof; industrial devices, etc. Each type of electronic device includes one or more components to provide some computing functions or features.

[0040] In an exemplary embodiment, the apparatus 100 includes at least one host device 102, at least one processor 104, and at least one cache memory 106. The apparatus 100 may also include at least one memory controller 108, at least one interconnect 110, and at least one memory 112. The memory 112 may be implemented, for example, with a dynamic random access memory (DRAM) device or module, including a three-dimensional (3D) stacked DRAM device (such as a high bandwidth memory (HBM) device or a hybrid memory cube (HMC) device). Additionally or alternatively, the memory 112 may be implemented with a storage class memory device, such as a memory device using 3DXPointTM or phase change memory (PCM). Referring to FIG. 1 , the memory 112 may be implemented with a storage class memory device, such as a memory device using 3DXPointTM or phase change memory (PCM). Figure 1-1 Other examples of memory 112 are described. As shown, host device 102 or host 102 includes processor 104, cache memory 106-1, and memory controller 108. Processor 104 is coupled to cache memory 106-1, and cache memory 106-1 is coupled to memory controller 108. Processor 104 is also coupled directly or indirectly to memory controller 108. Host device 102 is coupled to cache memory 106-2 via interconnect 110. Cache memory 106-2 is coupled to memory 112. Host device 102 is also coupled directly or indirectly to memory 112.

[0041] The depicted components of device 100 represent an exemplary computing structure with a hierarchical memory system. For example, cache memory 106-1 is logically coupled between processor 104 and cache memory 106-2. Further, cache memory 106-2 is logically coupled between processor 104 and memory 112. Here, cache memory 106-1 is at a higher level in the hierarchical memory system than cache memory 106-2. Similarly, cache memory 106-2 is at a higher level in the hierarchical memory system than memory 112. The depicted interconnect 110 and other interconnects that communicatively couple various components (not shown) together enable data to be transmitted between the various components. Examples of interconnects include a bus, a switch fabric, one or more wires carrying voltage or current signals, and the like.

[0042] Despite Figure 1 Various embodiments of the device 100 are depicted in and described herein, but the device 100 may be implemented in alternative ways. For example, the host device 102 may include multiple cache memories, including multi-level cache memories. Further, at least one other cache memory and memory pair may be coupled "below" the illustrated example of the cache memory 106-2 and the memory 112. The cache memory 106-2 and the memory 112 may be implemented in various ways. In some cases, both the cache memory 106-2 and the memory 112 may be set on the motherboard or physically supported by the motherboard, wherein the memory 112 includes "main memory". In other cases, the cache memory 106-2 may include DRAM, and the memory 112 includes "storage memory" implemented as flash memory or a magnetic hard drive. Nevertheless, the components may be implemented in alternative ways, including in a distributed or shared memory system. Further, a given device 100 may include more, fewer, or different components.

[0043] Figure 1-1 Another exemplary device 101-1 is shown that can implement balanced memory portion access and includes a host device 102 and a memory device 122. In the example shown, the host device 102 is coupled to the memory device 122 via an interconnect 110. For clarity, the host device 102 is depicted as including a processor 104, a cache memory 106-1, and a memory controller 108. However, the host device 102 may include more, fewer, or different components.

[0044] The interconnect 110 may include multiple buses, such as an address bus 116 and a data bus 118. Although shown separately, the address bus 116 and the data bus 118 may share one or more electrical paths. The data bus 118 may propagate data between the host device 102 and the memory device 122. The address bus 116 may transmit at least an address from the host device 102 to the memory device 122. Although not shown, the interconnect 110 may include a command bus. Alternatively, commands may be transmitted via the address bus 116 or the data bus 118. Thus, communications related to the memory, such as commands, messages, requests, or instructions, may be transmitted on the address bus 116, the data bus 118, a command bus (not shown), or a combination thereof.

[0045] In an exemplary embodiment, memory device 122 includes cache memory 106-2, memory 112, and interface 114. Interface 114 may include circuit systems such as latches, buffers, drivers, receivers, and control logic for facilitating communication on interconnect 110. The control logic of interface 114 may operate according to at least one protocol or memory access standard. Therefore, memory device 122 may be coupled to interconnect 110 via interface 114. Cache memory 106-2 may be coupled to interface 114, and memory 112 may be coupled to interface 114 directly or through cache memory 106-2. Memory 112 may be implemented as a main memory or primary memory of a device. Alternatively, memory 112 may be implemented as a backup memory or auxiliary memory of a device.

[0046] Memory 112 can be used as a stop to handle memory requests that cannot be satisfied by cache memory 106-2. In some cases, cache memory 106-2 is formed of static random access memory (SRAM) and memory 112 is formed of DRAM. In other cases, cache memory 106-2 is formed of DRAM and memory 112 is formed of a solid-state drive (SSD) or a magnetic drive. Additionally or alternatively, cache memory 106-1 can be formed of volatile memory and memory 112 is formed of non-volatile memory. Memory 112 can also be used as a lower-level cache memory relative to cache memory 106-2 of another memory 112 (not shown). Further, memory 112 may include storage class memory.

[0047] In some embodiments, host device 102 and memory device 122 are implemented on the same integrated circuit (IC) chip, such as on a system on a chip (SoC). In other embodiments, host device 102 and memory device 122 are implemented on or as separate integrated circuit (IC) chips. In other words, host device 102 may include at least one IC chip, and memory device 122 may include at least one other IC chip. These chips may be in the same package or module, in separate packages or modules, may be mounted on the same printed circuit board (PCB), may be arranged on separate PCBs, etc. In each of these multi-chip environments, interconnect 110 may provide inter-chip coupling between host device 102 and memory device 122.

[0048] The interconnect 110 may operate according to one or more standards to enable communication with a standard-compliant memory device 122. Exemplary standards include DRAM standards promulgated by JEDEC (e.g., DDR, DDR2, DDR3, DDR4, DDR5, etc.); stacked memory standards, such as high bandwidth memory (HBM) or hybrid memory cube (HMC); peripheral component interconnect (PCI) standards, such as the peripheral component interconnect express (PCIe) standard; storage area network (SAN) standards; computer express link (CXL) standards; HyperTransport TM The interconnect 110 may include a wireless connection, such as a cellular, wireless local area network (WLAN), wireless personal area network (WPAN), or passive network standard. The memory device 122 may be implemented as a memory card that supports the host device 102 through the interconnect 110. Although only one memory device 122 is shown, a given host device 102 may be coupled to multiple memory devices 122 using one or more interconnects 110.

[0049] Figure 1-2 An exemplary "discrete" implementation of a memory portion balancer 150 is generally shown at 101-2, which may be included in different separate devices. The memory portion balancer 150 includes at least a portion of the circuitry described herein for implementing balanced memory portion accesses. Figures 2-1 to 2-3 An exemplary implementation of the memory portion balancer 150 is described. Figure 1-21, the host device 102 is depicted as having a memory portion balancer 150 coupled between the processor 104 and the cache memory 106-1. In some cases, the memory portion balancer 150 can be implemented as part of a cache controller 152-1. In the host device 102, the memory portion balancer 150 can accept a memory address from the processor 104 and provide a shuffled memory address to the cache memory 106-1 to balance the memory portion accesses.

[0050] exist Figure 1-2 In the lower left portion of FIG. 1 , the memory device 122-1 includes a memory portion balancer 150 coupled between the interface 114 and the cache memory 106-2. The memory portion balancer 150 of the memory device 122-1 may be implemented as part of a cache controller 152-2. In the memory device 122-1, the memory portion balancer 150 may receive a memory address from the interface 114 and provide a shuffled memory address to the cache memory 106-2.

[0051] exist Figure 1-2 In the lower right portion of FIG. 1 , the memory device 122-2 includes a memory portion balancer 150 coupled between the interface 114 and the memory 112. In the memory device 122-2, the memory portion balancer 150 can receive a memory address from the interface 114 and provide a shuffled memory address to the memory 112. Figure 1-2 A specific component arrangement is depicted in FIG. 1 , but the device may be implemented in alternative ways. For example, the memory portion balancer 150 may be coupled between the cache memory 106-2 and the memory 112 of the memory device 122. In addition to the above reference Figure 1-2 In addition to or as an alternative to the described "discrete" implementation, a "distributed" implementation of the memory portion balancer 150 is described next.

[0052] Figure 1-3An exemplary "distributed" implementation of a memory portion balancer 150 included between a host device 102 and a memory device 122 is shown generally at 101-3. In this example, the memory portion balancer 150 is divided into a first memory portion balancer portion 150-1 (or the first portion 150-1 of the memory portion balancer 150) and a second memory portion balancer portion 150-2 (or the second portion 150-2 of the memory portion balancer 150). The host device 102 includes the first memory portion balancer portion 150-1, and the memory device 122 includes the second memory portion balancer portion 150-2. As shown, the first memory portion balancer portion 150-1 is coupled between the memory controller 108 and the interconnect 110. The second memory portion balancer portion 150-2 is coupled between the interface 114 and the memory 112. In other aspects, the cache memory 106-2 can be coupled between the second portion 150-2 of the memory portion balancer 150 and the memory 112. Referring to Figure 2-3 An exemplary allocation of circuits between the first memory section balancer section 150 - 1 and the second memory section balancer section 150 - 2 is described.

[0053] In an exemplary operation, the host device 102 sends at least one memory command 154 to the memory device 122 via the interconnect 110. For example, the memory controller 108 or the first memory portion balancer portion 150-1 may generate the memory command 154 and send the memory command 154 via the interconnect 110. The interface 114 or the second memory portion balancer portion 150-2 receives the memory command 154 from the host device 102 via the interconnect 110. The memory command 154 may be propagated via the address bus 116, the data bus 118, the command bus, a combination thereof, etc. The memory command 154 may include or indicate a reset remap cycle instruction 156. Additionally or alternatively, the memory command 154 may include or indicate a shuffle map 158. Referring to FIG. Figure 2-1 , 2-2 3 describe an example of shuffle mapping 158. Figure 5 An example of the memory command 154 is described.

[0054] Exemplary techniques and hardware for balancing memory portion accesses

[0055] Figure 2-1An exemplary memory 202 including a plurality of selected memory portions 204-1 ... 204-M and an exemplary memory portion balancer 150 including a memory address circuit system 206 and a bit counter array 212 is generally shown at 200-1. As shown, the memory 202 includes a first selected memory portion 204-1, a second selected memory portion 204-2 ... and an "Mth" selected memory portion 204-M, where "M" represents a positive integer greater than one. The memory 202 also includes one or more other memory portions 230.

[0056] In some cases, the selected memory portion 204 and the other memory portions 230 may represent portions of addressable memory portions or portions corresponding to a segment or portion of a memory address. Thus, at least portions of the plurality of selected memory portions 204-1 ... 204-M may overlap at least portions of the other memory portions 230. For example, a given byte of the memory 202 may be a portion of the selected memory portion 204 and a portion of one of the other memory portions 230. In some cases, the plurality of selected memory portions 204-1 ... 204-M may correspond to those portions of the memory 202 that contribute to higher memory performance in response to being accessed in a substantially balanced manner. For example, in a cache-based hierarchical memory system, the plurality of selected memory portions 204-1 ... 204-M may therefore correspond to cache groups, and the other memory portions 230 may correspond to cache ways. In a multi-bank memory system, the plurality of selected memory portions 204-1 ... 204-M may therefore correspond to banks, and the other memory portions 230 may correspond to memory rows or memory columns.

[0057] In an exemplary embodiment, the memory portion balancer 150 includes a memory address circuitry 206, at least one bit counter array 212, control logic 214, at least one transaction counter 216, at least one interval register 218, at least one remap register 220, and at least one shuffle circuit 222. The memory address circuitry 206 may be implemented with at least one memory address bus 208 or at least one memory address register 210. Given this description, and as described below, the memory address circuitry 206 may also be implemented with at least one memory address bus 208 and at least one memory address register 210 based on a non-exclusive interpretation of a disjunctive “or”. The memory address circuitry 206 provides a memory address 228 from a memory address register system 210 that holds a memory address 228 or from a memory address bus 208 that propagates a memory address 228.

[0058] As shown, the memory address circuit system 206 is coupled to the shuffle circuit 222 and the bit counter array 212. The memory address circuit system 206 can provide a memory address 228 to the shuffle circuit 222 and the bit counter array 212. The bit counter array 212 includes a plurality of bit counters, such as Figure 2-2 . The bit counter array 212 accumulates a plurality of bit count values ​​238-1 ... 238-B over time based on the reference bit value and in response to the bit values ​​of the plurality of bit positions between the plurality of instances of the memory address 228. Here, the variable "B" may represent a positive integer, such as the number of bits in each memory address 228 (e.g., 32 bits or 64 bits). Alternatively, the variable "B" may correspond to a positive integer less than the number of bits in each memory address 228. Figure 2-2 Exemplary operation of the bit counter array 212 in conjunction with the memory address circuitry 206 to generate a plurality of bit count values ​​238-1 ... 238-B is described.

[0059] The control logic 214 is coupled to the bit counter array 212, the transaction counter 216, the interval register 218, and the remap register 220. The transaction counter 216 counts the number of memory transaction requests 244 in each remap cycle, which refers to a cycle in which the same shuffle map 158 is used to shuffle memory addresses. Therefore, the transaction counter 216 stores a transaction count value 242 and provides the transaction count value 242 to the control logic 214. The interval register 218 operates as a timer to set the length of each remap cycle, which can be programmable. The interval period can be set short enough to account for variations in the execution behavior of different code segments, but long enough to avoid performing the overhead of remapping (e.g., flushing the cache) too frequently.

[0060] The interval register 218 and associated circuitry may decrement the interval period until the interval period expires. At the expiration of the interval period, the interval register 218 triggers the control logic 214 with a trigger signal 246. Alternatively, instead of using a timed interval period, the interval may correspond to a set number of memory transactions, which may also be programmable. Using transaction-based intervals, the interval register 218 may issue a trigger signal 246 based on a comparison between the set number of memory transactions and the current transaction count value 242. In response to the interval register 218 activating the trigger signal 246, the control logic 214 updates the shuffle map 158.

[0061] In an exemplary operation, the control logic 214 determines the shuffle map 158 based on a plurality of bit ratios corresponding to a plurality of bit positions of the memory address 228, respectively. In response to the respective bit count values ​​238 of the plurality of bit count values ​​238-1 ... 238-B, each respective bit ratio of the plurality of bit ratios is calculated for an occurrence of a reference bit value (e.g., 0 or 1). Each respective bit ratio may also be based on a bit count value of the transaction count value 242 or an opposite reference value (e.g., 0 or 1, respectively). The reference Figure 2-2 and 3 Determining the shuffle map 158 using the plurality of bit count values ​​238 - 1 . . . 238 -B is further described. The control logic 214 provides the determined shuffle map 158 to the remap register 220 .

[0062] Thus, the remapping register 220 holds the shuffle map 158. The remapping register 220 is coupled to the shuffle circuit 222 and provides the shuffle map 158 to the shuffle circuit 222. The shuffle circuit 222 receives or accesses the memory address 228 from the memory address circuitry 206 and receives or accesses the shuffle map 158 from the remapping register 220. The shuffle map 158 includes one or more indications that map each bit position of the first or input memory address to a corresponding bit position of the second or output memory address. The shuffle circuit 222 can therefore use the shuffle map 158 to map each bit position of the memory address 228 to a corresponding bit position of the shuffled memory address 226.

[0063] The shuffle circuit 222 can couple the data bit of any given input bit position of the memory address 228 to a specified output bit position of the shuffled memory address 226. The shuffle map 158 of the remapping register 220 specifies the mapping between the input and output bit positions. The shuffle circuit 222 can be implemented using, for example, a plurality of multiplexers. In a first-level implementation, for a memory address 228 having "B" bits (where "B" represents a positive integer), a "B" 1xB multiplexer can be used. In such a case, each corresponding input bit position is coupled to each output position via a corresponding 1xB multiplexer. In such a first-level implementation based on multiplexers, the remapping register 220 is coupled to the control input of each 1xB multiplexer. In other implementations, the shuffle circuit 222 can be implemented using one or more multiplexers, one or more switches, a multi-stage shuffle network, a shuffle switch network, a single-stage or multi-stage interconnect network, a Bayesian network, a butterfly network, a network having one or more stages or layers, some combination thereof, and the like.

[0064] As described herein, the shuffling of the memory addresses 228 according to the shuffle map 158 enables those bit positions of the memory addresses 228 having bit values ​​that are closer to a fifty-fifty split to be assigned or mapped to those bit positions of the shuffled memory addresses 226 that correspond to or address a plurality of selected memory portions 204-1 ... 204-M of the memory 202. These bit positions are referred to herein as selected memory portion bits 224. Thus, the shuffled memory addresses 226 include selected memory portion bits 224 that address or correspond to a plurality of selected memory portions 204-1 ... 204-M. Figure 3 An exemplary method of determining the shuffle map 158 using the plurality of bit count values ​​238-1 . . . 238-B is described and next referred to Figure 2-2 An exemplary method of tracking a plurality of bit count values ​​238-1 ... 238-B is described.

[0065] Figure 2-2 An exemplary memory address circuitry 206 and an exemplary bit counter array 212 that can track bit count values ​​are generally shown at 200-2. The memory address circuitry 206 includes a first bit position 236-1, a second bit position 236-2, ..., and a "Bth" bit position 236-B. The "B" variable represents a positive integer that can be equal to or less than the number of bits in the memory address 228 provided by the memory address circuitry 206. Each corresponding bit position 236 provides a corresponding bit value 234 for the memory address 228. More specifically, the memory address 228 includes a first bit value 234-1 from the first bit position 236-1, a second bit value 234-2 from the second bit position 236-2, ..., and a "Bth" bit value 234-B from the "Bth" bit position 236-B. Therefore, the plurality of bit positions 236-1 ... 236-B provide a plurality of bit values ​​234-1 ... 234-B to the bit counter array 212, respectively. These multiple bit values ​​234 - 1 . . . 234 -B may be provided for each memory address 228 over time at the multiple memory addresses 228 , such as during each remapping cycle.

[0066] In an exemplary embodiment, the bit counter array 212 can track at least one bit count value 238 corresponding to at least one bit position 236 on a plurality of memory addresses 228 over time. To perform this tracking, the bit counter array 212 includes a plurality of bit counters 232-1 ... 232-B. Each respective bit counter 232 accumulates a respective bit count value 238. More specifically, the first bit counter 232-1 tracks the first bit count value 238-1, the second bit counter 232-2 tracks the second bit count value 238-2 ... the "Bth" bit counter 232-B tracks the "Bth" bit count value 238-B. In operation, each respective bit counter 232 can increment the respective bit count value 238 in response to the respective bit value 234 and based on the reference bit value. For example, if the reference bit value is "1", then each time the bit value 234 of the corresponding bit position 236 of the memory address 228 is "1", the given bit counter 232 increments.

[0067] Thus, each bit count value 238 in the plurality of bit count values ​​238-1 . . . 238-B represents how many times one of the two binary bit values ​​has occurred in the current remapping cycle. Figure 2-1 and 3 The transaction count value) is used to calculate a plurality of bit ratios using the plurality of bit count values ​​238-1 ... 238-B. The bit ratios may be used to determine the shuffle map 158 by sorting the plurality of bit ratios. Figure 3 This bit rate ordering and shuffle mapping determination is described. First, however, a distributed implementation of the memory portion balancer 150 is described next.

[0068] Figure 2-3 An exemplary distributed memory portion balancer 150 is generally shown at 200-3 as being divided into two portions 150-1 and 150-2. Figure 1-3 , a first portion 150-1 of the memory portion balancer 150 may be included as part of the host device 102, and a second portion 150-2 of the memory portion balancer 150 may be included as part of the memory device 122. The first portion 150-1 includes a memory address circuitry 206, a bit counter array 212, control logic 214, a transaction counter 216, and an interval register 218. The first portion 150-1 of the memory portion balancer 150 may also include an interface 248 for coupling to the interconnect 110. The interface 248 may alternatively be a separate portion of the host device 102.

[0069] The second portion 150-2 of the memory portion balancer 150 includes a remapping register 220 and a shuffle circuit 222. The first portion 150-1 transmits the shuffle map 158 to the remapping register 220 of the second portion 150-2 via the interface 248 and through the interconnect 110. The first portion 150-1 also transmits a memory address 228 to the shuffle circuit 222 of the second portion 150-2 using the interface 248 and the interconnect 110. Using the received shuffle map 158 stored at the remapping register 220, the shuffle circuit 222 can generate a shuffled memory address 226 from the received memory address 228. The memory device 122 then uses the shuffled memory address 226 to access the memory 202.

[0070] Figure 3 236 (e.g., Figure 2-2 ) is an exemplary method 300 for determining a plurality of bit ratios 302 based on a bit count value 238 tracked over time. In an exemplary embodiment, a bit value relationship 304 is proposed for the bit ratios 302. The illustrated bit ratios 302 are based on corresponding bit count values ​​238 and transaction count values ​​242. For example, for a given bit position 236, the bit ratio 302 may be calculated by dividing the corresponding bit count value 238 by the transaction count value 242. More generally, for corresponding bit positions 236 of a plurality of bit positions 236-1 ... 236-B, corresponding corresponding bit ratios 302 of a plurality of bit ratios 302-1 ... 302-B may be calculated by dividing the corresponding bit count values ​​238 of a plurality of bit count values ​​238-1 ... 238-B by the transaction count value 242. The plurality of bit ratios 302 are then sorted relative to a reference bit ratio, as shown in a chart 310.

[0071] Graph 310 includes an abscissa axis 308 ("x" axis) corresponding to the distance from the 0.5 reference bit ratio and an ordinate axis 306 ("y" axis) corresponding to the calculated bit ratio 302 for each corresponding bit position 236. The ordinate axis 306 extends from 0 to 1.00, with indicators explicitly depicted as 0.25, 0.50, and 0.75. The abscissa axis 308 includes "B" entries for "B" bit ratios 302-1 ... 302-B. The first bit ratio 302-1, the second bit ratio 302-2 ... "M" bit ratio 302-M, the (M+1)th bit ratio 302-(M+1), the (M+2)th bit ratio 302(M+2) ... and the "B" bit ratio 302-B are explicitly shown.

[0072] In the example represented by the graph 310, the bit ratio 302 is calculated based on the corresponding bit count value 238 and the transaction count value 242, as shown in the example bit value relationship 304. Here, the bit ratio 302 therefore represents the percentage of the total examples that the reference bit value appears on those total memory transactions. In order to provide a fifty-fifty split between the two binary values ​​of "0" and "1", thereby balancing the memory access between two or more memory portions, in this case, the reference bit ratio is 0.5. The bit ratios 302-1...302-B are therefore sorted by being close to 0.5. In other words, those bit ratios 302 that are relatively closer to 0.5 are sorted together. In the graph 310, these higher-ranked bit ratios 302 are depicted as being closer to the left vertical axis 306. It should be understood that, at least in this case, the first bit ratio 302-1 and the second bit ratio 302-2 do not necessarily correspond to ( Figure 2-2 ) first bit position 236-1 and second bit position 236-2 unless these two bit positions happen to have the bit value 234 that is closest to 50-50 within a given remapping cycle.

[0073] ( Figure 2-1 204-M are addressed by and correspond to the selected memory portion bits 224, which are also shown in the diagram 310. As shown in the diagram 310, the other memory portions 230 (also Figure 2-1 ) is addressed by and corresponds to other memory portion bits 312. Line 314 provides a demarcation between two bit subgroups. In the case of "M" memory portions of a plurality of selected memory portions 204-1 ... 204-M, there are "M" bits 302-1 ... 302-M allocated to selected memory portion bits 224. There may be up to "BM" bits allocated to other memory portion bits 312.

[0074] Each corresponding bit ratio 302 in the plurality of bit ratios 302-1 ... 302-B represents or corresponds to a corresponding bit position 236 in the plurality of bit positions 236-1 ... 236-B for each memory address 228 (although not necessarily in the same order as described above). Thus, the ordering of the plurality of bit ratios 302-1 ... 302-B also orders the plurality of bit positions 236-1 ... 236-B for assignment to remapping of memory address bit positions. In other words, the plurality of bit ratios 302 are ordered to produce an ordering of corresponding bit positions in the plurality of bit positions 236 for each memory address 228. In a cache memory implementation, the higher-ordered, selected memory address bit positions may correspond to a cache set of the cache memory. In a multi-bank memory implementation, the higher-ordered, selected memory address bit positions may correspond to a bank of the multi-bank memory.

[0075] In the exemplary method 300 depicted above, each respective bit ratio 302 of the plurality of bit ratios 302-1 ... 302-B is calculated based on the transaction count value 242 and the respective bit count value 238 of the respective bit positions 236 of the plurality of bit positions 236-1 ... 236-B of each memory address 228. In general, each respective bit ratio 302 of the plurality of bit ratios 302-1 ... 302-B is based on a comparison of a relative number of occurrences of a reference bit value (e.g., 1 or 0) over time at the plurality of memory addresses 228 and an opposite reference bit value (e.g., 0 or 1, respectively) at each respective bit position 236 of the plurality of bit positions 236-1 ... 236-B of each memory address 228. Thus, instead of being calculated based on the transaction count value 242, the relative number of occurrences of the binary bit values ​​may be calculated using an alternative method.

[0076] In an exemplary alternative approach, each bit ratio 302 is calculated based on a bit count value 238 corresponding to a reference bit value and another bit count value corresponding to a relative bit value. Thus, each corresponding bit ratio 302 can be calculated by dividing the corresponding bit count value 238 of the reference bit value (e.g., "1") by another bit count value (not shown) of the relative bit value (e.g., "0"). In this case, a fifty-fifty split of binary values ​​that achieves balanced memory access is represented by and corresponds to a 1:1 or 1.0 bit ratio. Using this alternative approach, the reference bit ratio for sorting the bit ratios based on proximity is therefore 1.0. In other words, those bit ratios 302-1 ... 302-M that are closest to 1.0 can be assigned to the selected memory portion bit 224 on the left side of the line 314. The corresponding other bit count values ​​for each corresponding bit ratio 302 can be obtained by including a corresponding second bit counter in the bit counter array for each corresponding bit position 236 or by subtracting the corresponding bit count value 238 from the transaction count value 242.

[0077] Figure 4-1 An exemplary implementation 400-1 of balancing memory portion access in a hierarchical memory structure with a cache memory 202a is shown, wherein a plurality of selected memory portions are implemented as a plurality of cache groups 204a-1 ... 204a-M. More specifically, the cache memory 202a includes a first cache group 204a-1, a second cache group 204a-2 ... an "Mth" cache group 204a-M. The cache memory 202a also includes a plurality of cache ways, including a first cache way 404-1 and a second cache way 404-2 for a two-way set associative cache memory example. However, the cache memory 202a may have a different number of cache ways.

[0078] As shown in this example, each cache group 204 includes two cache lines, one cache line for each cache way 404. Each cache line includes data and an associated tag that stores tag bits for the corresponding cache data. Each cache line may also include one or more status or flag bits, such as a valid bit (V) or a modified bit (D). The cache memory 202a also includes or is associated with a comparator 402 for each cache way 404 to determine a hit or miss (for a hit / miss signal) in the corresponding cache way 404 of the indexed cache group 204.

[0079] Also refer to Figure 2-1 , for this exemplary cache memory implementation 400-1, memory 202 corresponds to cache memory 202a. The plurality of selected memory portions 204-1...204-M corresponds to the plurality of cache sets 204a-1...204a-M. Thus, the shuffled memory address 226a ( Figure 2-1 and 3 ) corresponds to the group bit 224a (or group index bit 224a). The other memory portions 230 may correspond to the plurality of cache ways 404-1 and 404-2. Figure 3 The other memory portion bits 312 may correspond to the tag bits 312a. Although not shown, the other memory portion bits 312 may also correspond to additional memory address bits, such as byte offset bits. Figure 2-2 Thus, as described herein, implementing the memory portion balancer 150 in conjunction with the cache memory 202a can balance memory accesses across the plurality of cache groups 204a-1 ... 204a-M to speed up access to the cache memory 202a by facilitating use of a greater percentage of the cache groups.

[0080] Figure 4-2 An exemplary embodiment 400-2 of balancing memory portion access in an associative memory structure with a multi-bank memory 202b is shown, wherein a plurality of selected memory portions are implemented as a plurality of banks 204b-1 ... 204b-M. More specifically, the multi-bank memory 202b includes a first bank 204b-1, a second bank 204b-2 ... and an "Mth" bank 204b-M. Although not explicitly shown, the multi-bank memory 202b may also include a plurality of rows and columns in a memory array. The multi-bank memory 202b may, for example, contain at least a portion of a primary memory or an auxiliary memory of a computing device.

[0081] Also refer to Figure 2-1For this exemplary associative memory implementation 400-2, the memory 202 corresponds to a multi-bank memory 202b. The plurality of selected memory portions 204-1...204-M corresponds to the plurality of memory banks 204b-1...204b-M. Therefore, the shuffled memory address 226b ( Figure 2-1 and 3 The selected memory portion bit 224 corresponds to the bank select bit 224b. The other memory portions 230 may correspond to rows or columns in a given bank, or rows or columns extending across two or more banks. Figure 3 ) other memory portion bits 312 may correspond to row select bits 312b-1 or column select bits 312b-2. Although not shown, other memory portion bits 312 may also correspond to additional memory address bits, such as channel select bits. Alternatively, the channel select bits may be incorporated into the selected memory portion bits 224 (e.g., replacing or adding the bank select bits 224b) to balance access to multiple channels of the memory. Therefore, as described herein, implementing the memory portion balancer 150 in conjunction with the multi-bank memory 202b may balance memory accesses on multiple banks 204b-1...204b-M to accelerate access to the multi-bank memory 202b by facilitating parallel access to the banks.

[0082] Exemplary method for balancing access to memory portions

[0083] refer to Figure 5 6 and 7, exemplary methods are described in this section. These descriptions are for example only with reference to Figures 1 to 4-2 The components, entities and other aspects depicted in. Figure 5 An exemplary flow chart 500 is shown that depicts operations performed by a device including a memory portion balancer 150 that uses a plurality of bit ratios to determine a shuffle map for shuffling memory addresses. The flow chart 500 includes thirteen blocks 502 to 524. At 502, an interval timer is started at the interval register 218. At 504, the memory portion balancer 150 determines whether a new memory transaction has been requested, for example, from a processor or host. If not, the flow chart continues at 514 as described below.

[0084] On the other hand, if it is determined at 504 that a new memory transaction has been requested, then at 506, the transaction count value 242 is incremented at the transaction counter 216, e.g., in response to the memory transaction request 244. At 508, the memory address 228 is obtained from the memory address circuitry 206. At 510, the memory portion balancer 150 updates the bit counter array 212 based on the memory address 228. At 510-1, the corresponding bit counter 232 may be incremented in response to the reference bit value appearing at the corresponding corresponding bit position 236 of the memory address 228. The incrementation of the corresponding bit counter 232 enables the corresponding bit count value 238 to be tracked, as described above with reference to FIG. Figure 2-2 described.

[0085] At 512, the shuffle circuit 222 shuffles the bits of the memory address 228 using the shuffle map 158 held by the remap register 220 to produce a shuffled memory address 226. The memory section balancer 150 provides the shuffled memory address 226 to the memory 202 so that the memory transaction request 244 can be processed by executing a memory transaction. At 514, the memory section balancer 150 determines whether the interval timer of the interval register 218 has expired. If not, the process returns to 504 to determine whether a new memory transaction request has been issued. If the interval timer has expired, the process continues at 516 to prepare for a new remap cycle.

[0086] At 516, the control logic 214 calculates a corresponding bit ratio 302 for each memory address bit position 236 based on the corresponding bit count value 238. The calculation may also be based on the transaction count value 242. At 518, the control logic 214 sorts the plurality of bit ratios 302-1 ... 302-B based on proximity to a reference bit ratio. The reference bit ratio may correspond to, for example, 0.5 or 1.0, depending on how each bit ratio is calculated, as described above with reference to Figure 3 The sorting may identify those bit ratios, and therefore those bit positions, that currently have a more balanced distribution (eg, approximately 50-50 bit values) among the concurrently executing code.

[0087] At 520, the control logic 214 assigns at least some of the memory address bit positions 236-1...236-B based on the ordering of the corresponding bit ratios 302-1...302-B, as described above with reference to Figure 3As described. The memory address bit positions 236-1 ... 236-B of the input memory address 228 may also be assigned to the bit positions of the output shuffled memory address 226 based on the number "M" of the plurality of selected memory portions 204-1 ... 204-M (e.g., "M" indicates how many address bits are related) and the bit positions of these selected memory portions of the addressing memory 202. Thus, those bit ratios that indicate that a given bit position has a balanced distribution of 0s and 1s may be assigned to those bit positions, i.e., those bits that enable the plurality of selected memory portions 204-1 ... 204-M to be accessed in a substantially balanced manner, at least relative to the other memory portions 230 of the memory 202. Using this analysis and these factors, the control logic 214 may determine at 522 an updated shuffle map 158 based on the memory address bit assignments derived from the ordering of the plurality of bit ratios 302-1 ... 302-B.

[0088] Before activating the updated shuffle map 158 (e.g., before storing the shuffle map 158 in the remapping register 220 or at least before the shuffle circuit 222 uses the updated shuffle map 158), the memory 202 may perform one or more actions to prepare or reset for the next remapping cycle. Typically, the memory 202 may clear a backlog or queue of existing memory requests before starting a new remapping cycle with a different shuffle map 158.

[0089] For example, for an embodiment of the cache memory 202a, receiving the reset remap cycle instruction 156 can trigger the execution of one or more of the following example actions. First, the cache memory 202a pauses and completes any pending cache requests. Second, the cache is flushed and each line is invalidated. Third, the remap register 220 is reprogrammed with the updated shuffle map 158, which can provide a new mapping of the host physical address bit positions to those address bit positions that are routed to the cache set bits and cache tag bits. Fourth, the memory portion balancer 150 can reset the transaction counter 216 (e.g., to zero), can reset the interval register 218 (e.g., to the currently programmed timer period), and can reset the plurality of bit counters 232-1...232-B (e.g., to zero).

[0090] These remap cycle reset operations may be initiated at any time after the positive determination of 514, and the associated actions may be completed prior to initiating the operation of 524. As indicated at 524, shuffling of the memory address bits by the shuffle circuit 222 may begin with an updated remap register 220 having an updated shuffle map 158 during the next interval cycle.

[0091] Figure 6An exemplary method of implementing balanced memory portion access by a device is illustrated by flowchart diagram 600. Flowchart diagram 600 includes four blocks 602 to 608. In an exemplary embodiment, at least a portion of device 100 may perform the operations of flowchart diagram 600.

[0092] At block 602, bit count values ​​for a plurality of bit positions are tracked across a plurality of memory addresses. For example, the memory portion balancer 150 may track bit count values ​​238-1 ... 238-B for a plurality of bit positions 236-1 ... 236-B across a plurality of memory addresses 228. For example, a corresponding bit counter 232-1 ... 232-B of the bit counter array 212 may be incremented in response to a reference bit value present at each of the corresponding bit positions 236-1 ... 236-B, such that the bit counter array 212 is counting occurrences of a given bit value (e.g., "1") at each memory bit address. Thus, the bit count values ​​238 may be accumulated across the plurality of memory addresses 228 over time.

[0093] At block 604, a shuffle map is determined based on the tracking. For example, the memory portion balancer 150 may determine the shuffle map 158 based on the tracking. To do this, the control logic 214 may sort the bit ratios 302 corresponding to the bit count values ​​238 based on closeness to a reference bit ratio (such as 0.5 or 1.0). Those bit ratios 302 that are relatively closer to the reference bit ratio may be assigned to memory address bit positions that address the selected memory portions 204 that are relatively more sensitive to being accessed in a balanced manner. By using tracking and sorting to assign memory address bit positions, the selected memory portions 204 addressed by those assigned memory address bit positions may be accessed at more equal percentages (e.g., more balanced) relative to each other than other memory portions 230 (e.g., more unbalanced).

[0094] At block 606, the memory address is shuffled using the shuffle map to produce a shuffled memory address. For example, the memory portion balancer 150 may shuffle the memory address 228 using the shuffle map 158 to produce the shuffled memory address 226. In some cases, the bit value 234 at the input bit position 236 of the memory address 228 may be mapped to a different output bit position of the shuffled memory address 226 based on one or more mapping indications in the shuffle map 158.

[0095] At block 608, the memory is accessed using the shuffled memory address. For example, the host device 102 or the memory device 122 may access the memory 202 using the shuffled memory address 226. This may require, for example, applying at least the selected memory portion bits 224 of the shuffled memory address 226 to the selected memory portion 204 of the cache memory 202a or the multi-bank memory 202b. The memory access may include transmitting the shuffled map 158 and the memory address 228 over the interconnect 110 in a "distributed" memory portion balancer implementation, or transmitting the shuffled memory address 226 over the interconnect 110 in a "discrete" memory portion balancer implementation.

[0096] For the flowcharts and process diagrams described above, the order in which the operations are shown and / or described is not intended to be construed as limiting. Any number or combination of the process operations described may be combined or rearranged in any order to implement a given method or an alternative method. Operations may also be omitted or added from the described methods. Further, the described operations may be implemented in a completely or partially overlapping manner.

[0097] Aspects of these methods may be implemented in, for example, hardware (e.g., fixed logic circuitry or a processor in conjunction with a memory), firmware, or some combination thereof. The methods may be implemented using Figures 1 to 4-2 The devices and components in these figures generally represent hardware, such as electronic devices, package modules, IC chips, or circuits; firmware or its actions; software; or a combination thereof. Figures 1-1 to 1-3 In some cases, the host device 102 or the memory device 122 may perform the operations of these methods alone. In other cases, the host device 102 and the memory device 122 may perform the operations together. Figures 2-1 to 2-3 Exemplary circuitry of a memory portion balancer 150 that may perform at least some of these operations is shown. Figure 3 An exemplary method of bit count value analysis that may be used to determine the shuffle map 158 is shown. Figure 4-1 and 4-2 Two exemplary memory implementations are shown: a cache memory implementation and a multi-bank memory implementation. Thus, these figures illustrate some of the many possible systems or devices that can implement the described methods.

[0098] Unless the context dictates otherwise, the word "or" as used herein may be considered to be used as an "inclusive or," or to allow for the inclusion or application of a term that includes or applies one or more items connected by the word "or" (e.g., the phrase "A or B" may be interpreted as allowing only "A," only "B," or both "A" and "B"). In addition, as used herein, phrases referring to "at least one" of a list of items refer to any combination of those items, including single members. For example, "at least one of a, b, or c" may encompass a, b, c, ab, ac, bc, and abc, as well as any combination of multiples of the same elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other order of a, b, and c). Further, the items shown in the accompanying drawings and the terms discussed herein may indicate one or more items or terms, and thus single or multiple forms of the items and terms may be referenced interchangeably in this written description.

[0099] in conclusion

[0100] Although embodiments for balancing memory portion access have been described in language specific to certain features and / or methods, the subject matter of the appended claims is not necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed as exemplary embodiments for balancing memory portion access.

Claims

1. A memory device, comprising: memory address circuitry configured to provide a plurality of memory addresses; a bit counter array coupled to the memory address circuitry and comprising a plurality of bit counters, the bit counter array configured to track a plurality of bit count values ​​corresponding to a plurality of bit positions at the plurality of memory addresses, each respective bit counter of the plurality of bit counters configured to increment a respective bit count value of the plurality of bit count values ​​in response to a reference bit value at the plurality of memory addresses appearing at a respective bit position of the plurality of bit positions at each memory address; a control logic coupled to the bit counter array, the control logic configured to determine a shuffle map based on the plurality of bit count values ​​and a plurality of bit ratios, each respective bit ratio of the plurality of bit ratios being based on the respective bit count value of the respective bit counter of the plurality of bit counters of the bit counter array; as well as A shuffle circuit is coupled to the memory address circuitry and the control logic, the shuffle circuit being configured to shuffle memory addresses using the shuffle map to produce shuffled memory addresses.

2. The memory device of claim 1, wherein the control logic is configured to determine the shuffle map to substantially balance accesses to the selected memory portion of the memory.

3. The memory device of claim 2 , wherein the control logic is configured to determine the shuffle map by assigning bit positions of the plurality of memory addresses having bit values ​​balanced over time to bit positions of the shuffled memory addresses corresponding to the selected memory portion of the memory.

4. The memory device of claim 1 , further comprising: Memory; and a memory section balancer coupled to the memory; the memory section balancer comprising at least the bit counter array, the control logic and the shuffle circuit; the memory section balancer configured to generate the shuffled memory address to access the memory, wherein the memory portion balancer Included as part of a host device.

5. The memory device of claim 1 , further comprising: a cache memory, the cache memory comprising a plurality of cache groups, Wherein the control logic is configured to determine the shuffle map based on the plurality of bit count values ​​corresponding to the plurality of bit positions at the plurality of memory addresses and memory address bit positions corresponding to the plurality of cache sets.

6. The memory device of claim 1, further comprising: A multi-bank memory, the multi-bank memory comprising a plurality of banks, Wherein the control logic is configured to determine the shuffle map based on the plurality of bit count values ​​corresponding to the plurality of bit positions at the plurality of memory addresses and memory address bit positions corresponding to the plurality of memory banks.

7. The memory device of claim 1 , further comprising: Memory; and a memory portion balancer coupled to the memory; The memory section balancer includes at least the bit counter array, the control logic, and the shuffle circuit; The memory portion balancer is configured to generate the shuffled memory addresses to access the memory, Wherein the memory portion balancer is included as part of the memory device.

8. The memory device of claim 1 , wherein the control logic is configured to: ordering the plurality of bit ratios to produce an ordering of corresponding bit positions of the plurality of bit positions for each memory address; and The shuffle map is determined based on the ordering of the corresponding bit positions.

9. The memory device of claim 8, wherein the control logic is configured to rank each respective bit ratio of the plurality of bit ratios to produce the ranking of the corresponding bit positions based on respective proximity to a reference bit ratio.

10. The memory device of claim 8, wherein each respective bit ratio of the plurality of bit ratios is based on a comparison of a relative number of occurrences of the reference bit value at the plurality of memory addresses and a relative bit value at each respective bit position of the plurality of bit positions at each memory address.

11. The memory device of claim 8, further comprising: a remapping register coupled between the control logic and the shuffle circuitry, the remapping register configured to store the shuffle map; and a transaction counter coupled to the control logic, the transaction counter configured to increment a transaction count value in response to each memory transaction, Wherein the control logic is configured to calculate each corresponding bit ratio of the plurality of bit ratios based on the transaction count value and the corresponding bit count value of the corresponding bit position of the plurality of bit positions of each memory address.

12. The memory device of claim 1, further comprising: Memory; and a memory portion balancer coupled to the memory; The memory section balancer includes at least the bit counter array, the control logic, and the shuffle circuit; The memory portion balancer is configured to generate the shuffled memory addresses to access the memory, The memory portion balancer is distributed between the host device and the memory device.

13. A method for balancing access to a portion of a memory, comprising: tracking a plurality of bit count values ​​corresponding to a plurality of bit positions at a plurality of memory addresses using a plurality of bit counters; counting occurrences of a reference bit value at each bit position of the plurality of bit positions at the plurality of memory addresses using the plurality of bit counters; calculating a respective bit ratio corresponding to each respective bit position of the plurality of bit positions based on respective bit count values ​​of the plurality of bit count values ​​accumulated at the plurality of memory addresses for respective bit positions; determining a shuffle map based on the plurality of bit count values, the count of the occurrences of the reference bit value at each of the plurality of bit positions, and the respective bit ratios corresponding to each respective bit position of the plurality of bit positions; shuffling memory addresses using the shuffle map to produce shuffled memory addresses; and A memory is accessed using the shuffled memory addresses.

14. The method according to claim 13, further comprising: In response to the reference bit value occurring at a bit position of the plurality of bit positions of the memory address of the plurality of memory addresses, incrementing a bit count value of the plurality of bit count values ​​stored in a bit counter of the plurality of bit counters, the positions of the bit counters of the plurality of bit counters corresponding to the positions of the bit positions of the plurality of bit positions.

15. The method according to claim 13, further comprising: The shuffle map is determined based on which bit positions of the plurality of bit positions of the memory address correspond to set bits of a cache memory.

16. The method according to claim 13, further comprising: The respective bit ratio corresponding to each respective bit position of the plurality of bit positions is calculated based on the respective bit count values ​​of the plurality of bit count values ​​and a transaction count value.

17. The method according to claim 13, further comprising: ranking each respective bit ratio corresponding to each respective bit position of the plurality of bit positions based on a closeness of the respective bit ratio to a reference bit ratio; and The shuffle map is determined based on the ordering.

18. The method according to claim 17, further comprising: The shuffle map is determined by assigning memory address bit positions based on: The ordering of each corresponding bit ratio, a plurality of memory address bit positions corresponding to a plurality of selected memory portions, and A number of the plurality of memory address bit positions corresponding to the plurality of selected memory portions.

19. The method of claim 13, further comprising: At least one memory command including the shuffle map is transmitted from the host device to the memory device.

20. A memory device comprising: The host device includes: memory address circuitry configured to provide a plurality of memory addresses; a bit counter array coupled to the memory address circuitry and comprising a plurality of bit counters configured to track over time a plurality of bit count values ​​corresponding to a plurality of bit positions at the plurality of memory addresses, respectively; a control logic coupled to the bit counter array, the control logic configured to determine a shuffle map based on the plurality of bit count values ​​and a plurality of bit ratios, each respective bit ratio of the plurality of bit ratios being based on a respective bit count value of a respective bit counter of the plurality of bit counters of the bit counter array; as well as an interface coupled to the control logic, the interface configured to transmit at least one memory command to a memory device via the interconnect, the at least one memory command including the shuffle map and instructing the memory device to use the shuffle map to generate a shuffled memory address in response to a memory address, the at least one memory command including a reset remap cycle instruction instructing the memory device to reset a remap cycle in preparation for using an updated shuffle map.

21. The memory device of claim 20, further comprising: said interconnection; and The memory device, the memory device coupled to the interconnect and comprising a memory, a remapping register coupled to the interconnect, and a shuffle circuit coupled to the remapping register, wherein: The remap register is configured to store the shuffle map; the shuffle circuitry configured to shuffle the memory addresses using the shuffle map to produce the shuffled memory addresses; and The memory device is configured to access the memory based on the shuffled memory addresses.

Images