FeFET with high speed, high durability and low fluctuation and preparation method thereof

Abstract

The application discloses a high-speed, high-durability and low-fluctuation FeFET and a preparation method thereof, and belongs to the technical field of semiconductors. The application first forms multiple grooves by etching a high-k gate dielectric, then grows ferroelectric HZO in the grooves, and finally prepares a FeFET gate stack by chemical mechanical polishing to a specific size and annealing. The ferroelectric HZO monophase grown in each groove is high, even close to single crystal, the polarization orientation and polarization flip consistency are very high, which is conducive to improving the read-write speed of the FeFET and reducing the fluctuation between devices, and the oxide semiconductor is used as a channel, so that the existence of an interface layer can be eliminated, and the retention characteristics and durability characteristics of the FeFET are improved. The preparation process is completely compatible with the CMOS back-end process, and is expected to be mixed and integrated with a CMOS logic circuit.

Description

Technical Field

[0001] This invention belongs to the field of micro-nano electronics technology, specifically relating to a high-speed, high-durability, low-fluctuation FeFET based on a novel gate structure and its fabrication method. Background Technology

[0002] The modern era is a digital age, and the development of technologies such as the Internet of Things, biomedicine, autonomous driving, and cloud computing necessitates further improvements in data computing and storage capabilities. In the traditional von Neumann architecture, data computation and storage are separated, increasing power consumption and hindering computing power development. Realizing new low-power, high-density, and high-speed memories, and developing in-memory computing architectures based on new devices, is a crucial means to break through the "memory wall" bottleneck. Under these opportunities and challenges, various new types of memories have emerged, including ferroelectric memories (FeFET / FeRAM), resistive random access memories (RRAM), phase-change memories (PCRAM), and magnetic random access memories (MRAM). Among these, hafnium oxide-based ferroelectric memories have attracted widespread attention from academia and industry due to their advantages such as fast read / write speeds, low power consumption, high integration potential, and non-volatility, and are considered one of the most promising new memories in the post-Moore's Law era.

[0003] However, novel hafnium oxide-based ferroelectric memory also faces several challenges. First, hafnium oxide-based FeFETs exhibit low durability. This is partly due to the large coercive field and high saturation polarization of hafnium oxide-based ferroelectric materials, leading to high operating voltages. Under high voltages, charge injection and defect formation are exacerbated, resulting in degraded durability. Secondly, a low-k interface layer exists between the ferroelectric layer and the channel, exhibiting a high partial voltage, which further intensifies charge injection and defect formation, another significant factor contributing to the durability degradation of hafnium oxide-based FeFETs. Furthermore, the poor polarization reversal consistency of hafnium oxide-based ferroelectric materials limits the read / write speed of FeFETs. From a materials physics perspective, this is attributed to the uneven phase distribution of hafnium oxide-based ferroelectric materials. Hafnium oxide-based ferroelectric materials exhibit polymorphism, typically with the coexistence of m, o, and t phases, but only the o phase is the polarizing phase, contributing to ferroelectricity. These three phases are randomly distributed within the ferroelectric gate dielectric. The varying environments of the o phase grains result in significant differences in polarization reversal barriers and poor polarization reversal consistency, limiting the read / write speed of hafnium oxide-based FeFETs. Furthermore, the uneven phase distribution and random domain nucleation process in ferroelectric materials also lead to significant fluctuations between hafnium oxide-based FeFET devices. Therefore, designing and implementing high-speed, high-endurance, and low-fluctuation FeFETs is particularly important and urgent. Summary of the Invention

[0004] The purpose of this invention is to propose a design and fabrication method for a high-speed, high-durability, and low-fluctuation FeFET based on a novel gate structure.

[0005] Specifically, the technical solution of the present invention is as follows:

[0006] A high-speed, high-durability, low-fluctuation FeFET mainly comprises an insulating substrate, a back gate material patterned by photolithography and etching on the substrate, a high-k gate dielectric material on the back gate material, the high-k gate dielectric material having multiple trenches, each trench having a length and width of 6nm to 18nm, ferroelectric HZO grown in the trenches, the high-k gate dielectric material having a thickness of 3 to 10nm, an oxide semiconductor channel on the high-k gate dielectric material, and source and drain contact metals on both sides above the oxide semiconductor channel.

[0007] The insulating substrate is not used as a functional layer, and the selection requirements are relatively broad, including but not limited to materials such as Si / SiO2, BN, STO, LAO, and YSZ.

[0008] Furthermore, the back gate material can be common metals such as Pt, TiN, TaN, and W, or heavily doped silicon or germanium, as well as conductive oxides such as LSMO, Nb-STO, and RuO2.

[0009] Furthermore, high-k gate dielectric materials can be selected from materials such as Al2O3, HfO2, and ZrO2.

[0010] Furthermore, oxide semiconductor channels can be made of materials such as IGZO, IWO, ITO, and ZnO2.

[0011] Furthermore, the source and drain metals should form good ohmic contacts with the oxide semiconductor to reduce contact resistance. Suitable metals include, but are not limited to, Al, Sc, Pt, Cr, Pd, Au, Ti, and other materials.

[0012] Furthermore, the thickness of the back gate material is generally 20nm to 50nm, the thickness of the oxide semiconductor channel is about 10nm to 30nm, and the thickness of the source and drain metals on the left and right sides above the channel is 30nm to 70nm.

[0013] The present invention also provides a method for preparing the above-mentioned FeFET, comprising the following steps:

[0014] (1) Back gate material is prepared on an insulating substrate by sputtering / physical vapor deposition (PVD) / atomic layer deposition (ALD) and then patterned by photolithography and etching.

[0015] (2) High-k gate dielectric material is deposited using atomic layer deposition (ALD) with a thickness of 3-10 nm;

[0016] (3) Define several square trenches using photolithography and dry etching. The length and width of the trenches are 6nm to 18nm.

[0017] (4) Ferroelectric HZO (Hf:Zr = 1:1) was grown by atomic layer deposition (ALD), and then chemical mechanical polishing (CMP) was used to form a gate structure with HZO embedded in a high-k gate dielectric.

[0018] (5) A metal stress layer is grown by atomic layer deposition (ALD) or physical vapor deposition (PVD), and the ferroelectricity of HZO is activated by rapid thermal annealing. Then, the metal stress layer is removed by wet etching.

[0019] (6) Spin-coat photoresist on the gate dielectric material, use photolithography to define the location of the active region, then grow oxide semiconductor material and strip it;

[0020] (7) The positions of the source and drain metals are defined on both sides above the oxide semiconductor material by photolithography. Then, the source and drain metals are grown and stripped by physical vapor deposition (PVD), sputtering, evaporation and other methods. The active region between the source and drain metals is the channel.

[0021] In this invention, during rapid thermal annealing, the trenches restrict the size of HZO grains, inhibiting the formation of the m-phase. However, the HZO in the trenches lacks stress from the top. The metal stress layer in step (3) above can compensate for the lack of top stress, further optimizing the single-phase nature of the HZO grains in the trenches. Therefore, the metal stress layer in step (3) above requires high uniformity of crystallographic orientation and a thermal expansion coefficient that differs significantly from that of HZO, thereby providing additional stress to restrict the growth of m-phase grains during rapid thermal annealing. Suitable metals include, but are not limited to, TiN, TaN, W, and Ru. The metal stress layer can be removed by selective etching with strong acid chemical reagents.

[0022] In the above process step (3), the annealing temperature is between 550℃ and 800℃, and the annealing time is about 30s to 120s. The combination of annealing temperature and annealing time must ensure that HZO is fully crystallized and that the O phase grains are fully grown. Therefore, if the annealing temperature is close to 550℃, the annealing time should be close to 120s, and if the annealing temperature is close to 800℃, the annealing time should be close to 30s.

[0023] The process steps of this invention are fully compatible with CMOS back-end processes, enabling the high-speed, high-durability, low-fluctuation FeFET with the novel gate structure proposed above to be integrated with CMOS logic circuits.

[0024] This invention first uses etching of a high-k gate dielectric to form square trenches, then grows ferroelectric HZO (Hf:Zr = 1:1) in the trenches, and finally prepares a FeFET gate stack by chemical mechanical polishing (CMP) to a specific size and annealing. For Zr-doped hafnium oxide-based ferroelectric thin films, although the formation of the o-phase is related to process conditions such as oxygen content, stress, and annealing temperature, the process is essentially strongly size-driven. First-principles calculations show the existence of a critical grain size C0. t When the grain size is greater than C t When the grain size is smaller than C, the proportion of the m phase in the material is the largest. t At that time, the t phase has the largest proportion in the material. For ferroelectric HZO, C t The t phase is approximately 18 nm. As a transitional phase for the formation of the o phase, the trenches of this invention limit the maximum grain size in HZO, preventing the formation of the m phase. Furthermore, rapid thermal annealing at 550℃~800℃ (the typical annealing temperature for traditional HZO is approximately 450℃) ensures sufficient grain growth, maximizing the transformation of the t phase to the o phase. The advantages of this approach are mainly:

[0025] 1) The ferroelectric HZO grown in each trench has high single-phase properties, even close to single crystal, and very high consistency in polarization orientation and polarization reversal, which is beneficial to improving the read and write speed of FeFET.

[0026] 2) The position of the square trench can be accurately defined by photolithography, so the phase distribution in the device gate stack is relatively fixed and the fluctuations between the device itself and between devices are very small;

[0027] 3) FeFETs, as storage applications, have certain requirements for polarization intensity. The polarization intensity can be controlled by adjusting the trench density to reduce the device operating voltage and thus improve device durability.

[0028] Furthermore, using high-mobility oxide semiconductors to replace traditional silicon as the channel material can theoretically completely eliminate the formation of low-k interface layers. The main advantages of doing so are:

[0029] 4) It avoids the problem of device durability degradation caused by excessively high interface layer voltage;

[0030] 5) The shielding length was reduced, the shielding effect was enhanced, and the problem of device retention characteristic degradation caused by depolarization field was alleviated.

[0031] In summary, combining gate dielectric structure optimization and semiconductor channel material optimization methods can achieve high-speed, high-durability, and low-fluctuation FeFETs.

[0032] The beneficial effects of this invention are as follows:

[0033] First, the grain size of HZO was strictly controlled by using high-k gate dielectric trench and high-temperature annealing process, which is beneficial to obtaining ferroelectric HZO with excellent single-phase properties, improving polarization reversal consistency and increasing FeFET read / write speed.

[0034] The characteristic size of the trench restricts the grain size during rapid thermal annealing, limiting the growth of the m-phase grains. The high-temperature annealing process promotes the maximum transformation of the t-phase to the polarized o-phase. Therefore, HZO in high-k gate trenches exhibits excellent single-phase properties, even approaching o-phase single crystals, with high polarization reversal consistency and fast polarization reversal speed, which is beneficial for improving the read / write speed of FeFETs.

[0035] Second, the trench location can be precisely defined by photolithography, the phase distribution in the gate stack is relatively fixed, and the fluctuations within the device itself and between devices are very small.

[0036] Traditional hafnium oxide-based FeFETs are constrained by the polymorphism of hafnium oxide, with different types of phases being relatively randomly distributed in the gate stack. The lack of control over the grain size of different phases results in large size fluctuations, which leads to significant fluctuations within the device itself and between devices. This invention is of great significance for optimizing device fluctuations.

[0037] III. Residual polarization P of the gate stack r The durability of FeFETs can be improved by controlling the trench density.

[0038] Relatively low polarization intensity is beneficial for reducing the operating voltage of FeFET and improving the durability of FeFET, while low residual polarization intensity can be achieved by reducing trench density.

[0039] Fourth, using oxide semiconductors as the channel can eliminate the presence of the interface layer and improve the retention and durability characteristics of FeFET.

[0040] In traditional hafnium oxide-based FeFETs, a 0.5nm–2nm interface layer often exists between the ferroelectric material and the silicon-based channel. This interface layer has a low dielectric constant and a high voltage division, which can lead to charge injection and defect generation, thus degrading the device's durability. Furthermore, the presence of the interface layer increases the shielding length, weakens the shielding effect, and exacerbates the depolarization effect, resulting in reduced device retention. Replacing the silicon-based channel material with an oxide semiconductor material, where both the channel and ferroelectric materials are oxides, avoids the formation of the interface layer due to excessively high temperatures in subsequent processes, thereby optimizing the device's retention and durability.

[0041] Fifth, the fabrication process is fully compatible with CMOS back-end processes, and it is expected to be integrated with CMOS logic circuits.

[0042] This structure can be implemented on the passivation layer of a traditional chip and interconnected with CMOS logic devices through vias to achieve hybrid memory-logic integration. Attached Figure Description

[0043] Figure 1 This is a cross-sectional schematic diagram of a high-speed, high-durability, low-fluctuation FeFET prepared according to an embodiment of the present invention.

[0044] In the picture:

[0045] 1—Insulating substrate; 2—Back gate material

[0046] 3—High-k gate dielectric; 4—Ferroelectric HZO (ferroelectricity activated)

[0047] 5 — Oxide semiconductor material; 6 — Source metal

[0048] 7 - Sinking end metal

[0049] Figure 2 This is a schematic diagram illustrating the steps involved in fabricating a high-speed, high-durability, low-fluctuation FeFET based on a novel gate structure according to an embodiment of the present invention, wherein:

[0050] (a) is a cross-sectional view of a back gate material grown on an insulating substrate by physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, etc., after being patterned by photolithography and etching.

[0051] (b) is a cross-sectional view of a 3 nm to 10 nm thick high-k gate dielectric grown using atomic layer deposition (ALD) based on (a);

[0052] (c) is a cross-sectional view of a number of square trenches with length and width dimensions of 6 to 18 nm defined on a high-k gate dielectric using photolithography and etching methods, based on (b).

[0053] (d) is a cross-sectional view of a 30 nm thick ferroelectric HZO (unactivated) grown using atomic layer deposition (ALD) based on (c);

[0054] (e) is a cross-sectional view of the gate stack after thinning using chemical mechanical polishing (CMP) based on (d);

[0055] (f) is a cross-sectional view of the metal stress layer grown by physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, etc., based on (e).

[0056] (g) is a cross-sectional view after (f) is performed by rapid hot annealing to activate the ferroelectricity of HZO and removing the metal stress layer by wet etching.

[0057] (h) is a cross-sectional view of an oxide semiconductor channel patterned by physical vapor deposition (PVD) or atomic layer deposition (ALD) based on (g);

[0058] (i) is a cross-sectional view of an oxide semiconductor channel patterned by photolithography and etching, based on (h) using physical vapor deposition (PVD) or atomic layer deposition (ALD).

[0059] In the picture:

[0060] 1—Insulating substrate; 2—Back gate material

[0061] 3—High-k gate dielectric; 4—Ferroelectric HZO (ferroelectricity activated)

[0062] 5 — Oxide semiconductor material; 6 — Source metal

[0063] 7 - Sinking end metal Detailed Implementation

[0064] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0065] like Figure 1 As shown, the fabricated FeFET based on a novel gate structure, exhibiting high durability, low fluctuation, and excellent consistency, comprises an insulating substrate, a back gate material, a high-k gate dielectric material, ferroelectric HZO, an oxide semiconductor channel, source metal, and drain metal. The patterned back gate material is located above the insulating substrate, and the high-k gate dielectric material with multiple trenches is located above the back gate material. Ferroelectric HZO is embedded within the trenches. The patterned oxide semiconductor channel is situated on the high-k gate dielectric material, with source metal and drain metal located on either side above the oxide semiconductor material.

[0066] The preparation method includes the following steps: Figure 2 As shown, it specifically includes:

[0067] 1) A back gate material of 20 nm to 50 nm is grown on an insulating substrate 1 using physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering and other methods, and then patterned by photolithography and etching, as shown in Figure (a).

[0068] 2) High-k gate dielectric materials of 3-10 nm grown by atomic layer deposition (ALD), such as HfO2 or Al2O3, are shown in Figure (b);

[0069] 3) Using photolithography, several square regions with a size of 6 to 18 nm are defined on a high-k gate dielectric and etched to form a 15 nm * 15 nm square trench, as shown in Figure (c).

[0070] 4) A 30 nm thick ferroelectric HZO (ferroelectricity not yet activated) was grown using atomic layer deposition (ALD), as shown in Figure (d);

[0071] 5) The protruding ferroelectric HZO is removed by chemical mechanical polishing (CMP) to form a gate stack structure with ferroelectric HZO embedded in the high-k gate dielectric material, as shown in Figure (e).

[0072] 6) Metal stress layers of 10 nm to 30 nm, such as TiN, TaN, W, Ru, etc., are grown by physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, etc., as shown in Figure (f).

[0073] 7) Perform rapid hot annealing at a temperature between 550℃ and 800℃ for a time of approximately 30s to 120s to activate the ferroelectricity of HZO and remove the metal stress layer by wet etching, as shown in Figure (g).

[0074] 8) Deposit 10nm-30nm oxide semiconductor materials (such as IGZO, IWO, ITO, ZnO2, etc.) using physical vapor deposition (PVD) or atomic layer deposition (ALD), define the location of the active region using photolithography, and form oxide semiconductor channels through photolithography and etching, as shown in Figure (h).

[0075] 9) Source and drain metals of 30nm to 70nm are grown by physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering and other methods. The metals that can be selected include, but are not limited to, Al, Sc, Pt, Cr, Pd, Au, Ti and other materials. Then, they are patterned by photolithography and etching to form source end metals and drain end metals on both sides above the oxide semiconductor channel, as shown in Figure (i).

[0076] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.

Claims

1. A method for fabricating a FeFET device, the FeFET device comprising an insulating substrate, characterized in that, A back gate material patterned by photolithography and etching is placed on an insulating substrate. A high-k gate dielectric material is placed on the back gate material. The high-k gate dielectric material has multiple trenches, each with a length and width of 6 nm to 18 nm. Ferroelectric HZO is grown in the trenches. The thickness of the high-k gate dielectric material is 3 to 10 nm. An oxide semiconductor channel is placed on the high-k gate dielectric material, with source and drain contact metals on either side above the oxide semiconductor channel. The fabrication process includes the following steps: 1) Back gate material is prepared on an insulating substrate by sputtering / physical vapor deposition / atomic layer deposition and then patterned by photolithography and etching. 2) High-k gate dielectric materials are deposited using atomic layer deposition; 3) Define several trenches using photolithography and dry etching; 4) Ferroelectric HZO is deposited using atomic layer deposition, followed by chemical mechanical polishing to form a high-k gate dielectric material with ferroelectric HZO filling the trenches; 5) A metal stress layer is grown using atomic layer deposition or physical vapor deposition, and rapid thermal annealing is used to activate the ferroelectricity of ferroelectric HZO. The metal stress layer is then removed by wet etching. The metal stress layer is selected from TiN, TaN, W, or Ru. The annealing temperature is between 550℃ and 800℃, and the annealing time is between 30s and 120s. During rapid thermal annealing, the trenches restrict the grain size of HZO, inhibit the formation of the m phase, and ensure that HZO is fully crystallized and that the o phase grains are fully grown. 6) Spin-coat photoresist onto a high-k gate dielectric material, use photolithography to define the location of the active region, then grow an oxide semiconductor material and strip it off; 7) The positions of the source and drain metals are defined on both sides above the oxide semiconductor material using photolithography. Then, the source and drain metals are grown and stripped by physical vapor deposition, sputtering, and evaporation. The active region between the source and drain metals is the channel.

2. The method for fabricating the FeFET device as described in claim 1, characterized in that, The insulating substrate is made of Si / SiO2, BN, STO, LAO or YSZ.

3. The method for fabricating the FeFET device as described in claim 1, characterized in that, The back gate material is Pt, TiN, TaN, W, or heavily doped silicon or germanium, as well as LSMO, Nb-STO, and RuO2.

4. The method for fabricating the FeFET device as described in claim 1, characterized in that, The high-k gate dielectric material is Al2O3, HfO2 or ZrO2.

5. The method for fabricating the FeFET device as described in claim 1, characterized in that, The oxide semiconductor channel uses IGZO, IWO, ITO or ZnO2.

6. The method for fabricating the FeFET device as described in claim 1, characterized in that, The source and drain metals are Al, Sc, Pt, Cr, Pd, Au, or Ti.

7. The method for fabricating the FeFET device as described in claim 1, characterized in that, The thickness of the back gate material ranges from 20 nm to 50 nm.

8. The method for fabricating the FeFET device as described in claim 1, characterized in that, The thickness of the oxide semiconductor channel ranges from 10 nm to 30 nm.

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