A multi-step recursive encoder logic circuit design method and device

Abstract

The present invention relates to a multi-step recursive encoder logic circuit design method and device, characterized in that the logic circuit of the multi-step recursive RS encoder is used to implement a k-step parallel encoding method, and the design method comprises the steps of: using a first formula to express the nth check element register R n The value R after the kth clock cycle n (k); The first formula is: R n (k) = R n‑1 (k‑1)+[R 2t‑1 (k‑1)+d k‑1 ]·g n (n≥1), where n=0, 1, …2t-1, t is the maximum number of error correction code elements, k is the number of recursive steps, d k represents the kth data input into the multi-step recursive RS encoder, g n is the constant coefficient of the nth multiplier; according to the first formula, the g n The k×k constant matrix is ​​constructed, and the logic circuit of the multi-step recursive RS encoder is determined by the matrix. The invention is used to reduce the iteration cycle required for encoding and improve the encoding speed.

Description

Technical Field

[0001] The present invention relates to the field of FEC coding in channel coding, and in particular to a multi-step recursive encoder logic circuit design method and device. Background Art

[0002] In communication systems, FEC (forward error correction coding) is widely used to correct transmission errors. RS code (Reed-Solomon code) is a linear block code with a significant ability to correct burst and random errors, so it is widely used in various communication methods. In the field of high-speed optical communications, due to the high data transmission rate, effective error correction coding technology can fully guarantee the reliability of information transmission, increase the transmission distance, and reduce equipment power consumption. Therefore, RS coding has become a commonly used forward error correction coding in ultra-100G optical networks. For example, the IEEE802.3 standard defines two RS codes for 100G BASE-R: RS (528, 514) and RS (544, 514). In the ITU-T G.709.1 recommendation, the frame structure of Flex0 uses RS (544, 514) code for error correction.

[0003] In the related art, a commonly used encoding method for the system RS (m, q) code is to shift the information polynomial d (x) to the value x after (mq) times. m-q d(x) modulo the generating polynomial g(x) to obtain the supervisory codeword polynomial r(x), thereby obtaining the codeword polynomial c(x)=x of the system code m-q d(x)+r(x). Usually the additional Figure 2 The feedback multiplication logic circuit shown in the figure realizes the polynomial remainder operation. Taking RS (544, 514) code as an example, the generating polynomial used is: g(x) = (x + α 0 )(x+α 1 )…(x+α 29 )=x 30 +575x 29 +552x 28 +…+523, where the generation coefficient is g 29 =575,g 28 =552, ..., g0=523. After k clock cycles, the register will get 2t=mq check elements. However, under this encoding method, neither the data throughput rate nor the latency can meet the requirements of 100G / 400G and higher-speed optical networks. In actual engineering applications, the speed of the encoder needs to be further improved. Summary of the invention

[0004] The embodiment of the present invention provides a multi-step recursive encoder logic circuit design method and device to solve the problems in the related art, reduce the iteration cycle required for encoding, and improve the encoding speed.

[0005] In a first aspect, an embodiment of the present invention provides a method for designing a logic circuit of a multi-step recursive RS encoder, wherein the logic circuit of the multi-step recursive RS encoder is used to implement a k-step parallel encoding method, and the design method comprises the steps of:

[0006] The first formula is used to express the nth check element register R n The value R after the kth clock cycle n (k);

[0007] The first formula is:

[0008] R n (k) = R n-1 (k-1)+[R 2t-1 (k-1)+d k-1 ]·g n (n≥1), where n=0, 1, …2t-1, t is the maximum number of error correction code elements, k is the number of recursive steps, d k represents the kth data input into the multi-step recursive RS encoder, g n is the constant coefficient of the nth multiplier;

[0009] According to the first formula, g is calculated in advance. n A k×k constant matrix is ​​constructed, and the logic circuit of the multi-step recursive RS encoder is determined based on it.

[0010] In some embodiments, the first formula is used to calculate in advance the g n The k×k constant matrix is ​​constructed, including the steps:

[0011] Let M(k) = R 2t-1 (k)+d k , M(k) = R 2t-1 (k)+d k Substitute the first formula into the second formula, and the second formula is R n (k) = R n-1 (k-1)+M(k-1)·g n ;

[0012] According to the second formula, g is calculated in advance. n The k×k constant matrix formed by

[0013] In some embodiments, the second formula is used to calculate in advance the value of g n The k×k constant matrix is ​​constructed, including the steps:

[0014] According to the second formula, the third formula is:

[0015] When n<k, R n-k (0) and g (n-k+i) Items with negative subscripts are 0;

[0016] According to the second formula and the third formula, the g n The k×k constant matrix formed by

[0017] In some embodiments, the second formula and the third formula are used to calculate in advance the value of g n The k×k constant matrix is ​​constructed, including the steps:

[0018] Substituting the second formula into M(k)=R 2t-1 (k)+d k , the fourth formula is derived as: M(k) = M(k-1)·g 2t-1 +R 2t-2 (k-1)+d k (k ≥ 1);

[0019] According to the fourth formula, define the row vector D(k) and the column vector G(k) so that D(k)=[R 2t-1 (0)+d0 R 2t-2 (0)+d1 … R 2t-k (0)+d k-1 ], and M(k-1)=D(k)·G(k);

[0020] Combining the third formula, the fourth formula, the row vector D(k) and the column vector G(k), the fifth formula is obtained as R n (k) = R n-k (0)+D(k)·G(k)·g, where g is the n The k×k constant matrix formed by

[0021] In some embodiments, the first formula is used to calculate in advance the g n The k×k constant matrix is ​​constructed, and the logic circuit of the multi-step recursive RS encoder is determined based on it, including the steps of:

[0022] Definition P n (k) = G(k)·g, and substitute it into the fifth formula to obtain the sixth formula: R n (k) = R n-k (0)+D(k)·P n (k)

[0023] Calculate the P n(k), and according to the P n (k) and the sixth formula determine the logic circuit of the multi-step recursive RS encoder.

[0024] In a second aspect, a logic circuit of a multi-step recursive RS encoder determined by the aforementioned design method is provided, characterized in that it is used to implement a k-step parallel encoding method, and the logic circuit of the multi-step recursive RS encoder includes:

[0025] 2t check element n value register R n (k) a logic circuit for implementing value iteration of 2t check elements n, where t is the maximum number of error correction code elements, k is the number of recursive steps, k ≥ 0, n = 0, 1, ... 2t-1;

[0026] R n-k (0) an initial state circuit, which is used to realize the initial value of the check element at time 0;

[0027] k×2t multiplexing circuits, whose input terminals are connected to the R n-k (0) The initial state circuit and the output end are connected to the value register R of the 2t check elements n. n (k) logic circuit, and the k×2t multiplexing circuits are used to implement the R n-k (0) Initial state circuit to the value register R of the 2t check elements n n (k) Multiplexing of logic circuits;

[0028] P n constant array circuit, the P n The constant array circuit includes 2t groups P n constant circuit, and the 2t group P n The constant circuits are respectively connected to the value registers R of the 2t check elements n. n (k) logic circuits;

[0029] The value registers R of the 2t check elements n n (k) The logic circuit is determined by the sixth formula;

[0030] The R n-k (0) Initial state circuit routing formula:

[0031] D(k)=[R 2t-1 (0)+d0 R 2t-2 (0)+d1 … R 2t-k (0)+d k-1 ]Sure;

[0032] The P n The constant value in the constant array circuit is determined by P n (k) = G(k)·g is calculated.

[0033] According to a third aspect, a multi-step recursive RS encoder is provided, characterized in that it adopts the logic circuit of the multi-step recursive RS encoder as described in claim 6, and the multi-step recursive RS encoder is used to implement a k-step parallel encoding method.

[0034] In a fourth aspect, a multi-step recursive RS encoder logic circuit design device is characterized in that it includes:

[0035] Multi-step recursive model design module, which is used to:

[0036] The first formula is used to express the nth check element register R n The value R after the kth clock cycle n (k);

[0037] The first formula is:

[0038] R n (k) = R n-1 (k-1)+[R 2t-1 (k-1)+d k-1 ]·g n (n≥1), where n=0, 1, …2t-1, t is the maximum number of error correction code elements, k is the number of recursive steps, d k represents the kth data input into the multi-step recursive RS encoder, g n is the constant coefficient of the nth multiplier;

[0039] A logic circuit determination module is used to calculate in advance the g according to the first formula n A k×k constant matrix is ​​constructed, and the logic circuit of the multi-step recursive RS encoder is determined based on it.

[0040] In some embodiments, the multi-step recursive model design module is further used to:

[0041] Let M(k) = R 2t-1 (k)+d k , M(k) = R 2t-1 (k)+d k Substitute the first formula into the second formula, and the second formula is R n (k) = R n-1 (k-1)+M(k-1)·g n ;

[0042] According to the second formula, the third formula is:

[0043] When n<k, R n-k (0) and g (n-k+i)Items with negative subscripts are 0;

[0044] According to the second formula and the third formula, the g n The k×k constant matrix formed by

[0045] Substituting the second formula into M(k)=R 2t-1 (k)+d k , the fourth formula is derived as: M(k) = M(k-1)·g 2t-1 +R 2t-2 (k-1)+d k (k ≥ 1);

[0046] According to the fourth formula, define the row vector D(k) and the column vector G(k) so that D(k)=[R 2t-1 (0)+d0 R 2t-2 (0)+d1 … R 2t-k (0)+d k-1 ], and M(k-1)=D(k)·G(k);

[0047] Combining the third formula, the fourth formula, the row vector D(k) and the column vector G(k), the fifth formula is obtained as R n (k) = R n-k (0)+D(k)·G(k)·g, where g is the n The k×k constant matrix formed by

[0048] The logic circuit determination module is also used for:

[0049] Definition P n (k) = G(k)·g, and substitute it into the fifth formula to obtain the sixth formula: R n (k) = R n-k (0)+D(k)·P n (k)

[0050] Calculate the P n (k), and according to the P n (k) and the sixth formula determine the logic circuit of the multi-step recursive RS encoder.

[0051] In a fifth aspect, a computer storage medium is provided, characterized in that a computer program is stored on the computer storage medium, wherein when the computer program is executed by a processor, the steps of the multi-step recursive RS encoder logic circuit design method as described in any one of claims 1 to 5 are implemented.

[0052] The embodiment of the present invention provides a high-speed, low-latency RS encoder and encoding method, which adopts a recursive parallel encoding method and a regular logic circuit to maximize the operating clock frequency and data throughput rate while reducing the encoding delay to meet the requirements of high-speed optical networks to reduce transmission delays. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0054] Figure 1 A method flow chart of a RS encoding algorithm provided by an embodiment of the present invention;

[0055] Figure 2 A schematic diagram of the structure of a logic circuit of an RS encoder in the related art provided by an embodiment of the present invention;

[0056] Figure 3 The calculation method of the nth check element register R provided in the embodiment of the present invention n (k) Logic circuit diagram of the value;

[0057] Figure 4 A schematic diagram of the logic circuit structure of a multi-step recursive RS encoder provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0059] The embodiment of the present invention provides a multi-step recursive RS encoder logic circuit design method, which includes the steps of:

[0060] S100: Use the first formula to express the nth check element register R n The value R after the kth clock cycle n (k);

[0061] The first formula is:

[0062] R n (k) = R n-1 (k-1)+[R2t-1 (k-1)+d k-1 ]·g n (n≥1), where n=0, 1, …2t-1, t is the maximum number of error correction code elements, k is the number of recursive steps, d k represents the kth data input into the multi-step recursive RS encoder, g n is the constant coefficient of the nth multiplier;

[0063] S200: Calculate in advance the value of g according to the first formula n A k×k constant matrix is ​​constructed, and the logic circuit of the multi-step recursive RS encoder is determined based on it.

[0064] It should be noted that R n-1 (k-1) represents the (n-1)th register R n-1 The value after the (k-1)th clock cycle, and [R 2t-1 (k-1)+d k-1 ] is the factor input to each multiplier at the (k-1)th clock cycle. The plus sign represents addition in the GF(1024) domain, that is, bitwise XOR. All operations related to RS codes are performed in a finite field (that is, Galois field GF).

[0065] In this embodiment, Figure 2 The RS encoder corresponding to the logic circuit shown is improved, and a logic circuit design method for an RS encoder that can realize multi-step advance recursive coding is proposed. The logic circuit structure determined by this method realizes the recursive parallel coding method, which can effectively improve the operating clock frequency and data throughput, and reduce the coding delay to meet the requirements of high-speed optical networks to reduce transmission delays.

[0066] In some embodiments, step S200 includes the steps of:

[0067] S210: Set M(k)=R 2t-1 (k)+d k , M(k) = R 2t-1 (k)+d k Substitute the first formula into the second formula, and the second formula is R n (k) = R n-1 (k-1)+M(k-1)·g n ;

[0068] S220: Calculate in advance the value of g according to the second formula n The k×k constant matrix formed by

[0069] This embodiment further optimizes the logical structure of the first formula to facilitate the subsequent calculation of g n The k×k constant matrix formed by

[0070] In some embodiments, step S220 includes the steps of:

[0071] S221: The third formula is derived from the second formula:

[0072] When n<k, R n-k (0) and g (n-k+i) Items with negative subscripts are 0;

[0073] S222: Calculate in advance the value of g according to the second formula and the third formula n The k×k constant matrix formed by

[0074] It should be noted that the addition and multiplication in each formula are addition and multiplication operations in the GF(1024) domain.

[0075] This embodiment further optimizes the logical structure of the second formula to facilitate the subsequent calculation of g n The k×k constant matrix formed by

[0076] In some embodiments, step S222 includes the steps of:

[0077] S222_1: Substitute the second formula into M(k)=R 2t-1 (k)+d k , the fourth formula is derived as: M(k) = M(k-1)·g 2t-1 +R 2t-2 (k-1)+d k (k ≥ 1);

[0078] S222_2: According to the fourth formula, define the row vector D(k) and the column vector G(k) so that D(k)=[R 2t-1 (0)+d0R 2t-2 (0)+d1 … R 2t-k (0)+d k-1 ], and M(k-1)=D(k)·G(k);

[0079] S222_3: Combining the third formula, the fourth formula, the row vector D(k) and the column vector G(k), the fifth formula is obtained as R n (k) = R n-k (0)+D(k)·G(k)·g, where g is the n The k×k constant matrix formed by

[0080] It should be noted that, from the fourth formula, we can know that M(k) can also be specifically represented by the values ​​of each register at time k=0, and can be expanded continuously. When M(k-1) is converted into the input value at time 0, the column vector in the formula is defined as G(k), and S222_3 The terms are expanded into an upper triangular matrix with only constants in the middle, and the k-step recursion R can be written as shown below n (k) is expressed in matrix form, and it is agreed that if a negative number appears in the subscript of each coefficient, the term is 0.

[0081]

[0082] visible g is the g n The k×k constant matrix formed by

[0083] To further facilitate observation, we can define P n (k) = G(k)·g, and the P is calculated according to the fifth formula n (k), and according to the P n (k) Determine the logic circuit of the multi-step recursive RS encoder.

[0084] In this embodiment, P n (k) is a constant matrix with k rows and 1 column, which can be simply written as

[0085]

[0086] Therefore, R n-k (0) and D(k) are variables, and P n (k) is composed of g and G(k), and both g and G(k) are constants, so P can be calculated in advance. n (k) value, which is convenient for hardware circuit implementation. Such a structure can save resources, flatten the structure and increase the system clock frequency.

[0087] In a specific embodiment, define R n (k) represents the nth register R n The value after the kth clock cycle, n = 0, 1, ..., 2t-1. d k represents the data of the kth input encoder, g n is the constant coefficient of the nth multiplier. Then R n (k) can be expressed as:

[0088] R n (k) = R n-1 (k-1)+[R 2t-1 (k-1)+d k-1 ]·gn (n≥1) (1)

[0089] Where R n-1 (k-1) represents the (n-1)th register R n-1 The value after the (k-1)th clock cycle, [R 29 (k-1)+d k-1 ] is the factor input to each multiplier at the (k-1)th clock cycle. The plus sign indicates addition in the GF(1024) field, i.e., bitwise XOR. All operations related to RS codes are performed in a finite field (i.e., Galois field GF). Let

[0090] M(k)=R 2t-1 (k)+d k (2)

[0091] R n (k) is expressed as:

[0092] R n (k) = R n-1 (k-1)+M(k-1)·g n (3)

[0093] Further we get:

[0094]

[0095] Therefore, for KP4 FEC defined by IEEE 802.3, namely RS (544, 514) code, there are 30 check registers R0 to R 29 .

[0096] Substitute R in formula (3) 29 Substituting (k) into formula (2) to obtain the value of M(i-1) in formula (4), we can obtain: M(k) = M(k-1) g 29 +R 28 (k-1)+d k (k≥1) (5)

[0097] When k=4, that is, 4-cycle look-ahead recursive coding is performed, using formula (4), we can get:

[0098] R 29 (4) = R 25 (0)+M(0)·g 26 +M(1)·g 27 +M(2)·g 28 +M(3)·g 29

[0099] …

[0100] R4(4)=R0(0)+M(0)·g1+M(1)·g2+M(2)·g3+M(3)·g4

[0101] R3(4)=M(0)·g0+M(1)·g1+M(2)·g2+M(3)·g3

[0102] R2(4)=M(1)·g0+M(2)·g1+M(3)·g2

[0103] R1(4)=M(2)·g0+M(3)·g1

[0104] R0(4)=M(3)·g0

[0105] From formulas (2) and (5), we can know that M(k) can also be specifically represented by the values ​​of each register at time k=0, and then we get:

[0106] M(0)=R 29 (0)+d0

[0107]

[0108]

[0109]

[0110]

[0111] In the four equations from M(0) to M(3), the row vectors are the four input data of each clock cycle and the values ​​of the last four registers of the encoder, while the coefficients in the column vectors are all constants. Through the above derivation, the multiplication series is reduced and half of the multipliers can be saved.

[0112] At the same time, according to

[0113] Combining formulas (4) and (5), we can write R when n≥4: n The matrix expression of (4) is:

[0114]

[0115] For example:

[0116]

[0117] In particular, when n < 4,

[0118]

[0119]

[0120]

[0121]

[0122] According to

[0123]

[0124] Available

[0125] R n (4) = R n-4 (0)+D(4)·P n (4) (9)

[0126] It is agreed that if the subscript has a negative value, the term is 0 and is discarded. n-4 (0) and D(4) are variables, and the product P of the 4*4 square matrix containing the g coefficients and the G(4) column matrix n (4) is a constant, so P can be calculated in advance n According to the value of (4), the multiplication operation in the final implementation only requires 4*30=120 constant multipliers, which saves resources, flattens the structure and improves the clock frequency.

[0127] like Figure 3 As shown, according to formula (9), the value register R for calculating the check element n can be easily obtained n In the logic circuit diagram of (4), all multipliers are constant coefficient GF multipliers.

[0128] According to the coefficient g in the KP4 FEC standard 29 ~g0=575,552,187,230,552,1,108,565,282,249,593,132,94,720,495,385,942,503,883,361,788,610,193,392,127,185,158,128,834,523. As shown in Table 1, the values ​​for each register R can be calculated. 29 (4)~R0(4) Simplify the calculation of the 30*4 p0(n)~p3(n) coefficients required for convenient tabulation R 29 (4)~R0(4) is abbreviated as R29 to R0. Corresponding to n=29~0.

[0129] Table 1 is used to simplify the calculation of each R n (4) p0(n) to p3(n) coefficients (decimal representation)

[0130]

[0131]

[0132] It is understandable that other look-ahead recursive step numbers k may also be selected according to different chip processes.

[0133] The encoder proposed in the present invention has low delay introduced in optical network transmission and high throughput rate, can fully meet the requirements of various high-speed and low-delay services, and has great application prospects.

[0134] In a second aspect, an embodiment of the present invention further provides a logic circuit of a multi-step recursive RS encoder, wherein the logic circuit of the multi-step recursive RS encoder comprises:

[0135] 2t check element n value register R n (k) a logic circuit for implementing value iteration of 2t check elements n, where t is the maximum number of error correction code elements, k is the number of recursive steps, k ≥ 0, n = 0, 1, ... 2t-1;

[0136] R n-k (0) an initial state circuit, which is used to realize the initial value of the check element at time 0;

[0137] k×2t multiplexing circuits, whose input terminals are connected to the R n-k (0) The initial state circuit and the output end are connected to the value register R of the 2t check elements n. n (k) logic circuit, and the k×2t multiplexing circuits are used to implement the R n-k (0) Initial state circuit to the value register R of the 2t check elements n n (k) Multiplexing of logic circuits;

[0138] P n constant array circuit, the P n The constant array circuit includes 2t groups P n constant circuit, and the 2t group P n The constant circuits are respectively connected to the value registers R of the 2t check elements n. n (k) logic circuits;

[0139] The value registers R of the 2t check elements n n (k) The logic circuit is determined by the sixth formula;

[0140] The R n-k (0) Initial state circuit routing formula:

[0141] D(k)=[R 2t-1 (0)+d0 R 2t-2 (0)+d1 … R 2t-k (0)+d k-1 ]Sure;

[0142] The Pn The constant value in the constant array circuit is determined by P n (k) = G(k)·g is calculated.

[0143] This embodiment can be used as Figure 4 The logic circuit structure of the encoder is shown in Figure 1. Among them, k×2t MUX is used to implement R n-k (0) Initial state circuit to 2t check element n value register R n (k) Logic circuit multiplexing, U0~U 2t-1 To realize the value register R of 2t check elements n n (k) Logic circuit.

[0144] like Figure 4 As shown, an embodiment of the present invention further provides a multi-step recursive RS encoder, which uses the logic circuit of the aforementioned embodiment to implement a k-step parallel encoding method.

[0145] The embodiment of the present invention further provides a multi-step recursive RS encoder logic circuit design device, characterized in that it includes:

[0146] Multi-step recursive model design module, which is used to:

[0147] The first formula is used to express the nth check element register R n The value R after the kth clock cycle n (k);

[0148] The first formula is:

[0149] R n (k) = R n-1 (k-1)+[R 2t-1 (k-1)+d k-1 ]·g n (n≥1), where n=0, 1, …2t-1, t is the maximum number of error correction code elements, k is the number of recursive steps, d k represents the kth data input into the multi-step recursive RS encoder, g n is the constant coefficient of the nth multiplier;

[0150] A logic circuit determination module is used to calculate in advance the g according to the first formula n A k×k constant matrix is ​​constructed, and the logic circuit of the multi-step recursive RS encoder is determined based on it.

[0151] In some embodiments, the multi-step recursive model design module is further used to:

[0152] Let M(k) = R 2t-1 (k)+d k , M(k) = R 2t-1(k)+d k Substitute the first formula into the second formula, and the second formula is R n (k) = R n-1 (k-1)+M(k-1)·g n ;

[0153] According to the second formula, the third formula is:

[0154] When n<k, R n-k (0) and g (n-k+i) Items with negative subscripts are 0;

[0155] According to the second formula and the third formula, the g n The k×k constant matrix formed by

[0156] Substituting the second formula into M(k)=R 2t-1 (k)+d k , the fourth formula is derived as: M(k) = M(k-1)·g 2t-1 +R 2t-2 (k-1)+d k (k ≥ 1);

[0157] According to the fourth formula, define the row vector D(k) and the column vector G(k) so that D(k)=[R 2t-1 (0)+d0 R 2t-2 (0)+d1 … R 2t-k (0)+d k-1 ], and M(k-1)=D(k)·G(k);

[0158] Combining the third formula, the fourth formula, the row vector D(k) and the column vector G(k), the fifth formula is obtained as R n (k) = R n-k (0)+D(k)·G(k)·g, where g is the n The k×k constant matrix formed by

[0159] The logic circuit determination module is also used for:

[0160] Definition P n (k) = G(k)·g, and substitute it into the fifth formula to obtain the sixth formula: R n (k) = R n-k (0)+D(k)·P n (k)

[0161] Calculate the P n (k), and according to the P n(k) and the sixth formula determine the logic circuit of the multi-step recursive RS encoder.

[0162] In a fourth aspect, a computer storage medium is provided, characterized in that a computer program is stored on the computer storage medium, wherein when the computer program is executed by a processor, the steps of the multi-step recursive RS encoder logic circuit design method as described in any one of claims 1 to 5 are implemented.

[0163] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable storage medium, which may include a computer-readable storage medium (or a non-transitory medium) and a communication medium (or a temporary medium).

[0164] As is known to those of ordinary skill in the art, the term computer-readable storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer-readable storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium.

[0165] In the description of the present invention, it should be noted that the terms "upper", "lower", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present invention. Unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be a connection between the two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0166] It should be noted that, in the present invention, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0167] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A multi-step recursive RS encoder logic circuit design method, characterized in that: The logic circuit of the multi-step recursive RS encoder is used to implement a k-step parallel encoding method, and the design method comprises the steps of: The first formula is used to express the nth check register R n The value R after the kth clock cycle n (k); The first formula is: R n (k) = R n-1 (k-1)+[R 2t-1 (k-1)+d k-1 ]·g n (n≥1), where n=0, 1, …2t-1, t is the maximum number of error correction code elements, k is the number of recursive steps, d k represents the kth data input into the multi-step recursive RS encoder, g n is the constant coefficient of the nth multiplier; According to the first formula, g is calculated in advance. n A k×k constant matrix is ​​constructed, and the logic circuit of the multi-step recursive RS encoder is determined based on it.

2. The multi-step recursive RS encoder logic circuit design method as claimed in claim 1, characterized in that: The first formula is used to calculate in advance the g n The k×k constant matrix is ​​constructed, including the steps: Let M(k) = R 2t-1 (k)+d k , M(k)=R 2t-1 (k)+d k Substitute the first formula into the second formula, and the second formula is R n (k) = R n-1 (k-1)+M(k-1)·g n ; According to the second formula, g is calculated in advance. n The k×k constant matrix formed by 3. The multi-step recursive RS encoder logic circuit design method as claimed in claim 2, characterized in that: The second formula is used to calculate in advance the g n The k×k constant matrix is ​​constructed, including the steps: According to the second formula, the third formula is: Among them, when n<k, it is agreed that R n-k (0) and g (n-k+i) Items with negative subscripts are 0; According to the second formula and the third formula, the g n The k×k constant matrix formed by 4. The multi-step recursive RS encoder logic circuit design method as claimed in claim 3, characterized in that: The g is calculated in advance according to the second formula and the third formula n The k×k constant matrix is ​​constructed, including the steps: Substituting the second formula into M(k)=R 2t-1 (k)+d k , the fourth formula is derived as: M(k) = M(k-1)·g 2t-1 +R 2t-2 (k-1)+d k (k ≥ 1); According to the fourth formula, define the row vector D(k) and the column vector G(k) so that D(k)=[R 2t-1 (0)+d0 R 2t-2 (0)+d1… R 2t-k (0)+d k-1 ], and M(k-1)=D(k)·G(k); Combining the third formula, the fourth formula, the row vector D(k) and the column vector G(k), the fifth formula is obtained as R n (k) = R n-k (0)+D(k)·G(k)·g, where g is the n The k×k constant matrix formed by 5. The multi-step recursive RS encoder logic circuit design method as claimed in claim 4, characterized in that: The first formula is used to calculate in advance the g n The k×k constant matrix is ​​constructed, and the logic circuit of the multi-step recursive RS encoder is determined based on it, including the steps of: Define P n (k) = G(k)·g, and substitute it into the fifth formula to obtain the sixth formula: R n (k) = R n-k (0)+D(k)·P n (k) Calculate the P n (k), and according to the P n (k) and the sixth formula determine the logic circuit of the multi-step recursive RS encoder.

6. A logic circuit of a multi-step recursive RS encoder determined by the design method of claim 5, characterized in that: It is used to implement a k-step parallel encoding method, and the logic circuit of the multi-step recursive RS encoder includes: 2t check element n value register R n (k) a logic circuit for implementing value iteration of 2t check elements n, where t is the maximum number of error correction code elements, k is the number of recursive steps, k ≥ 0, n = 0, 1, ... 2t-1; R n-k (0) an initial state circuit, which is used to realize the initial value of the check element at time 0; k×2t multiplexing circuits, whose input terminals are connected to the R n-k (0) The initial state circuit and the output end are connected to the value register R of the 2t check elements n. n (k) logic circuit, and the k×2t multiplexing circuits are used to implement the R n-k (0) Initial state circuit to the value register R of the 2t check elements n n (k) Multiplexing of logic circuits; P n constant array circuit, the P n The constant array circuit includes 2t groups P n constant circuit, and the 2t group P n The constant circuits are respectively connected to the value registers R of the 2t check elements n. n (k) logic circuits; The value registers R of the 2t check elements n n (k) The logic circuit is determined by the sixth formula; The R n-k (0) Initial state circuit routing formula: D(k)=[R 2t-1 (0)+d0 R 2t-2 (0)+d1 … R 2t-k (0)+d k-1 ]Sure; The P n The constant value in the constant array circuit is determined by P n (k) = G(k)·g is calculated.

7. A multi-step recursive RS encoder, characterized in that: It adopts the logic circuit of the multi-step recursive RS encoder as claimed in claim 6, and the multi-step recursive RS encoder is used to implement a k-step parallel encoding method.

8. A multi-step recursive RS encoder logic circuit design device, characterized in that: It includes: Multi-step recursive model design module, which is used to: The first formula is used to express the nth check register R n The value R after the kth clock cycle n (k); The first formula is: R n (k) = R n-1 (k-1)+[R 2t-1 (k-1)+d k-1 ]·g n (n≥1), where n=0, 1, …2t-1, t is the maximum number of error correction code elements, k is the number of recursive steps, d k represents the kth data input into the multi-step recursive RS encoder, g n is the constant coefficient of the nth multiplier; A logic circuit determination module is used to calculate in advance the g according to the first formula n A k×k constant matrix is ​​constructed, and the logic circuit of the multi-step recursive RS encoder is determined based on it.

9. The multi-step recursive RS encoder logic circuit design device as claimed in claim 8, characterized in that: The multi-step recursive model design module is also used for: Let M(k) = R 2t-1 (k)+d k , M(k)=R 2t-1 (k)+d k Substitute the first formula into the second formula, and the second formula is R n (k) = R n-1 (k-1)+M(k-1)·g n ; According to the second formula, the third formula is: Among them, when n<k, it is agreed that R n-k (0) and g (n-k+i) Items with negative subscripts are 0; According to the second formula and the third formula, the g n The k×k constant matrix formed by Substituting the second formula into M(k)=R 2t-1 (k)+d k , the fourth formula is derived as: M(k) = M(k-1)·g 2t-1 +R 2t-2 (k-1)+d k (k ≥ 1); According to the fourth formula, define the row vector D(k) and the column vector G(k) so that D(k)=[R 2t-1 (0)+d0 R 2t-2 (0)+d1… R 2t-k (0)+d k-1 ], and M(k-1)=D(k)·G(k); Combining the third formula, the fourth formula, the row vector D(k) and the column vector G(k), the fifth formula is obtained as R n (k) = R n-k (0)+D(k)·G(k)·g, where g is the n The k×k constant matrix formed by The logic circuit determination module is also used for: Define P n (k) = G(k)·g, and substitute it into the fifth formula to obtain the sixth formula: R n (k) = R n-k (0)+D(k)·P n (k) Calculate the P n (k), and according to the P n (k) and the sixth formula determine the logic circuit of the multi-step recursive RS encoder.

10. A computer storage medium, characterized in that: The computer storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the multi-step recursive RS encoder logic circuit design method as described in any one of claims 1 to 5 are implemented.

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