Storage device and method of operating a storage device

Abstract

This disclosure relates to an electronic device. According to the present technology, a storage device includes: a memory device configured to include memory cells for storing data and circuitry configured to generate voltage information indicating whether a voltage for performing an operation on the memory cells is within a preset voltage range; and a memory controller communicating with the memory device and configured to transmit a status command to the memory device requesting a status response indicating a state of operation, and to control the memory device to change the voltage for performing the operation based on the status response provided from the memory device and including voltage information.

Description

[0001] Cross-references to related applications

[0002] This patent document claims priority and benefit to Korean patent application No. 10-2020-0154017, filed on November 17, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] The technology and embodiments disclosed in this patent document relate to an electronic device, and more particularly, to a storage device and a method of operating the storage device. Background Technology

[0004] A storage device is an electronic component configured to permanently or temporarily store data. Each storage device may include one or more storage media for storing data and operates based on requests for control from a host device such as a computer or smartphone. A storage device may include a memory device for storing data and may further include a memory controller for controlling the memory device to store or retrieve data. Memory devices may be classified based on the type of storage media. For example, memory devices may be classified as volatile memory devices and non-volatile memory devices.

[0005] Volatile memory devices store data only when power is supplied. Therefore, such volatile memory devices lose their data when power is lost. Examples of volatile memory devices can include static random access memory (SRAM) or dynamic random access memory (DRAM).

[0006] Non-volatile memory devices can retain their data even when power is off. Non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Summary of the Invention

[0007] The disclosed embodiments provide a storage device and a method of operating the storage device, the storage device comprising: a memory device that provides information to a memory controller indicating whether the operation is at a valid operating voltage; and a memory controller that controls the memory device.

[0008] According to embodiments of the disclosed technology, a memory device may include: a memory cell array including a plurality of memory cells; peripheral circuitry connected to the memory cell array and configured to perform operations on selected memory cells among the plurality of memory cells; a register including information about a voltage for operation; an operation processor communicating with the register to receive information about the voltage for operation, communicating with a memory controller external to the memory device to receive commands to perform operations from the memory controller, and configured to control the peripheral circuitry to perform operations on the selected memory cells using the voltage and generate status information related to the state of the operation; a voltage information generator communicating with the register and configured to generate voltage information indicating whether the voltage is within a preset voltage range in response to a command; and a status register communicating with the voltage information generator and configured to store the status information and the voltage information.

[0009] According to embodiments of the disclosed technology, a memory device may include: a memory cell array including a plurality of memory cells, each memory cell being configured to store data; peripheral circuitry connected to the memory cell array and configured to perform a read operation to read data stored in a selected memory cell among the plurality of memory cells; a read level register including information about the level of a read voltage used for the read operation; a voltage information generator configured to generate voltage information indicating whether the read voltage is within a preset voltage range; a read operation processor configured to control whether the peripheral circuitry uses the read voltage to read data from the selected memory cell and to generate status information related to the completion of the read operation; and a status register configured to store the status information and the voltage information.

[0010] According to embodiments of the disclosed technology, a storage device may include: a memory device configured to include memory cells for storing data and circuitry configured to generate voltage information indicating whether a voltage used to perform an operation on the memory cells is within a preset voltage range; and a memory controller communicating with the memory device and configured to: 1) transmit a status command to the memory device requesting a status response indicating the status of an operation; and 2) control the memory device to change the voltage used to perform the operation based on the status response provided from the memory device and including voltage information.

[0011] According to the present technology, a storage device and a method of operating the storage device are provided. The storage device includes: a memory device that provides information to a memory controller indicating whether the operation is at a valid operating voltage; and a memory controller that controls the memory device. Attached Figure Description

[0012] Figure 1This is a diagram illustrating an example of a storage device based on an embodiment of the disclosed technology.

[0013] Figure 2 It is shown Figure 1 An example illustration of a memory device.

[0014] Figure 3 It is shown Figure 2 A diagram illustrating an example configuration of any one of the storage blocks.

[0015] Figure 4A and Figure 4B This is a diagram showing the threshold voltage distribution of a single-layer cell (SLC).

[0016] Figure 5A and Figure 5B This is a diagram showing the threshold voltage distribution of a multilayer cell (MLC).

[0017] Figure 6A and Figure 6B This is a diagram showing the threshold voltage distribution of a three-layer cell (TLC).

[0018] Figure 7 This is a diagram illustrating an example configuration of a memory device based on an embodiment of the disclosed technology.

[0019] Figure 8 It is shown Figure 7 A diagram illustrating the reading of data stored in the level register.

[0020] Figure 9 This is a diagram illustrating the data communication between the memory controller and the memory device.

[0021] Figure 10 It is shown Figure 7 A diagram of the status register.

[0022] Figure 11 It is shown Figure 1 A diagram illustrating the operation of the read operation controller and the read level manager of the memory controller.

[0023] Figure 12 It is shown Figure 1 A diagram illustrating another embodiment of the memory controller.

[0024] Figure 13 This is a block diagram illustrating a memory card system using a storage device based on an embodiment of the disclosed technology.

[0025] Figure 14 This is a block diagram illustrating a solid-state drive (SSD) system including a storage device based on an embodiment of the disclosed technology.

[0026] Figure 15 This is a block diagram illustrating a user system including a storage device based on an embodiment of the disclosed technology. Detailed Implementation

[0027] Various embodiments of the disclosed technology can be implemented in various forms. Below, some example embodiments of the disclosed technology will be described with reference to the accompanying drawings.

[0028] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the disclosed technology.

[0029] Reference Figure 1 Storage device 50 may include memory device 100 and memory controller 200. Storage device 50 may be a device that stores data under the control of a host 400 such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system. Optionally, storage device 50 may be a device that stores data under the control of a host 400 that stores high-capacity data in a location such as a server or data center.

[0030] Depending on the host interface, which serves as the communication interface between the host 400 and the storage device 50, the storage device 50 can be manufactured as one of various types of storage devices. For example, the storage device 50 can be configured as any of the following types of storage devices: SSD, multimedia cards in the form of MMC, eMMC, RS-MMC, and micro MMC, secure digital cards in the form of SD, mini SD, and micro SD, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, PCMCIA card-type storage devices, peripheral component interconnect (PCI) card-type storage devices, high-speed PCI (PCI-E) card-type storage devices, compact flash memory (CF) cards, smart media cards, or memory sticks.

[0031] The storage device 50 can be manufactured in any of a variety of packages. For example, the storage device 50 can be manufactured in any of the following package types: Point-of-Package (POP), System-in-Package (SIP), System-on-Chip (SOC), Multi-Chip Package (MCP), Chip-on-Board (COB), Wafer-Level Fabrication Package (WFP), or Wafer-Level Stacked Package (WSP).

[0032] The memory device 100 may provide storage space in which data to be processed and / or instructions to be executed are stored. The memory device 100 may include logic required for reading from and writing to the memory device 100, and may operate in response to requests from the memory controller 200. The memory device 100 may include a memory cell array (not shown) comprising a plurality of memory cells for storing data.

[0033] Each memory cell can be configured as a single-level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a three-level cell (TLC) that stores three data bits, or a four-level cell (QLC) that can store four data bits.

[0034] A memory cell array (not shown) may include multiple memory blocks. Each memory block may include multiple pages, and each page corresponds to multiple memory cells. In embodiments of the disclosed technology, read and program (write) operations are performed on a page-by-page basis, and erase operations are performed on a block-by-block basis.

[0035] In embodiments, the memory device 100 may be a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), a fourth-generation low-power Double Data Rate (LPDDR4) SDRAM, a Graphics Double Data Rate (GDDR) SDRAM, low-power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), etc. In this patent document, some embodiments of the memory device 100 implemented as NAND flash memory are described, but other embodiments are also possible.

[0036] By providing command / address signals to memory controller 200, memory controller 200 can access memory device 100 based on a request from a user / host. In some embodiments, memory device 100 may receive commands from memory controller 200 and an address for executing or running those commands. Memory device 100 may perform operations indicated by commands on regions selected by addresses. For example, memory device 100 may perform write operations (programming operations), read operations, and / or erase operations. During a programming operation, memory device 100 may program data into the region selected by address. During a read operation, memory device 100 may read data from the region selected by address. During an erase operation, memory device 100 may erase data stored in the region selected by address.

[0037] The memory device 100 may include a valid read level information generator 153.

[0038] The valid read level information generator 153 can generate valid read level information indicating whether the read voltage used during a read operation is within the valid read voltage range. In some embodiments, the valid read level information may be information indicating whether a read operation has been performed at a read voltage within the valid read voltage range. In some other embodiments, the valid read level information generator 153 may determine whether the read voltage set for the read operation is within the valid read voltage range before performing the read operation. In this case, the read operation can be performed or not performed based on the determination. The valid read voltage range may be between a minimum read voltage and a maximum read voltage, and is determined during testing of the memory device 100.

[0039] When a read operation is performed at a read voltage that is not included in the effective read voltage range, the read operation may obtain inaccurate read data and the read operation may fail.

[0040] The valid read level information generator 153 can store the generated valid read level information in a status register included in the memory device 100. The status register may be a register that stores status information indicating the operating status of the memory device 100. The memory controller 200 can provide the memory device 100 with a command to instruct the execution of an operation, and after a predetermined time, the memory controller 200 can provide the memory device 100 with a command to request the status information stored in the status register.

[0041] The status information provided by the memory device 100 indicates the status of a read command, for example, whether a previously provided read command to the memory device 100 has been completed. In embodiments of the disclosed technology, the memory device 100 configures the status information by including valid read level information, which indicates whether the read voltage used to perform the read operation is set within a valid read voltage range. Therefore, the memory controller 200 can be notified based on the status information whether the operation has been successfully completed and whether the read operation was performed at a voltage within the valid read voltage range.

[0042] In some implementations, when an operation is performed under an invalid read voltage, the memory controller 200 may provide the memory device 100 with a command instructing a change in the read voltage.

[0043] In another embodiment, the memory device 100 may determine, before performing a read operation, whether the voltage setting for performing the read operation has a voltage level within the valid read voltage range, and provide the result as valid read level information. In some embodiments, when the voltage set for the read operation has a voltage level outside the valid read voltage range, the memory controller 200 may control the memory device 100 not to perform the read operation. This prevents the read operation from being performed under an invalid read voltage.

[0044] In this patent document, the memory device 100 is described as generating valid read level information for read operations; however, the above method can be applied to programming and / or erasing operations, and is not limited to read operations.

[0045] Therefore, the memory device 100 can include valid voltage level information in its status information and can provide this valid voltage level information to the memory controller 200. This valid voltage level information indicates whether the operating voltage used to perform operations including programming, reading, and erasing operations is set within the valid voltage range. Thus, the memory controller 200 can obtain information from the status information regarding whether the corresponding operation has been completed or failed, as well as additional information regarding whether the corresponding operation has been performed within the valid operating voltage range.

[0046] In various embodiments, the memory device 100 can determine whether the voltage used to set the operation has a voltage level within the effective voltage range before performing the corresponding operation, and provide the result as effective voltage level information. This prevents the corresponding operation from being performed under an invalid voltage.

[0047] The memory controller 200 can control all operations of the storage device 50.

[0048] When power is applied to storage device 50, memory controller 200 can run firmware (FW). When storage device 100 is a flash memory device, memory controller 200 can run firmware such as flash translation layer (FTL) for controlling communication between host 400 and storage device 100.

[0049] In an embodiment, the memory controller 200 may receive data and a logical address (LA) from the host 400 and may translate the LA into a physical address (PA) that indicates the address of a memory cell from which data is to be written or read.

[0050] The memory controller 200 can control the memory device 100 to perform programming operations, read operations, and / or erase operations based on requests from the host 400. During a programming operation, the memory controller 200 can provide the memory device 100 with programming commands, processing arguments (PAs), and data. During a read operation, the memory controller 200 can provide the memory device 100 with read commands and processing arguments (PAs). During an erase operation, the memory controller 200 can provide the memory device 100 with erase commands and processing arguments (PAs).

[0051] In this embodiment, the memory controller 200 can autonomously generate commands, addresses, and data regardless of requests from the host 400, and transmit these commands, addresses, and data to the memory device 100. For example, the memory controller 200 can provide the memory device 100 with commands, addresses, and data for performing programming, reading, and erasing operations. The memory controller 200 can also provide commands, addresses, and data to the memory device 100 to perform wear leveling, read recycling, garbage collection, or other operations.

[0052] In an embodiment, the memory controller 200 may control at least two or more memory devices 100. In this case, the memory controller 200 may control the memory devices 100 according to an interleaving method to improve operational performance. The interleaving method may be a method of controlling operations for at least two memory devices 100 to overlap.

[0053] The memory controller 200 may include a read operation controller 210 and a read level manager 220.

[0054] The read operation controller 210 can control all operations related to read operations performed on the memory device 100. Specifically, the read operation controller 210 can provide the memory device 100 with a read command instructing it to read stored data.

[0055] After a predetermined time has elapsed since a read command has been provided to the memory device 100, the read operation controller 210 may provide a status read command to the memory device, which requests status information stored in the status register included in the memory device 100.

[0056] The read operation controller 210 can receive a status read response provided by the memory device 100 in response to a status read command. The read operation controller 210 can obtain valid read level information included in the read status response and provide the obtained valid read level information to the read level manager 220.

[0057] The read level manager 220 can provide the memory device 100 with a read voltage change command that indicates a change in the read voltage level. In some embodiments, the read level manager 220 can provide the read voltage change command to the memory device 100 using a parameter setting command (setting parameters) or a feature setting command (setting features). For example, the read level manager 220 can provide the memory device with the address of a read level register included in the memory device 100 and data corresponding to the read level to be changed by using a parameter setting command (setting parameters) or a feature setting command (setting features).

[0058] In this embodiment, the read level manager 220 can provide the memory device 100 with a read voltage change command that indicates a change in the read voltage level, based on valid read level information. When the read voltage level used in the read operation is not within the valid read voltage range, a read voltage change command can be provided to the memory device 100.

[0059] The host 400 can communicate with the storage device 50 using at least one of the following communication methods: Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM).

[0060] Figure 2 It is shown Figure 1 A diagram of a memory device.

[0061] Reference Figure 2The memory device 100 may include a memory cell array 110, a voltage generator 120, an address decoder 130, an input / output circuit 140, and control logic 150.

[0062] Memory cell array 110 includes multiple memory blocks BLK1 to BLKi. The multiple memory blocks BLK1 to BLKi are connected to address decoder 130 via row lines RL. The multiple memory blocks BLK1 to BLKi are connected to input / output circuitry 140 via column lines CL. In an embodiment, row lines RL may include word lines, source select lines, and drain select lines. In an embodiment, column lines CL may include bit lines.

[0063] Each of the plurality of memory blocks BLK1 to BLKi includes a plurality of memory cells. In an embodiment, the plurality of memory cells may be non-volatile memory cells. Memory cells connected to the same word line among the plurality of memory cells may be defined as a physical page. That is, the memory cell array 110 may include a plurality of physical pages. Each of the memory cells in the memory device 100 may be configured as an SLC storing one data bit, an MLC storing two data bits, a TLC storing three data bits, or a QLC capable of storing four data bits.

[0064] In this embodiment, the voltage generator 120, address decoder 130, and input / output circuitry 140 can be collectively referred to as peripheral circuitry. Peripheral circuitry can drive memory cell array 110 based on control logic 150. Peripheral circuitry can drive memory cell array 110 to perform programming, reading, and erasing operations.

[0065] Voltage generator 120 is configured to generate multiple operating voltages using an external power supply voltage supplied to memory device 100. Voltage generator 120 operates in response to control of control logic 150.

[0066] In this embodiment, the voltage generator 120 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by the voltage generator 120 is used as the operating voltage of the memory device 100.

[0067] In this embodiment, voltage generator 120 can generate multiple operating voltages using either an external power supply voltage or an internal power supply voltage. Voltage generator 120 can be configured to generate various voltages required in the memory device 100. For example, voltage generator 120 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple selected read voltages, and multiple unselected read voltages.

[0068] Voltage generator 120 may include multiple pump capacitors that receive an internal power supply voltage to generate multiple operating voltages having various voltage levels, and may generate multiple operating voltages by selectively activating the multiple pump capacitors in response to control of control logic 150.

[0069] The generated operating voltages can be supplied to the memory cell array 110 via the address decoder 130.

[0070] Address decoder 130 is connected to memory cell array 110 via row line RL. Address decoder 130 is configured to operate in response to control of control logic 150. Address decoder 130 can receive address ADDR from control logic 150. Address decoder 130 can decode the block address in the received address ADDR. Address decoder 130 selects at least one memory block from memory blocks BLK1 to BLKi based on the decoded block address. Address decoder 130 can decode the row address in the received address ADDR. Address decoder 130 can select at least one word line from the word lines of the selected memory block based on the decoded row address. In an embodiment, address decoder 130 can decode the column address in the received address ADDR. Address decoder 130 interconnects input / output circuitry 140 and memory cell array 110 based on the decoded column address.

[0071] For example, address decoder 130 may include components such as row decoder, column decoder, and address buffer.

[0072] Input / output circuitry 140 may include multiple page buffers. These page buffers can be connected to memory cell array 110 via bit lines. During programming operations, data can be stored in selected memory cells based on the data stored in the multiple page buffers.

[0073] During a read operation, data stored in the selected memory cell can be sensed via bit lines, and the sensed data can be stored in the page buffer.

[0074] Control logic 150 can control address decoder 130, voltage generator 122, and input / output circuitry 140. Control logic 150 can operate in response to commands (CMD) transmitted from external devices. Control logic 150 can generate control signals to control peripheral circuitry in response to commands (CMD) and addresses (ADDR).

[0075] Figure 3 It is shown Figure 2 A diagram illustrating the configuration of any one of the storage blocks.

[0076] Storage block BLKi is Figure 2Any one of the storage blocks BLK1 to BLKi.

[0077] Reference Figure 3 Multiple word lines arranged in parallel can be connected between a first select line and a second select line. Here, the first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL). More specifically, the memory block BLKi can include multiple string STs connected between bit lines BL1 to BLn and the source line SL. Bit lines BL1 to BLn can be connected to string STs respectively, and the source line SL can typically be connected to string STs. Since string STs can be configured to be identical to each other, as an example, a string ST connected to the first bit line BL1 will be specifically described.

[0078] A string ST may include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST. A string ST may include at least one or more source selection transistors SST and drain selection transistors DST, and may include more than the number of memory cells MC1 to MC16 shown in the figure.

[0079] The source of the source select transistor (SST) can be connected to the source line SL, and the drain of the drain select transistor (DST) can be connected to the first bit line BL1. Memory cells MC1 to MC16 can be connected in series between the source select transistors SST and Drain select transistors DST. The gates of the source select transistors SST included in different strings of STs can be connected to the source select line SSL, the gates of the drain select transistors DST can be connected to the drain select line DSL, and the gates of memory cells MC1 to MC16 can be connected to multiple word lines WL1 to WL16. A group of memory cells in different strings of STs connected to the same word line can be called a page PG. Therefore, a memory block BLKi can include the number of page PGs corresponding to word lines WL1 to WL16.

[0080] A memory cell can store one bit of data. This is often referred to as SLC. In this case, a physical page (PG) can store one logical page (LPG) of data. A logical page (LPG) of data can include the same number of data bits as the cells included in a physical page (PG).

[0081] A memory cell can store two or more bits of data. In this case, a physical page (PG) can store two or more logical pages (LPGs) of data.

[0082] Figure 4A and Figure 4B This is a diagram showing the threshold voltage distribution of an SLC.

[0083] Reference Figure 4A and Figure 4B The horizontal axis represents the threshold voltage (V) of the memory cell. TH The vertical axis represents the number of memory cells (#of cells).

[0084] Memory devices can be programmed on a word-line basis. Multiple memory cells connected to a word line can be configured into a physical page. Programming and / or reading operations can be performed on a page-by-page basis.

[0085] The memory device can perform programming operations to store data in a memory cell connected to a selected word line among a plurality of word lines.

[0086] Before performing programming operations, the selected memory cell can have the following characteristics: Figure 4A The threshold voltage distribution corresponding to the erase state E shown is the memory cell connected to the selected word line.

[0087] When a memory cell stores data corresponding to a single bit, the memory cell can be programmed to have a threshold voltage corresponding to either the erase state E or the first programming state P1.

[0088] In some implementations, the erase state E may correspond to data "1" and the first programming state P1 may correspond to data "0". However, other implementations are also possible. Therefore, in some implementations, the erase state E may correspond to data "0" and the first programming state P1 may correspond to data "1".

[0089] When the programming operation is complete, the selected memory cell can have the following characteristics: Figure 4B The threshold voltage corresponding to either the erase state E or the first programming state P1 is shown. The memory device can perform a read operation by using the first read voltage R1 between the erase state E and the first programming state P1 to read the data stored in the selected memory cell.

[0090] Figure 5A and Figure 5B This is a diagram showing the threshold voltage distribution of an MLC.

[0091] Reference Figure 5A and Figure 5B The horizontal axis represents the threshold voltage (V) of the memory cell. TH The vertical axis represents the number of memory cells (#of cells).

[0092] Before performing programming operations, the selected memory cell can have the following characteristics: Figure 5AThe threshold voltage distribution corresponding to the erase state E shown is the memory cell connected to the selected word line.

[0093] When a memory cell stores data corresponding to two bits, the memory cell can be programmed to have a threshold voltage corresponding to any one of the erase state E, the first programming state P1, the second programming state P2, and the third programming state P3.

[0094] In one example, erase state E can correspond to data "11", first programming state P1 can correspond to data "10", second programming state P2 can correspond to data "00", and third programming state P3 can correspond to data "01". However, other implementations are possible, and the data corresponding to each programming state can be modified in different ways. The two bits of data stored in each memory cell can include the least significant bit (LSB) and the most significant bit (MSB).

[0095] When the programming operation is complete, the selected memory cell can have the following characteristics: Figure 5B The threshold voltages corresponding to any one of the erase state E, the first programming state P1, the second programming state P2, and the third programming state P3 are shown. The memory device can read the data stored in the selected memory cell by performing a read operation using the first to third read voltages R1 to R3.

[0096] The first read voltage R1 can be the read voltage that distinguishes between the erase state E and the first programming state P1, the second read voltage R2 can be the read voltage that distinguishes between the first programming state P1 and the second programming state P2, and the third read voltage R3 can be the read voltage that distinguishes between the second programming state P2 and the third programming state P3.

[0097] Figure 6A and Figure 6B This is a diagram showing the threshold voltage distribution of a TLC.

[0098] Reference Figure 6A and 6B The horizontal axis represents the threshold voltage (V) of the memory cell. TH The vertical axis represents the number of memory cells (#of cells).

[0099] Before performing programming operations, the selected memory cell can have the following characteristics: Figure 6A The threshold voltage distribution corresponding to the erase state E shown is the memory cell connected to the selected word line.

[0100] When a memory cell stores data corresponding to three bits, the memory cell can be programmed to have a threshold voltage corresponding to any one of the erase state E, the first programming state P1, the second programming state P2, the third programming state P3, the fourth programming state P4, the fifth programming state P5, the sixth programming state P6, and the seventh programming state P7.

[0101] In one example, erase state E can correspond to the data "111", first programming state P1 can correspond to the data "011", second programming state P2 can correspond to the data "001", third programming state P3 can correspond to the data "101", fourth programming state P4 can correspond to the data "100", fifth programming state P5 can correspond to the data "000", sixth programming state P6 can correspond to the data "010", and seventh programming state P7 can correspond to the data "110". However, other implementations are possible, and therefore the data corresponding to each programming state can be modified in different ways. The three bits of data stored in each memory cell can include the least significant bit (LSB), the middle significant bit (CSB), and the most significant bit (MSB).

[0102] When the programming operation is complete, the selected memory cell can have the following characteristics: Figure 6B The threshold voltages shown correspond to any one of the erase state E, first programming state P1, second programming state P2, third programming state P3, fourth programming state P4, fifth programming state P5, sixth programming state P6, and seventh programming state P7. The memory device can read the data stored in the selected memory cell by performing a read operation using the first to seventh read voltages R1 to R7.

[0103] The first read voltage R1 can be the read voltage that distinguishes between the erase state E and the first programming state P1. The second read voltage R2 can be the read voltage that distinguishes between the first programming state P1 and the second programming state P2. The third read voltage R3 can be the read voltage that distinguishes between the second programming state P2 and the third programming state P3. The fourth read voltage R4 can be the read voltage that distinguishes between the third programming state P3 and the fourth programming state P4. The fifth read voltage R5 can be the read voltage that distinguishes between the fourth programming state P4 and the fifth programming state P5. The sixth read voltage R6 can be the read voltage that distinguishes between the fifth programming state P5 and the sixth programming state P6. The seventh read voltage R7 can be the read voltage that distinguishes between the sixth programming state P6 and the seventh programming state P7.

[0104] Figure 7 This is a diagram illustrating the configuration of a memory device according to an embodiment of the disclosed technology.

[0105] Reference Figure 1 , Figure 2and Figure 7 The memory device 100 may include a memory cell array 110, a read voltage generator 121, a read operation processor 151, a read level register 152, a valid read level information generator 153, and a status register 154.

[0106] The voltage generator 121 can be included in the reference. Figure 2 The voltage generator 120 is described.

[0107] The read voltage generator 121 can generate a read voltage under the control of the read operation processor 151 and provide the read voltage to the page to be read in the memory block whose address is selected by the memory controller 200. In embodiments, in addition to the read voltage generator 121, the voltage generator 120 may include voltage generators for each operation, such as a programming voltage generator and an erase voltage generator.

[0108] The read operation processor 151, read level register 152, valid read level information generator 153, and status register 154 may be included in the reference. Figure 2 The control logic described is in 150.

[0109] The read operation processor 151 can control the memory device 100 to perform a read operation in response to a read command received from the memory controller 200.

[0110] Specifically, when a read command is received, the read operation processor 151 can control the read voltage generator 121 to generate a read voltage for the read operation based on the current read level information stored in the read level register 152.

[0111] When the read operation is completed, the read operation processor 151 can store readiness information indicating the completion of the read operation in the status register 154.

[0112] The read level register 152 can store information about the level of the read voltage. In some implementations, the read level register 152 can store the current read level information and the reference read level information.

[0113] The current read level information may include information about the read level used for the read operation. The current read level information can be updated under the control of the read operation processor 151. In some embodiments, the read operation processor 151 may update the current read level information in response to a read voltage change command received from the memory controller 200. The read voltage change command may be a parameter setting command (set parameter) or a feature setting command (set feature). The parameter setting command (set parameter) or feature setting command (set feature) may include the address of the read level register 152 and data corresponding to the read level to be changed.

[0114] The reference read level information may include information indicating the effective read voltage range. The effective read voltage range may be a value experimentally determined through various tests during the manufacturing process of the memory device 100. The reference read level information may be stored in a system block (System BLK) among the multiple memory blocks included in the memory cell array 110. When power is applied to the memory device 100, the read operation processor 151 may read the reference read level information stored in the system block (System BLK) and store the read reference read level information in the read level register 152.

[0115] The valid read level information generator 153 can generate valid read level information indicating whether the current read voltage is within the valid read voltage range by using the current read level information and the reference read level information stored in the read level register 152. Specifically, the valid read level information generator 153 can compare the current read voltage with the reference read level in response to a read command, and store the valid read level information as a comparison result in the status register 154.

[0116] In various embodiments, in response to a read command, the read operation processor 151 can selectively execute a read operation based on the valid read level information stored in the status register 154. Specifically, the read operation processor 151 can control the read voltage generator 121 to generate a read voltage for the read operation based on the valid read level information indicating that the read voltage belongs to the valid read voltage range. Optionally, the read operation processor 151 can skip the read operation without executing it based on the valid read level information indicating that the read voltage does not belong to the valid read voltage range. That is, the read operation processor 151 can execute a read operation or skip a read operation based on whether the current read level belongs to the valid read voltage range. When executing or skipping a read operation, the read operation processor 151 can generate ready information indicating that the read operation is complete and store the ready information in the status register 154.

[0117] In an embodiment, in response to a status read command received from the memory controller 200, the read operation processor 151 may provide the memory controller 200 with status information stored in the status register 154. For example, the read operation processor 151 may provide the memory controller 200 with status information as a status read response, which is a response to the status read command.

[0118] Status register 154 can store status information about the operational status of memory device 100. Memory controller 200 can provide the memory device 100 with commands instructing it to perform a programming operation, a read operation, or an erase operation, and then provide a status read command to the memory device 100 after a predetermined time. Memory controller 200 can obtain status information in response to the status read command. According to embodiments of the disclosed technology, the status register can store valid read level information. That is, the status information can include valid read level information. Therefore, memory controller 200 can determine whether to perform a read operation using a read voltage within the valid read voltage range, or whether the read voltage set in memory device 100 is within the valid read voltage range, by obtaining the status information.

[0119] Figure 8 It is shown Figure 7 A diagram illustrating the reading of data stored in the level register.

[0120] exist Figure 8 In this context, it is assumed that the memory cells included in the memory device are programmed to be multi-level cells that each store two bits of data. That is, as shown in reference... Figure 5B As described, memory cells can be read using first to third read voltages R1 to R3, which are used to identify erase state E and first to third programming states P1 to P3. In other words, the read voltages used for the read operation can include the first to third read voltages R1 to R3.

[0121] Reference Figure 8 The read level register 152 can store information about the level of the read voltage. Specifically, the read level register 152 can store reference read level information 152_1 and current read level information 152_2.

[0122] The reference read level information 152_1 may include information about the minimum read levels Rmin1 to Rmin3 and the maximum read levels Rmax1 to Rmax3 corresponding to each of the first to third read voltages R1 to R3.

[0123] The current read level information 152_2 may include information about the current read levels Rcur1 to Rcur3 corresponding to each of the currently set first to third read voltages R1 to R3.

[0124] Reference Figure 7 The described valid read level information generator 153 can determine whether each of the current read levels Rcur1 to Rcur3 is included in the minimum read levels Rmin1 to Rmin3 and the maximum read levels Rmax1 to Rmax3 corresponding to each of the first to third read voltages R1 to R3. Specifically, when the current read levels Rcur1 to Rcur3 are greater than the minimum read levels Rmin1 to Rmin3 and less than the maximum read levels Rmax1 to Rmax3, the valid read level information generator 153 can generate valid read level information indicating that the current read levels Rcur1 to Rcur3 belong to the valid read voltage range. Conversely, when any of the current read levels Rcur1 to Rcur3 is less than or equal to the minimum read levels Rmin1 to Rmin3, or greater than or equal to the maximum read levels Rmax1 to Rmax3, the valid read level information generator 153 can generate valid read level information indicating that the current read levels Rcur1 to Rcur3 do not belong to the valid read voltage range.

[0125] Figure 9 This is a diagram illustrating the data communication between the memory controller and the memory device.

[0126] Reference Figure 9 The memory controller 200 can provide the memory device 100 with programming commands, read commands, or erase commands, and then, after a preset time has elapsed, the memory controller 200 can provide the memory device 100 with a status read command.

[0127] The Status Read command can be a command used to request a value stored in a status register, which stores status information indicating the operating status of the memory device 100.

[0128] When a status read command is received, the memory device 100 may respond to the status read command by providing the value stored in the status register to the memory controller 200 as a status read response.

[0129] According to embodiments of the disclosed technology, the memory device 100 can generate valid level information (or valid read level information) indicating whether the voltage used by the memory device 100 to perform an operation is within the valid voltage range. The valid level information (or valid read level information) can be a value of a configuration status register. For example, when the voltage used to perform the operation is within the valid voltage range, the memory device 100 can store the valid level information (or valid read level information) as a set state in the status register. When the voltage used to perform the operation is not within the valid voltage range, the memory device 100 can store the valid level information (or valid read level information) as a release state in the status register. In response to a status read command StatusRead, the memory device 100 can provide the memory controller 200 with a status register value including the valid level information (or valid read level information) as a Status Read Response.

[0130] Figure 10 It is shown Figure 7 A diagram of status register 154.

[0131] Status register 154 can store status information indicating the operating status of the memory device. The value of the data stored in status register 154 can be changed according to the operation of the memory device.

[0132] Reference Figure 10 The status information stored in the status register 154 may include ready information 154_1, valid read level information 154_2, and failure information 154_3.

[0133] Readiness information 154_1 can indicate that the memory device is waiting to execute a new command. In an embodiment, readiness information 154_1 can indicate that a new command can be received and the operation based on a previously received command can be completed. The memory controller can know from readiness information 154_1 whether the operation based on the previously provided command has been completed.

[0134] The valid read level information 154_2 can be information indicating whether the voltage used to perform the operation is within the effective voltage range. Specifically, when the valid read level information 154_2 is in a set state, it can indicate that the voltage used to perform the operation is within the effective voltage range, and when the valid read level information 154_2 is in a released state, it can indicate that the voltage used to perform the operation is not within the effective voltage range. In an embodiment, the set state can be represented as "0" and the released state can be represented as "1". Optionally, the set state can be represented as "1" and the released state can be represented as "0".

[0135] Failure message 154_3 can indicate that the operation corresponding to the most recently executed command failed. In embodiments, failure message 154_3 may only have valid values ​​for programming and erasing operations. In various embodiments, failure message 154_3 can also indicate that the operation corresponding to a command received before the most recent command failed.

[0136] Figure 11 It is shown Figure 1 A diagram illustrating the operation of the read operation controller 210 and the read level manager 220 of the memory controller 200.

[0137] Reference Figure 11 After providing a read command to the memory device 100, when a preset time has elapsed, the read operation controller 210 may provide the memory device 100 with a status read command STATUS READ requesting status information stored in the status register included in the memory device 100.

[0138] The read operation controller 210 can receive a status read response (STATUS READ RESPONSE) provided by the memory device 100 in response to the status read command (STATUS READ). The read operation controller 210 can obtain the valid read level information included in the status read response (STATUS READ RESPONSE) and provide the obtained valid read level information to the read level manager 220.

[0139] The read level manager 220 can provide the memory device 100 with a read voltage change command that indicates a change in the read voltage level. Specifically, the read level manager 220 can provide the read voltage change command to the memory device 100 using a parameter setting command (setting parameters) or a feature setting command (setting features). For example, the read level manager 220 can provide the memory device 100 with the address of the read level register included in the memory device 100 and the data corresponding to the read level to be changed by using a parameter setting command (setting parameters) or a feature setting command (setting features).

[0140] In this embodiment, the read level manager 220 can provide the memory device 100 with a read voltage change command that indicates a change in the read voltage level, based on valid read level information. When the read voltage level used to perform the read operation is not within the valid read voltage range, a read voltage change command can be provided to the memory device 100.

[0141] In this specification, refer to Figures 7 to 11The operation of the memory device and memory controller is described using a read operation as an example, but this is for ease of description, and the content of the disclosed technology is not limited to the read operation. That is, during programming or erasing operations, the memory device can provide the memory controller with a status read response (STATUS READ RESPONSE) regarding whether the level of the operating voltage is an effective voltage level in the same manner.

[0142] Figure 12 This illustrates some implementation schemes based on the disclosed technology. Figure 1 A diagram illustrating an embodiment of the memory controller.

[0143] Reference Figure 1 and Figure 12 The memory controller 1300 may include a processor 1310, RAM 1320, error correction code (ECC) circuitry 1330, ROM 1360, host interface 1370, and flash memory interface 1380.

[0144] The processor 1310 can control all operations of the memory controller 1300. The RAM 1320 can be used as a buffer memory, cache memory, and operation memory of the memory controller 1300.

[0145] ROM 1360 can store various information required for the memory controller 1300 to operate in the form of firmware.

[0146] The memory controller 1300 can communicate with external devices (e.g., host 400, application processor, etc.) via host interface 1370.

[0147] The memory controller 1300 can communicate with the memory device 100 via the flash interface 1380. The memory controller 1300 can transmit commands (CMD), addresses (ADDR), control signals (CTRL), etc., to the memory device 100 and receive data (DATA) via the flash interface 1380. For example, the flash interface 1380 may include a NAND interface.

[0148] Figure 13 This is a block diagram illustrating a memory card system including a storage device based on an embodiment of the disclosed technology.

[0149] Reference Figure 13 The memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0150] Memory controller 2100 is connected to memory device 2200. Memory controller 2100 is configured to access memory device 2200. For example, memory controller 2100 may be configured to control read operations, programming operations, erase operations, and background operations of memory device 2200. Memory controller 2100 is configured to provide an interface between memory device 2200 and a host computer. Memory controller 2100 is configured to perform firmware operations for controlling memory device 2200. Memory controller 2100 may be used with reference to... Figure 1 The memory controller 200 described is implemented in the same manner.

[0151] For example, memory controller 2100 may include components such as random access memory (RAM), processor, host interface, memory interface, and error corrector.

[0152] The memory controller 2100 can communicate with external devices via connector 2300. The memory controller 2100 can communicate with external devices (e.g., a host) according to specific communication standards. For example, the memory controller 2100 is configured to communicate with external devices via at least one of the following communication standards: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. For example, connector 2300 can be defined by at least one of the aforementioned communication standards.

[0153] For example, memory device 2200 can be configured with various non-volatile memory devices such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0154] The memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to configure a memory card. For example, the memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to configure memory cards such as PC cards (Personal Computer Memory Card International Association (PCMCIA)), compact flash (CF) cards, smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, micro MMC or eMMC), SD cards (SD, mini SD, micro SD or SDHC), or universal flash memory (UFS).

[0155] Figure 14 This is a block diagram illustrating a solid-state drive (SSD) system including a storage device based on an embodiment of the disclosed technology.

[0156] Reference Figure 14 The SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals with the host 3100 through a signal connector 3001 and receives power through a power connector 3002. The SSD 3200 includes an SSD controller 3210, multiple non-volatile memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0157] According to embodiments of the disclosed technology, the SSD controller 3210 can perform reference... Figure 1 The functions of the memory controller 200 are described.

[0158] SSD controller 3210 can control multiple non-volatile memories 3221 to 322n in response to signals received from host 3100. For example, the signals can be signals based on the interface between host 3100 and SSD 3200. For example, the signals can be signals defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0159] Auxiliary power supply 3230 is connected to host 3100 via power connector 3002. Auxiliary power supply 3230 can receive power from host 3100 and can be charged. When the power supply from host 3100 is unstable, auxiliary power supply 3230 can provide power to SSD 3200. For example, auxiliary power supply 3230 can be located inside SSD 3200 or external to SSD 3200. For example, auxiliary power supply 3230 can be located on the motherboard and can provide auxiliary power to SSD 3200.

[0160] Buffer memory 3240 operates as a buffer memory for SSD 3200. For example, buffer memory 3240 may temporarily store data received from host 3100 or data received from multiple non-volatile memories 3221 to 322n, or it may temporarily store metadata (e.g., mapping tables) of non-volatile memories 3221 to 322n. Buffer memory 3240 may include volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0161] Figure 15 This is a block diagram illustrating a user system including a storage device based on an embodiment of the disclosed technology.

[0162] Reference Figure 15 The user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0163] Application processor 4100 can drive components, operating system (OS), user programs, etc., included in user system 4000. For example, application processor 4100 may include controllers, interfaces, graphics engines, etc., that control components included in user system 4000. Application processor 4100 can be configured as a system-on-a-chip (SoC).

[0164] Memory module 4200 can operate as main memory, working memory, buffer memory, or cache memory of user system 4000. Memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memory such as FRAM, ReRAM, MRAM, and PRAM. For example, application processor 4100 and memory module 4200 may be packaged in a stacked package (POP) and configured as a single semiconductor package.

[0165] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), LTE, WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. For example, network module 4300 may be included in application processor 4100.

[0166] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Optionally, storage module 4400 can transfer data stored therein to application processor 4100. For example, storage module 4400 can be implemented using non-volatile semiconductor memory elements such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, and 3D NAND flash memory. For example, storage module 4400 can be provided as a removable storage device (removable drive) such as a memory card and external drive for user system 4000.

[0167] For example, storage module 4400 may include multiple non-volatile memory devices, and the multiple non-volatile memory devices may be configured with reference to... Figure 1 The memory device 100 described operates in the same manner. The memory module 4400 can operate in the same manner as the referenced... Figure 1 The storage device 50 described operates in the same manner.

[0168] User interface 4500 may include interfaces for inputting data or instructions to application processor 4100 or for outputting data to external devices. For example, user interface 4500 may include user input interfaces such as: keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric element. User interface 4500 may include user output interfaces such as: liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active-matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0169] Only some examples or embodiments of the disclosed technology have been described. Based on the disclosure, variations of the disclosed examples or embodiments, as well as other embodiments, are possible.

Claims

1. A memory device comprising: a memory cell array including a plurality of memory cells; a peripheral circuit coupled to the memory cell array and performing an operation on a memory cell selected among the plurality of memory cells; a register containing information on a voltage used for the operation; an operation handler in communication with the register to receive information on a voltage used for the operation, in communication with a memory controller external to the memory device to receive a command from the memory controller to perform the operation, and controlling the peripheral circuit to perform the operation on the selected memory cell using the voltage and to generate status information on a status of the operation; a voltage information generator in communication with the register and generating voltage information indicating whether the voltage is within a preset voltage range in response to the command; and a status register in communication with the voltage information generator and storing the status information and the voltage information, wherein the operation handler skips the operation in response to voltage information indicating that the voltage is not within the preset voltage range and stores ready information to the status register.

2. The memory device of claim 1, wherein the operation handler receives a voltage change command from the memory controller to change the voltage.

3. The memory device of claim 2, wherein the peripheral circuit performs the operation as a read operation to read data stored in the memory cell selected among the plurality of memory cells, the register includes a read level register including information on a level of a read voltage used for the read operation, the operation handler generates ready information indicating that the read operation is completed, and the voltage information generator generates valid read level information indicating whether the voltage is within a preset valid read voltage range.

4. The memory device of claim 2, wherein the operation handler updates the information on the voltage stored in the register based on the voltage change command.

5. The memory device of claim 1, wherein the information on the voltage contained in the register is set by the memory controller.

6. The memory device of claim 1, wherein the voltage information generator generates the voltage information indicating validity of the voltage based on whether the voltage is within the preset voltage range.

7. The memory device of claim 2, wherein the voltage change command corresponds to a parameter set command or a feature set command.

8. The memory device of claim 1, wherein the memory cell array further includes a storage storing the preset voltage range.

9. The memory device of claim 8, wherein the operation handler stores the preset voltage range obtained from the storage in a read level register.

10. The memory device of claim 1, wherein the operation handler provides the status information to the memory controller after performing the operation.

11. A memory device comprising: an array of memory cells including a plurality of memory cells each storing data; a peripheral circuit coupled to the array of memory cells and performing a read operation to read data stored in a selected memory cell among the plurality of memory cells; a read level register containing information about a level of a read voltage used for the read operation; a voltage information generator generating voltage information indicating whether the read voltage is within a preset voltage range; a read operation handler controlling whether the peripheral circuit reads data from the selected memory cell using the read voltage and generating status information about completion of the read operation; and a status register storing the status information and the voltage information, wherein the read operation handler skips the read operation and stores the status information to the status register in response to the voltage information indicating that the read voltage is not within the preset voltage range.

12. The memory device of claim 11, wherein the read operation handler controls the peripheral circuit to read data from the selected memory cell using the read voltage in response to the voltage information indicating that the read voltage is within the preset voltage range.

13. The memory device of claim 11, wherein the read operation handler receives a read voltage change command from a memory controller in communication with the memory device to change the level of the read voltage.

14. The memory device of claim 11, wherein the read level register includes the preset voltage range between a minimum voltage level and a maximum voltage level.

15. The memory device of claim 13, wherein the read operation handler updates the information about the level of the read voltage stored in the read level register based on the read voltage change command.

16. The memory device of claim 11, wherein the information about the level of the read voltage is set by a memory controller in communication with the memory device.

17. The memory device of claim 11, wherein the voltage information generator generates the voltage information indicating validity of the read voltage based on whether the read voltage is within the preset voltage range.

18. The memory device of claim 11, wherein the read operation handler provides the status information to a memory controller in communication with the memory device after performing the read operation.

19. A memory device comprising: a memory device including a memory cell storing data and a circuit generating voltage information indicating whether a voltage used for performing an operation on the memory cell is included in a preset voltage range; and a memory controller in communication with the memory device. ​ a memory controller in communication with the memory device and the memory controller: 1) transmits to the memory device a status command requesting a status response indicating a status of the operation; and 2) controls the memory device to change a voltage used to perform the operation based on the status response provided from the memory device and including the voltage information, wherein when the voltage information indicates that the voltage is not within the pre-set voltage range, the memory device skips the operation and stores status information related to completion of the operation to a status register included in the memory device.

Images