Tri-value programming mechanism for non-volatile memory structures

Abstract

This invention discloses a method for programming three pages of user data in a memory array of a non-volatile memory system, comprising: converting each three-bit data pattern of the user data into a pair of representative two-bit data values; simultaneously programming two single-state memory cells with the first of the pair of representative two-bit data values, wherein the two single-state memory cells are located along a first common word line of the two memory cell strings; and simultaneously programming two single-state memory cells with the second of the pair of representative two-bit data values, wherein the two single-state memory cells are located along a second common word line of the two memory cell strings.

Description

Technical Field

[0001] This disclosure relates to non-volatile memory storage systems in solid-state drives or other devices, including but not limited to flash drives or embedded / removable flash packages. More specifically, this disclosure relates to systems and methods for programming non-volatile memory structures. Background Technology

[0002] Due to emerging technological and market forces, solid-state drives (SSDs) have steadily replaced previous conventional data storage systems (e.g., hard disk drives) that relied on the rotation of magnetic media for reading and writing data. Solid-state memory does not include any mechanical or moving parts, but rather comprises integrated circuit components or interconnected flash memory components to provide non-volatile storage devices, where stored data is continuously retained even during planned or unplanned power outages. Therefore, compared to disk-based storage devices, solid-state drives are inherently faster and more robust (i.e., less susceptible to data loss and corruption), consume less power, and are more compact. Thus, non-volatile memory is a powerful storage solution relative to many types of computing, consumer electronics, and standalone external storage devices (e.g., USB drives).

[0003] Unlike some flash memory types, each individual memory cell includes a floating gate positioned above and isolated from the channel region of the semiconductor substrate, with the floating gate located between the source and drain regions. Additionally, a control gate is disposed above and isolated from the floating gate. Therefore, the resulting transistor's threshold voltage (V...) th The threshold voltage characteristic of the transistor is controlled by and depends on the amount of charge held on the floating gate. Specifically, in a switch-like manner, the minimum voltage that must be applied to the control gate before activating the transistor to allow conduction between its source and drain is determined by the charge level held on the floating gate. Therefore, bit value data can be programmed into and erased from the memory cell by changing the charge level on the floating gate to alter the threshold voltage characteristic of the transistor.

[0004] As explained in detail below, the number of bits that can be stored in a single memory cell depends on the number of different voltage ranges that can be divided within the threshold voltage window of that memory cell. For example, to store one bit of data (called binary data), the possible threshold voltages (V) of the memory cell are... th The memory cell is divided into two ranges, which are designated as logical data "1" and "0" respectively. This type of memory density can be called a "single-level cell" or SLC.

[0005] Multi-level information can be stored by further dividing the threshold voltage window of a memory cell into additional different voltage ranges. Such memory cells can be called "polymorphic cells." For example, to store two bits of data, the threshold voltage window of the cell can be divided into four different voltage ranges (or states), where each range is assigned a bit value equal to, for example, "11", "10", "01", and "00". Therefore, after an erase operation, the threshold voltage is negative and can be defined as logic "11". Thus, positive threshold voltages are used for the states "10", "01", and "00". Memory cells with this storage density can be called "multi-level cells" or MLCs. In another example, to store three bits of data, the voltage threshold window of the cell can be divided into eight different voltage ranges (or states), where each range is assigned a bit value equal to, for example, "111", "110", "100", "010", "011", "000", "001", and "101". Memory cells with this storage density can be called "triple-level cells" or "three-level cells" (TLCs). The specific relationship between the data programmed into the memory cell and the threshold voltage level of the memory cell depends on the data encoding scheme used by the memory cell.

[0006] Therefore, memory devices incorporating polymorphic data (through the combination of MLC and / or TLC type cells) offer increased storage capacity using the same MOSFET structure and wafer size as SLC type cells, thus providing considerable unit cost savings. However, programming occurs more slowly than with single-state memory cells due to the increased density of polymorphic memory cells and the tight tolerances between the divided voltage ranges, as data is programmed to multiple target threshold voltage ranges and a higher level of accuracy is required during programming. The increased density of polymorphic memory cells reduces the margin of error between state changes and decreases the available voltage range capacity required to withstand stress on the silicon oxide layer during consecutive program / erase cycles. Consequently, the durability of polymorphic memory elements is significantly lower compared to single-state memory cells. Therefore, for some applications, memory systems comprising only single-state memory cells are most suitable. However, in other applications, there are technologies employing memory dies that primarily store data in memory cells storing polymorphic data. Furthermore, in some memory systems, data is first programmed into a cache (using one or more data latches) of single-state memory cells storing binary data to take advantage of the faster programming speed of these memory cells. Subsequently, when the memory system is idle or busy with other data operations, the cache of the single-state memory cells storing binary data then transfers the stored data to polymorphic memory cells storing polymorphic data, thereby utilizing the larger storage capacity provided by the polymorphic memory cells. This beneficial mechanism for transferring data from single-state memory cells to polymorphic memory cells is known in the industry as a "folding" operation and is described in detail below. Therefore, multiple data latches can be employed in flash memory systems that program data into single-state memory cells and, in some cases, into polymorphic memory cells.

[0007] However, while using internal "folding" operations to program higher-density memory storage devices improves programming speed (and thus overall performance), the fact that "folding" operations still require at least two stages (i.e., initial programming of single-state memory cells and subsequent rewriting of polystate memory cells) adds complexity and processing time to memory device operations. Therefore, it would be beneficial to be able to optimize one or both of these stages to further improve its efficiency. Summary of the Invention

[0008] Various implementations include a method for programming three pages of user data in a memory array of a non-volatile memory system, wherein the method includes: converting each three-bit data pattern of the user data into a pair of representative two-bit data values; simultaneously programming two single-state memory cells with a first of the pair of representative two-bit data values, wherein the two single-state memory cells are located along a first common word line of the two memory cell strings; and simultaneously programming two single-state memory cells with a second of the pair of representative two-bit data values, wherein the two single-state memory cells are located along a second common word line of the two memory cell strings. Additionally, the two memory cell strings may be located adjacent to each other or in relatively close physical proximity.

[0009] Other embodiments include a memory controller including a first port configured to be coupled to a non-volatile memory structure, wherein the memory structure includes a memory array. The memory controller is configured to: convert each three-bit data pattern in a three-page user dataset into a pair of representative two-bit data values; simultaneously program two single-state memory cells with a first of the pair of representative two-bit data values, wherein the two single-state memory cells are located along a first common word line of two memory cell strings in the memory array; and simultaneously program two single-state memory cells with a second of the pair of representative two-bit data values, wherein the two single-state memory cells are located along a second common word line of the two memory cell strings. Additionally, the two memory cell strings may be located adjacent to each other or in relatively close physical proximity.

[0010] An additional embodiment includes a non-volatile memory system comprising: a memory array; and a memory controller coupled to the memory array and converting each three-bit data pattern in a three-page user dataset into a pair of representative two-bit data values; simultaneously programming two single-state memory cells with a first of the pair of representative two-bit data values, wherein the two single-state memory cells are located along a first common word line of two memory cell strings of the memory array; and simultaneously programming two single-state memory cells with a second of the pair of representative two-bit data values, wherein the two single-state memory cells are located along a second common word line of the two memory cell strings. Furthermore, the two memory cell strings may be located adjacent to each other or in relatively close physical proximity. Attached Figure Description

[0011] A more detailed description is set forth below with reference to the exemplary embodiments depicted in the accompanying drawings. It should be understood that these drawings depict only exemplary embodiments of this disclosure and are therefore not intended to be considered as limiting its scope. The disclosure is described and explained with added specificity and detail using the drawings, in which:

[0012] Figure 1 This is a block diagram of a memory system according to an exemplary embodiment;

[0013] Figure 2 This is a schematic depiction of a non-volatile memory cell according to an exemplary embodiment;

[0014] Figure 3 The source-drain current I of four different charges Q1 to Q4, which can be selectively stored at any time and stored with a fixed drain voltage, is depicted according to an exemplary embodiment for a non-volatile memory cell. D With control gate voltage V CG The relationship between them;

[0015] Figure 4A A series of NAND-type memory cells organized into a string according to an exemplary embodiment is schematically depicted;

[0016] Figure 4B A memory cell array according to an exemplary embodiment is schematically depicted, the memory cell array comprising a plurality of NAND type strings, such as Figure 4A The types described in the text;

[0017] Figure 5 A page of memory cell, which is sensed or programmed in parallel and associated with a memory array organized in a NAND-type configuration, is depicted according to an exemplary embodiment.

[0018] Figure 6A An alternative configuration of NAND-type strings arranged in a memory block structure according to an exemplary embodiment is schematically depicted;

[0019] Figure 6B A schematic depiction of a structure comprising multiple NAND-type memory blocks (such as...) according to an exemplary embodiment is shown. Figure 6A A memory cell array of the type shown;

[0020] Figures 7A to 7C The stages for programming four states of a group of MLC-type memory cells according to an exemplary embodiment are described;

[0021] Figures 8A to 8C The stages for programming a group of TLC-type memory cells according to an exemplary embodiment are described;

[0022] Figure 9 A vertical NAND string is depicted according to an exemplary embodiment;

[0023] Figure 10 A configuration of a nonvolatile memory array accessible by read / write circuitry via row decoder and column decoder according to an exemplary embodiment is schematically depicted.

[0024] Figure 11 This is a block diagram of a separate read / write module according to an exemplary implementation scheme;

[0025] Figure 12A A memory device having a partitioned read / write stack library is schematically depicted according to an exemplary embodiment;

[0026] Figure 12B The illustration schematically depicts a configuration in a slightly different way according to an exemplary embodiment. Figure 12A Memory devices;

[0027] Figure 13 A read / write stack (such as) according to an exemplary embodiment is schematically depicted. Figure 12A The various components of the read / write stack (described in the text);

[0028] Figure 14A An arrangement in a memory device (such as...) according to an exemplary embodiment is schematically depicted. Figure 12A Multiple read / write stacks in the read / write circuitry of the memory device depicted in the image;

[0029] Figure 14B It describes a read / write stack (such as) according to an exemplary implementation. Figure 12A A block diagram of the sensing block (read / write stack) depicted in the image;

[0030] Figure 15 An alternative configuration of a non-volatile memory array, accessible by read / write circuitry via row and column decoders according to an exemplary embodiment, is schematically depicted.

[0031] Figure 16A A read / write circuit (such as) according to an exemplary embodiment is schematically depicted. Figure 15 The various components of the read / write circuit depicted in the diagram;

[0032] Figure 16B A more detailed schematic depiction of the exemplary embodiment is provided. Figure 16A Part of the read / write circuit;

[0033] Figure 17 TLC programming operations according to an exemplary embodiment are shown;

[0034] Figure 18 An internal folding process during programming operation is illustrated according to an exemplary embodiment;

[0035] Figure 19 The illustration shows a memory-on-folding process for rewriting data in binary format from multiple word lines into a polymorphic format according to an exemplary embodiment;

[0036] Figure 20 A more detailed description is provided based on the exemplary embodiment. Figure 19 All aspects of the folding process;

[0037] Figures 21A to 21D An exemplary procedure for programming operations on a three-page dataset SLC according to an exemplary embodiment is shown, wherein two memory strings are written simultaneously along a common word line;

[0038] Figure 22 A set of methods for converting a three-page dataset into representative two-digit data values ​​is shown for use in accordance with... Figures 21A to 21D The process of programming; and

[0039] Figure 23 An exemplary procedure for programming operations on a four-page dataset SLC is shown according to an exemplary embodiment, wherein three memory strings are written simultaneously along two common word lines. Detailed Implementation

[0040] The following description relates to various embodiments of this disclosure. While one or more of these embodiments may be preferred, the disclosed embodiments should not be construed as or otherwise used to limit the scope of this disclosure, including the claims. Furthermore, those skilled in the art will understand that the following description has broad application, and the detailed explanation of any particular embodiment is intended only as an example of that embodiment and is not intended to imply that the scope of this disclosure (including the claims) is limited to that particular embodiment.

[0041] Several aspects of this disclosure may be embodied in the form of an apparatus, system, method, or computer program process. Therefore, aspects of this disclosure may be entirely in the form of a hardware implementation or a software implementation (including, but not limited to, firmware, resident software, microcode, etc.), or may be a combination of hardware and software components, which are generally referred to collectively as a “circuit,” “module,” “apparatus,” or “system.” Additionally, aspects of this disclosure may be, for example, in the form of a computer program process embodied in one or more non-transitory computer-readable storage media storing computer-readable program code and / or computer-executable program code.

[0042] Additionally, various terms are used herein to refer to specific system components. Different companies may use different names to refer to the same or similar components, and this document is not intended to distinguish components with different names rather than different functions. With regard to the various functional units described in the following disclosure being referred to as “modules,” this designation is intended not to unduly limit the scope of possible implementation mechanisms. For example, a “module” may be implemented as hardware circuitry comprising custom-designed very large-scale integration (VLSI) circuitry or gate arrays, or as off-the-shelf semiconductors comprising logic chips, transistors, or other discrete components. In another example, modules may also be implemented in programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic units, programmable logic devices, etc. Furthermore, modules may also be implemented, at least in part, by software executed by various types of processors. For example, a module may include executable code segments that constitute one or more physical or logical blocks of computer instructions that translate into objects, procedures, or functions. Furthermore, it is not required that the executable portions of such modules be physically located together, but rather that they may include different instructions stored in different locations, and when executed together, constitute the identified module and achieve the stated purpose of the module. Executable code may include a single instruction or a collection of instructions, and may be distributed across different code segments, different programs, or multiple memory devices. In specific implementations of software or portions of software modules, the software portions may be stored on one or more computer-readable and / or executable storage media, including but not limited to electronic, magnetic, optical, electromagnetic, infrared, or semiconductor-based systems, apparatuses, or devices, or any suitable combination thereof. Generally, for the purposes of this disclosure, computer-readable and / or executable storage media may include any tangible and / or non-transitory medium capable of containing and / or storing programs for use by or in connection with an instruction execution system, apparatus, processor, or device.

[0043] Similarly, for the purposes of this disclosure, the term "component" can refer to any tangible, physical, and non-transient device. For example, a component can be in the form of hardware logic circuitry composed of custom VLSI circuitry, gate arrays, or other integrated circuits, or of off-the-shelf semiconductors including logic chips, transistors, or other discrete components, or any other suitable mechanical and / or electronic equipment. Furthermore, components can also be implemented in programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic components, programmable logic devices, etc. Additionally, a component can be composed of one or more silicon-based integrated circuit devices (such as chips, dies, die planes, and packages) or other discrete electrical devices, which are electrically connected to one or more other components via electrical conductors such as printed circuit boards (PCBs). Therefore, modules as defined above can be embodied or implemented as components in some embodiments, and in some cases, the terms module and component are used interchangeably.

[0044] As used herein, the term "circuit" includes one or more electrical and / or electronic components that form one or more conductive paths allowing current to flow. A circuit can be in the form of a closed-loop configuration or an open-loop configuration. In a closed-loop configuration, the circuit components may provide a return path for current. In contrast, in an open-loop configuration, the circuit components may be considered to form a circuit, although a return path for current is not included. For example, an integrated circuit is referred to as a circuit regardless of whether it is grounded (as a return path for current). In some exemplary embodiments, a circuit may include a set of integrated circuits, a single integrated circuit, or a portion of an integrated circuit. For example, a circuit may include custom VLSI circuitry, gate arrays, logic circuitry, and / or other forms of integrated circuits, and may include off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices. In another example, a circuit may include one or more silicon-based integrated circuit devices (such as chips, dies, die planes, and packages) or other discrete electrical devices that are electrically connected to one or more other components via electrical conductors, such as a printed circuit board (PCB). A circuit may also be implemented as a composite circuit relative to programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic components, and / or programmable logic devices. In other exemplary embodiments, the circuit may include a network of non-integrated electrical and / or electronic components (with or without integrated circuit devices). Therefore, in some embodiments, modules as defined above may be embodied or implemented as circuits.

[0045] It should be understood that the exemplary embodiments disclosed herein may include one or more microprocessors and specifically stored computer program instructions that control one or more microprocessors to implement some, most, or all of the functions disclosed herein in conjunction with certain non-processor circuitry and other elements. Alternatively, some or all of the functions may be implemented by a state machine without stored program instructions or in one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs), wherein each function or some combinations of certain functions is implemented as custom logic. Combinations of these methods may also be used. Therefore, methods and apparatus for these functions are described herein. Furthermore, the reference to “controller” below should be defined as including individual circuit components, application-specific integrated circuits (ASICs), microcontrollers with control software, digital signal processors (DSPs), field-programmable gate arrays (FPGAs) and / or processors with control software, or combinations thereof.

[0046] Furthermore, as used herein, the terms “program,” “software,” “software application,” etc., refer to a sequence of instructions designed to be executed on a computer-implemented system. Therefore, “program,” “software,” “application,” “computer program,” or “software application” can include subroutines, functions, procedures, object methods, object implementations, executable applications, applets, service applets, source code, object code, shared libraries / dynamically loaded libraries, and / or other sequences of specific instructions designed to be executed on a computer system.

[0047] Additionally, as used herein, the terms “couple,” “coupled,” or “couples” are intended to indicate a direct or indirect connection. Therefore, if a first device is coupled to or is coupled to a second device, the connection can be made either directly or indirectly via other devices (or components) and connections.

[0048] Regarding the use of terms such as “implementation,” “one implementation,” “exemplary implementation,” “specific implementation,” or other similar terms herein, these terms are intended to indicate that a specific feature, structure, function, operation, or characteristic described in connection with that implementation exists in at least one embodiment of this disclosure. Therefore, the appearance of phrases such as “in one implementation,” “in an implementation,” “in a particular implementation,” etc., may, but not necessarily, refer to the same implementation, but rather to “one or more, but not all, implementations,” unless expressly stated otherwise. Furthermore, the terms “comprising,” “having,” “including,” and variations thereof are used in an open-ended manner and should therefore be construed as meaning “including, but not limited to…,” unless expressly stated otherwise. Additionally, an element preceded by “comprising…” does not exclude the presence of additional identical elements in the subject matter process, method, system, article, or apparatus that includes that element, unless further limited.

[0049] The terms “a,” “an,” and “the” also mean “one or more” unless otherwise expressly stated. Furthermore, the phrase “at least one of A and B” (where A and B are variables indicating a particular object or property) used herein and / or in the appended claims indicates a choice of A or B, or a choice of both A and B, similar to the phrase “and / or.” Where more than two variables are present in such a phrase, the phrase is thereby defined as including only one of the variables, any of the variables, any combination (or subcombination) of any of the variables, and all of the variables.

[0050] Furthermore, as used herein, the terms “about” or “approximately” apply to all numerical values, whether explicitly stated or not. These terms generally refer to a range of numerical values ​​that a person skilled in the art would consider equivalent to (e.g., having the same function or result) the value referenced. In some cases, these terms may include numerical values ​​rounded to the nearest significant figure.

[0051] Furthermore, any enumerated list of items presented herein does not imply that any or all of the listed items are mutually exclusive and / or mutually inclusive, unless otherwise expressly stated. Additionally, as used herein, the term “group” should be interpreted as “one or more” according to the established theory, and in the case of “multiple groups”, it should be interpreted as a plural (or multiple) number of “one or more,” “ones or more,” and / or “ones or mores,” unless otherwise expressly stated.

[0052] Various elements of this disclosure are described below with reference to schematic flowcharts and / or schematic block diagrams depicting methods, apparatus, systems, and computer program processes according to exemplary embodiments of this disclosure, wherein each block or combination of blocks in the schematic flowcharts and / or block diagrams may be implemented by specifically written computer program instructions. As understood in the art, computer program instructions are executed by a designated processor of a computer or other programmable data processing means, thereby creating mechanisms for implementing the functions, actions, and / or operations specifically set forth in one or more blocks of the schematic flowcharts and / or block diagrams. Furthermore, it should be noted that in some alternative process implementations, the functions specified in the blocks may not occur in the precise order depicted in the schematic flowcharts and / or block diagrams. For example, two blocks depicted as occurring consecutively in the figures may actually be executed substantially simultaneously (i.e., concurrently), or even in reverse order, depending on the functions involved. Additionally, other process steps and methods that are functionally, logically, or effectively equivalent to one or more blocks or portions thereof illustrated in the figures may be conceived and contemplated within the scope of this disclosure. Furthermore, while the diagrams may depict various arrow types, directions, and line types for illustrative purposes, they are not intended to limit the scope of the corresponding embodiments. For example, an arrow may indicate or imply a waiting or monitoring period of unspecified duration between enumerated steps of the illustrated exemplary embodiment.

[0053] In the following detailed description, reference is made to the accompanying drawings, which form a part thereof. It will be appreciated that the foregoing summary is merely exemplary and not intended to be limiting in any way. In addition to the illustrative aspects, exemplary embodiments, and features described above, further aspects, exemplary embodiments, and features will become apparent from the accompanying drawings and the following detailed description. The description of elements in each figure may refer to elements in the preceding figures. Similar reference numerals may refer to similar elements in the drawings, including alternative exemplary embodiments of similar elements.

[0054] Now refer to the accompanying drawings in detail and from... Figure 1The illustration begins by depicting an exemplary embodiment of the memory system 90 and illustrating its main hardware components. In this specific embodiment, the memory system 90 operates and communicates with a host device 80 via a host interface. Furthermore, the memory system 90 includes a memory device 102 whose operation is controlled by a controller 100. The host device 80 may include any device or system (e.g., a computing device) utilizing the memory system 90. Therefore, the memory system 90 may be in the form of a removable memory card or an embedded memory system. For example, the memory system 90 may be embedded in a solid-state drive installed in a laptop computer. In another example, the memory system 90 may be embedded within the host device 80, such that the host 80 and the memory system 90 (including the controller 100) are formed on a single integrated circuit chip. In an embodiment where the memory system 90 is implemented within a memory card, the host device 80 may include a built-in socket for one or more types of memory cards or flash drives (e.g., a Universal Serial Bus (USB) port or a memory card slot). Additionally, the host 80 may use an adapter in which a memory card is inserted.

[0055] Still referencing Figure 1 As detailed below, memory device 102 may include one or more memory arrays comprising a plurality of non-volatile memory cells distributed across one or more integrated circuit chips. Furthermore, according to this specific embodiment, controller 100 may include a number of components, including but not limited to interface circuitry 110, processor 120, ROM (Read-Only Memory) 122, RAM (Random Access Memory) 130, programmable non-volatile memory 124, and additional components. Controller 100 may be, for example, in the form of one or more application-specific integrated circuits (ASICs), including components in such ASICs that are typically application-specific.

[0056] Relative to the memory device 102 itself, Figure 2 This is a schematic diagram of a single non-volatile memory cell 10 according to an exemplary embodiment. As described above, the memory cell 10 can be implemented by a field-effect transistor having a charge storage cell 20 (such as a floating gate or dielectric layer). Furthermore, the memory cell 10 includes a source region 14 and a drain region 16. Additionally, a control gate 30 is positioned above the floating gate 20. Exemplary types of non-volatile memory cells having this general structure include, but are not limited to, electrically erasable programmable read-only memory (EEPROM) and flash memory EEPROM, NAND (NOT-AND) type cells, and memory devices utilizing dielectric storage elements (e.g., NROM). TMIn operation, according to certain embodiments, when a reference voltage is applied to the control gate 30, the memory state of the cell (e.g., programming or erasing) can be read by sensing the conduction current across the source and drain electrodes of the memory cell. More specifically, for each given charge on the floating gate 20 of the memory cell, a corresponding conduction current relative to a fixed reference control gate voltage can be detected. Thus, as described above, a range of charges programmable onto the floating gate defines a corresponding threshold voltage window or a corresponding conduction current window for the memory cell 10. Alternatively, instead of detecting the conduction current within a defined current window, a threshold voltage can be set at the control gate 30 for a given memory state under test, and the resulting conduction current can be detected as being higher or lower than the threshold current (i.e., the cell read reference current). In one such exemplary embodiment, the detection of the conduction current relative to the threshold current is achieved by examining the discharge rate of the conduction current through the capacitance of the bit line.

[0057] Figure 3 Provides, for example, a source-drain current I of a non-volatile memory cell 10 having four different charge states Q1 to Q4 that can be selectively stored at any given time with a floating gate. D With control gate voltage V CG A graphical illustration of the correlation between them. As shown in the figure, using a fixed drain voltage bias, there are four solid lines I representing the four charge levels that can be programmed on the floating gate of a memory cell. D For V CG The curves represent four charge levels, each corresponding to one of eight possible memory states. Therefore, for example, the threshold voltage window for a group of memory cells can range from 0.5V to 3.5V. In such an example, seven programmable memory states are designated as "0", "1", "2", "3", "4", "5", and "6", respectively, along with one erase state (which is in...). Figure 3 (Not shown in the figure) can be defined by dividing the threshold window into regions spaced 0.5V apart. Therefore, if a reference current I of 2μA is used as shown in the figure... REF Then, a cell programmed with voltage Q1 can be considered to be in memory state "1" because its curve is defined by the voltage range V. CG =0.5V and 1.0V in the threshold window region with I REF Intersecting. Similarly, Q4 is in memory state "5".

[0058] Therefore, as described above, the more states the memory cell 10 stores, the finer its threshold voltage window needs to be divided. For example, in a memory cell 10 with a threshold voltage window ranging from -1.5V to 5V, thus providing a possible maximum width of 6.5V and storing 16 memory states, each state could occupy only a voltage range of 200mV to 300mV. Such a narrow voltage range would necessitate higher precision in programming and reading operations to achieve the required resolution.

[0059] Individual memory cells 10 are organized into a string, and the memory cells are placed in series within this string. For example, Figure 4A The illustration depicts an exemplary embodiment of a string 50 comprising NAND-type memory cells, wherein the corresponding transistor elements M1, M2, ..., Mn (where "n" can be equal to 4, 8, 16 or higher) of the series of cells are daisy-chained relative to their source and drain. Furthermore, as relative to... Figure 3 As discussed, each memory cell 10 in string 50 has a charge storage element 20 (e.g., a floating gate) for storing a specific amount of charge to indicate the expected memory state of the cell. Furthermore, as explained in more detail below, each memory cell 10 includes a control gate 30 that allows control of read and write operations. Select transistors S1 and S2 are present at the source terminal 54 and drain terminal 56 of string 50, which control the connection of the transistor elements to the external memory array. Specifically, when the source select transistor S1 is turned on, the source terminal 54 is coupled to the source line. Similarly, when the drain select transistor S2 is turned on, the drain terminal 56 is coupled to the bit line of the memory array.

[0060] Expand the hierarchical levels outwards. Figure 4B It is a description of Figure 4A This is a schematic diagram of an exemplary embodiment of a memory array 210 consisting of multiple strings 50 of the type shown. Along each column of the strings 50, bit lines 36 are coupled to the drain terminal 56 of each NAND string. Furthermore, along each cell of the strings 50, source lines 34 are coupled to the source terminal 54 of each NAND string. Additionally, the control gate 30 of a memory cell 10 in a row of memory cells within a cell of the strings 50 is connected to the same word line 42. Therefore, when an addressed memory cell 10 within the string 50 is read or verified during a programming operation, an appropriate voltage is applied to its control gate 30. Simultaneously, the remaining unaddressed memory cells 10 within the string 50 are fully turned on by applying sufficient voltage to their respective control gates 30. Thus, conductive paths are formed from the source of the addressed memory cell 10 to the source terminal 54 of the string 50 and from the drain of the addressed memory cell 10 to the drain terminal 56 of the cell.

[0061] Additionally, the control gate 32 of the select transistors S1, S2 of each string 50 in the memory array 210 provides controllable access to the NAND string at its source terminal 54 and drain terminal 56. The control gate 32 of the select transistors S1, S2 along a row in the library of string 50 is connected to the same select line 44. Therefore, an entire row of memory cells 10 in the library of string 50 can be addressed by applying appropriate voltages to the word line 42 and select line 44 of the library of string 50.

[0062] Now go to Figure 5 This diagram depicts a detailed illustration of a library of strings 50 of a memory array 210 according to an exemplary embodiment thereof. This view is particularly useful for visualizing the row-by-row configuration of the memory array 210, where each row in the array 210 may be referred to as a "page". Thus, physical pages (such as...) Figure 5 Page 60 (represented in the original text) is a set of memory cells 10 that can be sensed or programmed in parallel. In fact, a page is the smallest unit of a memory device that can be programmed or written to. Page programming is implemented by corresponding pages of sense amplifiers 212, where each sense amplifier can be programmed via bit lines (e.g., see...). Figure 5 The corresponding bit lines BL0, BL1, BL2, BL3, BL4, BL5, ..., BLm-1 and BLm shown are coupled to the corresponding string 50. Therefore, page 60 is enabled by the control gates of the plurality of memory cells 10 connected to the common word line 42 in page 60, and each memory cell 10 of page 60 can be accessed via bit line 36 by a sense amplifier. Thus, when page 60 of memory cells 10 is programmed or sensed, a programming or sense voltage, along with an appropriate voltage on the bit line, is applied to the common word line (e.g., word line WL3 relative to page 60).

[0063] Regarding the method of data programming and erasure, it is important to note that, unlike flash memory, memory cells must be programmed from an erased state. In other words, the floating gate 20 must first be cleared of charge, thereby placing the memory cell in an erased state, after which a programming operation can subsequently add the desired amount of charge back to the floating gate 20. Therefore, the charge level on the floating gate 20 cannot be incrementally increased or decreased from its previous programming level. Thus, updated data cannot overwrite existing data in memory cell 10. Instead, updated data must be programmed to a previously unwritten location.

[0064] To improve the performance of erase operations, the array 210 of memory cells 10 is, for example, divided into a large number of memory cell blocks, where a block is the smallest unit of a memory device in which the memory cells contained can be erased together. Furthermore, each block of memory cells 10 can be divided into multiple physical pages 60, where programming operations are performed page by page as described above. Therefore, a logical page is a programming or reading unit containing a number of bits equal to the number of memory cells 10 in a given physical page. For example, in an SLC-type memory device where one bit of data is stored in each memory cell 10, one physical page 60 stores the data of one logical page. Therefore, in an MLC-type memory device where two bits of data are stored in each memory cell 10, one physical page 60 can store the data of two logical pages. Thus, the data of one or more logical pages is typically stored in a row (i.e., page 60) of memory cells. A page 60 can store one or more sectors, where a sector consists of both user data and overhead data. In an exemplary embodiment, a single page 60 can be divided into segments, where each segment contains the minimum number of memory cells 10 that can be written to at once in a basic programming operation.

[0065] See now Figure 6A and Figure 6B This illustrates an alternative configuration of an exemplary embodiment of the memory block or library structure 220 of the memory array 210. According to this embodiment, the memory block structure 220 may consist of, for example, four NAND-type strings 50 connected in parallel such that they share the same word line (WL) 42 connection. However, with... Figures 4A to 4B and Figure 5 Unlike the implementation depicted, each of the four control gates 32 at the drain-select-gate (SGD) terminal is electrically coupled to a separate select line 44. Therefore, each string 50 can be independently selected during memory operation by applying the necessary bias voltage to the corresponding select line 44 of the desired drain-select-gate (SGD). Thus, each string 50 belongs to a different programming page.

[0066] To illustrate an exemplary implementation of the programming phase of an MLC-type memory device comprising a group of four-state memory cells, reference is made to... Figures 7A to 7C .exist Figure 7A The diagram depicts a group of memory cells, where the characteristic threshold voltage window is divided into four distinct voltage distributions, each corresponding to a programmable memory state (i.e., memory states “0”, “1”, “2”, and “3”). Figure 7B The initial distribution of the "erased" threshold voltage of the erased memory is shown. Figure 7CIn this configuration, a majority of the memory cell group is programmed such that the initial "erased" threshold voltage of a given memory cell 10 is shifted to a higher value, entering one of the three voltage dividers defined by verification levels vV1, vV2, and vV3. Therefore, each memory cell can be programmed into one of three programmable states "1", "2", and "3", or remain in the "erased" state. At the bit level, a 2-bit code with a lower and a higher bit can be used to represent each of the four memory states. For example, as... Figure 7C As depicted, memory states “0”, “1”, “2”, and “3” can be assigned bit values ​​“11”, “01”, “00”, and “10”, respectively. In such an example, two bits of data can be read from the memory by sensing in “full sequence” mode, wherein the two bits are sensed together by sensing relative to the corresponding read-bound threshold voltages rV1, rV2, and rV3 in three sub-passes, respectively.

[0067] Similarly, Figures 8A to 8C The programming stage of a TLC-type memory device is illustrated. This TLC-type memory device comprises a group of eight-state memory cells, each of which can be programmed with eight different distributions of threshold voltages, which, according to this specific embodiment, represent memory states "0", "1", "2", "3", "4", "5", "6", and "7" (e.g., ...). Figure 8A (As shown). Therefore, Figure 8B The initial distribution of the "erased" threshold voltage of the erased memory is depicted. Additionally, Figure 8C An example of a memory after many memory cells have been programmed is depicted. Therefore, the threshold voltage of the cell shifts higher to one of the different voltage ranges defined by levels V1, V2, V3, V4, V5, V6, and V7. Thus, each memory cell can be programmed into one of the seven programming states "1" to "7", or it can remain unprogrammed in an "erase" state. As a result of programming, such as... Figure 8B The initial distribution of the "erased" states shown becomes narrower, as... Figure 8C The “0” state indicates this. In this case, a 3-bit code with a lower bit, a middle bit, and a higher bit can be used to represent each of the memory states (i.e., “111”, “011”, “001”, “101”, “100”, “000”, “010”, and “110”), and can also be read from memory by sensing in “full sequence” mode, where the three bits are sensed together by sensing relative to the defined thresholds V1 to V7 in seven sub-passes respectively.

[0068] exist Figures 4A to 4B , Figure 5 and Figures 6A to 6BAs discussed above, a two-dimensional (or planar) memory array 210 (e.g., located in the xy-plane) is generally described, which may include NAND-type memory cells. However, in an alternative configuration, the memory array may be in the form of a three-dimensional memory array, which, unlike being formed on a planar surface of a semiconductor substrate or wafer, extends upward from the wafer surface and includes a stack or column of memory cells extending vertically in the upward direction (e.g., in the z-direction perpendicular to the xy-plane). For example, in Figure 9 An exemplary embodiment of a NAND string 701 is shown, which operates in a manner similar to a planar two-dimensional NAND string (such as NAND string 50 described above). According to this configuration, memory cells are formed at the junctions of vertical bit lines (see, for example, local bit line 703) and word lines (see, for example, word lines WL0, WL1, etc.), wherein a charge-trapping layer located between the local bit line 703 and the intersecting word lines stores charge (which determines the threshold voltage of the transistor formed by the word line (gate) coupled to the vertical bit line (channel), the gate surrounding the channel). To form the vertical string 701, a stack of word lines is formed, and memory vias are etched at appropriate locations where cells are to be formed, wherein each memory via is lined with a charge-trapping layer and filled with a suitable local bit line / channel material. A dielectric layer is included for necessary isolation. Furthermore, located at either end of the NAND string 701 are select gates 705 and 707, which allow selective connection to or isolation from external components 709 and 711, including, for example, conductive lines, such as common source lines or bit lines serving the large number of strings 701 in the array. Figure 9 In the specific embodiment shown, the vertical NAND string 701 has 32 memory cells connected in series (i.e., at the junction between the local ground line 703 and word lines 0 to 31). However, the NAND string 701 may include any suitable number of memory cells.

[0069] Re-reference, for example Figure 1 The overall architecture of the memory system described in [the text] is... Figure 10A schematic depiction of a typical arrangement of such a memory array is shown. In this exemplary embodiment, a non-volatile memory array 200 is shown that can be accessed by read / write circuitry 170 via row decoder 140 and column decoder 160. As described above, individual memory cells of memory array 200 can be addressed via a selected set of word lines and bit lines. Therefore, row decoder 140 selects one or more word lines and column decoder 160 selects one or more bit lines to apply an appropriate voltage to the corresponding gate of the addressed memory cell. Furthermore, read / write circuitry 170 is provided to read or write the memory state of the addressed memory cell, wherein read / write circuitry 170 includes a plurality of read / write modules that can be connected to the memory elements of array 200 via bit lines. According to its exemplary embodiment, in Figure 11 A schematic block diagram of such a read / write module 190 is provided. In operation, during a read or verification step, a sense amplifier 150 determines the current flowing through the drain of an addressed memory cell connected via a select line. The level detected by the sense amplifier 150 is converted by level-to-bit conversion logic into a set of data bits to be stored in the data latch 155. Now refer back to Figure 10 The read / write circuitry 170 is organized into a library of read / write stacks 180, where each read / write stack 180 is a stack of read / write modules 190.

[0070] See now Figure 12A The illustration shows a memory device (such as a non-volatile memory array 300, which may include NAND-type SLC, MLC, TLC and / or QLC memory cells configured in two or three dimensions), a controller 310 and read / write circuitry 370. Figure 1 An exemplary embodiment of the memory device 102 is shown. Additionally, as depicted, the read / write circuitry 370 comprises one or more partitioned read / write stacks 400, thereby allowing parallel reading or programming of blocks (or “pages”) of memory cells, wherein, according to an exemplary embodiment, “pages” of memory cells constitute consecutive rows of memory cells. The memory array 300 is addressable by word lines via a row decoder 330 and by bit lines via a column decoder 360. Alternatively, the memory array 300 may include rows of memory cells divided into multiple blocks or pages. Therefore, in such exemplary embodiments, a block multiplexer 350 is provided to multiplex the read / write circuitry 370 into individual blocks.

[0071] Relative to controller 310, it operates in conjunction with read / write circuitry 370 to perform memory operations on memory array 300. In this specific embodiment, controller 310 includes state machine 312, on-chip address decoder 314, and power controller 316. State machine 312 provides chip-level control of memory operations. On-chip decoder 314 provides an address interface between the hardware addresses used by the host or memory controller and the hardware addresses used by decoders 330, 360. Finally, power controller 316 controls the power and voltage supplied to word lines and bit lines during memory operations.

[0072] Figure 12B Depicting Figure 12A A slightly different exemplary embodiment of the memory device. In this specific embodiment, access to the memory array 300 by various peripheral circuits is implemented symmetrically on opposite sides of the memory array 300. Therefore, compared with Figure 12A Compared to the previous configuration, the number of access lines and circuitry on each side of the memory array 300 is reduced by half. Specifically, the row decoder 330 is divided into multiple row decoders 330A and 330B, and the column decoder 360 is divided into multiple column decoders 360A and 360B. Furthermore, in such embodiments where one row of memory cells is divided into multiple blocks, the block multiplexer 350 is divided into multiple block multiplexers 350A and 350B. Similarly, the read / write circuitry 370 is divided into read / write circuitry 370A (connected to the bit lines from the bottom of the array 300) and read / write circuitry 370B (connected to the bit lines from the top of the memory array 300). Therefore, the density of the read / write modules (and the divided read / write stack 400) is substantially reduced by half.

[0073] See now Figure 13 This illustrates read / write stacking (such as...) Figure 12A An exemplary implementation of certain components in a read / write stack 400. According to this particular architecture, the read / write stack 400 includes a stack of sense amplifiers 212 for sensing “k” bit lines, I / O modules 440 for inputting or outputting data via I / O bus 231, a stack of data latches 430 for storing input and / or output data, a common processor 500 for processing and storing data in the read / write stack 400, and a stack bus 421 for communication between the components of the read / write stack 400. Furthermore, a stack bus controller provides control signals and timing signals via line 411 for controlling the various components of the read / write stack 400. Figure 14A Describing the use of Figure 13 The implementation scheme has a read / write stack of 400 inline. Figures 12A to 12BAn exemplary embodiment of the read / write circuitry 370 of the memory device depicted is described above. Each read / write stack 400 operates in parallel on a set of k bit lines. Therefore, if a page in the memory array 300 has p = r * k bit lines, there will be a number of r read / write stacks—that is, read / write stacks 400-1, ..., 400-r. Thus, the entire library of partitioned read / write stacks 400-1, ..., 400-r allows for parallel reading or programming of blocks (or pages) of p cells along a row, with p read / write modules for the entire row. Since each read / write stack 400-1, ..., 400-r serves as "k" memory cells, the total number of read / write stacks in the library can be expressed as r = p / k. Additionally, according to this example, each read / write stack correspondingly has a stack of sense amplifiers 212-1, ..., 212-k that serve in parallel a segment of "k" memory cells. Furthermore, each read / write stack has a corresponding stack of data latches 430-1, ..., 430-k, each data latch being associated with a memory cell. Therefore, there exists an I / O module 440 that enables the data latches 430-1, ..., 430-k to exchange data externally via I / O bus 231.

[0074] See still Figure 14A The diagram also shows a stack bus controller 410, which receives signals from the memory controller 310 (via line 311) and subsequently provides control and timing signals to the read / write circuitry 370 via line 411. Communication between the read / write stacks 400 is achieved through an interconnect stack bus controlled by the stack bus controller 410. Therefore, control line 411 provides control and clock signals from the stack bus controller 410 to components of the read / write stacks 400-1, ..., 400-r. In this particular example, the interconnect stack bus is divided into LBus (or local data bus) 422 and DBus (or data bus) 423, where LBus 422 provides a common processor 500 (which, according to some embodiments, may be in the form of a detection circuit including one or more data latch transistors), and stacked sense amplifiers 212-1, ..., 212-k and DBus 423 provide communication paths between the common processor 500 and the stack of data latches 430-1, ..., 430-k. In addition to the common processor 500, it also includes an output 507 for outputting status signals (such as error states) for memory operations. Figure 14A As depicted, the status signal can, for example, be used to drive the gate of an n-transistor 550 that is online or configured to be bound to a marker bus 509, wherein the marker bus 509 can be precharged by the controller 310 and pulled down when the status signal is asserted by any of the read / write stacks 400-1, ..., 400-r.

[0075] In addition, Figure 14B An exemplary embodiment of a separate sensing block (such as that covered by read / write stack 400) is depicted. Sensing block 400 is divided into one or more core portions including sensing modules 480 or sensing amplifiers and a common portion called management circuitry 490. In one embodiment, there is a separate sensing module 480 for each bit line and a common management circuitry 490 for a group of multiple (e.g., four or eight) sensing modules 480. Each sensing module in the group communicates with its associated management circuitry via a data bus 472. Thus, there are one or more management circuitries communicating with the sensing modules of the group of memory cells 10.

[0076] Sensing module 480 includes sensing circuitry 470 that performs sensing by determining whether the conduction current in the connected bit line is above or below a predetermined threshold level. Sensing module 480 also includes a bit line latch 482 for setting a voltage condition on the connected bit line. For example, a predetermined state latched in bit line latch 482 will cause the connected bit line to be pulled to a specified programming-disabled state (e.g., 1.5-3V). As an example, flag = 0 disables programming, while flag = 1 does not disable programming.

[0077] exist Figure 14B In an exemplary implementation, management circuitry 490 includes a processor 492, four sets of exemplary data latches 494, 495, 496, and 497, and an I / O interface 498 coupled between the data latch sets 494-497 and the I / O bus 231. A set of data latches may be provided for each sensing module 480, and each set may be provided with a data latch identified by XDL, DDL, ADL, BDL, and CDL. In some cases, additional data latches may be used. In one exemplary method, in a memory device using eight data states, XDL stores user data, DDL stores an indication of whether fast programming is used via write, ADL stores lower pages of data, BDL stores middle pages of data, and CDL stores higher pages of data.

[0078] Processor 492 performs calculations to determine the data stored in the sensed memory elements and stores the determined data in the set of data latches. Each set of data latches 494-497 stores the data bits determined by processor 492 during a read operation and stores the data bits imported from I / O bus 231 during a programming operation, which represents the write data to be programmed into memory. I / O interface 498 provides an interface between data latches 494-497 and I / O bus 231.

[0079] During the read operation, the system operates under the control of state machine 312, which controls the supply of different control gate voltages to the addressed memory cell 10. As it progresses through various predefined control gate voltages corresponding to different memory states supported by the memory, the sensing module 480 can trip at one of these voltages, and the corresponding output is provided from the sensing module 480 to the processor 492 via the data bus 472. At this time, the processor 492 determines the resulting memory state by considering the tripping event of the sensing module and information about the control gate voltage applied via the input line 493 from the state machine. It then calculates the binary code of the memory state and stores the resulting data bits in data latches 494-497. In another embodiment of the management circuit 490, the bit line latch 482 operates with dual capabilities, serving both as a latch for latching the output of the sensing module 480 and as a bit line latch as described above.

[0080] During programming or verification operations, the data to be programmed (written data) is stored from I / O bus 231 in the set of data latches 494-497. Under the control of state machine 312, the programming operation involves a series of programming voltage pulses being applied to the control gate of the addressed memory element. Each programming pulse is followed by a readback (verification) to determine whether the memory element has been programmed to the desired memory state. In some cases, processor 492 monitors the readback memory state relative to the desired memory state. When the two are in agreement, processor 492 proceeds to set bit-line latch 482 so that the bit line is pulled to a specified programming-disabled state. This prevents further programming of the memory element coupled to the bit line, even if a programming pulse occurs at its control gate. In other embodiments, the processor initially loads bit-line latch 482, and sensing circuitry sets it to a disabled value during verification.

[0081] As mentioned, each group of data latches 494-497 can be implemented as a stack of data latches for each sensing module. In one exemplary embodiment, each sensing module 480 has three data latches. In some specific implementations, the data latches are implemented according to shift registers, such that parallel data stored therein is converted into serial data on the I / O bus 231 and vice versa. For example, all data latches corresponding to a read / write block of M memory elements can be linked together to form a block shift register, enabling input or output data blocks to be transmitted serially. Specifically, the read / write module group can be adjusted such that each group of its data latches sequentially shifts data into or out of the data bus as if they were part of a shift register for the entire read / write block.

[0082] The data latch indicates when the associated memory cell 10 reaches certain milestones of a programming operation. For example, the latch can identify the V of the memory element. th Whether it is below a specific verification level. The data latch indicates whether the storage element is currently storing one or more bits from a page of data. For example, relative to an exemplary embodiment, the ADL latch is toggled (e.g., from 0 to 1) when the next page bit is stored in the associated storage element. Additionally, the BDL latch is toggled when the intermediate page bit is stored in the associated storage element. And the CDL latch is toggled when the previous page bit is stored in the associated storage element. When V th When the associated verification level is exceeded, the bit is stored in the storage element.

[0083] Now go to Figure 15 This describes another exemplary embodiment of a non-volatile memory array 800 accessible by read / write circuitry 870. Similar to... Figure 10 The memory array 200 of the embodiment, the individual memory cells of the memory array 800, can be addressed by a row decoder 840 and a column decoder 860 via a selected set of word lines and bit lines. Therefore, the row decoder 840 selects one or more word lines and the column decoder 860 selects one or more bit lines to apply an appropriate voltage to the corresponding gate of the addressed memory cell. Furthermore, read / write circuitry 870 is provided to read or write the memory state of the addressed memory cells, wherein the read / write circuitry 870 includes multiple read / write modules that can be connected to the memory elements of the array 800 via bit lines. This particular configuration is for implementing according to... Figure 6A and Figure 6B An example of the memory block structure 220 of the implementation scheme described herein.

[0084] Now for reference Figures 16A to 16B Exemplary implementations of certain components of the read / write circuit are shown, such as Figure 15The read / write circuitry 870 is shown as a segment of the bit lines (BL) of the memory array 800. According to this particular architecture, the read / write circuitry 900 may include one or more read / write modules, each module including a sense amplifier 912 for sensing one of a number of bit lines (e.g., according to a "full bit line scheme"), a stack of data latches 930 for storing input and / or output data, and a local bus 902 connecting the data latches 930 to the sense amplifier 912. Furthermore, the read / write circuitry 900 may include a data bus 921 for communication between the read / write modules, wherein the data bus 921 may be connected to a common processor 950 and an external data latch group 940. Specifically, the common processor 950 and the external data latches 940 may process and store data between the read / write modules, and provide control and timing signals to the various components of the read / write circuitry 900. Furthermore, Figure 16B It includes, for example Figure 15 A schematic diagram of an implementation of the read / write circuitry 870 of the memory array 800 and the circuitry portion 960 of the column decoder 860. Therefore, in Figures 16A to 16B In the specific embodiment shown, logic operations are performed using transistors in the data bus 921 and the external data latch group 940, and are implemented by the common processor 950. Additionally, the detection circuit 955 may be associated with each plane of the memory array 800, such that feedback from the detection circuit 955 is relayed to the state machine (e.g., via, for example, the tag bus 509 to...). Figure 14A (State machine 312).

[0085] The above discussion describes only a few non-limiting embodiments of non-volatile memory systems and devices. As previously mentioned, any of these systems and devices, as well as other exemplary embodiments, can operate in binary form (SLC) and polymorphic or multilevel (MLC or TLC) form. For example, because data can be written or programmed faster and has smaller critical tolerances (i.e., greater reliability) in binary form compared to polymorphic form, a memory device can be configured to initially program data in binary form when receiving data from a host, and then rewrite the data in polymorphic format at a later time to take advantage of greater storage density. Thus, in these types of memory devices, some memory cells can be used in single-mode form and other memory cells can be used in polymorphic form, or the same cells can be operated to store different numbers of bits. The process for rewriting data from binary format to polymorphic format is referred to as "folding". According to an exemplary embodiment of the folding process, data is initially transferred from a memory controller (e.g., controller 310) to memory and written in binary format along word lines of a memory array (e.g., array 300). For example, in the three-bit-per-cell polymorphic form, the contents of the three word lines are each read into their respective registers, rearranged to correspond to the three bits to be stored in each cell, and rewritten back to a single word line of the memory array in a three-bit-per-cell format. Figure 17 and Figure 18 The comparison between the different programming processes shown illustrates this situation. Figure 17 An exemplary implementation of a direct TLC programming process is described, in which a three-page dataset 1000 consisting of eight programming states (1 to 8) is programmed into a single word line (e.g., "WLn", where "n" is any integer 0 or higher). Thus, three bits of each programming state (i.e., the lower page bit, the middle page bit, and the higher page bit) are programmed into a single memory cell of the selected word line, such that each memory cell is programmed according to one of the eight programming states (1, 2, 3, 4, ..., 8). Therefore, using this TLC programming scheme increases the effective storage density by a factor of three compared to a binary SLC programming scheme where only one bit is stored per memory cell. However, as mentioned above, the increased complexity in the polymorphic programming process compared to the SLC programming process results in a slower programming time. In fact, in some situations, the amount of time that a TLC programming process may require is approximately three times the amount of time required to program the same amount of data in other ways according to an SLC or MLC programming scheme. Therefore, as mentioned above, an exemplary approach to overcome this negative performance effect is to employ a "folding" scheme, which is a hybrid two-stage solution utilizing, for example, both singleton and polymorphic programming schemes. Figure 18An exemplary implementation of the folding scheme is described, wherein three pages of dataset 1000 are programmed according to a binary SLC programming scheme in the first phase 1002a, such that each page (in Figure 18 The data (referred to as Data 1, Data 2, and Data 3) is programmed bit by bit per cell along its respective word line (see, for example, WLn+1, WLn, and WLn-1). Subsequently, in the second stage 1002b, the binary programming data from the first stage is encapsulated in three bits per cell of a single selected word line (see, for example, WLx) during the TLC programming process, according to the internal operation of the memory system.

[0086] Now for reference Figure 19 This shows that it can be used, for example, relative to the above. Figure 18 An exemplary implementation of the memory-on-memory folding process for the described programmable memory operations. As indicated, data is received from a controller or host and initially programmed in binary format (SLC) along N word lines of a representative memory block 611. Subsequently, the contents of the N word lines are rewritten in polymorphic (MLC) per-cell N-bit format along a single word line of another representative memory block 621, where this "folding" process is performed on the memory itself. In this particular example, three word lines (613, 615, 617) of the binary formatted block 611 undergo the folding process and are rewritten along a single word line 623 of the three-bit per-cell formatted block 621 (i.e., N=3). Block 611 may be specifically designated to operate only in binary mode, or it may be a block that can operate in MLC mode, for example by making only the lowest page of multiple logical pages available to be stored on a physical page. Similarly, block 621 may be designated only for polymorphic operation, or it may also operate in binary mode. Figure 20 Depicting Figure 19 An exemplary embodiment of the data rearrangement and rewriting in the exemplary folding process is shown, wherein three binary word lines in binary format are subsequently folded into a single polymorphic word line. Therefore, in Figure 20 At the top are three binary status word lines 613, 615, and 617, each of which is divided into, for example, three segments a, b, and c. Each segment contains one-third of a memory cell along its corresponding one-third bit line (considered adjacent here). Additionally, in Figure 20 At the bottom is a polymorphic word line 623, in which the three parts 613a-c of the first word line 613 are subsequently folded and written into the first third of word line 623; thereafter, the three parts 615a-c of the second word line 615 are folded and written into the second third of word line 623; and finally, the three parts 617a-c of the third word line 617 are folded and written into the last third of word line 623. Importantly, although... Figure 19 and Figure 20The exemplary implementation illustrates a case where three pages of data, rewritten from three physical pages to a polymorphic format, exist on a single physical page, but other amounts of storage density can be used. Additionally, although a full word line (where each word line corresponds to a page) is shown, partial pages can be used in memory systems that allow partial page operations. Finally, although Figure 20 The illustration highlights a scenario where memory cells along word lines are divided into segments along adjacent bit lines, but other arrangements can also be used.

[0087] As indicated above, the folding process is performed on the memory itself, so that data received from the host does not need to be transferred out of memory before it can be rewritten into the memory array in a polymorphic format. This capability can be achieved, for example, by reading data from multiple binary status word lines (e.g., 613, 615, 617) into corresponding registers (or latches) associated with the memory array, rearranging them within these registers into the form required for polymorphic programming, and then rewriting them into a single word line (e.g., 623) of the polymorphic memory block. Therefore, in Figure 19 and Figure 20 In the illustrated implementation, the binary contents of several memory cells (specifically, three) on the same word line but along different bit lines are read into the associated data register or latch, and then rearranged into multiple bits corresponding to a single cell on the corresponding unit line from which the binary contents can be written.

[0088] While the "folding" process offers the dual benefits of relatively fast programming speed and large storage capacity or density by combining an initial binary (SLC) programming phase and a second polymorphic (MLC, TLC, or QLC) rewrite phase, a drawback is that the process requires at least two phases instead of just a single phase, thereby increasing complexity and thus the amount of time required for processing speed. Therefore, it would be advantageous to be able to further optimize either or both of the programming and rewrite phases of the folding process. Figures 21A to 21D An exemplary implementation of a mechanism for improving the speed and efficiency of the initial binary (SLC) programming phase of the folding process is described. According to this specific implementation, the initial programming phase of the folding operation may include writing a three-page dataset (e.g., using two SLC programming operations along two word lines (WL) of two memory cell strings in a memory block) to two word lines (WL). Figure 17 and Figure 18 The dataset (1000) contains memory cells belonging to the common word line (WL) of two strings that are programmed simultaneously. Figures 6A to 6B In the case of a memory structure implementation, two memory cell strings can be adjacent. However, the two cell strings may not be relative to, for example... Figures 4A to 4B and Figure 5 The memory architecture implementations are adjacent. For example... Figures 21A to 21DAs shown, by changing the bit line voltage (V) at the selection transistors (SGD1 and SGD2) of each of the two adjacent cell strings (1010 and 1012) depicted, BL The number of combinations or iterations obtained by controlling the gate voltage allows the memory structure to be programmed to represent three different bit values.

[0089] Figure 21A The first programming mode is shown, wherein the corresponding control gate voltages (i.e., V) of the first cell string 1010 and the second cell string 1012 are shown. SGD1 and V SGD2 ) are respectively set at predetermined voltage levels (e.g., V) SGD1 =1.5V; V SGD2 =1.0V), and the bit line voltage (V BL Simultaneously, volt "A" is applied to both the first and second strings, causing the memory cells relative to the common selected word line (WLn) of the two strings to be in an "inhibited" state. In other words, volt "A" is applied to control the gate voltage V. SGD1 and V SGD2 Between and bit line voltage (V) BL The voltage difference (i.e., "A" volts) is low enough that both selection transistors are turned off, and therefore both memory cell strings 1010 and 1012 are "disabled". For the purposes of this particular example, the bit line voltage (V... BL "A" can be equal to 2.0V. Therefore, a (1,1) bit data value can be represented by this specific programming scheme.

[0090] exist Figure 21B The second programming mode is shown, where a predetermined voltage (V) is applied at a given selected transistor. SGD1 V SGD2 In the case of ), bit line voltage (V BL A voltage level "B" is simultaneously applied to both the first unit string 1010 and the second unit string 1012, wherein the control gate voltage V SGD1 and V SGD2 and bit line voltage (V) BL The voltage difference between the two transistors causes the select transistor (SGD1) of the first cell string 1010 to effectively switch to the ON state (generating a "programming" state at memory cell 1020 located at the common word line (WLn),) while the select transistor (SGD2) remains in the OFF state, thus maintaining the "disabled" state (at memory cell 1022 located at the common word line (WLn)). In this particular example, the bit line voltage (V... BL "B" is the intermediate voltage between voltages "A" and "C" (see below for details). Figure 21C(as discussed in the previous section), and can be equal to, for example, 0.7V. Therefore, (0,1) bit data values ​​can be represented by this particular programming scheme.

[0091] Compared to Figure 21C The third programming mode is described, in which a predetermined gate voltage (V0) is given again at the first string select transistor and the second string select transistor. SGD1 V SGD2 In the case of ), bit line voltage (V BL A voltage of "C" is simultaneously applied to both the first unit string 1010 and the second unit string 1012, causing both strings to transition to the ON state. Therefore, the memory cells (1030, 1032) of the first and second strings respectively (located at the common selected word line (WLn)) undergo a "programming" state. For the purposes of this particular example, the bit line voltage (V) BL "C" can be equal to, for example, zero volts (VSS). Therefore, a (0,0) bit data value can be represented by this particular programming scheme.

[0092] It is conceivable that the final iteration of the bit data value will be the (1,0) pattern. This pattern is... Figure 21D As shown in the diagram. However, because of the gate voltage (V... SGD1 V SGD2 The bit line voltage (V) is predetermined and cannot be changed during programming operations, so there cannot be a selectable bit line voltage. BL The voltage level is used to generate an "inhibited" state at the first unit string 1010 and a "programmed" state at the second unit string 1012 to achieve a (1,0) bit data value. Therefore, the SLC programming mechanism described in this paper can be called a "three-value" programming scheme.

[0093] See now Figure 22 This shows the method for using the above relative to Figures 21A to 21D This is an exemplary implementation of the process of programming an exemplary three-page dataset 1050 using the two-string simultaneous SLC programming mechanism. For illustrative purposes, Figure 22 Special attention is paid to the exemplary case of host or user data values ​​with the pattern (0,0,0) (see 1060). In the initial step, the three-page dataset 1050 must undergo an algorithmic transformation within the memory system such that each data pattern of the three-page dataset is represented by a combination of two-bit data values ​​(1055), which can be written into two strings according to the programming mechanism just described above. Specifically, only three possible bit data values ​​(0,0), (0,1), and (1,1) must be used to assign one or more representative two-bit data values ​​to each pattern of the three-page dataset 1050 accordingly. Thus, relative to the exemplary case of the three-page data pattern (0,0,0), it can be transformed into a combination of two-bit data values, such as (0,0) and (0,1), (e.g., Figure 22As shown), the "1" bit data value thus corresponds to the low threshold voltage (V). th The condition is such that the "0" bit data value corresponds to the high threshold voltage (V). th The converted data patterns (0,0) and (0,1) can then be simultaneously written to two adjacent memory cell strings (1040 and 1042) at selected common word lines (i.e., WLi and WLi+1). Therefore, using this two-string programming method and combining the two word lines (WLi and WLi+1), the desired result can be obtained according to... Figure 22 The nine transformation combinations (1055) described in the text fully represent and subsequently program a three-page dataset (e.g., set 1050).

[0094] According to some exemplary embodiments, this conversion can be implemented using a data latch scheme. For example, to initially store three pages of user data, the first, second, and third data can be stored in data latches ADL, BDL, and CDL, respectively. In a second step, a common processor (e.g., 500) attached to the data bus and / or combined with transistors consisting of an external data latch group can perform the necessary logic operations to convert the user data into a converted two-bit data value combination 1055, which can be stored as needed using, for example, data latches ADL, BDL, CDL, and DDL. Finally, the stored converted data is then used to determine the bit line level, as described above relative to... Figures 21A to 21D As stated above.

[0095] Re-reference Figures 21A to 21D The exemplary implementation described presents a significant challenge in terms of the ability to perform the necessary verification steps during programming operations, as existing configurations cannot simultaneously verify multiple memory strings along the same word line. However, upon close inspection, this programming scheme actually provides a predictive mechanism based on the verification results of the voltage distribution of only the first string, which can then be aggregated to determine the voltage distribution of the second string in the two-string programming schemes discussed above. Specifically, in Figure 21A In the programming configuration shown, the first unit string 1010 is in an off state, and therefore, based on the fact that the two units are in relatively close physical proximity and have similar physical shapes and properties, it can be axially determined that the second unit string 1012 is also in an off state. Furthermore, relative to... Figure 21B In the programming scenario shown, the standard verification operation is sufficient due to the fact that the second unit string 1012 is in a disabled state (i.e., in a "prohibited" state), and therefore no verification operation is required. Furthermore, relative to... Figure 21C The programming status shown in the diagram, and the verification operation, reveal that the first unit string 1010 is in an ON state (i.e., in a "programming" state). Therefore, it can be assumed that based on the above description relative to... Figures 21A to 21Dand Figure 22 The available possibilities outlined are similarly enabled across the voltage distribution of the second unit string 1012.

[0096] The aforementioned multi-string simultaneous SLC programming mechanism is not limited to programming three pages of host or user data. Instead, this fundamental mechanism, which performs multiple SLC programming operations simultaneously across two common word lines (WL) of more than one memory cell string, can be applied to datasets with higher storage densities. For example, Figure 23 An exemplary implementation of an SLC programming mechanism suitable for programming four pages of host or user data during internal folding is described, wherein the resulting converted data is stored in QLC format. Therefore, in order to provide a sufficient number of possible iterations or combinations of converted bit data values ​​to completely cover the original four pages of host or user data bit values, it is necessary to simultaneously apply the SLC programming protocol across two common word lines of three adjacent memory strings, such as... Figure 23 As shown.

[0097] The foregoing discussion is intended to illustrate the principles and various embodiments of the invention. Once the foregoing disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. For example, although the on-memory controller has been described as performing or controlling the methods described above, any processor executing software within a host system can perform the methods described above without departing from the scope of this disclosure. Specifically, the methods and techniques described herein that are performed in the on-memory controller can also be performed in the host system. Furthermore, the methods and concepts disclosed herein can be applied to other types of persistent memory besides flash memory. The following claims are intended to be interpreted as covering all such variations and modifications.

Claims

1. A method for programming a tri-page data set in a memory array of a non-volatile memory system, comprising: converting each tri-bit value data pattern in a tri-page user data set into a pair of representative two-bit data values; simultaneously programming two unipolar memory cells with a first of the pair of representative two-bit data values, wherein the two unipolar memory cells are located along a first common word line of two memory cell strings; and simultaneously programming two unipolar memory cells with a second of the pair of representative two-bit data values, wherein the two unipolar memory cells are located along a second common word line of the two memory cell strings.

2. The method of claim 1, wherein the programming of the first and second of the pair of representative two-bit data values occurs simultaneously.

3. The method of claim 1, wherein: the two memory cell strings are located adjacent to each other; and the programming of the unipolar memory cells includes changing a bit line voltage applied to two adjacent memory cell strings.

4. The method of claim 1, wherein the programming of the unipolar memory cells includes applying a bit line voltage to the two memory cell strings such that: a first of the two memory cell strings is in an off state; and a second of the two memory cell strings is in an off state.

5. The method of claim 1, wherein the programming of the unipolar memory cells includes applying a bit line voltage to the two memory cell strings such that: a first of the two memory cell strings is in an on state; and a second of the two memory cell strings is in an off state.

6. The method of claim 1, wherein the programming of the unipolar memory cells includes applying a bit line voltage to the two memory cell strings such that: a first of the two memory cell strings is in an on state; and a second of the two memory cell strings is in an on state.

7. The method of claim 1, wherein the two-bit data values are one of: 1, 1; 0, 1; and 0,0。 8. The method of claim 1, wherein the unipolar memory cells are NAND type memory cells.

9. A memory controller, comprising: a first port configured to be coupled to a non-volatile memory structure, the memory structure including a memory array; and the memory controller is configured to: convert each tri-bit value data pattern in a tri-page user data set into a pair of representative two-bit data values; simultaneously program two unipolar memory cells with a first of the pair of representative two-bit data values, wherein the two unipolar memory cells are located along a first common word line of two memory cell strings of the memory array; and simultaneously program two unipolar memory cells with a second of the pair of representative two-bit data values, wherein the two unipolar memory cells are located along a second common word line of the two memory cell strings.

10. The memory controller of claim 9, wherein the first and second of the pair of representative two-bit data values are programmed simultaneously.

11. The memory controller of claim 9, wherein: the two strings of memory cells are positioned adjacent to each other; and the unimodal memory cells are programmed by varying a bit line voltage applied to two adjacent strings of memory cells.

12. The memory controller of claim 9, wherein the unimodal memory cells are programmed by applying a bit line voltage to the two strings of memory cells such that: a first of the two strings of memory cells is in an off state; and a second of the two strings of memory cells is in an off state.

13. The memory controller of claim 9, wherein the unimodal memory cells are programmed by applying a bit line voltage to the two strings of memory cells such that: a first of the two strings of memory cells is in an on state; and a second of the two strings of memory cells is in an off state.

14. The memory controller of claim 9, wherein the unimodal memory cells are programmed by applying a bit line voltage to the two strings of memory cells such that: a first of the two strings of memory cells is in an on state; and a second of the two strings of memory cells is in an on state.

15. A non-volatile memory system comprising: a memory array; a memory controller coupled to the memory structure and: converting each three-bit value data pattern in a set of three pages of user data into a pair of representative two-bit data values; simultaneously programming two unimodal memory cells with a first of the pair of representative two-bit data values, wherein the two unimodal memory cells are positioned along a first common word line of two strings of memory cells of the memory array; and simultaneously programming two unimodal memory cells with a second of the pair of representative two-bit data values, wherein the two unimodal memory cells are positioned along a second common word line of the two strings of memory cells.

16. The non-volatile memory system of claim 15, wherein the first and second of the pair of representative two-bit data values are programmed simultaneously.

17. The non-volatile memory system of claim 15, wherein: the two strings of memory cells are positioned adjacent to each other; and the unimodal memory cells are programmed by varying a bit line voltage applied to two adjacent strings of memory cells.

18. The non-volatile memory system of claim 15, wherein the unimodal memory cells are programmed by applying a bit line voltage to the two strings of memory cells such that: a first of the two strings of memory cells is in an off state; and a second of the two strings of memory cells is in an off state.

19. The nonvolatile memory system of claim 15, wherein the unipolar memory cell is programmed by applying a bit line voltage to the two strings of memory cells such that: a first of the two strings of memory cells is in an on state; and a second of the two strings of memory cells is in an off state.

20. The nonvolatile memory system of claim 15, wherein the unipolar memory cell is programmed by applying a bit line voltage to the two strings of memory cells such that: a first of the two strings of memory cells is in an on state; and a second of the two strings of memory cells is in an on state. ​ ​ ​ ​

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