Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, the method comprising: providing a substrate including a substrate and discrete fin portions located on the substrate, a gate structure spanning the fin portions being formed on the substrate, a first hard mask layer being formed on the top of the gate structure, a second hard mask layer being formed on the first hard mask layer, the material hardness of the first hard mask layer being less than that of the second hard mask layer, an interlayer dielectric material layer covering the second hard mask layer being further formed on the substrate; removing a first portion of the thickness of the interlayer dielectric material layer to expose the second hard mask layer, and the remaining interlayer dielectric material layer covering the sidewalls of the first hard mask layer; removing a portion of the thickness of the second hard mask layer; after removing a portion of the thickness of the second hard mask layer, simultaneously removing a second portion of the thickness of the interlayer dielectric material layer, the remaining second hard mask layer and the first hard mask layer, and the remaining interlayer dielectric material layer serving as an interlayer dielectric layer, the interlayer dielectric layer covering a partial sidewall or the entire sidewall of the gate structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and particularly to a method for forming a semiconductor structure. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, people's requirements for the integration and performance of integrated circuits have become increasingly high. In the application of fin field-effect transistor (FinFET) devices, the gate height is a very critical parameter, which directly affects the threshold voltage. The interlayer dielectric layer structure plays a decisive role in the control of the gate height. Therefore, a robust process is required to form the interlayer dielectric layer structure. The process of forming a groove in the interlayer dielectric layer helps to control the gate height of the entire silicon wafer at the same height.

[0003] Currently, when forming a groove in the interlayer dielectric layer, it will affect other film layers on the gate structure, and further cause peeling defects in other film layers on the gate structure. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0005] To solve the above problems, embodiments of the present invention provide a method for forming a semiconductor structure, including: providing a substrate, including a substrate and discrete fin portions located on the substrate, a gate structure is formed across the fin portions on the substrate, a first hard mask layer is formed on the top of the gate structure, a second hard mask layer is formed on the first hard mask layer, the material hardness of the first hard mask layer is less than the material hardness of the second hard mask layer, an interlayer dielectric material layer covering the second hard mask layer is further formed on the substrate; removing a first part of the thickness of the interlayer dielectric material layer to expose the second hard mask layer, and the remaining interlayer dielectric material layer covers the sidewalls of the first hard mask layer; removing a part of the thickness of the second hard mask layer; after removing a part of the thickness of the second hard mask layer, simultaneously removing a second part of the thickness of the interlayer dielectric material layer, the remaining second hard mask layer and the first hard mask layer, and the remaining interlayer dielectric material layer serves as an interlayer dielectric layer, and the interlayer dielectric layer covers a part of the sidewalls of the gate structure.

[0006] Optionally, in the step of removing a first part of the thickness of the interlayer dielectric material layer to expose the second hard mask layer, the top of the remaining interlayer dielectric material layer is higher than the top of the first hard mask layer.

[0007] Optionally, in the step of providing the substrate, spacers are further formed on the sidewalls of the gate structure, the first hard mask layer, and the second hard mask layer; after forming the interlayer dielectric layer, the method further includes: removing the spacers that are higher than the top of the interlayer dielectric layer.

[0008] Optionally, the material of the interlayer dielectric material layer is the same as that of the first hard mask layer.

[0009] Optionally, a wet etching process is used to simultaneously remove the second part of the thickness of the interlayer dielectric material layer, the remaining second hard mask layer, and the first hard mask layer.

[0010] Optionally, the etching selectivity of the wet etching process for the interlayer dielectric material layer and the second hard mask layer is less than 5:1.

[0011] Optionally, a wet etching process is used to remove the first part of the thickness of the interlayer dielectric material layer.

[0012] Optionally, a dry etching process is used to remove a part of the thickness of the second hard mask layer.

[0013] Optionally, the dry etching process includes a plasma etching process.

[0014] Optionally, a dry etching process is used to remove the spacers that are higher than the top of the interlayer dielectric layer.

[0015] Optionally, in the step of removing the first part of the thickness of the interlayer dielectric material layer, the thickness of the exposed second hard mask layer is 10 nm to 45 nm.

[0016] Optionally, in the step of removing a part of the thickness of the second hard mask layer, the thickness of the remaining second hard mask layer is 2 nm to 20 nm.

[0017] Optionally, the material of the interlayer dielectric material layer includes silicon oxide.

[0018] Optionally, the material of the first hard mask layer includes silicon oxide.

[0019] Optionally, the material of the second hard mask layer includes one or both of silicon nitride and carbon-doped silicon.

[0020] Optionally, the material of the spacers includes one or both of silicon nitride and carbon-containing silicon oxide.

[0021] Optionally, the gate structure is a dummy gate structure.

[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0023] In the forming method provided by the embodiment of the present invention, the thinning of the interlayer dielectric material layer is divided into two times. The first time is to remove the interlayer dielectric material layer with the first part of the thickness, exposing the second hard mask layer, and the remaining interlayer dielectric material layer covers the top sidewall of the first hard mask layer. Therefore, when removing the interlayer dielectric material layer with the first part of the thickness, the probability of the first hard mask layer being damaged or removed is relatively low. Correspondingly, the probability of the second hard mask layer collapsing is also relatively low. After that, remove a part of the thickness of the second hard mask layer, reducing the thickness of the second hard mask layer, which is beneficial to removing the remaining second hard mask layer simultaneously when removing the interlayer dielectric material layer with the second part of the thickness later. The second time is to simultaneously remove the interlayer dielectric material layer with the second part of the thickness, the remaining second hard mask layer and the first hard mask layer after removing a part of the thickness of the second hard mask layer. And at this time, the thickness of the remaining second hard mask layer is relatively small, and the probability of the second hard mask layer collapsing is still relatively low. In summary, by first removing the interlayer dielectric material layer with the first part of the thickness, exposing the second hard mask layer, and the top of the remaining interlayer dielectric material layer is higher than the top of the first hard mask layer; and after removing a part of the thickness of the second hard mask layer, then simultaneously removing the interlayer dielectric material layer with the second part of the thickness, the remaining second hard mask layer and the first hard mask layer, while making the thickness of the interlayer dielectric layer meet the process requirements, the problem of the second hard mask layer collapsing is improved, ensuring the reliability of the process, and thus improving the performance of the semiconductor structure. Description of the Drawings

[0024] Figures 1 to 2 are schematic structural diagrams corresponding to each step in a forming method of a semiconductor structure;

[0025] Figures 3 to 7 are schematic structural diagrams corresponding to each step in an embodiment of the forming method of the semiconductor structure of the present invention. Detailed Embodiments

[0026] Currently, the performance of semiconductor structures still needs to be improved. Now, in combination with a forming method of a semiconductor structure, analyze the reasons why its performance needs to be improved.

[0027] Figures 1 to 2 are schematic structural diagrams corresponding to each step in a forming method of a semiconductor structure.

[0028] Reference Figure 1, a substrate is provided, including a substrate 10 and discrete fin portions 11 located on the substrate 10. A gate structure 22 spanning the fin portions 11 is formed on the substrate 10. A first hard mask layer 31 is formed on the top of the gate structure 22. A second hard mask layer 32 is formed on the first hard mask layer 31. The material hardness of the first hard mask layer 31 is less than that of the second hard mask layer 32. An interlayer dielectric material layer 20 covering the second hard mask layer 32 is also formed on the substrate.

[0029] In the step of providing the substrate, sidewalls 21 are also formed on the sidewalls of the gate structure 22, the first hard mask layer 31, and the second hard mask layer 32.

[0030] Reference Figure 2 , etch a part of the thickness of the interlayer dielectric material layer 20 (as Figure 1 shown), and the remaining interlayer dielectric material layer 20 serves as the interlayer dielectric layer 23.

[0031] In the current process, the height control of the sidewall 21 is unstable, and it is easy to have a situation where the height of the sidewall 21 is lower than the height of the gate structure. Then, when etching the interlayer dielectric material layer 20, it is easy to expose the sidewall of the first hard mask layer 31. Usually, the material of the first hard mask layer 31 is the same as that of the interlayer dielectric material layer. Therefore, when etching the interlayer dielectric material layer 20, etching will also occur on the first hard mask layer 31, resulting in the consumption of the first hard mask layer 31 and even its complete removal, thus making it difficult for the first hard mask layer 31 to support the second hard mask layer 32 located above the first hard mask layer 31. As shown by the dotted circle in the figure, too much of the first hard mask layer 31 is etched and removed simultaneously, which will further cause the collapse of the second hard mask layer 32 and generate peeling defects.

[0032] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, including a substrate and discrete fin portions located on the substrate, a gate structure spanning the fin portions is formed on the substrate, a first hard mask layer is formed on top of the gate structure, a second hard mask layer is formed on the first hard mask layer, the material hardness of the first hard mask layer is less than the material hardness of the second hard mask layer, and an interlayer dielectric material layer covering the second hard mask layer is further formed on the substrate; removing a first part of the thickness of the interlayer dielectric material layer to expose the second hard mask layer, and the remaining interlayer dielectric material layer covers the sidewalls of the first hard mask layer; removing a part of the thickness of the second hard mask layer; after removing a part of the thickness of the second hard mask layer, simultaneously removing a second part of the thickness of the interlayer dielectric material layer, the remaining second hard mask layer and the first hard mask layer, and the remaining interlayer dielectric material layer serves as an interlayer dielectric layer, and the interlayer dielectric layer covers part of the sidewalls of the gate structure.

[0033] In the forming method provided by the embodiment of the present invention, the thinning of the interlayer dielectric material layer is divided into two times. The first time is to remove a first part of the thickness of the interlayer dielectric material layer to expose the second hard mask layer, and the remaining interlayer dielectric material layer covers the sidewalls of the first hard mask layer. Therefore, when removing the first part of the thickness of the interlayer dielectric material layer, the probability of the first hard mask layer being damaged or removed is relatively low. Correspondingly, the probability of the second hard mask layer collapsing is also relatively low. Then, a part of the thickness of the second hard mask layer is removed, reducing the thickness of the second hard mask layer, which is beneficial to simultaneously removing the remaining second hard mask layer when removing the second part of the thickness of the interlayer dielectric layer in the subsequent process. The second time is that after removing a part of the thickness of the second hard mask layer, simultaneously removing a second part of the thickness of the interlayer dielectric material layer, the remaining second hard mask layer and the first hard mask layer, and at this time, the thickness of the remaining second hard mask layer is relatively small, and the probability of the second hard mask layer collapsing is still relatively low. In summary, by first removing a first part of the thickness of the interlayer dielectric material layer to expose the second hard mask layer, and the top of the remaining interlayer dielectric material layer is higher than the top of the first hard mask layer; and after removing a part of the thickness of the second hard mask layer, then simultaneously removing a second part of the thickness of the interlayer dielectric material layer, the remaining second hard mask layer and the first hard mask layer, while making the thickness of the interlayer dielectric layer meet the process requirements, the problem of collapse of the second hard mask layer is improved, ensuring the reliability of the process, thereby improving the performance of the semiconductor structure.

[0034] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0035] Figures 3 to 7 These are schematic diagrams corresponding to the steps in an embodiment of the method for forming a semiconductor structure of the present invention.

[0036] Refer to Figure 3 , a substrate is provided, including a substrate 100 and discrete fin portions 110 located on the substrate 100. A gate structure 220 spanning the fin portions 110 is formed on the substrate 100. A first hard mask layer 310 is formed on the top of the gate structure 220. A second hard mask layer 320 is formed on the first hard mask layer 310. The material hardness of the first hard mask layer 310 is less than that of the second hard mask layer 320. An interlayer dielectric material layer 200 covering the second hard mask layer 320 is also formed on the substrate.

[0037] The substrate provides a process operation basis for subsequent processes.

[0038] In this embodiment, the substrate includes a substrate 100 and fin portions 110 formed on the substrate.

[0039] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate 100 can also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium. The substrate 100 can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate 100 can be a material suitable for process requirements or easy to integrate.

[0040] The fin portions 110 are used to provide channels for forming fin field-effect transistors.

[0041] In this embodiment, the fin portions 110 and the substrate 100 are of an integral structure. In other embodiments, the fin portions can also be semiconductor layers epitaxially grown on the substrate 100, so as to achieve the purpose of precisely controlling the height of the fin portions 110.

[0042] In this embodiment, the material of the fin portions 110 is the same as that of the substrate 100, and the material of the fin portions 110 is silicon. In other embodiments, the material of the fin portions can also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium, and the material of the fin portions 110 can also be different from that of the substrate 100.

[0043] In this embodiment, the gate structure 220 is a dummy gate structure. The dummy gate structure occupies a spatial position for the formation of a metal gate structure in subsequent processes.

[0044] In this embodiment, the dummy gate structure is formed by a chemical vapor deposition process.

[0045] The pseudo-gate structure can be a single-layer structure or a stacked structure, and the material of the pseudo-gate structure includes one or both of amorphous silicon and polysilicon. In other embodiments, the material of the pseudo-gate structure can also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, or amorphous carbon.

[0046] In this embodiment, the pseudo-gate structure is a single-layer structure, and the material of the pseudo-gate structure is amorphous silicon. Amorphous silicon does not have a crystal orientation. Therefore, the etching rate uniformity and etching effect uniformity of amorphous silicon are better, thereby improving the subsequent removal effect of the pseudo-gate structure.

[0047] It should be noted that according to process requirements, a gate oxide layer (not shown in the figure) can also be formed between the pseudo-gate structure and the fin 110. Among them, the material of the gate oxide layer can be silicon oxide.

[0048] The first hard mask layer 310 and the second hard mask layer 320 form a mask layer.

[0049] The mask layer is used to act as an etching mask during the formation of the gate structure 220.

[0050] In this embodiment, the material hardness of the first hard mask layer 310 is less than the material hardness of the second hard mask layer 320. The second hard mask layer 320 and the first hard mask layer 310 are used together as an etching mask, and at the same time, the first hard mask layer 310 can buffer the stress of the second hard mask layer 320.

[0051] The mask layer is a non-metal mask layer. As an example, the material of the first hard mask layer 310 is silicon oxide. The silicon oxide material is relatively soft and can better buffer stress.

[0052] The material of the second hard mask layer 320 includes one or both of silicon nitride and carbon-doped silicon.

[0053] The silicon nitride and carbon-doped silicon materials are relatively hard and cover the surface of the first hard mask layer 310 to act as a good etching mask.

[0054] As an example, the material of the second hard mask layer 320 is silicon nitride.

[0055] In this embodiment, the mask layer is formed by a chemical deposition process.

[0056] The interlayer dielectric material layer 200 is used to form an interlayer dielectric layer subsequently and acts as an isolation between adjacent devices.

[0057] In this embodiment, the interlayer dielectric material layer 200 is formed by a chemical vapor deposition process.

[0058] The material of the interlayer dielectric material layer 200 is an insulating material. In this embodiment, the material of the interlayer dielectric material layer 200 includes silicon oxide.

[0059] In this embodiment, the materials of the interlayer dielectric material layer 200 and the first hard mask layer 310 are the same.

[0060] To simplify the process and facilitate the removal together in subsequent processes, the materials of the interlayer dielectric material layer 200 and the first hard mask layer 310 are the same.

[0061] In this embodiment, in the step of providing the substrate, spacers 210 are further formed on the sidewalls of the gate structure 220, the first hard mask layer 310, and the second hard mask layer 320.

[0062] The spacers 210 are used to define the height of the metal gate structure in subsequent processes.

[0063] The material of the spacers 210 includes one or both of silicon nitride and carbon-containing silicon oxide. The spacers 210 can be a single-layer structure or a stacked structure. In this embodiment, the spacers 210 are a single-layer structure, and the material of the spacers 210 is silicon nitride.

[0064] It should be noted that in the actual process, due to the influence of process instability, there may be a situation where the spacers 210 only cover the sidewalls of the gate structure 220, or cover the sidewalls of the gate structure 220 and part of the sidewalls of the first hard mask layer 310.

[0065] Reference Figure 4 , remove a first part of the thickness of the interlayer dielectric material layer 200 to expose the second hard mask layer 320, and the remaining interlayer dielectric material layer 200 covers the sidewalls of the first hard mask layer 310.

[0066] Exposing the second hard mask layer 320 facilitates the subsequent removal of a part of the thickness of the second hard mask layer 320.

[0067] And the remaining interlayer dielectric material layer 200 covers the sidewalls of the first hard mask layer 310, which protects the first hard mask layer 310 from being exposed. Thus, in the process of removing the first part of the thickness of the interlayer dielectric material layer 200, the probability of damage to the first hard mask layer 310 is reduced, and further, the first hard mask layer 310 can still provide support for the second hard mask layer 320, correspondingly reducing the probability of collapse of the second hard mask layer 320.

[0068] In addition, when subsequently removing a part of the thickness of the second hard mask layer 320, the remaining interlayer dielectric material layer 200 can still protect the sidewalls of the first hard mask layer 310, thereby reducing the probability of loss of the first hard mask layer 310 during the process of removing a part of the thickness of the second hard mask layer 320, and further enabling the first hard mask layer 310 to still support the second hard mask layer 320.

[0069] In this embodiment, the top of the remaining interlayer dielectric material layer 200 is higher than the top of the first hard mask layer 310, so as to cover the sidewalls of the first hard mask layer 310 and part of the sidewalls of the second hard mask layer 320.

[0070] Since in the process of the manufacturing process, the top of the higher sidewall 210 in the sidewall 210 is usually higher than the top of the first hard mask layer 310, so as to cover the sidewalls of the first hard mask layer 310 and part of the sidewalls of the second hard mask layer 320. Therefore, when removing the first part of the thickness of the interlayer dielectric material layer 200, the top of the remaining interlayer dielectric material layer 200 is higher than the top of the first hard mask layer 310, so as to cover the sidewalls of the first hard mask layer 310 and part of the sidewalls of the second hard mask layer 320, which is beneficial to reducing the damage to the higher sidewall 210 in the sidewall 210.

[0071] In this embodiment, a wet etching process is used to remove the first part of the thickness of the interlayer dielectric material layer 200.

[0072] The wet etching process has the characteristic of isotropic etching, which is beneficial to removing the first part of the thickness of the interlayer dielectric material layer 200 completely, and the uniformity during the removal process is also good.

[0073] In this embodiment, in the step of removing the first part of the thickness of the interlayer dielectric material layer 200, the exposed thickness of the second hard mask layer 320 is 10 nm to 45 nm.

[0074] In this embodiment, in the step of removing a first portion of the thickness of the interlayer dielectric material layer 200, the thickness of the exposed second hard mask layer 320 should not be too large or too small. If the thickness of the exposed second hard mask layer 320 is too large, it is likely to increase the probability that the remaining interlayer dielectric material layer 200 exposes the first hard mask layer 310, correspondingly increasing the probability of loss of the first hard mask layer 310, and thus increasing the probability of collapse of the second hard mask layer 320; if the thickness of the exposed second hard mask layer 320 is too small, it is not easy to remove a portion of the thickness of the second hard mask layer 320 in subsequent processes. Therefore, in this embodiment, in the step of removing a first portion of the thickness of the interlayer dielectric material layer 200, the thickness of the exposed second hard mask layer 320 is 10 nm to 45 nm. For example, the thickness of the exposed second hard mask layer 320 is 30 nm.

[0075] Reference Figure 5 , remove a portion of the thickness of the second hard mask layer 320.

[0076] In subsequent processes, when etching the interlayer dielectric material layer 200, the remaining second hard mask layer 320 will be removed together. Therefore, removing a portion of the thickness of the second hard mask layer 320 first is beneficial for removing the remaining second hard mask layer 320 together when etching the interlayer dielectric material layer 200 subsequently.

[0077] In this embodiment, a dry etching process is used to remove a portion of the thickness of the second hard mask layer 320.

[0078] The dry etching process has the characteristic of anisotropic etching. Therefore, by selecting the dry etching process, it is beneficial to reduce the damage to other film layers during the etching of the second hard mask layer 320. At the same time, it is beneficial to accurately control the etching amount of the second hard mask layer 320.

[0079] In this embodiment, the dry etching process includes a plasma etching process.

[0080] The plasma etching process has a high etching selectivity for different materials according to the selection of different gases. Therefore, when etching the second hard mask layer 320, it is not easy to cause damage to other film layers, and the plasma etching process has a high etching rate, thereby improving the process operation efficiency.

[0081] In this embodiment, in the step of removing a portion of the thickness of the second hard mask layer 320, the thickness of the remaining second hard mask layer 320 is 2 nm to 20 nm.

[0082] In this embodiment, in the step of removing a part of the thickness of the second hard mask layer 320, the thickness of the remaining second hard mask layer 320 should not be too large or too small. If the thickness of the remaining second hard mask layer 320 is too large, it is not conducive to removing the remaining second hard mask layer 320 simultaneously when etching the interlayer dielectric material layer 200 subsequently, and the first hard mask layer 310 will be removed simultaneously when etching the interlayer dielectric material layer 200 subsequently. If there is too much remaining second hard mask layer 320, it may also cause the collapse of the second hard mask layer 320; if the thickness of the remaining second hard mask layer 320 is too small, the sidewall 210 on the side of the second hard mask layer 320 is likely to be damaged during the etching process. Therefore, in the step of removing a part of the thickness of the second hard mask layer 320, the thickness of the remaining second hard mask layer 320 is 2 nm to 20 nm. For example, the thickness of the remaining second hard mask layer 320 is 10 nm.

[0083] As an example, a situation where the top of the remaining second hard mask layer 320 is flush with the top of the remaining interlayer dielectric material layer 200 is shown. In other embodiments, according to the thickness of the second hard mask layer exposed after removing the first part of the thickness of the interlayer dielectric material layer and the thickness of the remaining second hard mask layer after removing a part of the thickness of the second hard mask layer, the top of the remaining second hard mask layer may also be higher than the top of the remaining interlayer dielectric material layer or lower than the top of the remaining interlayer dielectric material layer.

[0084] Reference Figure 6 , after removing a part of the thickness of the second hard mask layer 320, the second part of the thickness of the interlayer dielectric material layer 200 (as shown in Figure 5 ), the remaining second hard mask layer 320 (as shown in Figure 5 ) and the first hard mask layer 310 (as shown in Figure 5 ) are removed simultaneously. The remaining interlayer dielectric material layer 200 serves as the interlayer dielectric layer 230, and the interlayer dielectric layer 230 covers a part of the sidewall or the entire sidewall of the gate structure 220.

[0085] In this embodiment, the thinning of the interlayer dielectric material layer 200 is divided into two times. The first time is to remove a first part of the thickness of the interlayer dielectric material layer 200 to expose the second hard mask layer 320, and the top of the remaining interlayer dielectric material layer 200 is higher than the top of the first hard mask layer 310. Therefore, when removing the first part of the thickness of the interlayer dielectric material layer 200, the probability of the first hard mask layer 310 being damaged or removed is relatively low. Correspondingly, the probability of the second hard mask layer 320 collapsing is also relatively low. After that, a part of the thickness of the second hard mask layer 320 is removed, reducing the thickness of the second hard mask layer 320, which is beneficial to removing the remaining second hard mask layer 320 simultaneously when removing the second part of the thickness of the interlayer dielectric material layer 200 later. The second time is to simultaneously remove the second part of the thickness of the interlayer dielectric material layer 200, the remaining second hard mask layer 320, and the first hard mask layer 310 after removing a part of the thickness of the second hard mask layer 320. At this time, the thickness of the remaining second hard mask layer 320 is small, and the probability of the second hard mask layer 320 collapsing is still relatively low. In summary, by first removing the first part of the thickness of the interlayer dielectric material layer 200 to expose the second hard mask layer 320, and the top of the remaining interlayer dielectric material layer 200 is higher than the top of the first hard mask layer 310; and then, after removing a part of the thickness of the second hard mask layer 320, simultaneously removing the second part of the thickness of the interlayer dielectric material layer 200, the remaining second hard mask layer 320, and the first hard mask layer 310, while making the thickness of the interlayer dielectric layer 230 meet the process requirements, the problem of the second hard mask layer 320 collapsing is improved, ensuring the reliability of the process, and thus improving the performance of the semiconductor structure.

[0086] In this embodiment, a wet etching process is used to simultaneously remove the second part of the thickness of the interlayer dielectric material layer 200, the remaining second hard mask layer 320, and the first hard mask layer 310.

[0087] The wet etching process has the characteristic of isotropic etching, which is beneficial to simultaneously removing the second part of the thickness of the interlayer dielectric material layer 200, the remaining second hard mask layer 320, and the first hard mask layer 310 completely, and it is not easy to have residue remaining, thereby providing a good interface foundation for subsequent processes and further improving the formation quality of subsequent structures.

[0088] In this embodiment, the etching selectivity of the wet etching process for the interlayer dielectric material layer 200 and the second hard mask layer 320 is less than 5:1.

[0089] In this embodiment, the etching selectivity of the wet etching process for the interlayer dielectric material layer 200 and the second hard mask layer 320 should not be too large. If the etching selectivity of the wet etching process for the interlayer dielectric material layer 200 and the second hard mask layer 320 is too large, when etching to remove the second part of the thickness of the interlayer dielectric material layer 200 and the remaining second hard mask layer 320, it is not easy to remove the first hard mask layer 310 at the same time, resulting in residues of the second hard mask layer 320 being difficult to clean up. Moreover, when etching to remove the second part of the thickness of the interlayer dielectric material layer 200, the first hard mask layer 310 is easily removed, thereby increasing the probability of collapse of the remaining second hard mask layer 320. Therefore, the etching selectivity of the wet etching process for the interlayer dielectric material layer 200 and the second hard mask layer 320 is less than 5:1.

[0090] In this embodiment, after removing the second part of the thickness of the interlayer dielectric material layer 200, the height of the interlayer dielectric layer 230 is made to reach the target height.

[0091] Among them, according to the height of the gate structure 220 and the target height of the interlayer dielectric layer 230, the interlayer dielectric layer 230 covers a part of the sidewall or the entire sidewall of the gate structure 220.

[0092] Specifically, the target height of the interlayer dielectric layer 230 can be determined according to the target height of the metal gate structure.

[0093] It should be noted that the material of the second hard mask layer 320 includes silicon nitride, and the material of the sidewall 210 also includes silicon nitride. Therefore, during the etching process of the second hard mask layer 320, certain damage will be caused to the sidewall 210. However, in the subsequent manufacturing process, the sidewall layer higher than the interlayer dielectric layer 230 will be removed. Therefore, the damage caused to the sidewall 210 has little impact on the subsequent manufacturing process.

[0094] Reference Figure 7 , after forming the interlayer dielectric layer 230, it further includes: removing the sidewall 210 higher than the top of the interlayer dielectric layer 230.

[0095] By removing the sidewall 210 higher than the top of the interlayer dielectric layer 230, the remaining sidewall 210 reaches the target height required by the process.

[0096] In this embodiment, a dry etching process is used to remove the sidewall 210 higher than the top of the interlayer dielectric layer 230.

[0097] The dry etching process has the characteristic of anisotropic etching. Therefore, by selecting the dry etching process, it is beneficial to reduce the damage to the fin portion 220 and the interlayer dielectric layer 230. At the same time, the dry etching has more etching directionality, which is beneficial to improving the topography quality and dimensional accuracy of the sidewall 210, and it is easy to control the etching stop position during the etching of the sidewall 210.

[0098] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate, including a substrate and discrete fin portions located on the substrate, a gate structure spanning the fin portions is formed on the substrate, a first hard mask layer is formed on the top of the gate structure, a second hard mask layer is formed on the first hard mask layer, the material hardness of the first hard mask layer is less than the material hardness of the second hard mask layer, and an interlayer dielectric material layer covering the second hard mask layer is further formed on the substrate; Removing a first part of the thickness of the interlayer dielectric material layer to expose the second hard mask layer, and the remaining interlayer dielectric material layer covers the sidewalls of the first hard mask layer; Removing a part of the thickness of the second hard mask layer; After removing a part of the thickness of the second hard mask layer, simultaneously removing a second part of the thickness of the interlayer dielectric material layer, the remaining second hard mask layer and the first hard mask layer, and the remaining interlayer dielectric material layer serves as an interlayer dielectric layer, and the interlayer dielectric layer covers a part or the whole sidewall of the gate structure.

2. The method for forming a semiconductor structure according to claim 1, wherein, In the step of removing a first part of the thickness of the interlayer dielectric material layer to expose the second hard mask layer, the top of the remaining interlayer dielectric material layer is higher than the top of the first hard mask layer.

3. The method for forming a semiconductor structure according to claim 1, wherein In the step of providing the substrate, sidewalls are further formed on the sidewalls of the gate structure, the first hard mask layer and the second hard mask layer; After forming the interlayer dielectric layer, further including: removing the sidewalls higher than the top of the interlayer dielectric layer.

4. The method for forming a semiconductor structure according to claim 1, wherein, The material of the interlayer dielectric material layer is the same as the material of the first hard mask layer.

5. The method for forming a semiconductor structure according to claim 1, wherein, Adopting a wet etching process to simultaneously remove a second part of the thickness of the interlayer dielectric material layer, the remaining second hard mask layer and the first hard mask layer.

6. The method for forming a semiconductor structure according to claim 5, wherein, The etching selectivity of the wet etching process for the interlayer dielectric material layer and the second hard mask layer is less than 5:

1.

7. The method for forming a semiconductor structure according to claim 1, wherein, Adopting a wet etching process to remove a first part of the thickness of the interlayer dielectric material layer.

8. The method for forming a semiconductor structure according to claim 1, wherein, Adopting a dry etching process to remove a part of the thickness of the second hard mask layer.

9. The method for forming a semiconductor structure according to claim 8, wherein, The dry etching process includes a plasma etching process.

10. The method for forming a semiconductor structure according to claim 3, wherein, Adopting a dry etching process to remove the sidewalls higher than the top of the interlayer dielectric layer.

11. The method for forming a semiconductor structure according to claim 1, wherein, In the step of removing a first part of the thickness of the interlayer dielectric material layer, the thickness of the exposed second hard mask layer is 10 nm to 45 nm.

12. The method for forming a semiconductor structure according to claim 1, wherein, In the step of removing a part of the thickness of the second hard mask layer, the thickness of the remaining second hard mask layer is 2 nm to 20 nm.

13. The method for forming a semiconductor structure as claimed in claim 1, wherein, The material of the interlayer dielectric material layer includes silicon oxide.

14. The method for forming a semiconductor structure according to claim 1, wherein The material of the first hard mask layer includes silicon oxide.

15. The method for forming a semiconductor structure according to claim 1, wherein, The material of the second hard mask layer includes one or both of silicon nitride and carbon-doped silicon.

16. The method for forming a semiconductor structure according to claim 3, wherein, The material of the sidewalls includes one or both of silicon nitride and carbon-containing silicon oxide.

17. The method for forming a semiconductor structure according to claim 1, wherein, The gate structure is a dummy gate structure.

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