Scanning circuit and method

Abstract

Embodiments of the present disclosure relate to scan circuits and methods. In one embodiment, a method of performing a scan includes entering a scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and de-asserting a scan enable signal to perform a shift and a capture operation, respectively, on the first scan chain; controlling a further scan flip-flop with the first scan chain while applying the test pattern through the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect a fault.

Description

Technical Field

[0001] This disclosure generally relates to an electronic system and method, and in certain embodiments, to a scanning circuit and method. Background Technology

[0002] Fault testing is typically performed on integrated circuits (ICs). A method often called scan testing is used to perform general testing on logic circuits. During scan testing, a pattern is moved in through one or more flip-flop chains (also called scan chains) to stimulate one or more logic circuits. The result of stimulating the logic circuit is loaded into the scan chain and removed for evaluation. No fault is detected when the removed pattern matches the expected pattern (based on the correct functioning of one or more logic circuits). A fault is detected when the removed pattern does not match the expected pattern.

[0003] Figure 1 An exemplary launch-on-capture (LOC) waveform is shown for the scan chain clock signal clk and the scan enable signal scan_en. Figure 1 As shown, when scan_en is high, data (also known as test vectors, test patterns, vectors, or patterns) is shifted into the scan chain on each clock signal clk pulse. When the scan enable signal scan_en transitions low, the first pulse of the clock signal clk causes the logic circuit with inputs coupled to the scan chain to switch in a step commonly referred to as startup. The second pulse of the clock signal clk causes the output of the activated logic circuit to be loaded into the flip-flops of the scan chain. Once the scan enable signal scan_en transitions high, data in the scan chain is shifted out on each clock signal clk pulse. The shifted-out data is then subjected to fault evaluation.

[0004] It can perform high-speed startup and capture clock pulses to test logic circuits for faults related to switching delays.

[0005] like Figure 1 As shown, LOC testing allows data to be shifted in or out of the scan chain at a low speed while still performing full-speed testing of the logic circuitry. Therefore, in some implementations, LOC testing can be more easily implemented for the scan circuitry (compared to LOS testing) because the scan enable signal scan_en transition can be slow.

[0006] Figure 2 An exemplary launch-on-shift (LOS) waveform is shown for the scan chain clock signal clk and the scan enable signal scan_en. As shown, the LOS test is very similar to the LOC test. However, the LOS test performs the launch operation during the last shift pulse of the clock signal clk. Therefore, as... Figure 2 As shown, the scan enable signal scan_en is switched to a low state after the last shift pulse of the clock signal clk, but before the capture pulse of the clock signal clk.

[0007] Similar to LOC testing, LOS testing can be performed at high speed. Therefore, in some implementations, the scan enable signal scan_en is designed to switch quickly enough to allow full-speed testing during LOS.

[0008] from Figure 2 As can be seen, in some implementations, LOS testing can allow for faster test times (compared to LOC testing) because LOS testing uses the last shifted clock pulse to move data through the scan chain and to initiate the operation.

[0009] Figure 3 An exemplary pipelined LOS waveform is shown, comprising the scan chain clock signal clk, the scan enable signal scan_en, and the internal scan enable signal internal_scan_en. As illustrated, the pipelined LOS test is a hybrid of LOC and LOS tests. For example, pipelined LOS is similar to LOC because it performs high-speed startup and capture operations while the external scan enable signal "scan_en" is low. Pipeline LOS is similar to LOS because it performs the startup operation during the last shift pulse of the clock signal clk. However, pipelined LOS relies on the internal scan enable signal "internal_scan_en" (e.g., forced high) instead of the external scan enable signal "scan_en" for the capture operation, where the internal scan enable signal may be delayed (e.g., gated) based on, for example, timing design constraints. Therefore, pipelined LOS testing can allow for faster test times (compared to LOC testing) because pipelined LOS testing uses a clock pulse to enable the last shift using an internal scan enable, which is used to move data and initiate operations throughout the scan chain. It can also be easier to implement than LOS testing because the timing considerations for the scan enable signal scan_en can be relaxed.

[0010] In some implementations, the internal scan enable signal `internal_scan_en` can be changed from "1" to "0" on the negative edge of the start clock pulse instead of on the positive edge of the start clock pulse (e.g., ...). Figure 3 (As shown).

[0011] Scanning tests, for example, using Figure 1-3The illustrated implementation can be carried out in an automated test apparatus (ATE), where, for example, the ATE provides test vectors to the IC and evaluates the results (data shift out) to determine a fault. Scan testing can also be performed as a Logic Built-in Self-Test (LBIST), where the IC applies test vectors to itself (e.g., using a virtual random number generator) and determines whether a fault has occurred using the IC's LBIST controller. Summary of the Invention

[0012] According to one embodiment, a method of performing a scan includes: entering a scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to perform shift and capture operations on the first scan chain, respectively; while applying the test pattern through the first scan chain, controlling another scan trigger using the first scan chain without switching another scan enable input of the other scan trigger; and evaluating the output of the first scan chain to detect a fault.

[0013] According to one embodiment, an integrated circuit includes multiple logic circuits and a scanning circuit. The integrated circuit is configured to: enter a scanning mode; receive a test pattern; and apply the test pattern through a first scan chain of the scanning circuit via assertion and deassertion scan enable signals to perform shift and capture operations on the first scan chain, respectively. Furthermore, while applying the test pattern through the first scan chain, the first scan chain is used to control additional scan triggers of the scanning circuit without switching additional scan enable inputs of the additional scan triggers.

[0014] According to one embodiment, a method of performing a scan includes: entering a scan mode; receiving a test pattern; selecting a sub-scan chain to become part of a first scan chain; applying the test pattern through the first scan chain by asserting and deasserting a scan enable signal to perform shift and capture operations on the first scan chain, respectively; while applying the test pattern through the first scan chain, controlling an unselected sub-scan chain using the first scan chain without switching the scan enable input of the scan trigger of the unselected sub-scan chain, wherein the selected sub-scan chain has a length of N, the unselected sub-scan chain has a length of N, and N is a positive integer greater than or equal to 1; and evaluating the output of the first scan chain to detect a fault.

[0015] According to one embodiment, a method includes: entering a scan mode; receiving a test pattern; decompressing the test pattern; dynamically selecting a scan chain from a plurality of scan chains; applying the decompressed test pattern to the selected scan chain via a pulse clock signal and switching the scan enable signal coupled to the selected scan chain; applying the decompressed test pattern to an unselected scan chain without switching the scan enable signal coupled to the unselected scan chain; compressing the outputs of the plurality of scan chains; and evaluating the compressed output to detect faults. Attached Figure Description

[0016] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, wherein:

[0017] Figure 1-3 Exemplary start capture (LOC), start shift (LOS), and pipeline LOS waveforms according to the prior art are shown respectively;

[0018] Figure 4 , 5 Figures 6 and 6A illustrate a portion of a scanning circuit according to an embodiment of the present invention;

[0019] Figure 6B The waveform generated by the scanning circuit of FIG6 according to an embodiment of the present invention is shown;

[0020] Figure 7-11 A portion of the scanning circuit according to an embodiment of the present invention is shown;

[0021] Figure 12 and 13 A flowchart of an embodiment method for performing a scan according to an embodiment of the present invention is shown;

[0022] Figure 14 A flowchart of an embodiment method for scanning compression according to an embodiment of the present invention is shown; and

[0023] Figure 15 A flowchart of an embodiment of a method according to an embodiment of the present invention is shown for modifying a scan circuit to provide observability and / or controllability to logic circuitry added or modified after a scan insertion.

[0024] Unless otherwise stated, the numbers and symbols corresponding to different figures generally refer to the corresponding parts. These figures are drawn to clearly illustrate relevant aspects of the preferred embodiments and are not necessarily drawn to scale. Detailed Implementation

[0025] The following discussion details the implementation and use of the disclosed embodiments. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in various specific contexts. The specific embodiments discussed are merely illustrative of particular ways of carrying out and using the invention and do not limit the scope of the invention.

[0026] The following description illustrates various specific details to provide a thorough understanding of several exemplary embodiments according to the description. These embodiments may be obtained without one or more specific details, or by other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been shown or described in detail so as not to obscure different aspects of the embodiments. References to "an embodiment" in this specification indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in one embodiment" that may appear at different points in this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, specific constructions, structures, or features may be combined in any suitable manner.

[0027] Embodiments of the present invention will be described in a specific context, including the scanning circuitry of an IC, methods for performing scans using LBIST or ATPG modes, and methods for modifying the scanning circuitry, for example, after scan insertion. Embodiments of the present invention can be used with non-integrated circuits, such as circuits implemented on printed circuit boards (PCBs). Some embodiments can be used with LBIST modes other than ATPG, and / or without modifying the scanning circuitry after scan insertion.

[0028] In one embodiment of the invention, the scan circuitry including the first scan chain provides controllability during scan to logic circuitry having the output of an additional scan flip-flop not within the first scan chain. The additional scan flip-flop operates without switching its scan enable signal (e.g., similar to pipelined LOS mode, but the additional scan flip-flop's SE remains '1' in both clock pulses (start and capture) when scan_en = '0'). In some embodiments, by replacing a given scan flip-flop in the first scan chain, a scan flip-flop can be incorporated into the first scan chain without changing the length of the first scan chain (e.g., based on a select signal). When the additional scan flip-flop is incorporated into the first scan chain, the replaced given scan flip-flop operates without switching its scan enable signal (e.g., similar to pipelined LOS mode, but the replaced given scan flip-flop's SE is '1' in both clk pulses (make and capture) when scan_en = '0'), for example, providing controllability to logic circuitry coupled to the replaced given scan flip-flop.

[0029] Scanning circuitry may include, for example, one or more scan chains, test pattern compression and decompression circuitry, and other circuitry. Scanning circuitry is typically designed to, for example, detect faults in the IC under test (often referred to as the device under test, or DUT). In some applications, it is common practice to use Automated Test Pattern Generation (ATPG) technology to generate test patterns that maximize coverage and minimize execution time (often referred to as scan test time) while performing reliably and consistently.

[0030] In some ICs, both LBIST and ATPG can be implemented.

[0031] After scan insertion (e.g., once the scan circuitry and other functional circuitry of the IC have been implemented in the IC and timing closure has been performed), the scan circuitry is typically able to test the IC at the desired speed (e.g., full speed) using the test pattern.

[0032] It is not uncommon to make changes to one or more logic circuits after a scan insertion, which can be specified in an Engineering Change Order (ECO). For example, logic circuits (which may include one or more flip-flops) can be added or modified after a scan insertion, for example, to fix design problems (often referred to as bugs), add new functionality, or remove features. For instance, logic circuits can be added after a scan insertion to determine field aging.

[0033] When a logic circuit is modified after a scan insertion, it may not be covered by the already implemented scan circuit. For example, this lack of coverage could be due to unobservability or uncontrollability. Unobservability can result from the modified logic circuit not providing outputs to the flip-flops of the scan chain. Uncontrollability can stem from the modified logic circuit lacking inputs coupled to the scan chain that allow the scan chain to (e.g., effectively) stimulate the modified logic circuit with shifted data.

[0034] After the logic circuitry is changed, the scan circuitry can be modified to include additional flip-flops in the scan chain to cover the changed logic. Since adding new flip-flops to the scan chain changes the length of the scan chain and / or the flip-flop sequence, the LBIST controller, scan compressor and decompressor, and / or ATPG can be regenerated.

[0035] In some IC design flows, scan circuits can be designed with additional dummy flip-flops in the scan chain, allowing them to be used if the logic circuit changes after scan insertion. When the logic circuit changes after scan insertion, the dummy flip-flops are rerouted to provide coverage for the changed logic. However, if there is no logic circuit change after scan insertion, adding dummy flip-flops may unnecessarily increase the scan chain length. If there are not enough dummy flip-flops to accommodate the logic circuit change after scan insertion, it may be necessary to add new scan flip-flops to the scan chain to provide scan coverage for the changed logic. This may alter the scan chain length and / or the flip-flop sequence, LBIST controller, scan compressor and decompressor, and / or require ATPG regeneration.

[0036] In embodiments of the invention, during scan mode, scan triggers not in the scan chain are controlled by the scan chain. The scan enable input terminal of the scan trigger not in the scan chain remains active, causing the scan trigger not in the scan chain to operate in shift mode during scan. In some embodiments, the scan enable input terminal of the scan trigger not in the scan chain is not triggered during scan mode.

[0037] Some embodiments offer the advantage of enabling controllability of logic circuitry not directly controlled by scan triggers in the scan chain during a scan by using additional scan triggers not in the scan chain, thereby advantageously allowing controllability of the logic circuitry without interfering with the operation of the scan chain. Thus, some embodiments advantageously allow controllability of logic circuitry added, for example, after a scan insertion, without adding scan triggers to the scan chain, and in some embodiments, the use of virtual scan triggers in the scan chain is unnecessary.

[0038] Figure 4 A portion of a scan circuit 400 according to an embodiment of the present invention is shown. The scan circuit 400 includes a scan chain 402 comprising scan flip-flops 404, 406, 408, and 410 for testing logic circuits 424, 426, 428, and 430. The scan circuit 400 also includes a scan flip-flop 452 for controlling logic circuit 472. It will be understood that the scan chain 402 may include additional scan flip-flops (not shown).

[0039] In some embodiments, scan chain 402 can operate in LOC mode. For example, when the scan enable signal scan_en is asserted (e.g., high), during each pulse of the clock signal clk, scan flip-flops 404, 406, 408, and 410 perform a shift operation at their respective SI inputs by outputting data at their respective Q outputs. When the scan enable signal scan_en is deasserted (e.g., low), during the pulse of the clock signal clk, data at the respective D inputs of each scan flip-flop 404, 406, 408, and 410 is output at its respective Q output. Therefore, when the scan enable signal scan_en is deasserted, the outputs from logic circuits 424, 426, 428, and 430 are captured in scan flip-flops 404, 406, 408, and 410. After capture, the scan enable signal scan_en is asserted, causing each pulse of the clock signal clk to be shifted in scan chain 402.

[0040] The scan flip-flops of scan chain 402 can activate one or more logic circuits. For example, logic circuits 440 and 442 are activated by the outputs of scan flip-flops 406 and 408, respectively. Other logic circuits can be coupled to the outputs of one or more scan flip-flops in scan chain 402. In some embodiments, some scan flip-flops may not have logic circuits coupled to their outputs.

[0041] It should be understood that logic circuits 424, 426, 428, and 430 can (e.g., during startup operation) be activated by other circuits of scan chain 402, such as other scan chain flip-flops (not shown), or other scan chains. It should also be understood that one or more of scan flip-flops 404, 406, 408, and 410 can couple their output Q to one or more logic circuits (not shown).

[0042] In some embodiments, scan chain 402 can operate in LOS mode or pipeline mode without affecting the controllability of scan trigger 452 (e.g., the SE input of scan trigger 452 remains high).

[0043] Scan circuit 400 can be used to provide scan controllability to logic circuitry (e.g., 472) by using scan flip-flops (e.g., 452) that are not inside scan chain 402. For example, in Figure 4 In some embodiments, logic circuitry 472 may be controlled during a scan by the output of scan trigger 472, which is not within scan chain 402. In some embodiments, one or more outputs of logic circuitry 472 are coupled to scan triggers (not shown) during a scan.

[0044] In some embodiments, the controllability of trigger 452 can be as follows: During scan modes (e.g., in LBIST or ATPG modes), the output of OR gate 432 remains high. For example, the signal LBIST_mode can be received from a register bit that is high during LBIST mode. Similarly, the signal ATPG_mode can be received from a register bit that is high during ATPG mode.

[0045] Since the output of OR gate 432 remains high during the scan (e.g., regardless of whether the scan enable signal scan_en is high or low), the output of scan flip-flop 408 (which is coupled to the SI input of scan flip-flop 452) is output at the Q output of scan flip-flop 452 according to each pulse of the clock signal clk, thereby stimulating logic circuit 472 (which can capture its output using, for example, other scan flip-flops with, for example, LOC, LOS, or pipelined LOS).

[0046] like Figure 4 As shown, in some embodiments, by keeping the SE input of scan trigger 452 high during scan mode, scan chain 402 provides controllability to scan trigger 452 in a manner similar to pipelined LOS mode, without SE input transitions during startup and capture clk pulses. Therefore, some embodiments advantageously use shorter test patterns (due to extended pipelined LOS controllability) without the challenges associated with SE transitions during LOS mode and pipelined LOS mode, such as timing challenges associated with fast SE transitions.

[0047] In some embodiments, it is advantageous to add scan trigger 452 and / or logic circuitry 472 after scan insertion without modifying scan chain 402 (e.g., without increasing / decreasing the length of scan chain 402 or otherwise modifying scan chain 402 in a way that affects shift / start / capture operations of scan chain 402). Therefore, in some embodiments, logic circuitry 472 can be advantageously controlled (e.g., activated) during scanning by scan chain 402 without modifying scan chain 402.

[0048] Logic circuits 424, 426, 428, and 430 can be parts of the same or different logic circuits of an IC.

[0049] Scan triggers 404, 406, 408, 410, and 452 have D, SI, SE, CLK, and XR inputs and a Q output. Figure 4In the illustrated embodiment, the scan trigger is configured to output the value at D at Q when the CLK pulse and input SE are low. Scan triggers 404, 406, 408, 410, and 452 are configured to output the value at SI at Q when the CLK pulse and input SE are high. When input XR is set (e.g., low), the output at Q is cleared (e.g., set low). Scan triggers 404, 406, 408, 410, and 452 can be implemented in other ways known in the art.

[0050] In some embodiments, the output of logic circuit 472 may be coupled (e.g., directly connected) to a virtual scan trigger of scan chain 402. In some embodiments, the output of logic circuit 472 may be coupled (e.g., directly connected) to a virtual scan trigger of a scan chain different from scan chain 402.

[0051] In some embodiments, the frequency of the clock signal clk can be, for example, 500 MHz. Faster frequencies, such as 550 MHz, 800 MHz, or even faster, or slower frequencies, such as 450 MHz, 200 MHz, or even slower, can also be used. In some embodiments, when operating at high speed, the frequency of the clock signal clk can be based on the IC's functional specifications (e.g., datasheet).

[0052] In embodiments of the invention, the scan chain can be configured to select one scan trigger from a plurality of scan triggers to be located within the scan chain. In some embodiments, an unselected scan trigger among the plurality of scan triggers, although not within the scan chain, can receive input from the scan chain, for example, to control logic circuitry during a scan, such as in a mode similar to a pipelined LOS mode, where there is no SE input transition during startup and capture of the clk pulse.

[0053] Figure 5 A portion of a scan circuit 500 according to an embodiment of the present invention is shown. The scan circuit 500 includes a scan chain 502 comprising scan flip-flops 404, 406, and 410 for testing logic circuits 424, 426, 428, and 430. The scan circuit 500 also includes a scan flip-flop 452 for controlling logic circuit 472 and observing the output of logic circuit 572. As will be described in more detail later, the scan chain 502 also includes a scan flip-flop 408 or a scan flip-flop 452.

[0054] During a scan, the signal ff_sel selects either scan trigger 408 or scan trigger 452 within scan chain 502. For example, when ff_sel is low, the scan enable signal scan_en controls the SE input of scan trigger 408, and MUX 504 couples the Q output of scan trigger 408 to the SI input of scan trigger 410. Since ff_sel is coupled to the SE input of scan trigger 452 via inverter 508 and OR gate 510, the SE input of scan trigger 452 remains high when ff_sel is low. Therefore, when the signal ff_sel is low, the scan circuit 500 operates in a similar manner to the scan circuit 400 (e.g., the difference being that the scan flip-flop 406 provides controllability to the scan flip-flop 452 instead of the scan flip-flop 408), thereby providing controllability to the scan flip-flop 452 (which drives the logic circuit 472) in a manner similar to a pipelined LOS mode, without any SE input transitions during the start-up and capture of the clk pulse, and providing observability to the logic circuit 428 (via the scan flip-flop 408 and the MUX 504).

[0055] When the signal ff_sel is high, the scan enable signal scan_en controls the SE input of scan flip-flop 452. MUX 504 couples the Q output of scan flip-flop 452 to the SI input of scan flip-flop 410, and the SE input of scan flip-flop 408 remains high. Therefore, when the signal ff_sel is high, scan circuit 500 provides controllability to scan flip-flop 408 (its excitation logic circuit 442) in a pipeline-like LOS mode, without SE input switching during startup and capture clk pulses, and provides observability to logic circuit 572 (through scan flip-flop 452 and MUX 504).

[0056] In some embodiments, the outputs of OR gates 506 and 510 can be gated based on the scan mode signal scan_mode, which indicates whether the IC is in scan mode (e.g., using the corresponding AND gates).

[0057] For example Figure 5 As shown, some embodiments advantageously allow for scan observability and controllability to logic circuitry that can be added or modified after scan insertion without changing the length of the scan chain. For example, in one embodiment, logic circuitry 472 and 572, as well as scan trigger 452, can be added after scan insertion.

[0058] In some embodiments, a first set of test vectors can travel through scan chain 502 when the signal ff_sel is low, to provide observability to logic circuit 428 and controllability to logic circuits 442 and 472, for example, and a second set of test vectors can travel through scan chain 50 when the signal ff_sel is high, to provide observability to logic circuit 572 and controllability to logic circuits 442 and 472, for example. Therefore, in some embodiments, the signal ff_sel can be static when running a set of test patterns.

[0059] exist Figure 5 In some embodiments, scan trigger 408 is shown between two scan triggers. For example, when scan trigger 408 is selected in scan chain 502 (when signal ff_sel is low), scan trigger 408 receives its SI input from another scan trigger (scan trigger 406) in scan chain 502 and provides its Q output to another scan trigger (scan trigger 410) in scan chain 502. In some embodiments, scan trigger 408 may be implemented as the first scan trigger of scan chain 502 (e.g., receiving its SI input directly from the LBIST controller or from the ATE). In some embodiments, scan trigger 408 may be implemented as the last scan trigger of scan chain 502 (e.g., providing its Q output directly to the LBIST controller or the ATE).

[0060] In some embodiments, the scan chain is configured to dynamically select scan triggers within the scan chain, for example, based on a test pattern. Figure 6A A portion of a scan circuit 600 according to an embodiment of the present invention is shown. The scan circuit 600 includes a scan chain 602, which includes scan triggers 404, 406, and 410 and an Ethernet scan trigger 408 or 452. The scan circuit 600 also includes a scan chain 652. As will be described in more detail later, the scan chain 652 may be a scan chain that receives a test pattern that is not compressed using a test pattern compression technique.

[0061] exist Figure 6A In this embodiment, during scanning (when the scan_mode signal is high), if the static_sel signal is high, the scan circuit 600 operates in a similar manner to the scan circuit 500. For example, as Figure 6A As shown, when the static_sel signal is high, the ff_sel signal can be controlled based on the LBIST_FF_ctrl signal or the ATPF_FF_ctrl signal, for example, through the OR gate 608.

[0062] If the signal static_sel is low, then the signal ff_sel is controlled by scan chain 652. For example, when the signal static_sel is low, the signal ff_sel is equal to the signal sc_ff_sel. The signal sc_ff_sel is latched based on the scan enable signal scan_en and has a value based on the output of scan flip-flop 654. When the value of the signal sc_ff_sel is high, the value of the signal ff_sel is high, and scan circuit 600 provides observability to logic circuit 572 and controllability to logic circuits 442 and 472 (e.g., to relate to...). Figure 5 (Similar to the described manner). When the value of signal sc_ff_sel is low, the value of signal ff_sel is low, and scan circuit 600 provides observability to logic circuit 428 and controllability to logic circuits 442 and 472 (e.g., to relate to...). Figure 5 (Similar to the described method).

[0063] like Figure 6A As shown, some embodiments advantageously allow, during the execution of the test pattern, the dynamic selection of which scan trigger is in the scan chain (e.g., scan chain 602) based on the output of the scan trigger from another scan chain (e.g., scan chain 652).

[0064] In some embodiments, the signals LBIST_FF_ctrl and ATPF_FF_ctrl are based on their respective register bits. In some embodiments, the signal LBIST_FF_ctrl is generated by the LBIST controller 622. In some embodiments, the signal ATPF_FF_ctrl is generated outside the scan circuit 600, for example, by ATE or from register bits.

[0065] In some embodiments, the signal static_sel may be based on register bits (e.g., static_sel_reg) or bits stored in non-volatile memory (e.g., static_sel_nvm).

[0066] In some embodiments, a signal scan_mode indicating whether the IC including the scan circuit 600 is in scan mode is generated based on either the signal LBIST_mode (which indicates whether the scan circuit 600 is in LBIST mode) or the signal ATPG_mode (which indicates whether the scan circuit 600 is in ATPG mode). In some embodiments, the signals LBIST_mode and ATPG_mode are based on their respective register bits.

[0067] In some embodiments, the scan enable signal scan_en is generated based on the signal ATPG_SE (which is a scan enable signal associated with the ATPG test pattern), the signal LBIST_SE (which is a scan enable signal associated with the LBIST test pattern), and the signals ATPG_mode and LBIST_mode.

[0068] In some embodiments, the LBIST controller 622 is part of the scan circuit 600 and is configured to generate test patterns for logic circuitry (e.g., logic circuits 424, 426, 428, 430) used to test an IC. In some embodiments, the LBIST controller 622 uses a random number generator to generate the test patterns. The LBIST controller 622 can be implemented in any manner known in the art. Identical or similar LBIST controllers can be included in other scan circuits (e.g., scan circuits 400 or 500).

[0069] In some embodiments, scan trigger 654 is configured to control the state of the control signal ff_sel. Scan trigger 654 may be the first scan trigger of scan chain 652, the last scan trigger of scan chain 652, or a scan trigger coupled between the first and last scan triggers of scan chain 652.

[0070] Figure 6B The waveform of a scanning circuit 600 according to an embodiment of the present invention is shown. Figure 6B As shown, when the signal ff_sel is low, scan_en_alt1 is, for example, the same as the scan enable signal scan_en, while the signal scan_en_alt2 remains high. When the signal ff_sel is high, scan_en_alt2 is, for example, the same as the scan enable signal scan_en, while the signal scan_en_alt1 remains high. Therefore, in some embodiments, one of the alternative scan flip-flops (e.g., 408 / 452) operates in, for example, LOC mode, while the other of the alternative scan flip-flops (e.g., 452 / 408) shifts during each pulse of the clock signal clk, regardless of the state of the scan enable signal scan_en.

[0071] Scan circuit 600 is one possible implementation for dynamically selecting which scan trigger is in the scan chain (e.g., scan chain 602) during the execution of the test pattern, based on the output of the scan trigger from another scan chain (e.g., scan chain 652). Other implementations are also possible. For example, Figure 7A portion of a scanning circuit 700 according to an embodiment of the present invention is shown. The scanning circuit 700 is similar to the scanning circuit 600 and can operate in a similar manner to the scanning circuit 600. In some embodiments, the scanning circuit 700 can generate... Figure 6B The waveforms shown are similar or identical. However, the scan circuit 700 includes a latch 704 instead of a scan trigger 604.

[0072] Latch 704 is configured to latch the value of its D input and output the value at its Q output when its L input transitions from high to low. Latch 704 may be implemented in any manner known in the art.

[0073] In some embodiments, more than one scan flip-flop can be selected (statically or dynamically) as part of a scan chain, while others provide controllability to one or more logic circuits in a mode similar to a pipelined LOS mode, without requiring the start-up and capture of SE input transitions in the clock pulse. For example, Figure 8 A portion of a scan circuit 800 according to an embodiment of the present invention is shown. Scan circuit 800 is similar to and operates in a similar manner to scan circuit 600. However, scan circuit 800 has two scan flip-flops that can be selected as part of scan chain 802. For example, when signal ff_sel is low, scan flip-flops 406 and 408 provide observability to logic circuits 426 and 428, respectively, and controllability to logic circuits 440 and 442, respectively, while scan flip-flops 852 and 452 provide controllability to logic circuits 874 and 472 in a mode similar to a pipelined LOS mode, without SE input transitions during startup and capture of clk pulses. When the signal ff_sel is high, scan flip-flops 852 and 452 provide observability to logic circuits 872 and 572, respectively, and controllability to logic circuits 874 and 472, respectively. Meanwhile, scan flip-flops 406 and 408 provide controllability to logic circuits 440 and 442 in a pipeline-like LOS mode, respectively. There is no SE input transition during startup and capture of clk pulses.

[0074] like Figure 8 As shown, and with Figure 6A and 6B Similarly, signals ff_sel, scan_en_altl, and scan_en_alt2 can be generated by circuit 640. In some embodiments, scan circuit 800 can be replaced by circuit 740 instead of circuit 640 (where latch 704 is used instead of scan trigger 604). Other implementations are also possible.

[0075] like Figure 8As shown, alternative optional scan triggers 852 and 452 can be understood as part of an alternative scan chain 803, which is alternatively optional based on the signal ff_sel to replace a portion of a scan chain 802 of similar length (the same number of scan triggers, two scan triggers in this example). In some embodiments, the alternative scan chain 803 may have more than two scan triggers. For example, in some embodiments, the alternative scan chain 803 has L scan triggers that are alternatively optional based on the signal ff_sel to replace L scan triggers of the scan chain 802, where L is a positive integer greater than or equal to 1, such as 2, 3, 4, 10, 50, 100, or higher.

[0076] In some embodiments, the scan chain may have more than one independent section, which is optional based on the signal ff_sel alternative. For example, Figure 9 A portion of a scanning circuit 900 according to an embodiment of the present invention is shown. The scanning circuit 900 includes a scanning chain 802 having five sections (802a, 802b, 802c, 802d, and 802e).

[0077] During scan mode, scan chain 802 at its input (si 802 ) receives the test pattern at its output (so 802 Output is generated at (). When the signal ff_sel is low, scan chain 802 is synchronized with the output when the signal ff_sel is low. Figure 8 The operation is similar to that described above. When the signal ff_sel is high, alternative scan chains 803 and 903 replace portions 802b and 802d of scan chain 802, respectively, so that portions 802b and 802d are controllable in a mode similar to pipeline LOS mode, without SE input conversion during startup and capture clk pulses.

[0078] like Figure 9 As shown, MUX 504 and 904 are controlled by the signal ff_sel, parts 802b and 802d receive the same signal scan_en_alt1 (e.g., scan enable for the scan triggers of parts 802b and 802d), and scan chains 803 and 903 receive the same signal scan_en_alt2 (e.g., scan enable for the scan triggers of parts 803 and 903). In some embodiments, signals ff_sel, scan_en_alt1, and scan_en_alt2 can be generated, for example as follows: Figure 8As shown. Other implementations are also possible. For example, in some embodiments, MUX 504, part 802b, and scan chain 803 may receive a first set of signals (e.g., signals ff_sel1, scan_en_alt11, and scan_en_alt21, respectively), and MUX 904, part 802d, and scan chain 903 may receive a second set of signals (e.g., signals ff_sel2, scan_en_alt12, and scan_en_alt22, respectively), wherein the first and second sets of signals are generated based on different scan triggers. For example, in some embodiments, the first set of signals may be based on scan trigger 654, while the second set of signals may be based on another scan trigger, which may be scan chain 652 or another scan trigger of another scan chain.

[0079] In some embodiments, alternative scan chains 803 and 903 have the same length. For example, in some embodiments, both scan chains 803 and 903 have a scan trigger. In other embodiments, scan chains 803 and 903 may have more than one scan trigger, such as 2, 3, 10 or more.

[0080] In some embodiments, alternative scan chains 803 and 903 have different lengths. For example, in some embodiments, scan chain 803 has two scan triggers while scan chain 903 has three scan triggers. It is also possible to use different numbers of scan triggers for scan chains 803 and 903.

[0081] Although Figure 9 Two alternative scan chains (803 and 903) are shown, but more than two alternative scan chains can be used in the same scan chain (802).

[0082] It should be understood that scanning circuits 400, 500, 600, 700, 800 and 900 can be adapted to operate with signals of different polarities.

[0083] In some embodiments, the test pattern traveling through the scan chain 652 is not decompressed / compressed. For example, Figure 10 A portion of a scan circuit 1000 according to an embodiment of the present invention is shown. The scan circuit 1000 includes a decompressor 1002, a compressor 1004, a plurality of scan chains coupled between the decompressor 1002 and the compressor 1004, and a compression-independent scan chain 1008.

[0084] Despite Figure 10The scanning circuit 1000 is illustrated as having 10 inputs (si1 to si10) coupled to the decompressor 1002, 10 outputs (so1 to so10) coupled to the compressor 1004, and 100 scan chains coupled between the decompressor 1002 and the compressor 1004. It should be understood that different numbers of scan inputs coupled to the decompressor 1002 (e.g., 9, 8 or lower, or 11, 15, 20 or higher), different numbers of scan outputs (e.g., 9, 8 or lower, or 11, 15, 20 or higher), and / or different numbers of scan chains coupled between the decompressor 1002 and the compressor 1004 (e.g., 99, 90, 50 or lower, or 101, 110, 1000 or higher) are also possible.

[0085] During a scan, decompressor 1002 receives compressed test patterns at its inputs (e.g., si1 to si10) from, for example, LBIST controller 622 or ATE. The inputs (e.g., si1 to si10) coupled to decompressor 1002 are decompressed in a known manner and converted into multiple outputs coupled to multiple scan chains (e.g., scan chain 1 to scan chain 100). Data output from the multiple scan chains (e.g., scan chain 1 to scan chain 100) is compressed in a known manner and converted into compressed outputs (e.g., so1 to so10). The compressed outputs are transmitted to, for example, LBIST controller 622 or ATE and evaluated in a known manner to detect faults in logic circuitry coupled to the multiple scan chains (e.g., scan chain 1 to scan chain 100). By using decompressor 1002 and compressor 1004, some embodiments advantageously run test patterns across N scan chains using fewer than N inputs and outputs (e.g., 10 times fewer inputs and outputs).

[0086] In some embodiments, one or more scan chains among a plurality of scan chains (e.g., scan chain 1 to scan chain 100) can be implemented as scan chains 402, 502, 602, 802, or / or 902. For example, in Figure 10 In the embodiments, scan chain i (also known as scan chain 1006) can be implemented as 402, 502, 602, 802 or 902, where i is an integer greater than or equal to 1 and less than or equal to 100.

[0087] In some embodiments, at least one scan chain is not coupled between the decompressor and the compressor. For example, such as Figure 10 As shown, in the scan circuit 1000, the scan chain 1008 is not coupled between the decompressor 1002 and the compressor 1004, and is, for example, independent of compression. For example, in some embodiments, the scan chain 1008 may be used, for example, for on-chip clock (OCC), power control, shift power control (SPC), etc.

[0088] In some embodiments, scan chain 1008 is implemented as scan chain 652 and includes scan trigger 654. For example, in some embodiments, scan chain 1006 is implemented as scan chain 602 and scan chain 1008 is implemented as scan chain 652, such that scan chains 1006 and 1008 are configured to interact with each other regarding... Figure 6A The operation is similar to that described above. As another example, in some embodiments, scan chain 1006 is implemented as scan chain 802 and scan chain 1008 is implemented as scan chain 652, such that scan chains 1006 and 1008 are configured to operate in a manner consistent with... Figure 8 It operates in a similar manner. Other implementations are also possible.

[0089] In some embodiments, the same scan enable signal scan_en is applied to all scan chains of circuit 800. For example, in some embodiments, the same scan enable signal scan_en is applied to scan chains 1 to 100 and scan chain 1008. In some embodiments, the scan enable signal scan_en may be generated by (e.g., a single) circuit 613.

[0090] As shown in Figures 6 and 7, some embodiments advantageously allow (statically or dynamically) selection of which scan trigger to use within the scan chain, wherein the selected scan trigger provides observability and controllability (e.g., in LOC mode), and the non-selected scan trigger provides controllability in a mode similar to pipelined LOS mode, without SE input transitions during startup and capture of the clk pulse. Figure 8 As shown, some embodiments advantageously allow (static or dynamic) selection of which sub-scan chain to use within the scan chain, wherein the selected sub-scan chain provides observability and controllability (e.g., in LOC mode), and the unselected sub-scan chain provides controllability in a mode similar to pipeline LOS mode, without SE input conversion in the start and capture clk pulses.

[0091] In some embodiments, the size of the sub-scan chain can be the same as the size of the scan chain. In other words, in some embodiments, a scan chain can be selected from two scan chains such that the selected scan chain provides controllability and observability (e.g., in LOC mode), while the unselected scan chain provides controllability in a mode similar to pipeline LOS mode, without SE input transitions during startup and capture clk pulses. For example, Figure 11 A portion of a scan circuit 1100 according to an embodiment of the present invention is shown. The scan circuit 1100 includes a decompressor 1102, a compressor 1104, a plurality of scan chains coupled between the decompressor 1102 and the compressor 1104, and a compression-independent scan chain 1008.

[0092] like Figure 11 As shown, the scan circuit 1100 can dynamically select a first group of scan chains (scan chains 1 to 100) or a second group of scan chains (scan chains 101 to 200) to provide observability and controllability to the logic circuits of the scan chains coupled to the selected scan chain group, while an unselected scan chain group provides controllability to the logic circuits of the scan chains coupled to the unselected scan chain group.

[0093] like Figure 11 As shown, signals ff_sel, scan_en_altl, and scan_en_alt2 can be generated by circuit 640. Signal ff_sel is applied to all MUXs 1112, 1114, 1116, 1118, 1120, and 1122. Signal scan_en_alt1 is applied to the SE inputs of all scan flip-flops in scan chains 1 to 100. Signal scan_en_alt2 is applied to the SE inputs of all scan flip-flops in scan chains 101 to 200.

[0094] MUX 1112, 1114, 1116, 1118, 1120 and 1122 are configured to select between the first set of scan chains (scan chains 1 to 100) and the second set of scan chains (scan chains 101 to 200) based on the signal ff_sel.

[0095] In some embodiments, when ff_sel is low, scan chains 1 to 100 provide observability to logic circuits having outputs of scan flip-flops coupled to scan chains 1 to 100 and controllability to logic circuits having inputs of scan flip-flops coupled to scan chains 1 to 100 (e.g., in LOC mode), and scan chains 101 to 200 provide controllability to logic circuits having inputs of scan flip-flops coupled to scan chains 101 to 200 in a mode similar to pipelined LOS mode, without SE input switching during startup and capture clk pulses. When ff_sel is high, scan chains 101 to 200 provide observability to logic circuits with outputs of scan flip-flops coupled to scan chains 101 to 200 and controllability to logic circuits with inputs of scan flip-flops coupled to scan chains 101 to 200 (e.g., in LOC mode), and scan chains 1 to 100 provide controllability to logic circuits with inputs of scan flip-flops coupled to scan chains 1 to 100 in a mode similar to pipelined LOS mode, without SE input switching during startup and capture clk pulses.

[0096] In some embodiments, the logic circuitry controllable by scan chains 101 to 200 has outputs coupled to scan flip-flops of scan chains 1 to 100 such that they are observable when the signal ff_sel is low. In some embodiments, the logic circuitry controllable by scan chains 1 to 100 has outputs coupled to scan flip-flops of scan chains 101 to 200 such that they are observable when the signal ff_sel is high.

[0097] like Figure 11 As shown, some embodiments can be implemented using a decompressor 1102 that independently drives each of the scan chains 1 to 200. In other embodiments, the decompressor 1102 can provide the same input to scan chains i and i+100 (e.g., scan chains 1 and 101 are driven by the same input, etc.). By independently driving each of the scan chains 1 to 200, some embodiments advantageously achieve higher coverage and / or lower test time compared to embodiments with scan chains i and 100+i sharing the same input.

[0098] Some advantages of these embodiments include reduced scan test time without compromising scan coverage, and the elimination of the need to design scan enable signals to meet the fast transition times between LOS mode and pipelined LOS mode. For example, a conventional codec with an LOC architecture and an internal scan chain length of 100 (100 scan triggers), 10,000 test patterns, and a 40ns clock cycle could result in a test time of 4,040,400ns (because ((10,000*100)+10,000+100)*40=4,040,400ns). If the decompression / compression architecture of the embodiments is used, for example... Figure 11 As shown, a scan chain with half the length (e.g., 50) can be used. For this architecture, similar coverage can be achieved using approximately 19,000 test patterns, with a test time of 38,762,000 ns over a 40 ns clock cycle (because ((19000*50)+19000+50)*40=38,762,000ns). Therefore, the saved test time could be approximately 1,642,000 ns, or more than 4%.

[0099] Figure 12 A flowchart of an embodiment method 1200 for performing a scan according to an embodiment of the present invention is shown. Method 1200 may be implemented, for example, by scanning circuits 400, 500, 600, 700, 800, 900, 1000 or 1100.

[0100] During step 1202, an IC including a scan circuit (e.g., 400, 500, 600, 700, 800, 900, 1000, 1100) enters a scan mode. In some embodiments, entering a scan mode includes asserting (e.g., high) a scan mode signal (e.g., scan_mode). In some embodiments, entering LBIST mode (e.g., LBIST_mode set high) or entering ATPG mode (e.g., ATPG_mode set high) causes the scan mode signal to be asserted.

[0101] In some embodiments, the scanning circuit can enter either LBIST mode or ATPG mode, but not both simultaneously. In some embodiments, the scanning circuit can enter both LBIST mode and ATPG mode.

[0102] During step 1204, the scanning circuit receives a test pattern. For example, in some embodiments, the scanning circuit receives the test pattern directly from the ATPG or LBIST controller into the input of a first scan chain (e.g., at the SI input of the first scan trigger of the first scan chain, where the first scan chain may be, for example, scan chain 402, 502, 602, or 802). In some embodiments, the test pattern is received at the input of a decompressor (e.g., 1002, 1102) having an output coupled to the first scan trigger of the first scan chain.

[0103] During step 1206, the received pattern is decompressed by a decompressor in a known manner and applied to the first scan chain. In embodiments where the first scan chain is independent of compression, step 1206 may be omitted.

[0104] During step 1208, when the test pattern is applied to the first scan chain (e.g., in LOC mode), an additional scan trigger (e.g., 452) is controlled using the output of the scan trigger of the first scan chain (e.g., 408) without switching the SE input of the additional scan trigger (e.g., in a mode similar to pipelined LOS mode, there is no SE input switching during startup and capture clk pulses), for example, to control additional logic circuitry (e.g., 472) using the additional scan trigger. In some embodiments, the output of the additional logic circuitry is coupled to the scan trigger of the first scan chain. In some embodiments, the output of the additional logic circuitry is coupled to the scan trigger of a different scan chain than the first scan chain.

[0105] During step 1210, the output of the first scan chain is compressed by a compressor (e.g., 1004, 1104) and output for evaluation. In embodiments where the first scan chain is independent of compression, step 1210 may be omitted.

[0106] During step 1212, the output of the first scan chain is evaluated in a known manner to detect faults (e.g., fixed faults, timing faults, etc.) in logic circuits having outputs coupled to the first scan chain.

[0107] like Figure 12 As shown, some embodiments advantageously provide controllability throughout the first scan chain to additional scan triggers that are not within the first scan chain during scan mode.

[0108] Figure 13 A flowchart of an embodiment of a scanning method 1300 according to an embodiment of the present invention is shown. Method 1300 may be implemented, for example, by scanning circuits 500, 600, 700, 800, 900, 1000, or 1100. Method 1300 includes steps 1202, 1204, 1206, 1302, 1304, 1210, and 1212. Steps 1202, 1204, 1206, 1210, and 1212 may be performed in a manner similar to that of method 1200.

[0109] During step 1302, one of the two sub-scan chains is selected to become part of the first scan chain. In some embodiments, the selected sub-scan chain receives input at the SI input of the first scan trigger of the selected sub-scan chain from the Q output of the scan trigger of the first scan chain, and provides the output at the Q output of the last scan trigger of the selected sub-scan chain to the SI input of the scan trigger of the first scan chain. In some embodiments, the unselected sub-scan chain receives input at the SI input of the first scan trigger of the unselected sub-scan chain from the Q output of the scan trigger of the first scan chain, but the output at the Q output of the last scan trigger of the unselected sub-scan chain is not coupled to the SI input of the scan trigger of the first scan chain.

[0110] The lengths of the two sub-scan chains can be one or more. For example, in some embodiments (e.g., scan circuits 500, 600, and 700), the length of the two sub-scan chains can be a single scan trigger (e.g., scan trigger 452 is one sub-scan chain, and scan trigger 408 is another sub-scan chain). In other embodiments (e.g., scan circuits 800 and 1100), the two sub-scan chains can have more than one scan trigger, such as two or more. For example, scan circuit 800 shows an embodiment with two sub-scan chains, each sub-scan chain having two scan triggers (one with scan triggers 406 and 408, and the other with scan triggers 852 and 452).

[0111] In some embodiments, a sub-scan chain is selected based on the state of a selection signal (e.g., ff_sel). In some embodiments, the state of the selection signal is based on a register bit (e.g., LBIST_FF_ctrl or ATPF_FF_ctrl). In some embodiments, the state of the selection signal is based on the output of a scan trigger (e.g., 654) of the scan chain.

[0112] During step 1304, when the test pattern is applied to the first scan chain (e.g., in LOC mode), additional scan triggers of unselected sub-scan chains are controlled using the outputs of the scan triggers of the first scan chain without switching the SE inputs of the additional scan triggers (e.g., in a mode similar to pipelined LOS mode, there is no SE input switching during startup and capture clk pulses), for example, to control additional logic circuitry using the additional scan triggers. In some embodiments, the outputs of the additional logic circuitry are coupled to the scan triggers of the first scan chain. In some embodiments, the outputs of the additional logic circuitry are coupled to scan triggers of a different scan chain than the first scan chain.

[0113] Figure 14 A flowchart of an embodiment of a method 1400 for scanning compression according to an embodiment of the present invention is shown. Method 1400 may be implemented, for example, by a scanning circuit 1100. Method 1400 includes steps 1202, 1402, 1404, 1406, 1408, and 1410. Step 1202 may be performed in a manner similar to that of method 1200.

[0114] During step 1402, a test pattern is received at the input (e.g., si1 to si10) of a scan circuit (e.g., 1100). During step 1404, the test pattern is decompressed by a decompressor (e.g., 1102) such that the test pattern is applied to multiple scan chains.

[0115] During step 1406, scan chains from a plurality of scan chains (scan chains 1 to 200) are dynamically selected (e.g., scan chains 1 to 100 or 101 to 200 are selected) such that a test pattern is applied to the selected scan chain, for example in LOC mode, while unselected scan chains are controlled in a mode similar to pipeline LOS mode, without SE input conversion during startup and capture clk pulses. In some embodiments, a selection signal (e.g., ff_sel) is used to select between a first group (e.g., scan chains 1 to 100) and a second group (e.g., scan chains 101 to 200). In some embodiments, the selection signal is controlled, for example, by the output of a scan trigger (e.g., 654) in a compression-independent scan chain (e.g., scan chain 1008).

[0116] During step 1408, the outputs of multiple scan chains are compressed so that they can be evaluated during step 1410 to detect faults.

[0117] Some embodiments advantageously allow for observability and / or controllability of logic circuitry added after scan insertion without affecting the original scan chain length. For example, Figure 15 A flowchart of an embodiment of a method 1500 according to an embodiment of the present invention is shown for modifying a scan circuit to provide observability and / or controllability to logic circuits added or modified after a scan insertion.

[0118] During step 1502, the SI input of another scan trigger is coupled to the Q output of the scan trigger of the first scan chain. For example, as Figure 5 , 6A As shown in Figure 7, in some embodiments, the SI input of an additional scan trigger (e.g., 452) is coupled to the Q output of a scan trigger (e.g., 406) of a first scan chain (e.g., 502, 602). In some embodiments, such as... Figure 4 As shown, the SI input of an additional scan trigger (e.g., 452) is coupled to the Q output of a scan trigger (e.g., 408) in the first scan chain (e.g., 402). In some embodiments, an additional scan trigger may be added after the scan insertion. In other embodiments, no additional scan trigger is added after the scan insertion. For example, in some embodiments, the additional scan trigger may be an already implemented dummy scan trigger, for example, in one of the scan chains of the IC.

[0119] During step 1504, the Q output of another scan trigger is coupled to another logic circuit (e.g., 472). In some embodiments, steps 1502 and 1504 are performed to provide controllability to the other scan trigger in a mode similar to a pipelined LOS mode, without SE input transitions during the start-up and capture clk pulses, such that the other logic circuit is activated when the first scan chain runs the test pattern.

[0120] During step 1506, the Q output of the additional scan trigger is further coupled to the SI input of another scan trigger (e.g., 410), for example via a MUX (e.g., 504). When the additional scan trigger is selected by the MUX, the length of the first scan chain does not change, for example, because the additional scan trigger replaces the original scan trigger (e.g., 408) upon selection.

[0121] In some embodiments, the selection signal (e.g., ff_sel) for controlling the MUX is based on a scan trigger (e.g., 654) of the scan chain (e.g., 652). In some embodiments, the scan trigger (e.g., 654) is implemented as a virtual scan trigger before scan insertion, for example, such a trigger is intended to be used to control the selection signal.

[0122] In some embodiments, all or part of the additional logic for performing steps 1502, 1504, and / or 1506 (e.g., circuits 432, 504, 506, 508, 510, 606, 608, 610, 613, 614, 616, 618, 620, 624, 626, and / or 904) may be added after the scan insertion. In some embodiments, all or part of the additional logic for performing steps 1502, 1504, and / or 1506 may be implemented before the scan insertion and the coupling may be modified after the scan insertion.

[0123] In some embodiments, step 1506 may be omitted.

[0124] Some of the advantages of the embodiments include providing a static or dynamic selection of scan triggers to be included in the scan chain, while unselected scan triggers provide additional controllability using a pipelined LOS architecture-like pattern, but the SE input remains high throughout the capture.

[0125] Exemplary embodiments of the invention are summarized herein. Other embodiments may also be understood from the entire specification and the claims filed herein.

[0126] Example 1. A method for performing a scan, the method comprising: entering a scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to perform shift and capture operations on the first scan chain, respectively; controlling another scan trigger using the first scan chain while applying the test pattern through the first scan chain without switching another scan enable input of the other scan trigger; and evaluating the output of the first scan chain to detect a fault.

[0127] Example 2. The method described in Example 1, wherein an additional scan enable input is kept high while the test pattern is applied through the first scan chain.

[0128] Example 3. The method according to Example 1 or 2 further includes decompressing the compressed input test pattern to generate the test pattern.

[0129] 4. The method according to any one of Examples 1 to 3, wherein controlling an additional scan trigger using a first scan chain comprises: controlling the additional scan trigger using the output of a first given scan trigger of the first scan chain, the output of the first given scan trigger being further coupled to the SI input of a second given scan trigger of the first scan chain, the method further comprising: generating a selection signal; and selectively connecting the output of the second given scan trigger or the output of the additional scan trigger to the input of a third given scan trigger of the first scan chain based on the selection signal.

[0130] Example 5. The method according to any one of Examples 1 to 4, wherein generating the selection signal includes generating the selection signal based on register bits.

[0131] Example 6. The method according to any one of Examples 1 to 5, wherein generating the selection signal includes generating the selection signal based on a scan trigger of another scan chain.

[0132] Example 7. The method according to any one of Examples 1 to 6, wherein the first scan chain depends on compression, and the other scan chain does not depend on compression.

[0133] Example 8. The method according to any one of Examples 1 to 7, wherein receiving the test pattern includes receiving the test pattern from an LBIST controller.

[0134] Example 9. The method according to any one of Examples 1 to 8, wherein receiving the test pattern includes receiving the test pattern from an automated test equipment (ATE).

[0135] Example 10. The method according to any one of Examples 1 to 9, wherein entering the scan mode includes asserting a scan mode signal.

[0136] Example 11. An integrated circuit includes: a plurality of logic circuits; and a scanning circuit, wherein the integrated circuit is configured to: enter a scanning mode; receive a test pattern; apply the test pattern through a first scan chain of the scanning circuit by asserting and deasserting scan enable signals to perform shift and capture operations on the first scan chain, respectively; and apply the test pattern through the first scan chain to control additional scan triggers of the scanning circuit using the first scan chain without switching additional scan enable inputs of the additional scan triggers.

[0137] Example 12. The integrated circuit according to Example 11 further includes an LBIST controller configured to provide the test pattern.

[0138] Example 13. The integrated circuit according to Example 11 or 12 further includes an OR gate having an output coupled to the additional scan enable input of the additional scan trigger, the output of the OR gate indicating whether the integrated circuit is in scan mode.

[0139] Example 14. An integrated circuit according to any one of Examples 11 to 13, wherein the scan circuit further includes a multiplexer (MUX) having a first input coupled to the output of a scan trigger of the first scan chain, a second input coupled to the output of the other scan trigger, and an output coupled to the first scan chain.

[0140] Example 15. The integrated circuit according to any one of Examples 11 to 14 further includes a second additional scan trigger having an output coupled to a selection input of the MUX.

[0141] Example 16. An integrated circuit according to any one of Examples 11 to 15, wherein the second additional scan trigger is part of a second scan chain that is different from the first scan chain.

[0142] Example 17. The integrated circuit according to any one of Examples 11 to 16 further includes a third additional scan trigger having a clock input coupled to a scan enable input of the second additional scan trigger and an output coupled to a selection input of the MUX.

[0143] Example 18. The integrated circuit according to any one of Examples 11 to 17 further includes a latch coupled between the second additional scan trigger and the selection input of the MUX.

[0144] Example 19. A method of performing a scan, the method comprising: entering a scan mode; receiving a test pattern; selecting a sub-scan chain to become part of a first scan chain; applying the test pattern through the first scan chain by asserting and deasserting a scan enable signal to perform shift and capture operations on the first scan chain, respectively; while applying the test pattern through the first scan chain, controlling an unselected sub-scan chain using the first scan chain without switching the scan enable input of a scan trigger of the unselected sub-scan chain, wherein the selected sub-scan chain has a length of N, the unselected sub-scan chain has a length of N, and N is a positive integer greater than or equal to 1; and evaluating the output of the first scan chain to detect a fault.

[0145] Example 20. The method according to Example 19, wherein the first scan chain has a length of N.

[0146] Example 21. A method comprising: entering a scan mode; receiving a test pattern; decompressing the test pattern; dynamically selecting a scan chain from a plurality of scan chains; applying the decompressed test pattern to the selected scan chain via a pulse clock signal and switching a scan enable signal coupled to the selected scan chain; and applying the decompressed test pattern to an unselected scan chain without switching the scan enable signal coupled to the unselected scan chain; compressing the outputs of the plurality of scan chains; and evaluating the compressed outputs to detect faults.

[0147] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Referring to the specification, those skilled in the art will understand various modifications and combinations of exemplary embodiments and other embodiments of the invention. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A method of performing a scan, the method comprising: entering a scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and de-asserting a scan enable signal to perform shift and capture operations, respectively, on the first scan chain; controlling a further scan flip-flop of the first scan chain with the first scan chain without transitioning a further scan enable input of the further scan flip-flop while applying the test pattern through the first scan chain; and evaluating an output of the first scan chain to detect a fault.

2. The method of claim 1, wherein the further scan enable input is held high while applying the test pattern through the first scan chain.

3. The method of claim 1, further comprising decompressing a compressed input test pattern to generate the test pattern.

4. The method of claim 1, wherein controlling the additional scan flip-flops with the first scan chain comprises: controlling the further scan flip-flop with an output of a first given scan flip-flop of the first scan chain, the output of the first given scan flip-flop further coupled to a SI input of a second given scan flip-flop of the first scan chain, the method further comprising: generating a selection signal; and selectively connecting an output of the second given scan flip-flop or an output of the further scan flip-flop to an input of a third given scan flip-flop of the first scan chain based on the selection signal.

5. The method of claim 4, wherein generating the selection signal comprises generating the selection signal based on a register bit.

6. The method of claim 4, wherein generating the selection signal comprises generating the selection signal based on a scan flip-flop of a further scan chain.

7. The method of claim 6, wherein the first scan chain is compression dependent and the further scan chain is compression independent.

8. The method of claim 1, wherein receiving the test pattern comprises receiving the test pattern from an LBIST controller.

9. The method of claim 1, wherein receiving the test pattern comprises receiving the test pattern from an automatic test equipment (ATE).

10. The method of claim 1, wherein entering a scan mode comprises asserting a scan mode signal.

11. An integrated circuit comprising: a plurality of logic circuits; and a scan circuit, wherein the integrated circuit is configured to: enter a scan mode; receive a test pattern; apply a test pattern through a first scan chain of the scan circuit by asserting and de-asserting a scan enable signal to perform shift and capture operations, respectively, on the first scan chain, and control a further scan flip-flop of the scan circuit with the first scan chain without transitioning a further scan enable input of the further scan flip-flop while applying the test pattern through the first scan chain.

12. The integrated circuit of claim 11, further comprising an LBIST controller configured to provide the test pattern.

13. The integrated circuit of claim 11, further comprising an OR gate having an output coupled to the further scan enable input of the further scan flip-flop, the output of the OR gate indicating whether the integrated circuit is in a scan mode.

14. The integrated circuit of claim 11, wherein the scan circuit further comprises a multiplexer (MUX) having a first input coupled to an output of a scan flip-flop of the first scan chain, a second input coupled to an output of the further scan flip-flop, and an output coupled to the first scan chain.

15. The integrated circuit of claim 14, further comprising a second further scan flip-flop having an output coupled to a select input of the MUX.

16. The integrated circuit of claim 15, wherein the second further scan flip-flop is part of a second scan chain different from the first scan chain.

17. The integrated circuit of claim 15, further comprising a third further scan flip-flop having a clock input coupled to a scan enable input of the second further scan flip-flop and an output coupled to the select input of the MUX.

18. The integrated circuit of claim 15, further comprising a latch coupled between the second further scan flip-flop and the select input of the MUX.

19. A method of performing a scan, the method comprising: entering a scan mode; receiving a test pattern; selecting a sub-scan chain to be part of a first scan chain; applying the test pattern through the first scan chain by asserting and de-asserting a scan enable signal to perform shift and capture operations, respectively, on the first scan chain; applying the test pattern through the first scan chain, controlling an unselected sub-scan chain with the first scan chain without toggling a scan enable input of scan flip-flops of the unselected sub-scan chain, wherein a selected sub-scan chain has a length of N, the unselected sub-scan chain has a length of N, and N is a positive integer greater than or equal to one; and evaluating an output of the first scan chain to detect a fault.

20. The method of claim 19, wherein the first scan chain has a length of N.

21. A method for scan compression, comprising: entering a scan mode; receiving a test pattern; decompressing the test pattern; dynamically selecting a scan chain from a plurality of scan chains; applying the decompressed test pattern to a selected scan chain by pulsing a clock signal and toggling a scan enable signal coupled to the selected scan chain; and applying the decompressed test pattern to an unselected scan chain without toggling a scan enable signal coupled to the unselected scan chain; compressing outputs of the plurality of scan chains; and evaluating the compressed outputs to detect a fault.

22. The method of claim 21, wherein the selected scan chain has a length of N and the unselected scan chain has a length of N, and N is a positive integer greater than or equal to one. ​

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