Semiconductor structure and method of fabricating the same

Abstract

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure and a manufacturing method thereof, which comprises: a substrate comprising an array region and a peripheral circuit active region, wherein the peripheral circuit active region comprises at least a first PMOS region and a second PMOS region, the gate oxide layer thickness of the PMOS tube formed in the first PMOS region is less than that of the PMOS tube formed in the second PMOS region; a first insulating layer covering the bottom and sidewall of the first PMOS region towards the substrate, and the top of the first insulating layer is flush with the top of the substrate; a dielectric layer covering the first insulating layer, and the top of the dielectric layer in the first PMOS region is lower than the top of the substrate; a second insulating layer covering the dielectric layer, and the top of the second insulating layer in the first PMOS region is flush with the top of the substrate; and a pad layer covering the top of the substrate in the first PMOS region, so as to improve the defect problem between the isolation structure of the first PMOS region in the peripheral circuit active region and the top of the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for fabricating the same. Background Technology

[0002] Semiconductor integrated circuits typically have isolation structures to separate adjacent active areas (AA). Currently, the main methods for forming isolation structure domains are local oxidation of silicon (LOCOS) or shallow trench isolation (STI).

[0003] Memory is a common semiconductor structure, comprising an array region and an active peripheral circuit region. The array region contains the memory array, and the active peripheral circuit region contains the circuitry controlling the memory array. Isolation structures are present within the substrates of both the array region and the active peripheral circuit region. Because different transistors in the active peripheral circuit region require different functions, different structures are needed. For example, in the first PMOS region, the gate oxide layer used to form the PMOS transistor is relatively thinner than in other PMOS regions, and a pad layer needs to be formed on top of the substrate of the first PMOS region to improve the read speed of the PMOS transistors formed in the first PMOS region.

[0004] However, the filling process of the isolation structure in the first PMOS region is difficult and complex, and the trench filling of the isolation structure in the first PMOS region is prone to defects, affecting the performance of the semiconductor structure. Therefore, it is necessary to form an isolation structure with a flatter surface in the first PMOS region during the semiconductor structure fabrication process. Summary of the Invention

[0005] This disclosure provides a semiconductor structure and its fabrication method, which at least helps to solve the defect problem between the isolation structure of the first PMOS region in the active region of the peripheral circuit and the top of the substrate.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: a substrate, including an array region and a peripheral circuit active region, wherein the peripheral circuit active region includes at least a first PMOS region and a second PMOS region, the thickness of the gate oxide layer of the first PMOS region used to form a PMOS transistor is less than the thickness of the gate oxide layer of the second PMOS region used to form a PMOS transistor; a first insulating layer, covering the bottom and sidewalls of the first PMOS region facing the substrate, and the top of the first PMOS region is flush with the top of the substrate; a dielectric layer, covering the first insulating layer, and the top of the dielectric layer in the first PMOS region is lower than the top of the substrate; a second insulating layer, covering the dielectric layer, and the top of the second insulating layer in the first PMOS region is flush with the top of the substrate; and a pad layer, covering the top of the substrate in the first PMOS region.

[0007] In some embodiments, in the direction perpendicular to the top surface of the substrate, the height difference between the top of the dielectric layer and the top of the substrate is 0 nm to 20 nm.

[0008] In some embodiments, the thickness of the pad layer is 0–10 nm in the direction perpendicular to the top surface of the substrate.

[0009] In some embodiments, the material of the liner layer includes silicon germanide or silicon.

[0010] In some embodiments, the system further includes: an isolation layer, at least located on top of the substrate in the array region; the isolation layer includes: a first isolation layer, a second isolation layer, and a third isolation layer; wherein the third isolation layer is located on top of the substrate in the array region, the second isolation layer is located on top of the third isolation layer, the first isolation layer is located on top of the second isolation layer, and the thickness of the first isolation layer is 5nm to 30nm, and the first isolation layer and the third isolation layer are made of the same material.

[0011] In some embodiments, the density of the second isolation layer is greater than that of the first isolation layer, and the density of the second isolation layer is greater than that of the third isolation layer.

[0012] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, the substrate including an array region and a peripheral circuit active region, wherein the peripheral circuit active region includes at least a first PMOS region and a second PMOS region, the thickness of the gate oxide layer of the first PMOS region for forming a PMOS transistor is less than the thickness of the gate oxide layer of the second PMOS region for forming a PMOS transistor; before the array region is formed, forming an initial first insulating layer, the initial first insulating layer covering the substrate of the peripheral circuit active region and the substrate of the array region; forming an initial dielectric layer, the initial dielectric layer covering the initial first insulating layer; forming an initial second insulating layer, the initial second insulating layer covering... An initial dielectric layer is formed; an initial second insulating layer is patterned to form a second insulating layer that covers the dielectric layer, with the top of the second insulating layer in the first PMOS region flush with the top of the substrate; an initial dielectric layer is patterned to form a dielectric layer that covers the first insulating layer, with the top of the dielectric layer in the first PMOS region flush with the top of the substrate; an initial first insulating layer is patterned to form a first insulating layer that covers the bottom and sidewalls of the first PMOS region facing the substrate, with the top of the first insulating layer flush with the top of the substrate; after the array region is fabricated, a pad layer is formed, the pad layer is located on top of the substrate in the first PMOS region, and a portion of the height of the top of the dielectric layer in the first PMOS region is removed.

[0013] In some embodiments, after the array region is formed and before the pad layer is formed and a portion of the height of the top of the dielectric layer in the first PMOS region is removed, the method further includes: forming an initial first oxide layer, the initial first oxide layer being located on top of the active region of the peripheral circuit and the array region; removing the initial first oxide layer from the top of the substrate and the top of the first insulating layer, the dielectric layer and the second insulating layer in the first PMOS region, with the remaining initial first oxide layer serving as the first oxide layer.

[0014] In some embodiments, the step of forming a pad layer and removing a portion of the height of the top of the dielectric layer in the first PMOS region includes: forming a pad layer that covers the top of the substrate in the first PMOS region; forming an initial second oxide layer located on the surface of the first oxide layer and the surface of the pad layer, and also located on top of the dielectric layer in the first PMOS region; removing the initial second oxide layer on top of the dielectric layer in the first PMOS region, leaving the remaining initial second oxide layer as a second oxide layer; removing a portion of the height of the top of the dielectric layer in the first PMOS region; and removing the second oxide layer on the surface of the pad layer.

[0015] In some embodiments, the method includes: after forming the pad layer and before forming the initial second oxide layer, forming a sacrificial layer covering the surface of the pad layer; and removing the sacrificial layer on top of the substrate in the first PMOS region after removing a portion of the height of the top of the dielectric layer in the first PMOS region.

[0016] In some embodiments, the process for forming the liner layer and the sacrificial layer includes: molecular beam epitaxy, atmospheric pressure and depressurized pressure epitaxy, or ultra-high vacuum chemical vapor deposition.

[0017] In some embodiments, the step of forming a pad layer and removing a portion of the height of the top of the dielectric layer in the first PMOS region includes: forming an initial second oxide layer, the initial second oxide layer being located on the surface of the first oxide layer and also located on top of the substrate in the first PMOS region and on top of the dielectric layer in the first PMOS region; removing the initial second oxide layer on top of the dielectric layer in the first PMOS region, leaving the remaining initial second oxide layer as a second oxide layer; removing a portion of the height of the top of the dielectric layer in the first PMOS region; removing the second oxide layer on top of the substrate in the first PMOS region; and forming a pad layer that covers the top of the substrate in the first PMOS region.

[0018] In some embodiments, the thickness of the initial second oxide layer is 2 nm to 6 nm.

[0019] In some embodiments, the process for forming the initial second oxide layer includes: a rapid thermal oxidation process or a low-pressure rapid oxidation thermal annealing process.

[0020] In some embodiments, after the array region is formed and before the pad layer is formed and a portion of the height above the dielectric layer in the first PMOS region is removed, the method further includes: forming an isolation layer. The step of forming the isolation layer includes: depositing a third isolation layer on top of the array region and the active region of the peripheral circuit; depositing a second isolation layer on top of the third isolation layer; depositing a first isolation layer on top of the second isolation layer; wherein the first isolation layer and the third isolation layer are made of the same material; removing the first isolation layer, the second isolation layer and the third isolation layer from the top of the active region of the peripheral circuit, leaving the remaining first isolation layer, the second isolation layer and the third isolation layer as an isolation layer.

[0021] The technical solutions provided in this disclosure have at least the following advantages:

[0022] The substrate includes an array region and an active region for peripheral circuitry. The active region for peripheral circuitry includes at least a first PMOS region and a second PMOS region. The gate oxide layer thickness of the first PMOS region used to form the PMOS transistor is less than the gate oxide layer thickness of the second PMOS region used to form the PMOS transistor. The first PMOS region has a first insulating layer, a dielectric layer, and a second insulating layer as an isolation structure. By forming a structure in the first PMOS region where the top of the substrate has a padding layer and the top of the dielectric layer is lower than the top of the substrate, the height difference between the top of the dielectric layer and the top of the substrate in the first PMOS region is reduced. This improves the problem of defects easily forming in the dielectric layer between the isolation structure and the substrate in the first PMOS region, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0023] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the isolation structure in the first PMOS region within the active region of the peripheral circuit in a semiconductor structure.

[0025] Figure 2 A top view of a semiconductor structure provided in an embodiment of this disclosure;

[0026] Figure 3 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0027] Figure 4 for Figure 2 A schematic diagram of the cross-sectional structure along the AA1 direction;

[0028] Figures 5 to 12 This is a schematic diagram of the structure corresponding to each step of a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

[0029] Figures 13 to 16 A schematic diagram of the structure corresponding to each step of a method for fabricating another semiconductor structure according to another embodiment of this disclosure;

[0030] Figures 17 to 20 This is a schematic diagram of the steps in another method for fabricating a semiconductor structure according to another embodiment of the present disclosure. Detailed Implementation

[0031] As is known from the background art, defects can occur between the isolation structure of the first PMOS region and the substrate in semiconductor structures.

[0032] Analysis revealed that the causes of the above problems include: (Reference) Figure 1 , Figure 1This diagram illustrates the isolation structure within the first PMOS region of the active area of ​​the peripheral circuit in a semiconductor structure. Due to the different densities of the first insulating layer 102 and the dielectric layer 103 in the first PMOS region 111, the etchant will consume or damage the first insulating layer 102 and the dielectric layer 103 to varying degrees under certain etching or cleaning conditions. Taking silicon nitride as the dielectric layer 103 and silicon oxide as the first insulating layer 102 as an example, after etching the first insulating layer 102 and the dielectric layer 103 at the top of the first PMOS region 111, the top height of the dielectric layer 103 is higher than the height of the top substrate 100 of the first PMOS region 111. Therefore, the portion of the dielectric layer 103 that protrudes above the top surface substrate 100 of the first PMOS region 111 forms a protrusion 105, resulting in a decrease in the flatness between the isolation structure 101 and the substrate 100 in the first PMOS region 111, which will affect the performance of the semiconductor structure.

[0033] One embodiment of this disclosure provides a semiconductor structure to improve the problem of defects appearing between the isolation structure of the first PMOS region and the substrate.

[0034] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0035] Figure 2 This is a top view of a semiconductor structure provided in this embodiment. Figure 3 This is a schematic diagram of the semiconductor structure provided in this embodiment. Figure 4 for Figure 2 A cross-sectional view along the AA1 direction is shown below. The semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0036] refer to Figure 2 and Figure 3The semiconductor structure includes: a substrate 200, including an array region 201 and an active peripheral circuit region 202, wherein the active peripheral circuit region 202 includes at least a first PMOS region 221 and a second PMOS region 222, the thickness of the gate oxide layer of the first PMOS region 221 for forming a PMOS transistor is less than the thickness of the gate oxide layer of the second PMOS region 222 for forming a PMOS transistor; a first insulating layer 203, covering the bottom and sidewalls of the first PMOS region 221 facing the substrate 200, and the top of the insulating layer is flush with the top of the substrate; and a dielectric layer. 204, covering the first insulating layer 203, and the top of the dielectric layer 204 in the first PMOS region 221 is lower than the top of the substrate 200; the second insulating layer 205, covering the dielectric layer 204, and the top of the second insulating layer 205 in the first PMOS region 221 is flush with the top of the substrate 200; the pad layer 209, covering the top of the substrate 220 in the first PMOS region 221; wherein, the first insulating layer 203, the dielectric layer 204 and the second insulating layer 205 in the active region 202 of the peripheral circuit constitute the first isolation structure 206.

[0037] By forming a structure in the first PMOS region 221 where the top of the substrate 200 has a pad layer 209 and the top of the dielectric layer 204 is lower than the top of the substrate 200, the height difference between the top of the dielectric layer 204 and the top of the substrate 200 in the first PMOS region 221 is reduced, thereby improving the problem of easy protrusion of the dielectric layer 204 between the first isolation structure 206 and the substrate 200 in the first PMOS region 221, and thus improving the performance of the semiconductor structure.

[0038] The substrate 200 is a semiconductor material, including but not limited to any one of a silicon substrate, a germanium substrate, a germanium-silicon substrate, or a silicon carbide substrate. The substrate 200 can also be an ion-doped substrate, with the doping ions being N-type or P-type ions. Specifically, N-type ions can be phosphorus ions, arsenic ions, or antimony ions, and P-type ions can be boron ions, indium ions, or boron fluoride ions.

[0039] For array region 201, there are arrayed storage cells, which can be used to store data in semiconductor integrated circuits.

[0040] refer to Figure 4 In some embodiments, the semiconductor structure may further include a second isolation structure 207, which is located within the substrate 200 of the array region 201. The second isolation structure 207 can be used to isolate the memory cells within the array region 201, preventing the memory cells from being too close together and interfering with each other, thus avoiding interconnection between adjacent memory cells and resulting in a degradation of the semiconductor structure's performance.

[0041] In some embodiments, the material of the second isolation structure 207 and the material of the first insulating layer 203 may be the same; for example, the materials of the second isolation structure 207 and the first insulating layer 203 may be silicon oxide or carbon-doped silicon oxide. In other embodiments, the materials of the second isolation structure 207 and the first insulating layer 203 may be different.

[0042] Continue to refer to Figure 4 In some embodiments, the semiconductor structure further includes: an isolation layer 208, which is located at least on top of the substrate 200 in the array region 201 and also on top of the second isolation structure 207 in the array region 201; the isolation layer 208 includes: a first isolation layer 218, a second isolation layer 228, and a third isolation layer 238; wherein, the third isolation layer 238 is located on top of the substrate 200 in the array region 201 and also on top of the second isolation structure 207 in the array region 201, the second isolation layer 228 is located on top of the third isolation layer 238, the first isolation layer 218 is located on top of the second isolation layer 228, and the thickness of the first isolation layer 218 is 5nm to 30nm, for example, it can be 5nm, 15nm, or 30nm, and the first isolation layer 218 and the third isolation layer 238 are made of the same material. When the first PMOS region 221 needs to be processed, the isolation layer 208 can protect the substrate 200 of the array region 201 and the second isolation structure 208, so that the substrate 200 and the second isolation structure 208 of the array region 201 are not affected by the process of the first PMOS region 221.

[0043] Understandably, since the surface of the first PMOS region 221 needs to be processed, which may damage the isolation layer 208, it is necessary to ensure that the first isolation layer 218 is still retained after the processing of the first PMOS region 221. Therefore, the thickness of the first isolation layer 218 needs to be controlled within a certain range. When the thickness of the first isolation layer 218 is less than 5nm, the first isolation layer 218 may be removed during the processing of the first PMOS region 221, thereby exposing the second isolation layer 228 and reducing its shielding effect. When the thickness of the first isolation layer 218 is greater than 30nm, the height difference between the array region 201 and the first PMOS region 221 will be too large, which is not conducive to subsequent processing. Understandably, the second isolation layer 228 and the third isolation layer 238, as barrier layers and buffer layers, need to be removed after the processing of the first PMOS region 221, therefore, no limit is placed on the thickness of the second isolation layer 228 and the third isolation layer 238.

[0044] In some embodiments, the materials of the first isolation layer 218 and the third isolation layer 238 may be silicon oxide or carbon-doped silicon oxide.

[0045] In some embodiments, the material of the second isolation layer 228 may be silicon nitride or carbon-doped silicon nitride.

[0046] In some embodiments, the density of the second isolation layer 228 is greater than that of the first isolation layer 218, and the density of the second isolation layer 228 is greater than that of the third isolation layer 238. The second isolation layer 228 can prevent the substrate 200 from being over-oxidized during subsequent oxidation processes, serving as a shielding layer for oxygen diffusion during local oxidation processes, and can also be a shielding layer during chemical polishing. The density of the third isolation layer 238 is smaller than that of the second isolation layer 228, serving as a transition layer between the second isolation layer 228 and the substrate 200, preventing poor interfacial bonding between the second isolation layer 228 and the substrate 200, and the third isolation layer 238 can also serve as a protective layer for the substrate 200. The first isolation layer 218 can prevent the second isolation layer 228 from being damaged during the processing of the dielectric layer 204 of the first PMOS region 221, thereby reducing the protective effect on the array region 201. Therefore, the first isolation layer 218 can enhance the protective effect of the second isolation layer 228 on the substrate 200.

[0047] The peripheral circuit active region 202 surrounds the array region 201 and has a circuit structure for controlling the storage array. The circuit structure can transmit data to a specified storage cell for storage to realize the write operation, and can also transmit data in a specified storage cell to the circuit structure to realize the read operation.

[0048] For the first PMOS region 221, the gate oxide layer thickness of the first PMOS region 221 used to form the PMOS transistor is less than the gate oxide layer thickness of the second PMOS region 222 used to form the PMOS transistor, thereby improving the signal readout rate of the transistor formed in the first PMOS region 221 during use.

[0049] refer to Figure 3 In some embodiments, the top of the second PMOS region 222 may also have a first oxide layer 210. The first oxide layer 210 can protect the second PMOS region 222, ensuring that the second PMOS region 222 is not affected during the process operation of the first PMOS region 221, and preventing damage to the structure of the second PMOS region 222. (See reference...) Figure 4 The first oxide layer 210 can also be located on top of the isolation layer 208 in the array region 201 to further protect the first isolation layer 218 in the isolation layer 208 from the influence of the process operation of the first PMOS region 221.

[0050] For the first insulating layer 203 and the second insulating layer 205, the materials of the first insulating layer 203 and the second insulating layer 205 can be silicon oxide or carbon-doped silicon oxide. When the dielectric layer 204 is directly deposited on the surface of the substrate 200, the stress between the dielectric layer 204 and the surface of the substrate 200 is relatively large, which may lead to misalignment. The first insulating layer 203, located between the substrate 200 and the dielectric layer 204, can prevent the dielectric layer 204 from directly contacting the surface of the substrate 200. For example, when the first insulating layer 203 is silicon oxide, the density of silicon oxide is relatively low. Therefore, silicon oxide can act as a buffer layer between the dielectric layer 204 and the substrate 200, thereby preventing the dielectric layer 204 from directly contacting the substrate 200 and forming misalignment, which would affect the performance of the semiconductor structure. The second insulating layer 205 can be used to fill the semiconductor structure, thereby improving the morphology of the semiconductor structure. The second insulating layer 205 can also isolate adjacent active regions, thereby forming discrete active regions. For example, when the second insulating layer 205 is silicon oxide, silicon oxide has good insulation properties, which can isolate adjacent active regions and prevent adjacent active regions from interconnecting, thereby enabling the semiconductor structure to have better performance.

[0051] In some embodiments, the first insulating layer 203 may include a first oxide film, a second oxide film, and a third oxide film stacked sequentially. The materials of the first oxide film, the second oxide film, and the third oxide film may be silicon oxide or carbon-doped silicon oxide.

[0052] For dielectric layer 204, the material of dielectric layer 204 can be silicon nitride or carbon-doped silicon nitride. For example, when the material of dielectric layer 204 is silicon nitride, silicon nitride has a high density, which can prevent excessive consumption of substrate 200 in subsequent oxidation processes, and serve as a shielding layer for substrate 200 in subsequent oxidation processes; at the same time, silicon nitride can also be a shielding layer in the chemical polishing process. Silicon nitride has high density and high hardness, which can prevent damage to substrate 200 caused by excessive chemical polishing during chemical polishing.

[0053] In some embodiments, in the direction perpendicular to the top surface of the substrate 200 of the first PMOS region 221, the height difference between the top of the dielectric layer 204 and the top surface of the substrate 200 of the first PMOS region 221 is 0 nm to 20 nm, specifically 0 nm, 5 nm, 15 nm, or 20 nm. It is understood that if the height of the top of the dielectric layer 204 is too high, a protrusion will be generated between the first isolation structure 206 and the substrate 200 in the first PMOS region 221, thereby affecting the semiconductor structure and performance. When the height difference between the top of the dielectric layer 204 and the top surface of the substrate 200 of the first PMOS region 221 is greater than 0 nm, the flatness between the first isolation structure 206 and the substrate 200 in the first PMOS region 221 in the semiconductor structure can be improved. However, when the height difference between the top of the dielectric layer 204 and the top surface of the substrate 200 of the first PMOS region 221 is greater than 20nm, it will cause the height difference between the top of the dielectric layer 204 and the top surface of the substrate 200 of the first PMOS region 221 to be too large, which will make the recess depth of the top of the dielectric layer 204 too deep. This will reduce the flatness between the first isolation structure 206 in the first PMOS region 221 and the substrate 200, and affect the performance of the semiconductor structure.

[0054] The material of the pad layer 209 can be either silicon germanide or silicon. The pad layer 209 can significantly improve the carrier mobility of the channel, thereby improving the performance of the semiconductor device, and further shrinking the size of the transistor to achieve a larger scale of integration.

[0055] In some embodiments, the thickness of the pad layer 209 in the direction perpendicular to the top surface of the substrate 200 is 0–10 nm, specifically 1 nm, 5 nm, or 10 nm. It is understood that a thickness greater than 0 nm in the pad layer 209 can improve the performance of the semiconductor structure; however, a thickness greater than 10 nm can increase the probability of lattice misalignment, thus leading to a decrease in the performance of the semiconductor structure.

[0056] The semiconductor structure provided in this disclosure reduces the height difference between the top of the dielectric layer 204 and the top of the substrate 200 in the first PMOS region 221 by forming a structure in which the top of the substrate 200 in the first PMOS region 221 has a pad layer 209 and the top of the dielectric layer 204 is lower than the top of the substrate 200. This improves the problem of easy protrusion of the dielectric layer 204 between the first isolation structure 206 and the substrate 200 in the first PMOS region 221, thereby improving the performance of the semiconductor structure.

[0057] Another embodiment of the present invention provides a method for manufacturing a semiconductor structure, which can be used to form the above-described semiconductor structure to improve the performance of the formed semiconductor structure. It should be noted that the parts that are the same as or corresponding to those in the above embodiments can be referred to the corresponding descriptions in the foregoing embodiments, and will not be described in detail below.

[0058] Figures 5 to 12 This is a schematic diagram showing the structural steps corresponding to each step of a semiconductor structure fabrication method provided in this embodiment. Figures 13 to 16 This is a schematic diagram showing the structural steps corresponding to each step of another semiconductor structure fabrication method provided in this embodiment. Figures 17 to 20 The accompanying drawings provide a schematic diagram of each step in the fabrication method of another semiconductor structure provided in this embodiment. The following will describe in detail the semiconductor structure fabrication method provided in this embodiment with reference to the accompanying drawings:

[0059] refer to Figure 2 and Figure 5 A substrate 200 is provided, which includes an array region 201 and an active peripheral circuit region 202. The active peripheral circuit region 202 includes at least a first PMOS region 221 and a second PMOS region 222. The thickness of the gate oxide layer of the first PMOS region 221 used to form a PMOS transistor is less than the thickness of the gate oxide layer of the second PMOS region 222 used to form a PMOS transistor. The substrate 200 of the array region 201 has a groove 217, and the substrate 200 of the first PMOS region 221 and the second PMOS region 222 has a trench 216.

[0060] Specifically, the substrate 200 can be patterned to form grooves 217 and trenches 216.

[0061] refer to Figure 6 Before the array region 201 is formed, an initial first insulating layer 213 is formed, which covers the substrate 200 of the active region 202 of the peripheral circuit and the substrate 200 of the array region 201. Since the groove 217 of the array region 201 is small, the initial first insulating layer 213 directly fills the groove 217 when the initial first insulating layer 213 is formed.

[0062] In some embodiments, the initial first insulating layer 213 can be formed by a three-layer deposition process, for example, forming an initial first oxide film, an initial second oxide film, and an initial third oxide film stacked sequentially. Specifically, the initial second oxide film can be formed by a deposition process, and the initial second oxide film is located at the bottom and sidewalls of the trench 216, and also at the bottom and sidewalls of the recess 217, and also on the surface of the substrate 200 of the array region 201 and the peripheral circuit active region 202; a third oxide film is formed on the surface of the initial second oxide film facing the substrate 200 by a thermal oxidation process; and a first oxide film is formed on the surface of the second oxide film by a deposition process. The structure that uses a deposition process to form the initial second oxide film can form the initial second oxide film on the substrate surface without consuming the substrate. Then, the initial second oxide film is oxidized by a thermal oxidation process, which can further oxidize the initial second oxide film towards the substrate to form the initial third oxide film, while increasing the density of the initial second oxide film. Further oxidation towards the substrate can improve the interfacial bonding between the initial second oxide film and the initial third oxide film and the substrate. Finally, the initial first oxide film is deposited on the surface of the initial second oxide film, which can increase the thickness of the initial first insulating layer without excessive oxidation consumption of the substrate.

[0063] Specifically, the deposition process can be chemical vapor deposition, physical vapor deposition, or atomic layer deposition; the thermal oxidation process can be dry oxygen oxidation, wet oxygen oxidation, water vapor oxidation, or rapid thermal oxidation, etc.

[0064] refer to Figure 7 An initial dielectric layer 214 is formed, which covers the initial first insulating layer 213.

[0065] Specifically, the process for forming the initial dielectric layer 214 can be a deposition process, which can be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0066] In some embodiments, after the deposition process to form the initial dielectric layer 214 is completed, a cleaning process is also included. The cleaning process is used to remove residual organic or inorganic particles to avoid the residual particles affecting subsequent processes. The cleaning process can be a high-pressure cleaning process or rinsing the wafer in a cleaning solution with heat.

[0067] refer to Figure 8 An initial second insulating layer 215 is formed, which covers the initial dielectric layer 214.

[0068] Specifically, the initial second insulating layer 215 can be formed by spin-coating an insulating medium. The initial second insulating layer 215 is spin-coated onto the dielectric layer 204. The thickness of the initial second insulating layer 215 can be 3000 to 6000 angstroms, for example, 3000 angstroms, 4000 angstroms, 5000 angstroms or 6000 angstroms.

[0069] In some embodiments, an annealing process may be included after the initial second insulating layer 215 is formed, so that the spin-coated initial second insulating layer 215 solidifies and forms a denser structure.

[0070] refer to Figure 9 The first insulating layer 215 is patterned to form a second insulating layer 205, which covers the dielectric layer 204. The top of the second insulating layer 205 in the first PMOS region 221 is flush with the top of the substrate 200. The first dielectric layer 214 is patterned to form a dielectric layer 204, which covers the first insulating layer 203. The top of the dielectric layer 204 in the first PMOS region 221 is flush with the top of the substrate 200. The first insulating layer 213 is patterned to form a first insulating layer 203, which covers the bottom and sidewalls of the first PMOS region 221 facing the substrate 200. The top of the first insulating layer 203 is flush with the top of the substrate 200. The first insulating layer 203, dielectric layer 204 and second insulating layer 205 in the active region 202 of the peripheral circuit constitute a first isolation structure 206. The remaining first insulating layer 203 in the array region 201 constitutes a second isolation structure 207.

[0071] Specifically, the method for patterning the initial second insulating layer 215 can be chemical mechanical polishing. Chemical mechanical polishing can remove part of the initial second insulating layer 215 and keep the surface of the remaining initial second insulating layer 215 flat, which facilitates subsequent processes.

[0072] Specifically, an etching process can be used to pattern the initial dielectric layer 214 and the initial first insulating layer 213, wherein the etching process can be a wet etching process or a dry etching process.

[0073] refer to Figure 10 In some embodiments, a bit line structure 301 may also be formed in the substrate 200 and the second isolation structure 207 of the array region 201. The bit line structure 301 may be a single-layer structure or a stacked structure.

[0074] Specifically, the material of bit line 301 is the same as that of substrate 200. Bit line 301 can be regarded as an extension of substrate 200, which can simplify the process flow and avoid interface defects caused by contact between different media.

[0075] Specifically, the material of the bit line structure 301 includes metals, such as cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum. Metals have low resistance, which can reduce the contact resistance between the bit line 301 and the substrate 200, effectively avoid leakage current problems, and improve the conductivity between the bit line structure 301 and the substrate 200.

[0076] refer to Figure 11 In some embodiments, after the array region 201 is formed, and before the pad layer 209 is formed and a portion of the height of the top of the dielectric layer 204 in the first PMOS region 221 is removed, the method further includes: forming an isolation layer 208. The step of forming the isolation layer 208 includes: depositing a third isolation layer 238, the third isolation layer 238 being located on top of the array region 201 and the peripheral circuit active region 202, i.e., covering the top of the substrate 200 of the array region 201 and the second isolation structure 207, and also covering the substrate 200 of the peripheral circuit active region 202 and the first isolation layer 207. A second isolation layer 228 is deposited on top of an isolation structure 206, with the second isolation layer 228 located on top of a third isolation layer 238. A first isolation layer 218 is deposited on top of the second isolation layer 228; wherein the first isolation layer 218 and the third isolation layer 238 are made of the same material. The first isolation layer 218, the second isolation layer 228, and the third isolation layer 238 on top of the active region 202 of the peripheral circuit are removed, and the remaining first isolation layer 218, the second isolation layer 228, and the third isolation layer 238 serve as isolation layer 208. Isolation layer 208 is located on the surface of array region 201, which can protect the structure within array region 201 from the process influence of the active region 202 of the peripheral circuit and prevent the structure within array region 201 from being damaged by subsequent etching processes.

[0077] Specifically, the process for forming the isolation layer 208 can be a deposition process, which can be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0078] Specifically, the process for removing the isolation layer 208 can be an etching process, which can be a dry etching process or a wet etching process.

[0079] In some embodiments, the isolation layer 208 may also be a single-layer structure, and the material of the single-layer isolation layer 208 may be silicon nitride, silicon oxide, or silicon oxynitride.

[0080] refer to Figure 12In some embodiments, after the array region 201 is formed, and before the pad layer 209 is formed and a portion of the height of the top of the dielectric layer 204 in the first PMOS region 221 is removed, the process further includes: forming an initial first oxide layer, the initial first oxide layer being located on top of the peripheral circuit active region 202 and the array region 201, that is, on top of the substrate 200 and the first isolation structure 206 within the peripheral circuit active region 202, and also on top of the isolation layer 208 of the array region 201; removing the initial first oxide layer on top of the substrate 200 and the first insulating layer 203, the dielectric layer 204, and the second insulating layer 205 in the first PMOS region 221, with the remaining initial first oxide layer serving as the first oxide layer 210. It is understood that when the first PMOS region 221 needs to be processed, the first oxide layer 210 can protect other areas within the peripheral circuit active region 202 outside the first PMOS region 221 from the process effects of the first PMOS region 221.

[0081] Specifically, the process for forming the initial first oxide layer can be a deposition process, which can be a chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The process for removing the initial first oxide layer can be an etching process, which can be a dry etching process or a wet etching process.

[0082] This embodiment provides two methods for forming the pad layer 209 and removing the top portion of the dielectric layer 204 in the first PMOS region 221. The two methods will be described in detail below with reference to the accompanying drawings.

[0083] The method for forming the pad layer 209 and removing the top portion of the dielectric layer 204 in the first PMOS region 221 is referenced. Figures 13 to 16 .

[0084] refer to Figure 13 A pad layer 209 is formed, which covers the top of the substrate 200 in the first PMOS region 221.

[0085] In some embodiments, after forming the liner layer 209, the process further includes forming a sacrificial layer that covers the surface of the liner layer 209. The sacrificial layer can replace the oxidation of the liner layer 209 in subsequent processes, preventing the liner layer 209 from being excessively oxidized and consumed.

[0086] Specifically, the processes for forming the liner layer 209 and the sacrificial layer include: molecular beam epitaxy, atmospheric pressure and depressurized pressure epitaxy, or ultra-high vacuum chemical vapor deposition.

[0087] refer to Figure 14An initial second oxide layer is formed, located on the surface of the first oxide layer 210 and the surface of the pad layer 209, and also on top of the dielectric layer 204 in the first PMOS region 221. Additionally, the initial second oxide layer can also be located on the surface of the first oxide layer 210 in the second PMOS region 222 and the surface of the first oxide layer 210 in the array region 201. The initial second oxide layer on top of the dielectric layer 204 in the first PMOS region 221 is removed, leaving the remaining initial second oxide layer as the second oxide layer 220. Because the dielectric layer 204 has a high density and is difficult to oxidize, only a thin initial second oxide layer grows on top of the dielectric layer 204. The surface of the pad layer 209 is easily oxidized, so the initial second oxide layer formed on the surface of the pad layer 209 is thicker than the initial second oxide layer on top of the dielectric layer 204. Therefore, when removing the initial second oxide layer, the initial second oxide layer on top of the dielectric layer 204 is removed, while the initial second oxide layer in other areas is retained as the second oxide layer 220.

[0088] In some embodiments, a cleaning process is included before forming the initial second oxide layer. The cleaning process is used to remove particles and chemical reagent residues on the wafer surface to avoid the particles and organic chemical reagent residues in the removal process from affecting the oxidation process, increasing the oxidation nucleation sites, and resulting in poor uniformity of the initial second oxide layer.

[0089] Specifically, the process for forming the initial second oxide layer includes: rapid thermal oxidation process or low-pressure rapid oxidation thermal annealing process.

[0090] In some embodiments, the thickness of the initial second oxide layer is 2 nm to 6 nm, for example, 2 nm, 4 nm, or 6 nm. The initial second oxide layer can protect the pad layer 209. If the thickness of the initial second oxide layer is less than 2 nm, the protection of the pad layer 209 may be insufficient, still causing contamination or damage to the surface of the pad layer 209, which may have an adverse effect on the semiconductor structure. However, if the thickness of the initial second oxide layer is greater than 6 nm, it may cause excessive oxidation consumption of the pad layer 209, thereby affecting the linewidth of the pad layer 209, which may have an adverse effect on the semiconductor structure and performance.

[0091] refer to Figure 15 Remove a portion of the height at the top of the dielectric layer 204 in the first PMOS region 221.

[0092] Specifically, the process for removing the top of the dielectric layer 204 can be an etching process, which can be a wet etching process or a dry etching process.

[0093] Because organic solvents have different etching selectivity for different materials, for example, when the etchant is phosphoric acid, the dielectric layer 204 is silicon nitride, and the second oxide layer 220 is silicon oxide, the etching rate of phosphoric acid for silicon nitride is high, while the etching rate for silicon oxide is low. Consequently, the etching depth to remove the top of silicon nitride is deeper, while the etching depth to remove silicon oxide is smaller, so some silicon oxide is still retained.

[0094] refer to Figure 16 The second oxide layer 220 on the surface of the pad layer 209 is removed, and the second oxide layer 220 on the surface of the first oxide layer 210 of the second PMOS region 222 and the surface of the first oxide layer 210 of the array region 201 is also removed.

[0095] In some embodiments, if a sacrificial layer is formed on the surface of the pad layer 209 after the pad layer 209 is formed and before the initial second oxide layer is formed, then after removing a portion of the height of the top of the dielectric layer 204 in the first PMOS region 221, the sacrificial layer on top of the pad layer 209 in the first PMOS region 221 also needs to be removed.

[0096] Specifically, the removal process can be an etching process, which can be either a wet etching process or a dry etching process.

[0097] The second method for forming the pad layer 209 and removing the top portion of the dielectric layer 204 in the first PMOS region 221 is referred to [reference]. Figures 17 to 20 .

[0098] refer to Figure 17 An initial second oxide layer is formed, located on the surface of the first oxide layer 210, and also on top of the substrate 200 in the first PMOS region 221 and on top of the dielectric layer 204 in the first PMOS region 221. The initial second oxide layer on top of the dielectric layer 204 in the first PMOS region 221 is removed, leaving the remaining initial second oxide layer as the second oxide layer 220. The second oxide layer 220 can protect the substrate 200 in the first PMOS region 221 from being affected during process operations on the first PMOS region 221.

[0099] In some embodiments, a cleaning process is included before forming the initial second oxide layer. The cleaning process is used to remove particles and chemical reagent residues on the wafer surface to avoid the particles and organic chemical reagent residues in the removal process from affecting the oxidation process, increasing the oxidation nucleation sites, and resulting in poor uniformity of the initial second oxide layer.

[0100] Specifically, the process for forming the initial second oxide layer includes: rapid thermal oxidation process or low-pressure rapid oxidation thermal annealing process.

[0101] In some embodiments, the thickness of the initial second oxide layer is 2 nm to 6 nm, for example, 2 nm, 4 nm, or 6 nm. The initial second oxide layer can protect the pad layer 209. If the thickness of the initial second oxide layer is less than 2 nm, the protection of the pad layer 209 may be insufficient, still causing contamination or damage to the surface of the pad layer 209, which may have an adverse effect on the semiconductor structure. However, if the thickness of the initial second oxide layer is greater than 6 nm, it may cause excessive oxidation consumption of the pad layer 209, thereby affecting the linewidth of the pad layer 209, which may have an adverse effect on the semiconductor structure and performance.

[0102] Specifically, the removal process can be an etching process, which can be either wet etching or dry etching. Because the dielectric layer 204 has a high density and is difficult to oxidize, only a thin initial second oxide layer grows on top of the dielectric layer 204. The surface of the liner layer 209 is easily oxidized, so the initial second oxide layer formed on the surface of the liner layer 209 is thicker than the initial second oxide layer on top of the dielectric layer 204. Therefore, when removing the initial second oxide layer, the initial second oxide layer on top of the dielectric layer 204 is removed, while the initial second oxide layer in other areas is retained as the second oxide layer 220.

[0103] refer to Figure 18 Remove a portion of the height at the top of the dielectric layer 204 in the first PMOS region 221.

[0104] Specifically, the process for removing the top of the dielectric layer 204 can be an etching process, which can be a wet etching process or a dry etching process.

[0105] Because organic solvents have different etching selectivity for different materials, for example, when the etchant is phosphoric acid, the dielectric layer 204 is silicon nitride, and the second oxide layer 220 is silicon oxide, the etching rate of phosphoric acid for silicon nitride is high, while the etching rate for silicon oxide is low. Consequently, the etching depth to remove the top of silicon nitride is deeper, while the etching depth to remove silicon oxide is smaller, so some silicon oxide is still retained.

[0106] refer to Figure 19 The second oxide layer 220 on top of the substrate 200 in the first PMOS region 221 is removed, and the second oxide layer 220 on the surface of the first oxide layer 210 is also removed.

[0107] Specifically, the removal process can be an etching process, which can be either a wet etching process or a dry etching process.

[0108] refer to Figure 20 A pad layer 209 is formed, which covers the top of the substrate in the first PMOS region 221.

[0109] Specifically, the process for forming the pad layer 209 includes: molecular beam epitaxy, atmospheric pressure and depressurized pressure epitaxy, or ultra-high vacuum chemical vapor deposition. The pad layer 209 can significantly improve the carrier mobility of the channel, thereby improving the performance of semiconductor devices, and further enabling the continuous miniaturization of transistors to achieve greater integration.

[0110] The semiconductor structure fabrication method provided in this disclosure reduces the height difference between the top of the dielectric layer 204 and the top of the substrate 200 in the first PMOS region 221 by forming a structure in which the top of the substrate 200 in the first PMOS region 221 has a pad layer 209 and the top of the dielectric layer 204 is lower than the top of the substrate 200. This improves the problem of easy protrusion of the dielectric layer 204 between the first isolation structure 206 and the substrate 200 in the first PMOS region 221, thereby improving the performance of the semiconductor structure.

[0111] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including an array region and an active region of peripheral circuits, wherein the active region of peripheral circuits includes at least a first PMOS region and a second PMOS region, and the thickness of the gate oxide layer of the first PMOS region used to form a PMOS transistor is less than the thickness of the gate oxide layer of the second PMOS region used to form a PMOS transistor. Before the array region is formed, an initial first insulating layer is formed, the initial first insulating layer covering the substrate of the active region of the peripheral circuit and the substrate of the array region; an initial dielectric layer is formed, the initial dielectric layer covering the initial first insulating layer; an initial second insulating layer is formed, the initial second insulating layer covering the initial dielectric layer; the initial second insulating layer is patterned to form a second insulating layer, the top of the second insulating layer in the first PMOS region being flush with the top of the substrate; the initial dielectric layer is patterned to form a dielectric layer, the top of the dielectric layer in the first PMOS region being flush with the top of the substrate; the initial first insulating layer is patterned to form a first insulating layer, the first insulating layer covering the bottom and sidewalls of the first PMOS region facing the substrate, and the top being flush with the top of the substrate, the dielectric layer covering the first insulating layer, and the second insulating layer covering the dielectric layer; After the array region is formed, an initial first oxide layer is formed, which is located on top of the active region of the peripheral circuit and the array region; the initial first oxide layer on top of the substrate, the first insulating layer, the dielectric layer, and the second insulating layer in the first PMOS region is removed, leaving the initial first oxide layer as the first oxide layer; a pad layer is formed, which is located on top of the substrate in the first PMOS region; an initial second oxide layer is formed, which is located on the surface of the first oxide layer and the surface of the pad layer, and is also located on top of the dielectric layer in the first PMOS region; the initial second oxide layer on top of the dielectric layer in the first PMOS region is removed, leaving the initial second oxide layer as the second oxide layer; a portion of the height of the top of the dielectric layer in the first PMOS region is removed; and the second oxide layer on the surface of the pad layer is removed.

2. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, include: After forming the liner layer and before forming the initial second oxide layer, the method further includes: forming a sacrificial layer that covers the surface of the liner layer; After removing a portion of the height of the top of the dielectric layer in the first PMOS region, the sacrificial layer on top of the substrate in the first PMOS region is removed.

3. The method for manufacturing a semiconductor structure as described in claim 2, characterized in that, The process for forming the padding layer and the sacrificial layer includes: molecular beam epitaxy, atmospheric pressure and depressurized pressure epitaxy, or ultra-high vacuum chemical vapor deposition.

4. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, The thickness of the initial second oxide layer is 2 nm to 6 nm.

5. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, The process for forming the initial second oxide layer includes: a rapid thermal oxidation process or a low-pressure rapid oxidation thermal annealing process.

6. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, After the array region is formed, and before the pad layer is formed and a portion of the height at the top of the dielectric layer in the first PMOS region is removed, the method further includes: forming an isolation layer, the step of forming the isolation layer comprising: A third isolation layer is deposited, the third isolation layer being located on top of the array region and the active region of the peripheral circuit; A second isolation layer is deposited on top of the third isolation layer; A first isolation layer is deposited, which is located on top of the second isolation layer; The first isolation layer and the third isolation layer are made of the same material; Remove the first isolation layer, the second isolation layer, and the third isolation layer from the top of the active region of the peripheral circuit, and the remaining first isolation layer, the second isolation layer, and the third isolation layer serve as the isolation layer.

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