Semiconductor structure and method of fabricating the same

Abstract

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure and a manufacturing method thereof, the method comprising: providing a semiconductor substrate, the semiconductor substrate being provided with a plurality of first bit lines extending along a first direction; forming a first transistor array on the semiconductor substrate, the first transistor array comprising a plurality of first semiconductor columns; forming first word lines, each first semiconductor column being connected with a corresponding first word line and a first bit line; forming a second transistor array on the first transistor array, the second transistor array comprising a plurality of second semiconductor columns, the first semiconductor columns and the second semiconductor columns corresponding to each other; and forming second word lines and second bit lines, each second semiconductor column being connected with a corresponding second word line and a second bit line, so as to form a 2T0C semiconductor structure, and the capacitor process in the manufacturing process of the semiconductor structure can be simplified.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for fabricating the same. Background Technology

[0002] With the continuous growth of demand in the semiconductor market, semiconductor memory technology has developed rapidly, especially Dynamic Random Access Memory (DRAM), which occupies the most important position in the memory market. A common DRAM cell consists of a transistor and a capacitor, forming a 1T1C structure. In order to improve cell performance and reduce cell area, it is necessary to fabricate capacitors with large capacitance values ​​per unit area.

[0003] With increasingly stringent requirements for DRAM cell performance and size, 1T1C cells have faced significant challenges. Research indicates that transistors, under certain dimensions and with appropriate doping, can also store small amounts of charge without requiring any capacitors, as the transistor gate is a natural capacitor. By forming a 2T0C embedded DRAM structure, a two-transistor, capacitor-free structure can be fabricated, simplifying the capacitor fabrication process in semiconductor manufacturing. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and its fabrication method, forming a 2TOC semiconductor structure, which can simplify the capacitor process in the semiconductor structure fabrication process.

[0005] One embodiment of this disclosure provides a method for fabricating a semiconductor structure, comprising: providing a semiconductor substrate having a plurality of first bit lines extending along a first direction; forming a first transistor array on the semiconductor substrate, the first transistor array including a plurality of first semiconductor pillars; forming a first word line, each first semiconductor pillar connecting a corresponding first word line and a first bit line; forming a second transistor array on the first transistor array, the second transistor array including a plurality of second semiconductor pillars, the first semiconductor pillars corresponding one-to-one with the second semiconductor pillars; and forming a second word line and a second bit line, each second semiconductor pillar connecting a corresponding second word line and a second bit line.

[0006] In some embodiments, the formed first semiconductor pillar extends along a third direction and is arranged in an array in a first direction and a second direction; the formed first word line extends along a second direction and surrounds the first semiconductor pillar.

[0007] In some embodiments, the step of forming a first transistor array includes: forming a first sacrificial layer covering the surface of a semiconductor substrate; forming a plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction, the first trenches and second trenches being located within the first sacrificial layer, the bottom of which is flush with the top surface of a first first line, and in the second direction, the projection of the first trenches and the projection of the first first line are parallel to each other and alternately arranged; forming first isolation structures to fill the first trenches and second trenches; removing the first sacrificial layer between the first isolation structures and forming first semiconductor pillars to fill the gaps between the first isolation structures.

[0008] In some embodiments, the step of forming a first transistor array includes: forming an initial first isolation structure that covers the surface of a semiconductor substrate; forming a plurality of first semiconductor holes extending along a third direction, the first semiconductor holes being located within the initial first isolation structure and arranged in an array in a first direction and a second direction, the first semiconductor holes exposing the surface of a first line, the remaining initial first isolation structure serving as a first isolation structure; and forming first semiconductor pillars to fill the first semiconductor holes.

[0009] In some embodiments, the step of forming the first word line includes: removing a portion of the height of the first isolation structure; forming the first word line covering the surface of the first isolation structure; forming a second isolation structure covering the surface of the first word line; forming a first isolation layer, the first isolation layer extending along a second direction and located between two adjacent columns of first semiconductor pillars, wherein the first isolation layer and the first semiconductor pillars are alternately spaced in the first direction.

[0010] In some embodiments, the steps of forming a first transistor array and forming a first word line include: forming an initial first isolation structure covering the surface of a semiconductor substrate; forming a plurality of first isolation trenches extending along a second direction and a plurality of first semiconductor holes extending along a third direction, the first isolation trenches and first semiconductor holes being located within the initial first isolation structure, the first semiconductor holes being arrayed in a first direction and a second direction and exposing the surface of the first word line, wherein in the first direction, the first isolation trenches and first semiconductor holes are alternately spaced; forming a first isolation layer to fill the first isolation trenches and forming a first semiconductor pillar to fill the first semiconductor holes; removing a portion of the height of the initial first isolation structure, leaving the remaining initial first isolation structure as the first isolation structure; forming a first word line covering the surface of the first isolation structure; and forming a second isolation structure covering the first word line.

[0011] In some embodiments, after forming the first word line and before forming the second transistor layer, the method further includes: forming a contact structure located on the top surface of the first semiconductor pillar; and forming a dielectric layer that at least covers the surface of the contact structure.

[0012] In some embodiments, the formed second semiconductor pillars extend along a third direction and are arranged in an array in a first direction and a second direction; forming the second transistor array further includes forming a third isolation structure, the third isolation structure filling the gaps between the second semiconductor pillars.

[0013] In some embodiments, the step of forming a second transistor array includes: forming an initial third isolation structure located above the first transistor array; forming a plurality of second semiconductor holes extending along a third direction, the second semiconductor holes being located within the initial third isolation structure and corresponding one-to-one with the first semiconductor pillars, the remaining initial third isolation structure serving as a third isolation structure; and forming second semiconductor pillars to fill the second semiconductor holes.

[0014] In some embodiments, the step of forming a second transistor array includes: forming a second semiconductor layer located above the first transistor array; forming a plurality of first grooves extending along a first direction and a plurality of second grooves extending along a second direction, the first grooves and the second grooves located within the second semiconductor layer, the remaining second semiconductor layer serving as second semiconductor pillars corresponding one-to-one with the first semiconductor pillars; and forming a third isolation structure to fill the first grooves and the second grooves.

[0015] In some embodiments, the step of forming a second transistor array includes: forming a second sacrificial layer located above the first transistor array; forming a plurality of third grooves extending along a first direction and a plurality of fourth grooves extending along a second direction, the third grooves and fourth grooves located within the second sacrificial layer, the remaining second sacrificial layer corresponding one-to-one with the first semiconductor pillars; forming a third isolation structure to fill the third grooves and fourth grooves; removing the second sacrificial layer within the third isolation structure, and forming second semiconductor pillars to fill the gaps between the third isolation structures.

[0016] In some embodiments, the step of forming a second word line and a second bit line includes: forming a first insulating layer that covers the surface of a second transistor array; forming a plurality of second word lines and second bit lines extending along a second direction, wherein the second word lines and second bit lines are located within the first insulating layer, are parallel to each other and alternately spaced in a first direction, and in a second direction, the same second word line or second bit line connects a portion of the surface of two adjacent columns of second semiconductor pillars.

[0017] In some embodiments, the step of forming a second word line and a second bit line includes: forming a second insulating layer covering the surface of a second transistor array; forming a plurality of second word lines extending along a second direction, the second word lines being located within the second insulating layer, wherein in the second direction, the same second word line connects to a portion of the surface of two adjacent columns of second semiconductor pillars, and in a first direction, the surface of every two columns of second semiconductor pillars is connected to the same second word line; forming a third insulating layer covering the surfaces of the second word lines and the second insulating layer; forming a plurality of second bit lines, each second bit line including a plurality of second bit line contact lines extending along a third direction and a plurality of second bit line extension lines extending along a first direction, the second bit line contact lines being located within the second insulating layer and the third insulating layer, and the second bit line extension lines being located within the third insulating layer; the second bit line contact lines are arranged in an array in the first direction and the second direction, the second bit line contact lines and the second word lines are alternately spaced in the first direction, each second bit line contact line connects to a portion of the surface of two adjacent second semiconductor pillars, and the bottom of the second bit line extension line is connected to the top of the second bit line contact line.

[0018] In some embodiments, the materials forming the first semiconductor pillar and the second semiconductor pillar include at least one or more of IGZO, IZO, or ITO.

[0019] Another embodiment of this disclosure also provides a semiconductor structure, employing a method for fabricating the semiconductor structure provided in the above embodiments, comprising: a semiconductor substrate having a plurality of first bit lines extending along a first direction; a first transistor array located on the semiconductor substrate, the first transistor array including a plurality of first semiconductor pillars; a first word line, each first semiconductor pillar connecting a corresponding first word line and a first bit line; a second transistor array located on the first transistor array, the second transistor array including a plurality of second semiconductor pillars, the first semiconductor pillars corresponding one-to-one with the second semiconductor pillars; a second word line and a second bit line, each second semiconductor pillar connecting a corresponding second word line and a second bit line.

[0020] In some embodiments, the semiconductor structure further includes: a first semiconductor pillar extending along a third direction and arranged in an array in a first direction and a second direction; a first isolation layer extending along the second direction and located between two adjacent columns of the first semiconductor pillars, wherein the first isolation layer and the first semiconductor pillars are alternately spaced in the first direction; a first isolation structure filling the gap between the first isolation layer and the first semiconductor pillars, and a first word line located on the surface of the first isolation structure; and a second isolation structure located on the surface of the first word line.

[0021] In some embodiments, the semiconductor structure further includes: a contact structure located on the surface of the first semiconductor pillar; and a dielectric layer covering at least the surface of the contact structure.

[0022] In some embodiments, the second transistor array includes: second semiconductor pillars extending along a third direction and arranged in an array in a first direction and a second direction; and a third isolation structure filling the gaps between the second semiconductor pillars.

[0023] In some embodiments, the second word line and the second bit line include: a first insulating layer covering the surface of the second transistor array, the second word line and the second bit line extending along a second direction and disposed parallel to each other within the first insulating layer, wherein in the second direction, the same second word line or the second bit line connects a portion of the surface of two adjacent columns of second semiconductor pillars.

[0024] In some embodiments, the second word line and the second bit line include: a second insulating layer covering the surface of the second transistor array; the second word lines extending along a second direction and disposed parallel to each other within the second insulating layer; in the second direction, the same second word line connects to a portion of the surface of two adjacent columns of second semiconductor pillars; and in the first direction, a portion of the surface of every two columns of second semiconductor pillars connects to the same second word line; a third insulating layer covering the surface of the second word line and the second insulating layer; the second bit line includes a second bit line contact line and a second bit line extension line; the second bit line contact line is disposed along a third direction within the second insulating layer and the third insulating layer, arranged in an array in the first and second directions; in the first direction, the second bit line contact line and the second word line are alternately spaced; and each second bit line contact line connects to a portion of the surface of two adjacent second semiconductor pillars; and the second bit line extension line is disposed along the second direction within the third insulating layer, with its bottom connected to the top of the second bit line contact line.

[0025] The technical solution provided by the embodiments of this disclosure has at least the following advantages: forming a first transistor array with multiple first semiconductor pillars and a second transistor array with multiple second semiconductor pillars, wherein the first transistor is connected to the corresponding first word line and the first bit line, and the second transistor is connected to the corresponding second word line and the second bit line, and the first transistor and the second transistor correspond one-to-one to form a structure with two transistors and no capacitor, which solves the problem that a large number of capacitors need to be prepared in a unit area in the semiconductor structure manufacturing process. The structure with two transistors and no capacitor can increase the space utilization of the semiconductor structure and improve the integration density of the semiconductor structure.

[0026] In addition, the first semiconductor pillar extends along a third direction and is arranged in an array in the first and second directions; the first word line extends along the second direction and surrounds the first semiconductor pillar, which can form a first transistor array with a fully surrounding gate structure to improve the control capability of the first transistor on current, thereby improving the performance of the semiconductor structure, and the fully surrounding gate structure can improve the integration density of the semiconductor structure.

[0027] Furthermore, the materials forming the first and second semiconductor pillars include at least one or more of IGZO, IZO, or ITO, which is beneficial to improving the carrier mobility of the semiconductor channels in the first and second transistor arrays. This allows the semiconductor channels to transmit electrical signals more efficiently, reduces leakage current during semiconductor structure operation, thereby reducing power consumption and improving the operating efficiency of the semiconductor structure. Attached Figure Description

[0028] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figures 1 to 13 This is a schematic diagram of the structure corresponding to each step of the method for fabricating a semiconductor structure according to an embodiment of the present disclosure. Detailed Implementation

[0030] As is known from the background technology, by forming a 2T0C embedded DRAM structure, a structure with two transistors and no capacitors can be fabricated, which can simplify the capacitor process in the semiconductor structure fabrication process.

[0031] Analysis revealed that, given a certain size and appropriate doping, even small transistors can hold a small amount of charge without requiring any capacitor, because the transistor's gate is a natural capacitor capable of storing a small amount of charge. Therefore, compared to the conventional 1T1C DRAM structure, which requires fabricating a one-to-one correspondence between a transistor and a capacitor, the 2T0C embedded DRAM structure can form a structure with two transistors and no capacitor, eliminating the capacitor fabrication process in semiconductor fabrication and thus improving the efficiency of semiconductor fabrication. Furthermore, by not occupying excessive space for capacitors, it is possible to further increase the transistor integration density.

[0032] One embodiment of this disclosure provides a method for fabricating a semiconductor structure to form a 2TOC semiconductor structure, simplifying the capacitor process in the semiconductor structure fabrication process.

[0033] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0034] Figures 1 to 13 This is a schematic diagram of the structure corresponding to each step of the semiconductor structure fabrication method provided in this embodiment, wherein, Figures 3 to 8 as well as Figures 11 to 13 for Figure 1 Schematic diagram of cross-sectional structure along the AA1 and BB1 directions. Figure 10 for Figure 9 A cross-sectional view along the CC1 and DD1 directions is shown below. The fabrication method of the semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0035] Methods for fabricating semiconductor structures include:

[0036] refer to Figure 1 A semiconductor substrate 100 is provided, the semiconductor substrate 100 being provided with a plurality of first bit lines 201 extending along a first direction X.

[0037] Specifically, the step of providing the semiconductor substrate 100 may include: providing a substrate 101 and forming a first insulating structure 102 to cover the surface of the substrate 101; forming a plurality of first line slots extending along a first direction X in the first insulating layer 101, and arranging the first line slots parallel to each other and spaced apart in a second direction Y, and filling the first line slots to form a first line 201.

[0038] It should be noted that in this embodiment, the angle between the first direction X and the second direction Y is 90°. This embodiment does not constitute a limitation on the specific angle between the first direction X and the second direction Y. In specific applications, the angle between the first direction X and the second direction Y can be set to 30°, 45° or 60° according to the specific application scenario.

[0039] The substrate 101 can be made of an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanide, gallium arsenide, or indium gallium, etc.

[0040] The first insulating structure 102 is formed by insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, which are used to isolate adjacent first lines 201, prevent the first lines 201 from being interconnected, and avoid affecting the performance of the semiconductor structure.

[0041] For the first line 201, the material forming the first line 201 includes at least one selected from metal silicide, copper, or tungsten. In some embodiments, the material forming the first line 201 can be a single metal, a metal compound, or an alloy. The single metal can be copper, aluminum, tungsten, gold, or silver, etc.; the metal compound can be tantalum nitride or titanium nitride; the alloy can be an alloy material composed of at least two of copper, aluminum, tungsten, gold, or silver. Setting the material of the first line 201 to a metallic material can give the first line a lower resistivity, which is beneficial for reducing the resistance of the first line 201, increasing the transmission rate of electrical signals in the first line 201, reducing the parasitic capacitance of the first line 201, and reducing heat loss to reduce power consumption.

[0042] refer to Figure 1 and Figure 2 A first transistor array 200 is formed on a semiconductor substrate 100, the first transistor array 200 including a plurality of first semiconductor pillars 203.

[0043] For details, please refer to the following: Figure 2 A first semiconductor pillar 203 extends along a third direction Z and is arranged in an array along a first direction X and a second direction Y. In the first direction X, the bottoms of different first semiconductor pillars 203 contact the same first bit line 201, and in the second direction Y, the bottoms of different first semiconductor pillars 203 contact different first bit lines 201. A first word line 202 is formed. Each first semiconductor pillar 203 connects to its corresponding first word line 202 and first bit line 201. The first word line 202 extends along the second direction Y and surrounds the first semiconductor pillar 203. By forming a first transistor array with a fully surrounding gate structure, the current control capability of the first transistor is improved, thereby improving the performance of the semiconductor structure. Furthermore, the fully surrounding gate structure can increase the integration density of the semiconductor structure.

[0044] It should be noted that in this embodiment, the angle between the third direction Z and the plane containing the first direction X and the second direction Y is 90°. This embodiment does not constitute a limitation on the angle between the third direction Z and the plane containing the first direction X and the second direction Y. Depending on the specific application scenario, the angle between the third direction Z and the plane containing the first direction X and the second direction Y can be 30°, 45° or 60°.

[0045] This embodiment provides two methods for forming the first transistor array 200. Specifically, in one example, the steps for forming the first transistor array 200 include: referring to... Figure 3 A first sacrificial layer 231 is formed, which covers the surface of the semiconductor substrate 100; Reference Figure 4Multiple first trenches 233 extending along the first direction X and multiple second trenches 232 extending along the second direction Y are formed. The first trenches 233 and the second trenches 232 are located within the first sacrificial layer 231, with their bottoms flush with the top surface of the first line 201. In the second direction Y, the projections of the first trenches 233 and the projections of the first line 201 are parallel to each other and alternately arranged. (Reference) Figure 5 A first isolation structure 211 is formed to fill the first trench 233 and the second trench 232; Reference Figure 6 The first sacrificial layer 231 between the first isolation structures 211 is removed, and the first semiconductor pillar 203 is formed to fill the gap between the first isolation structures 211.

[0046] The materials used to form the first sacrificial layer 231 and the first isolation structure 211 include silicon oxide, silicon nitride, silicon oxynitride, etc. The different materials used to form the first sacrificial layer 231 and the first isolation structure 211 can result in different degrees of etching under the same etching conditions, thereby removing the first sacrificial layer 231 while retaining the first isolation structure 211, so as to facilitate the subsequent filling of the gaps between the first isolation structures 211 to form the first semiconductor pillar 203.

[0047] In some embodiments, after forming the first trench 233 and the second trench 232, and before filling the first isolation structure 211, a rounding process may be included to form the remaining first sacrificial layer 231 into a cylindrical structure, so that the surface of the subsequent removal of the first sacrificial layer 231 and the formation of the first semiconductor pillar 203 is smoothly transitioned, thereby helping to avoid the phenomenon of tip discharge or leakage of the first semiconductor pillar 203 when it is working in the semiconductor structure.

[0048] In another example, the steps of forming the first transistor array include: forming an initial first isolation structure covering the surface of a semiconductor substrate; forming a plurality of first semiconductor holes extending along a third direction, the first semiconductor holes being located within the initial first isolation structure and arranged in an array in a first direction and a second direction, different first semiconductor holes exposing a portion of the top surface of the same first first line in the first direction, and different first semiconductor holes exposing a portion of the top surface of different first first lines in the second direction, the remaining initial first isolation structure serving as the first isolation structure; and forming first semiconductor pillars to fill the first semiconductor holes.

[0049] For the initial first isolation structure, the materials forming the initial first isolation structure include silicon oxide, silicon nitride, silicon oxynitride, etc.

[0050] In some embodiments, the shape of the first semiconductor hole can be circular, elliptical, or polygonal to facilitate a smooth transition of the surface of the subsequent filling to form the first semiconductor pillar, thereby preventing tip discharge or leakage during operation. It is understood that the edges of the polygon can be chamfered to ensure a gentle transition of the angles of the first semiconductor pillar, also preventing the formation of sharp points that could lead to leakage or discharge.

[0051] For the first semiconductor pillar 203, the material forming the first semiconductor pillar 203 includes at least one of IGZO (Indium Gallium Zinc Oxide), IZO (Indium Zinc Oxide), or ITO (Indium Tin Oxide). When the first semiconductor pillar 203 is composed of the above materials, it is beneficial to improve the carrier mobility of the first semiconductor pillar 203, thereby facilitating more efficient transmission of electrical signals. For example, when the material of the first semiconductor pillar 203 is IGZO, the carrier mobility of IGZO is 20 to 50 times that of polycrystalline silicon, which is beneficial to improving the carrier mobility in the first semiconductor pillar 203, thereby reducing the leakage current during semiconductor structure operation, thus reducing the power consumption and improving the operating efficiency of the semiconductor structure. Furthermore, the retention time of a memory cell configured with a gate-all-around transistor formed by the first semiconductor pillar 203 formed of IGZO can exceed 400 seconds, which is beneficial to reducing the refresh rate and power consumption of the memory.

[0052] Based on the two methods for forming the first transistor array 200 described above, a first word line 202 is formed, and each first semiconductor pillar 203 is connected to the corresponding first word line 202 and the first bit line 201; wherein, the step of forming the first word line 202 includes: referring to Figure 7 A portion of the height of the first isolation structure 211 is removed; a first word line 202 is formed to cover the surface of the first isolation structure 211, and the top surface of the first word line 202 is lower than the top surface of the first semiconductor pillar 203; a second isolation structure 212 is formed to cover the surface of the first word line 202, and the top surface of the second isolation structure 212 is flush with the top surface of the first semiconductor pillar 203; Reference Figure 8A first isolation layer 213 is formed, extending along the second direction Y and located between two adjacent columns of first semiconductor pillars 203. The height of the first isolation layer 213 is equal to the height of the first semiconductor pillars 203. In the first direction X, the first isolation layer 213 and the first semiconductor pillars 203 are alternately arranged. The first isolation layer 213, located between two adjacent columns of first semiconductor pillars 203 along the second direction Y, can separate the first word line 202 along the second direction Y, thereby allowing the first semiconductor pillars 203 in the same column of first semiconductor pillars 203 in the second direction Y to share the same first word line 202, thereby improving the control capability of the first word line 202 over the first transistor array 200.

[0053] For the first word line 202, in some embodiments, the step of forming the first word line includes: forming a gate dielectric layer that covers the surface of the first semiconductor pillars; and forming a gate conductive layer that covers the surface of the gate dielectric layer and fills the gaps between the first semiconductor pillars. The gate dielectric layer covering the surface of the first semiconductor pillars can prevent the gate conductive layer from reacting with the first semiconductor pillars during subsequent processes, thus avoiding damage to the semiconductor structure.

[0054] For the gate dielectric layer, the material forming the gate dielectric layer includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0055] For the gate conductive layer, the material forming the gate conductive layer includes at least one of polycrystalline silicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, copper, aluminum, lanthanum, or tungsten.

[0056] The materials forming the second isolation structure 212 and the first isolation layer 213 include silicon oxide, silicon nitride, silicon oxynitride, etc. In this embodiment, the materials forming the second isolation structure 212 are the same as those forming the first isolation structure 211, and are represented by the same characteristics; the materials forming the first isolation layer 213 are different from those forming the first isolation structure 211, and are represented by different characteristics. In other embodiments, the materials forming the second isolation structure 212 and the first isolation structure 211 may be different, while the materials forming the first isolation layer 213 and the first isolation layer 211 may be the same.

[0057] This embodiment also provides a method for forming a first transistor array and a first word line, specifically, referring to... Figure 9An initial first isolation structure 230 is formed, covering the surface of the semiconductor substrate 100. A plurality of first isolation trenches 250 extending along a second direction Y and a plurality of first semiconductor holes 240 extending along a third direction Z are formed. The first isolation trenches 250 and first semiconductor holes 240 are located within the initial first isolation structure 230. The first semiconductor holes 240 are arranged in an array along a first direction X and a second direction Y. In the first direction X, different first semiconductor holes 240 expose a portion of the top surface of the same first first line 201, and in the second direction Y, different first semiconductor holes 240 expose portions of the top surfaces of different first first lines 201. Furthermore, in the first direction X, the first isolation trenches 250 and the first semiconductor holes 240 are alternately spaced, and the depth of the first isolation trenches 250 is equal to the depth of the first semiconductor holes 240. (Reference) Figure 10 A first isolation layer 213 is formed to fill the first isolation trench 250, and a first semiconductor pillar 203 is formed to fill the first semiconductor via 240; Return to Reference Figure 8 A portion of the initial first isolation structure 230 is removed, leaving the remaining initial first isolation structure 230 as the first isolation structure 211. A first word line 202 is formed to cover the surface of the first isolation structure 211, with the top surface of the first word line 202 lower than the top surface of the first semiconductor pillar 203. A second isolation structure 212 is formed to cover the first word line 202, with the top surface of the second isolation structure 212 flush with the top surface of the first semiconductor pillar 203, thereby forming the first transistor array 200. This method, by first forming the first isolation layer 213 and the first semiconductor pillar 203, and then forming the first word line 202, avoids the subsequent etching process after forming the first word line 202, simplifying the formation method of the first word line 202 and improving the manufacturing efficiency of the semiconductor structure.

[0058] The methods for forming the first transistor array 200 and the first word line 202 provided by the above three embodiments can reduce the etching of the first semiconductor pillar 203. For example, when the material of the first semiconductor pillar 203 is an amorphous material such as IGZO, etching requires a lot of cost. For example, in dry etching, the power consumption of the main body of the equipment, the exhaust gas treatment system and the peripheral gas supply system is large, and the maintenance cost is high. In addition, there is the problem of particulate contamination of the equipment, which shortens the service life of the equipment. Wet etching is isotropic and has the problem of under-mask biting. Therefore, by adopting the methods for forming the first transistor array 200 and the first word line 202 in the above embodiments, the etching of amorphous materials such as IGZO can be reduced, thereby avoiding the above problems.

[0059] refer to Figure 11In some embodiments, after forming the first word line 202 and before forming the second transistor layer, the method further includes: removing a portion of the height of the first semiconductor pillar 203 and forming a contact structure 320, the contact structure 320 being located on the top surface of the first semiconductor pillar 203; forming a dielectric layer 310, the dielectric layer 310 at least covering the surface of the contact structure 320, and also covering the top surfaces of the second isolation structure 212 and the first isolation layer 213. The contact structure 320 connects one end of the source or drain of the first transistor and the gate of the second transistor, and the dielectric layer 310 can constitute an insulating layer for the gate portion of the second transistor array, forming a one-to-one correspondence between the first semiconductor pillar 203 and the second semiconductor pillar through the contact structure 320 and the dielectric layer 310.

[0060] For the contact structure 320, the material forming the contact structure 320 includes at least one of metal silicide, copper, or tungsten. In some embodiments, the material forming the contact structure 320 can be a single metal, a metal compound, or an alloy. The single metal can be copper, aluminum, tungsten, gold, or silver, etc.; the metal compound can be tantalum nitride or titanium nitride; and the alloy can be an alloy material composed of at least two of copper, aluminum, tungsten, gold, or silver.

[0061] For the dielectric layer 310, the material forming the dielectric layer 310 includes silicon oxide, silicon nitride, silicon oxynitride, etc. In this embodiment, the material forming the dielectric layer 310 is the same as the material forming the first isolation layer 213, and is represented by the same characteristics; in other embodiments, the material forming the dielectric layer 310 and the material forming the first isolation layer 213 may be different.

[0062] refer to Figure 12 A second transistor array 300 is formed on the first transistor array 200, the second transistor array 300 covers the surface of the dielectric layer 310, and includes a plurality of second semiconductor pillars 303 extending along a third direction Z, and the second semiconductor pillars 303 are arranged in an array in a first direction X and a second direction Y, with the first semiconductor pillar 203 corresponding to the second semiconductor pillar 303 one by one; a third isolation structure 311 is formed, the third isolation structure 311 fills the gaps between the second semiconductor pillars 303; a second word line 302 and a second bit line 301 are formed, and each second semiconductor pillar 303 is connected to the corresponding second word line 302 and second bit line 301.

[0063] For the second semiconductor pillar 303, the material forming the second semiconductor pillar 303 includes at least one or more of IGZO or ITO. For example, when the material of the second semiconductor pillar 303 is IGZO, the carrier mobility of IGZO is 20 to 50 times that of polycrystalline silicon, which is beneficial to improving the carrier mobility in the second semiconductor pillar 303, thereby helping to reduce the leakage current during semiconductor structure operation, so as to reduce the power consumption of the semiconductor structure and improve the operating efficiency of the semiconductor structure.

[0064] For the third isolation structure 311, the material forming the third isolation structure 311 includes silicon oxide, silicon nitride, silicon oxynitride, etc. In this embodiment, the material forming the third isolation structure 311 is the same as the material forming the first isolation structure 211, and is represented by the same characteristics; in other embodiments, the material forming the third isolation structure 311 may be different from the material forming the first isolation structure 211.

[0065] For the second word line 302, the material forming the second word line 302 includes at least one selected from polycrystalline silicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, copper, aluminum, lanthanum, or tungsten. In this embodiment, the material forming the second word line 302 is the same as the material forming the first word line 202, and is represented by the same characteristics; in other embodiments, the material forming the second word line 302 may be different from the material forming the first word line 202.

[0066] For the second bit line 301, the material forming the second bit line includes at least one selected from metal silicide, copper, or tungsten. In some embodiments, the material forming the second bit line 301 can be a single metal, a metal compound, or an alloy. The single metal can be copper, aluminum, tungsten, gold, or silver, etc.; the metal compound can be tantalum nitride or titanium nitride; the alloy can be an alloy material composed of at least two of copper, aluminum, tungsten, gold, or silver. In this embodiment, the material forming the second bit line 301 is the same as the material forming the first bit line 201, and is represented by the same characteristics; in other embodiments, the material forming the second bit line 301 can be different from the material forming the first bit line 201.

[0067] In some embodiments, the step of forming a second transistor array includes: forming an initial third isolation structure located above the first transistor array and covering the surface of a dielectric layer; forming a plurality of second semiconductor holes extending along a third direction, the second semiconductor holes being located within the initial third isolation structure and corresponding one-to-one with the first semiconductor pillars, the remaining initial third isolation structure serving as a third isolation structure; and forming second semiconductor pillars to fill the second semiconductor holes.

[0068] In other embodiments, the step of forming the second transistor array includes: forming a second sacrificial layer located above the first transistor array; forming a plurality of third grooves extending along a first direction and a plurality of fourth grooves extending along a second direction, the third grooves and fourth grooves located within the second sacrificial layer, the fourth grooves exposing the top surface of the first isolation layer, the third grooves and fourth grooves having equal depths, and in the second direction, the third grooves and contact structures are alternately spaced, the remaining second sacrificial layer corresponding one-to-one with the first semiconductor pillars; forming a third isolation structure to fill the third grooves and fourth grooves; removing the second sacrificial layer within the third isolation structure, and forming second semiconductor pillars to fill the gaps between the third isolation structures.

[0069] The methods for forming the second transistor array provided by the above two embodiments can reduce the etching of the second semiconductor pillar. For example, when the material of the second semiconductor pillar is an amorphous material such as IGZO, etching requires a lot of cost. For example, in dry etching, the power consumption of the main body of the equipment, the exhaust gas treatment system and the peripheral gas supply system is large, and the maintenance cost is high. In addition, there is the problem of particulate contamination of the equipment, which shortens the service life of the equipment. Wet etching is isotropic and has the problem of under-mask biting. Therefore, by using the second transistor array in the above embodiments, the etching of amorphous materials such as IGZO can be reduced, thereby avoiding the above problems.

[0070] In other embodiments, the step of forming the second transistor array includes: forming a second semiconductor layer located above the first transistor array; forming multiple first grooves extending along a first direction and multiple second grooves extending along a second direction, the first and second grooves located within the second semiconductor layer, the remaining second semiconductor layer serving as second semiconductor pillars corresponding one-to-one with the first semiconductor pillars; and forming a third isolation structure to fill the first and second grooves. By directly etching the second semiconductor layer, the semiconductor structure fabrication process can be simplified, and the fabrication efficiency of the semiconductor structure can be improved.

[0071] Continue to refer to Figure 12In some embodiments, the step of forming the second word line 302 and the second bit line 301 includes: forming a first insulating layer 314 covering the surface of the second transistor array 300; forming multiple second word lines 302 and second bit lines 301 extending along a second direction Y, wherein the second word lines 302 and second bit lines 301 are located within the first insulating layer 314, are parallel to each other and alternately spaced in the first direction X, and in the second direction Y, the same second word line 302 or second bit line 301 connects a portion of the surface of two adjacent columns of second semiconductor pillars 303. The second word line 302 and second bit line 301 formed by this method are arranged parallel to each other, and in the second direction Y, two adjacent columns of second semiconductor pillars 303 can share a single second word line 302 or second bit line 301, thereby increasing the space utilization of the semiconductor structure and further increasing the integration density of the semiconductor structure.

[0072] refer to Figure 13 In other embodiments, the step of forming the second word line 302 and the second bit line 301 includes: forming a second insulating layer 312 covering the surface of the second transistor array 300; forming a plurality of second word lines 302 extending along a second direction Y, the second word lines 302 being located within the second insulating layer 312, wherein in the second direction Y, the same second word line 302 connects a portion of the top surface of two adjacent columns of second semiconductor pillars 303, and in the first direction X, the surfaces of every two columns of second semiconductor pillars 303 are connected to the same second word line 302; forming a third insulating layer 313 covering the surfaces of the second word lines 302 and the second insulating layer 312; and forming a plurality of second bit lines 301. 01. The second bit line 301 includes a plurality of second bit line contact lines 334 extending along a third direction Z and a plurality of second bit line extension lines 333 extending along a first direction X. The second bit line contact lines 334 are located within the second insulating layer 312 and the third insulating layer 313, and the second bit line extension lines 333 are located within the second insulating layer 312. The second bit line contact lines 334 are arranged in an array in the first direction X and the second direction Y. The second bit line contact lines 334 and the second word lines 302 are alternately spaced in the first direction X. Each second bit line contact line 334 connects to a portion of the top surface of two adjacent second semiconductor pillars 303. The bottom of the second bit line extension line 333 is connected to the top of the second bit line contact line 334.

[0073] By forming the second word line 302 and the second bit line 301 with the above-described structure, the second bit line 301 includes a second bit line contact line 334 and a second bit line extension line 333, so that the extension directions of the second word line 302 and the second bit line 301 are different. This prevents parasitic capacitance from being generated between the second word line 302 and the second bit line 301 when they are arranged in parallel, thus avoiding affecting the performance of the semiconductor structure. It is understood that the positions of the second word line 302 and the second bit line 301 can be interchanged, and a structure can still be formed in which one second semiconductor pillar 303 corresponds to one second word line 302 and one second bit line 301.

[0074] In this embodiment, the first insulating layer 314, the second insulating layer 312, and the third insulating layer 313 are made of the same material, and are made of the same material as the third isolation structure 311, and are represented by the same features. In other embodiments, the materials of the first insulating layer 314, the second insulating layer 312, and the third insulating layer 313 may be different. The materials of the first insulating layer 314, the second insulating layer 312, and the third insulating layer 313 include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0075] In some embodiments, the semiconductor structure fabrication methods provided in the above embodiments can be repeatedly stacked to form a stacked structure, so as to integrate more transistor structures in a unit volume, thereby improving the integration density of the semiconductor structure and the performance of the semiconductor structure.

[0076] The semiconductor structure fabrication method provided in this disclosure forms a first transistor array having multiple first semiconductor pillars and a second transistor array having multiple second semiconductor pillars. The first transistors are connected to corresponding first word lines and first bit lines, and the second transistors are connected to corresponding second word lines and second bit lines. The first transistors and second transistors are in one-to-one correspondence to form a structure with two transistors and no capacitors. This solves the problem of needing to fabricate a large number of capacitors per unit area in the semiconductor structure fabrication process. The structure with two transistors and no capacitors can increase the space utilization of the semiconductor structure and improve the integration density of the semiconductor structure.

[0077] Another embodiment of this disclosure provides a semiconductor structure, employing the above-described method for fabricating the semiconductor structure to improve the performance of the formed semiconductor structure. It should be noted that the parts that are the same as or corresponding to those in the above embodiments can be referred to the corresponding descriptions in the foregoing embodiments, and will not be elaborated upon further below.

[0078] Continue to refer to Figure 12 The semiconductor structure provided in this embodiment includes:

[0079] A semiconductor substrate 100 has a plurality of first bit lines 201 extending along a first direction X; a first transistor array 200 is located on the semiconductor substrate 100, the first transistor array includes a plurality of first semiconductor pillars 203, and the first semiconductor pillars 203 extend along a third direction Z and are arranged in an array in the first direction X and the second direction Y; a first isolation layer 213 extends along the second direction Y and is located between two adjacent columns of first semiconductor pillars 203, and the first isolation layer 213 and the first semiconductor pillars 203 are alternately arranged in the first direction X; a first isolation structure 211 fills the gap between the first isolation layer 213 and the first semiconductor pillars 203; and a first word line 202 is formed by each first semiconductor pillar. 203 connects the corresponding first word line 202 and first bit line 201, and the first word line 202 is located on the surface of the first isolation structure 211; the second isolation structure 212 is located on the surface of the first word line 202; the second transistor array 300 is located on the first transistor array 200, and the second transistor array 300 includes a plurality of second semiconductor pillars 303 extending along a third direction Z, arranged in an array in a first direction X and a second direction Y, and corresponding one-to-one with the first semiconductor pillars 203; the third isolation structure 311 fills the gaps between the second semiconductor pillars 303; the second word line 302 and the second bit line 301, and each second semiconductor pillar connects the corresponding second word line 302 and the second bit line 301.

[0080] In some embodiments, the semiconductor structure further includes: a contact structure 320 located on the surface of the first semiconductor pillar 203; and a dielectric layer 310 covering at least the surface of the contact structure 320 and also covering the top surfaces of the second isolation structure 212 and the first isolation layer 213. The contact structure 320 connects one end of the source or drain of the first transistor and the gate of the second transistor. The dielectric layer 310 can form an insulating layer for the gate portion of the second transistor array, thereby forming a one-to-one correspondence between the first semiconductor pillar 203 and the second semiconductor pillar through the contact structure 320 and the dielectric layer 310.

[0081] In some embodiments, reference Figure 12 The second word line 302 and the second bit line 301 include: a first insulating layer 314 covering the surface of the second transistor array 300; the second word line 302 and the second bit line 301 extending along a second direction Y and arranged parallel to each other within the first insulating layer 314; in the second direction Y, the same second word line 302 or second bit line 301 connects a portion of the surface of two adjacent columns of second semiconductor pillars 303. The second word line 302 and the second bit line 301 are arranged parallel to each other, and in the second direction Y, two adjacent columns of second semiconductor pillars 303 can share a single second word line 302 or second bit line 301, thereby increasing the space utilization of the semiconductor structure and further increasing the integration density of the semiconductor structure.

[0082] refer to Figure 13 In other embodiments, the second word line 302 and the second bit line 301 include: a second insulating layer 312 covering the top surfaces of the second semiconductor pillars 303 and the third isolation structure 311; the second word lines 302 extending along a second direction Y and disposed parallel to each other within the second insulating layer 312; in the second direction Y, the same second word line 302 connects a portion of the surface of two adjacent columns of second semiconductor pillars 303; and in the first direction X, a portion of the surface of every two columns of second semiconductor pillars 303 connects to the same second word line 302; and a third insulating layer 313 covering the surfaces of the second word lines 302 and the second insulating layer 312. The second bit line 301 includes a second bit line contact line 334 and a second bit line extension line 333. The second bit line contact line 334 is disposed in the second insulating layer 312 and the third insulating layer 313 along the third direction Z, and is arranged in an array in the first direction X and the second direction Y. In the first direction X, the second bit line contact line 334 and the second word line 302 are alternately spaced. Each second bit line contact line 334 connects to a portion of the surface of two adjacent second semiconductor pillars 303. The second bit line extension line 333 is disposed in the third insulating layer 313 along the second direction Y, and its bottom is connected to the top of the second bit line contact line 334. By forming the second word line 302 and the second bit line 301 with the above structure, the second bit line 301 includes a second bit line contact line 334 and a second bit line extension line 333, so that the extension directions of the second word line 302 and the second bit line 301 are different, thereby preventing the generation of parasitic capacitance between the second word line 302 and the second bit line 301 when the second word line 302 and the second bit line 301 are arranged in parallel, and avoiding the impact on the performance of the semiconductor structure.

[0083] It is understood that, in some embodiments, the semiconductor structures provided in the above embodiments can be stacked to form a stacked 2TOC type semiconductor structure, thereby increasing the integration density of the semiconductor structure and improving the performance of the semiconductor structure.

[0084] The semiconductor structure disclosed herein includes a first transistor array having multiple first semiconductor pillars and a second transistor array having multiple second semiconductor pillars. The first transistors are connected to corresponding first word lines and first bit lines, and the second transistors are connected to corresponding second word lines and second bit lines. The first transistors and second transistors are in one-to-one correspondence to form a structure with two transistors and no capacitors. This solves the problem of needing to prepare a large number of capacitors per unit area in the semiconductor structure manufacturing process. The structure with two transistors and no capacitors can increase the space utilization of the semiconductor structure and improve the integration density of the semiconductor structure.

[0085] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate having a plurality of first bit lines extending along a first direction; A first transistor array is formed on the semiconductor substrate, the first transistor array comprising a plurality of first semiconductor pillars; A first word line is formed, and each first semiconductor pillar is connected to the corresponding first word line and the first bit line; A second transistor array is formed on the first transistor array, the second transistor array including a plurality of second semiconductor pillars, and the first semiconductor pillar and the second semiconductor pillar correspond one-to-one; A second word line and a second bit line are formed, and each second semiconductor pillar is connected to the corresponding second word line and the second bit line; The formed second semiconductor pillar extends along a third direction and is arranged in an array in the first and second directions; The formation of the second transistor array further includes: forming a third isolation structure, the third isolation structure filling the gaps between the second semiconductor pillars; The steps for forming the second word line and the second bit line include: A first insulating layer is formed, which covers the surface of the second transistor array; Multiple second word lines and second bit lines extending along the second direction are formed. The second word lines and second bit lines are located within the first insulating layer, are parallel to each other and are alternately spaced in the first direction, and in the second direction, the same second word line or second bit line connects a portion of the surface of two adjacent columns of second semiconductor pillars.

2. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The first semiconductor pillar extends along a third direction and is arranged in an array in the first and second directions; the first word line extends along the second direction and surrounds the first semiconductor pillar.

3. The method for fabricating a semiconductor structure as described in claim 2, characterized in that, The step of forming the first transistor array includes: A first sacrificial layer is formed, which covers the surface of the semiconductor substrate; Multiple first trenches extending along the first direction and multiple second trenches extending along the second direction are formed. The first trenches and the second trenches are located within the first sacrificial layer, with their bottoms flush with the top surface of the first bit line. In the second direction, the projections of the first trenches and the projections of the first bit lines are parallel to each other and alternately arranged. A first isolation structure is formed to fill the first trench and the second trench; The first sacrificial layer between the first isolation structures is removed, and the first semiconductor pillars are formed to fill the gaps between the first isolation structures.

4. The method for fabricating a semiconductor structure as described in claim 2, characterized in that, The step of forming the first transistor array includes: An initial first isolation structure is formed, the initial first isolation structure covering the surface of the semiconductor substrate; Multiple first semiconductor holes are formed extending along the third direction. The first semiconductor holes are located within the initial first isolation structure and are arranged in an array in the first direction and the second direction. The first semiconductor holes expose the surface of the first bit line. The remaining initial first isolation structure serves as the first isolation structure. The first semiconductor pillar is formed to fill the first semiconductor hole.

5. The method for fabricating a semiconductor structure as described in claim 3 or 4, characterized in that, The steps for forming the first character line include: Remove a portion of the height of the first isolation structure; A first character line is formed to cover the surface of the first isolation structure; A second isolation structure is formed to cover the surface of the first word line; A first isolation layer is formed, which extends along the second direction and is located between two adjacent columns of the first semiconductor pillars. In the first direction, the first isolation layer and the first semiconductor pillars are alternately spaced.

6. The method for fabricating a semiconductor structure as described in claim 2, characterized in that, The steps of forming the first transistor array and forming the first word line include: An initial first isolation structure is formed, the initial first isolation structure covering the surface of the semiconductor substrate; A plurality of first isolation trenches extending along the second direction and a plurality of first semiconductor holes extending along the third direction are formed. The first isolation trenches and the first semiconductor holes are located within the initial first isolation structure. The first semiconductor holes are arranged in an array in the first direction and the second direction and expose the surface of the first bit line. In the first direction, the first isolation trenches and the first semiconductor holes are alternately spaced. A first isolation layer is formed to fill the first isolation trench, and a first semiconductor pillar is formed to fill the first semiconductor hole; Remove a portion of the initial first isolation structure, leaving the remaining initial first isolation structure as the first isolation structure; A first character line is formed to cover the surface of the first isolation structure; A second isolation structure is formed to cover the first word line.

7. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, After the formation of the first word line and before the formation of the second transistor, the method further includes: A contact structure is formed, the contact structure being located on the top surface of the first semiconductor pillar; A dielectric layer is formed, which at least covers the surface of the contact structure.

8. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The step of forming the second transistor array includes: An initial third isolation structure is formed, which is located above the first transistor array; Multiple second semiconductor holes are formed extending along the third direction. The second semiconductor holes are located within the initial third isolation structure and correspond one-to-one with the first semiconductor pillars. The remaining initial third isolation structure serves as the third isolation structure. The second semiconductor pillar is formed to fill the second semiconductor hole.

9. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The step of forming the second transistor array includes: A second semiconductor layer is formed, which is located above the first transistor array; Multiple first grooves extending along the first direction and multiple second grooves extending along the second direction are formed. The first grooves and the second grooves are located within the second semiconductor layer. The remaining second semiconductor layer serves as the second semiconductor pillar, which corresponds one-to-one with the first semiconductor pillar. A third isolation structure is formed to fill the first groove and the second groove.

10. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The step of forming the second transistor array includes: A second sacrificial layer is formed, which is located above the first transistor array; Multiple third grooves extending along the first direction and multiple fourth grooves extending along the second direction are formed. The third grooves and the fourth grooves are located within the second sacrificial layer, and the remaining second sacrificial layer corresponds one-to-one with the first semiconductor pillar. A third isolation structure is formed to fill the third groove and the fourth groove; The second sacrificial layer within the third isolation structure is removed, and the second semiconductor pillars are formed to fill the gaps between the third isolation structures.

11. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The steps for forming the second word line and the second bit line include: A second insulating layer is formed, which covers the surface of the second transistor array; Multiple second word lines are formed extending along the second direction. The second word lines are located within the second insulating layer. In the second direction, the same second word line connects a portion of the surface of two adjacent columns of the second semiconductor pillars. In the first direction, the surface of every two columns of the second semiconductor pillars is connected to the same second word line. A third insulating layer is formed, which covers the second letter line and the surface of the second insulating layer; Multiple second bit lines are formed, each second bit line including multiple second bit line contact lines extending along the third direction and multiple second bit line extension lines extending along the first direction. The second bit line contact lines are located within the second insulating layer and the third insulating layer, and the second bit line extension lines are located within the third insulating layer. The second bit line contact lines are arranged in an array in the first direction and the second direction. In the first direction, the second bit line contact lines and the second word lines are alternately spaced. Each second bit line contact line connects to a portion of the surface of two adjacent second semiconductor pillars, and the bottom of the second bit line extension line is connected to the top of the second bit line contact line.

12. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The materials forming the first semiconductor pillar and the second semiconductor pillar include at least one or more of IGZO, IZO, or ITO.

13. A semiconductor structure, based on a method for fabricating the semiconductor structure according to any one of claims 1 to 12, characterized in that, include: A semiconductor substrate having a plurality of first bit lines extending along a first direction; A first transistor array is located on the semiconductor substrate, and the first transistor array includes a plurality of first semiconductor pillars; First word line, each of the first semiconductor pillars is connected to the corresponding first word line and the first bit line; A second transistor array is located on the first transistor array. The second transistor array includes a plurality of second semiconductor pillars, and the first semiconductor pillars correspond one-to-one with the second semiconductor pillars. The second word line and the second bit line, each of the second semiconductor pillars is connected to the corresponding second word line and the second bit line.

14. The semiconductor structure as described in claim 13, characterized in that, include: The first semiconductor pillar extends along a third direction and is arranged in an array in the first and second directions; A first isolation layer extends along the second direction and is located between two adjacent columns of the first semiconductor pillars. In the first direction, the first isolation layer and the first semiconductor pillars are alternately spaced. A first isolation structure fills the gap between the first isolation layer and the first semiconductor pillar, and the first word line is located on the surface of the first isolation structure; A second isolation structure is located on the surface of the first word line.

15. The semiconductor structure as described in claim 13, characterized in that, include: A contact structure located on the surface of the first semiconductor pillar; A dielectric layer that at least covers the surface of the contact structure.

16. The semiconductor structure as described in claim 13, characterized in that, The second transistor array includes: The second semiconductor pillars extend along a third direction and are arranged in an array in the first and second directions; A third isolation structure fills the gap between the second semiconductor pillars.

17. The semiconductor structure as claimed in claim 16, characterized in that, The second word line and the second bit line include: A first insulating layer covers the surface of the second transistor array. The second word line and the second bit line extend along the second direction and are disposed parallel to each other within the first insulating layer. In the second direction, the same second word line or the second bit line connects a portion of the surface of two adjacent columns of the second semiconductor pillars.

18. The semiconductor structure as claimed in claim 16, characterized in that, The second word line and the second bit line include: A second insulating layer covers the surface of the second transistor array. The second word line extends along a second direction and is disposed parallel to each other within the second insulating layer. In the second direction, the same second word line connects a portion of the surface of two adjacent columns of the second semiconductor pillars. In the first direction, a portion of the surface of every two columns of the second semiconductor pillars is connected to the same second word line. A third insulating layer covers the second word line and the surface of the second insulating layer. The second bit line includes a second bit line contact line and a second bit line extension line. The second bit line contact line is disposed within the second insulating layer and the third insulating layer along the third direction and is arranged in an array in the first direction and the second direction. In the first direction, the second bit line contact line and the second word line are alternately spaced. Each second bit line contact line connects to a portion of the surface of two adjacent second semiconductor pillars. The second bit line extension line is disposed within the third insulating layer along the second direction, and its bottom is connected to the top of the second bit line contact line.

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