DRAM-based LIDAR pixels

Abstract

A light detection and ranging (LIDAR) detector circuit includes a memory device and at least one control circuit. The memory device includes a non-transitory storage medium configured to store data indicating a detection event in a corresponding memory bin. The at least one control circuit is configured to receive a detection signal from one or more photodetector elements, identify the presence or absence of a detection event indicated by the detection signal during a portion of time between pulses of an emitter signal output from a LIDAR emitter element, and, in response to the identification of the presence or absence of a detection event, respectively, perform one of a first memory operation or a second memory operation to update the data in the corresponding memory bin. Related circuits and operating methods are also discussed.

Description

[0001] Priority claim

[0002] This application claims priority from U.S. Provisional Patent Application No. 62 / 966,171, entitled “DRAM-Based LIDAR Pixel,” filed in the U.S. Patent and Trademark Office on January 27, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure is directed to light detection and ranging (LIDAR; also known as laser radar) systems, and more particularly to memory operations in time-of-flight lidar systems. Background Art

[0004] Time-of-flight (ToF)-based imaging is used in a variety of applications, including range determination, depth profiling, and 3D imaging (e.g., LiDAR). Direct time-of-flight measurements involve directly measuring the length of time between emitting radiation and sensing the radiation after reflection from an object or other target. From this, the distance to the target can be determined. Indirect time-of-flight measurements involve determining the distance to the target by phase modulating the amplitude of the signal emitted by the LiDAR system's transmitter element(s) and measuring the phase (e.g., relative to a delay or shift) of the return signal received at the LiDAR system's detector element(s). These phases can be measured using a series of individual measurements, or samples.

[0005] In certain applications, photodetector arrays, such as single-photon avalanche diode (SPAD) arrays, can be used to perform sensing of reflected radiation in direct or indirect time-of-flight systems. One or more photodetectors can define a detector pixel of the array. SPAD arrays can be used as solid-state detectors in imaging applications where high sensitivity and timing resolution may be required.

[0006] SPADs are based on a semiconductor junction (e.g., a pn junction) that can detect incident photons when biased beyond its breakdown region, for example, by or in response to a gating signal with a desired pulse width. A high reverse bias generates an electric field of sufficient magnitude so that a single charge carrier introduced into the device's depletion layer can cause a self-sustaining avalanche via impact ionization. The avalanche is quenched either actively (e.g., by reducing the bias) or passively (e.g., by using a voltage drop across a series-connected resistor) by a quenching circuit, allowing the device to be "reset" to detect additional photons. The initial charge carrier can be photogenerated by a single incident photon striking the high-field region. It is this characteristic that gives rise to the name "single-photon avalanche diode." This single-photon detection mode of operation is often referred to as "Geiger mode."

[0007] When imaging a scene, a ToF sensor for LiDAR applications can include circuitry to time-stamp and / or count incoming photons, such as those reflected from a target. Some ToF pixel approaches can use digital or analog circuitry to count the detection and arrival time of photons, also known as time-stamping.

[0008] The data rate can be compressed by plotting a histogram of the timestamps; however, this may involve considerable memory resources that may be used inefficiently in a typical ToFLIDAR system. For example, the memory depth (e.g., the number of bits) of each histogram bin (which may correspond to a corresponding sub-range of photon arrival times) is typically set by the peak or maximum expected laser return, however, in practice, many or most of the histogram bins will be sparsely occupied (e.g., occupied only by background noise). Furthermore, thousands of time bins (each corresponding to a corresponding photon arrival time) can typically be used to form a histogram sufficient to cover the typical time range (e.g., microseconds) of a LIDAR system with a typical time-to-digital converter (TDC) resolution (e.g., 50-100 ps).

[0009] Memory devices such as static random access memory (SRAM) can be used for memory storage. SRAM is typically more than twenty times more compact per bit than some counters that can conventionally be applied to SPAD pixels. In standard cell libraries, a single bit in a counter is represented by a D-type (or T-type) flip-flop with approximately 32 transistors. Additionally, each bit can use a readout unit (e.g., a tri-state buffer). However, SRAM can present challenges, as the read-increment-write logic conventionally incorporated into some SRAM configurations can be large and difficult to incorporate into smaller pixels due to layout and space limitations, especially as speed and memory requirements increase. Summary of the Invention

[0010] Some embodiments described herein provide a lidar system comprising one or more emitter units (comprising one or more semiconductor lasers, such as surface-emitting or edge-emitting laser diodes; generally referred to herein as emitters, which output emitter signals), one or more photodetector pixels (comprising one or more photodetectors, such as semiconductor photodiodes, including avalanche photodiodes and single-photon avalanche detectors; generally referred to herein as detectors, which output detection signals in response to incident light), and one or more control circuits configured to selectively operate a subset of the emitter units and / or detector pixels (including their corresponding emitters and / or detectors, respectively) to provide a 3D time-of-flight (ToF) flash lidar system.

[0011] In some embodiments, the one or more control circuits are configured to perform one of the first or second memory operations, respectively, in response to a detection signal indicating the presence or absence of a detection event, to update data stored in the corresponding memory bin during a portion of the time between pulses of the transmitter signal output from the LIDAR transmitter element.

[0012] According to some embodiments of the present disclosure, a LIDAR detector circuit includes a memory device and at least one control circuit, the memory device including a non-transitory storage medium configured to store data in corresponding memory bins. The at least one control circuit is configured to receive a detection signal from one or more photodetector elements; identify the presence or absence of a detection event indicated by the detection signal during a portion of time between pulses of an emitter signal output from a LIDAR emitter element; in response to the detection signal indicating the presence of a detection event during the portion of time between pulses of the emitter signal, perform a first memory operation to update the data in the corresponding memory bin; and in response to the detection signal indicating the absence of a detection event during the portion of time between pulses of the emitter signal, perform a second memory operation to update the data in the corresponding memory bin.

[0013] In some embodiments, the first memory operation may be an increment operation and the second memory operation comprises a refresh operation.

[0014] In some embodiments, the at least one control circuit may be configured to perform refresh operations at a frequency greater than or less than a transmitter signal pulse frequency.

[0015] In some embodiments, the frequency of refresh operations may be temperature dependent.

[0016] In some embodiments, the at least one control circuit may include a logic-based counter circuit configured to perform an increment operation or a refresh operation.

[0017] In some embodiments, the counter circuit may include a plurality of adder circuits connected in series.

[0018] In some embodiments, the counter circuit may include a linear feedback shift register configured to perform an incrementing operation by shifting bits stored in corresponding memory bins forward using a linear feedback loop.

[0019] In some embodiments, a linear feedback shift register may be configured to perform a refresh operation by feeding back bits stored in corresponding memory bins to at least one of its inputs.

[0020] In some embodiments, an increment operation or refresh operation may be completed during the time between transmitter signal pulses to update data stored in corresponding memory bins of the memory device.

[0021] In some embodiments, the increment or refresh operations may be performed sequentially on the respective memory bins.

[0022] In some embodiments, the memory device may be a memory array comprising respective rows or columns of dynamic random access memory (DRAM) cells defining respective memory bins, and the at least one control circuit may be further configured to output a read signal in response to read signals sequentially applied to the respective rows or columns.

[0023] In some embodiments, the memory device and the one or more photodetector elements may include a DRAM cell and multiple photodetector elements natively located on the same die.

[0024] In some embodiments, the memory device and the one or more photodetector elements may include a DRAM cell and a plurality of photodetector elements provided on respective wafers and electrically connected to each other.

[0025] In some embodiments, DRAM cells may be provided in corresponding trenches between the photodetector elements, and optical and / or electrical barriers may be defined between adjacent ones of the photodetector elements.

[0026] In some embodiments, the readout signal may include a count signal and / or a time-integrated signal, and the at least one control circuit may be configured to calculate an estimated arrival time of a photon incident on the photodetector element based on the readout signal.

[0027] In some embodiments, the portion of time between pulses of the transmitter signal may correspond to a respective distance sub-range, and wherein the respective memory bin includes histogram data corresponding to the respective distance sub-range.

[0028] In some embodiments, the photodetector elements may include single photon avalanche detectors (SPADs), and the histogram data may include photon counts indicated by detection signals corresponding to respective ranges of distance sub-ranges.

[0029] In some embodiments, at least one control circuit can be configured to transmit respective gating signals that activate one or more photodetector elements for respective detection windows that are differently delayed between pulses of the emitter signal.

[0030] In some embodiments, respective detection windows may correspond to respective distance sub-ranges, and wherein the at least one control circuit is configured to transmit respective gating signals to activate one or more photodetector elements to sequentially cycle through the respective distance sub-ranges.

[0031] According to some embodiments of the present disclosure, a LIDAR detector circuit includes one or more photodetector elements defining LIDAR detector pixels, a memory device including a non-transitory storage medium, and at least one processor circuit, the non-transitory storage medium configured to store data in corresponding memory bins. The at least one processor circuit is configured to receive a detection signal from the one or more photodetector elements, identify the absence of a detection event indicated by the detection signal during a portion of time between pulses of an emitter signal output from a LIDAR emitter element, and, in response to the identification of the absence of a detection event, perform a memory operation to update the data in the corresponding memory bin.

[0032] In some embodiments, the memory operation may be a refresh operation. The at least one processor circuit may be further configured to identify the presence of a detection event indicated by the detection signal during the portion of time between pulses of the transmitter signal, and in response to identifying the presence of the detection event, perform an increment operation to update data in the corresponding memory bin.

[0033] In some embodiments, the at least one processor circuit may be configured to perform refresh operations at a frequency greater than or less than the transmitter signal pulse frequency. For example, the frequency of the refresh operations may be temperature dependent.

[0034] In some embodiments, at least one processor circuit may include a linear feedback shift register configured to perform an increment operation by shifting bits stored in a corresponding memory bin forward using a linear feedback loop, and configured to perform a refresh operation by feeding back bits stored in the corresponding memory bin to at least one of its inputs.

[0035] In some embodiments, an increment operation or refresh operation may be completed during the time between transmitter signal pulses to update data stored in corresponding memory bins of the memory device.

[0036] In some embodiments, the portion of time between pulses of the emitter signal may correspond to a respective distance sub-range, and the respective memory bin may include histogram data corresponding to the respective distance sub-range. The histogram data may include a photon count indicated by the detection signal.

[0037] In some embodiments, a memory device may include dynamic random access memory (DRAM) cells that define respective memory bins.

[0038] According to some embodiments of the present disclosure, a method of operating a LIDAR detector circuit includes receiving a detection signal from one or more photodetector elements; identifying the presence or absence of a detection event indicated by the detection signal during a portion of time between pulses of an emitter signal output from a LIDAR emitter element; and performing one of a first memory operation or a second memory operation to update data stored in corresponding memory bins of a memory device in response to identifying the presence or absence of the detection event, respectively, wherein the memory device is a non-transitory storage medium.

[0039] In some embodiments, the first memory operation may be an increment operation and the second memory operation may be a refresh operation.

[0040] In some embodiments, performing a refresh operation may include performing a refresh operation at a frequency greater than or less than a transmitter signal pulse frequency.

[0041] In some embodiments, performing the increment operation may include shifting bits stored in corresponding memory bins forward using a linear feedback loop of a linear feedback shift register.

[0042] In some embodiments, performing a refresh operation may include feeding back bits stored in corresponding memory bins to at least one input of a linear feedback shift register.

[0043] In some embodiments, one of an increment operation or a refresh operation may be performed to update data stored in a corresponding memory bin of the memory device during the time between transmitter signal pulses.

[0044] According to some embodiments of the present disclosure, a LIDAR system may include a detector circuit as described in any of the embodiments herein. The LIDAR system is configured to be coupled to an autonomous vehicle such that the LIDAR transmitter element and one or more photodetector elements are oriented relative to an intended direction of travel of the autonomous vehicle.

[0045] Other devices, apparatuses and / or methods according to some embodiments will become apparent to those skilled in the art after reviewing the following figures and detailed description. It is intended that all such additional embodiments, in addition to any and all combinations of the above-described embodiments, be included within this description, be within the scope of the invention, and be protected by the following claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1is a schematic block diagram illustrating an example of a LIDAR system or circuit according to an embodiment of the present disclosure.

[0047] Figure 2 is a schematic block diagram further illustrating components of a measurement system or circuit in LIDAR applications according to some embodiments of the present disclosure.

[0048] Figure 3 is a schematic block diagram illustrating an example configuration of a memory circuit implementing a memory pixel according to some embodiments of the present disclosure.

[0049] Figure 4A An example memory device is illustrated that implements an n×k bit DRAM array using gain cell DRAMs, such as 3T DRAM cells, according to some embodiments of the present disclosure.

[0050] Figure 4B An example memory device implementing an n×k bit DRAM array using 1T1C DRAM cells is illustrated according to some embodiments of the present disclosure.

[0051] Figure 5A Illustrated are example circuits configured to perform increment and refresh operations according to some embodiments of the present disclosure.

[0052] Figure 5B Illustrated are example circuits configured to perform increment and refresh operations according to some embodiments of the present disclosure.

[0053] Figure 6 Illustrated are example timing diagrams for precharge, read, modify, and write operations for performing increment and refresh operations according to some embodiments of the present disclosure.

[0054] Figure 7 An example sample and increment or refresh circuit is illustrated according to some embodiments of the present disclosure.

[0055] Figure 8 Illustrated are example timing diagrams for generating signals used to assert or enable write and read signals to perform increment and refresh operations according to some embodiments of the present disclosure.

[0056] Figure 9 is a graph illustrating an example simulation of memory cell leakage or retention time as a function of temperature.

[0057] Figure 10 is a cross-sectional view illustrating a memory structure including a trench capacitor according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0058] In the following detailed description, many specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure. However, it will be understood by those skilled in the art that the present disclosure can be practiced without these specific details. In some instances, well-known methods, procedures, components, and circuits are not described in detail to avoid confusing the present disclosure. It is intended that all embodiments disclosed herein can be implemented individually or combined in any manner and / or combination. Aspects described with respect to one embodiment can be incorporated into different embodiments, although not specifically described with respect to it. That is, all embodiments and / or features of any embodiment can be combined in any manner and / or combination.

[0059] Embodiments of the present disclosure are described herein with reference to lidar applications and systems. A lidar system may include an emitter array and a detector array, or a system having a single emitter and detector array, or a system having an emitter array and a single detector. As described herein, one or more emitters may define an emitter cell, and one or more detectors may define a detector pixel. A detector pixel may also include or provide outputs to dedicated circuitry, such as memory and logic circuitry (including correlators, counters, and / or time integrator logic), which is not shared with other pixels, referred to herein as an "in-pixel" configuration. A flash lidar system may acquire an image by emitting light from an emitter array, or a subset of the array, for short durations (pulses) over a field of view (FoV) or scene, and detecting return signals reflected from one or more targets in the FoV at one or more detectors. A non-flash or scanning lidar system may generate image frames by scanning light emissions (e.g., continuously) over the field of view or scene, for example, using a point scan or line scan to transmit the necessary power for each point and scanning sequentially to reconstruct the full FoV.

[0060] In the embodiments described herein, a detection window or gating window may refer to a time period between signal pulses output by (one or more) emitters, or the duration of activation and deactivation of one or more detectors (e.g., in response to a corresponding detector time gate / control signal from a control circuit) (which may also be in response to a corresponding emitter control signal from a control circuit). The relative timing and duration of the respective detection windows may be determined by the respective gating signals (Strobe) as described herein. <x>) to control, in this case, the detection window can be called the gating window.

[0061] Some conventional SRAM-based detector pixel implementations may include six transistors per SRAM cell (e.g., NMOS and PMOS; also referred to as 6T), where each bit can be stored on four transistors, which form two cross-coupled inverters (providing two stable states for indicating logic 0 and logic 1), with two additional access transistors (used to control access to the memory cell during read and write operations). Such a configuration can impose limitations on both surface area per bit and power per bit. For example, in a histogramming memory application, such limitations may include (but are not limited to) the number of detector pixels, the bit depth of the histogram bins (also referred to herein as memory bins), and the number of histogram bins. In particular, including more transistors per memory cell or pixel can cause peak power requirements to increase with the number of detector pixels (e.g., for arrays with a large number of detector pixels in the presence of high background light levels or signals reflected from retroreflectors), which can lead to data integrity issues. Furthermore, particularly if pixel area is limited (e.g., due to optical or cost considerations), a larger number of transistors per memory cell or pixel may limit the bit depth of the histogram bins (which may lead to saturation in the presence of retroreflectors) and the number of histogram bins (where, due to the large number of gating windows of finite duration, photons may not be counted or “lost” when the emitter is active outside or between gating windows, thereby increasing emitter power requirements, which may cause surface area and emitter peak efficiency issues).

[0062] Furthermore, some conventional SRAM-based detector pixel implementations may include limitations on binary counting and arithmetic logic unit (ALU) cycle time. For example, some binary counters may use a k-bit carry chain, which, if implemented with chained full adders (e.g., whereby the carry output (Co) of one full adder is connected to the carry input (Ci) of the next full adder), may require k gate delays to stabilize. However, in some instances, such a configuration may make it difficult to stabilize within or within approximately half the bin time, which may consequently impose limitations on the histogram bin time and associated depth resolution. Furthermore, the logic required to precharge, read, modify, and write SRAM-based detector pixels can be relatively complex and area-consuming, thereby limiting the available histogram bin area and, consequently, the dynamic range and gating window duration (because fewer gating windows with longer durations can be used as memory capacity increases).

[0063] Some embodiments of the present disclosure may arise from the recognition that in some lidar applications, memory may be accessed sequentially, for example, by gradually stepping through and updating memory bins (which may indicate corresponding subranges of photon arrival times) in real time using incoming photon counts returned from laser pulses reflected from targets in response to continuously or periodically applying control signals to emitter units and applying gating signals to detector pixels to cycle through a series of range subranges. In contrast, in some conventional uses of SRAM, data states may typically be retained for unpredictable durations of time, set by sporadic accesses from external systems, and memory accesses may be random.

[0064] Thus, some embodiments of the present disclosure may provide detector pixels including memory array implementations and associated control schemes that allow for greater memory density (e.g., by utilizing fewer transistors) than would be possible using SRAM-based memory. For example, some embodiments of the present disclosure may provide memory devices (such as dynamic random access memory (DRAM)-based memory) that utilize sequential memory access and memory refresh operations that are coordinated with cycling through a series of range sub-ranges performed by the lidar detector pixel and with the timing between pulses of the lidar transmitter signal. Compared to an SRAM implementation, the use of DRAM may require fewer transistors (e.g., 1-3 transistors) of the same type (e.g., only NMOS) per pixel, wherein the memory refresh operations may be performed at a sufficient refresh rate (e.g., once per transmitter signal cycle, once every two transmitter signal cycles, etc.) to prevent leakage of the stored value in each DRAM cell and may be completed within the time between pulses of the lidar transmitter signal.

[0065] Some embodiments may include a gain cell DRAM implementation, such as a two-transistor, three-transistor, or four-transistor (2T / 3T / 4T) DRAM configuration (i.e., where each DRAM cell / storage bit has 2 / 3 / 4 transistors), where the DRAM cells of each memory bin may be incremented in response to a detection event, or may be refreshed (e.g., periodically) in the absence of a detection event during the time between transmitter signal pulses. For example, for an imaging distance range of 400 meters (m), the transmitter cycle may have a frequency of 375 kHz, where the period between pulses of the transmitter signal is approximately 2.667 In this example, the maximum refresh time for a memory bin may correspond to 2.667 Emitter cycling may be sufficient to overcome bit leakage issues (e.g., at temperatures of approximately 125°C or higher). Alternatively, some embodiments may include a single-transistor (1T1C) DRAM configuration (i.e., where each DRAM cell / storage bit has one transistor and one capacitor) with associated sense amplifier circuitry to increment or refresh the DRAM cell of each memory bin.

[0066] In some embodiments, a logic-based counter circuit can be used to perform memory bin increment or refresh operations. For example, a series or string of adders can be used to increment or refresh the value of the DRAM cells of each memory bin. As another example, linear feedback shift register (LFSR) based counting can be used to reduce or minimize memory bin update time (and therefore improve time resolution), as well as reduce or minimize precharge-read-modify-write (PRMW) logic overhead (and therefore reduce or minimize the total number of DRAM bits and histogram area). Although described primarily with reference to DRAM-based memories in the examples herein, it will be understood that embodiments of the present disclosure are not limited to DRAM or any particular memory storage technology, and can be applied to memory devices other than those specifically described herein.

[0067] Examples of lidar systems or circuits 100 that may utilize embodiments of the present disclosure are described in Figure 1 . The lidar system 100 includes control circuitry 105, timing circuitry 106, an emitter array 115 comprising a plurality of emitters 115e, and a detector array 110 comprising a plurality of detectors 110d. Detector 110d comprises a time-of-flight sensor (e.g., an array of single-photon detectors, such as SPADs). One or more emitter elements 115e of emitter array 115 may define an emitter unit that emits a pulse of radiation or a continuous wave signal, respectively, at a time and frequency controlled by a timing generator or driver circuit 116 (e.g., through a diffuser or filter 114). In certain embodiments, emitter 115e may be a pulsed light source, such as an LED or a laser (such as a vertical-cavity surface-emitting laser (VCSEL)). Radiation is reflected from target 150 and sensed by detector pixels defined by one or more detector elements 110d of detector array 110. The control circuit 105 implements a pixel processor that measures and / or calculates the time of flight of an illumination pulse over its journey from the emitter array 115 to the target 150 and back to the detector 110 d of the detector array 110 using direct or indirect ToF measurement techniques.

[0068] In some embodiments, the emitter module or circuitry 115 may include an array of emitter elements 115e (e.g., VCSELs), a corresponding array of optical elements 113, 114 coupled to one or more emitter elements (e.g., lens(es) 113 (such as microlenses) and / or diffuser 114), and / or drive electronics 116. The optical elements 113, 114 may be optional and may be configured to provide a sufficiently low beam divergence output from the emitter elements 115e to ensure that the illumination fields of individual or groups of emitter elements 115e do not significantly overlap, and also to provide a sufficiently large beam divergence output from the emitter elements 115e to provide eye safety to an observer.

[0069] The drive electronics 116 can each correspond to one or more emitter elements and can each operate in response to a timing control signal referenced to a master clock and / or a power control signal that controls the peak power and / or repetition rate of light output by the emitter elements 115e. In some embodiments, each emitter element 115e in the emitter array 115 is connected to and controlled by a corresponding driver circuit 116. In other embodiments, corresponding groups of emitter elements 115e in the emitter array 115 (e.g., emitter elements 115e that are spatially proximate to each other) can be connected to the same driver circuit 116. The driver circuit or circuits 116 can include one or more driver transistors configured to control the modulation frequency, timing, and amplitude of the light emission signal output from the emitter 115e.

[0070] The light signals emitted from multiple emitters 115e provide a single image frame for the flash LIDAR system 100, but embodiments of the present disclosure may also include non-flash or scanning LIDAR systems. The maximum optical power output of the emitters 115e can be selected to produce a signal-to-noise ratio for the return signal from the most distant, least reflective target under the brightest background illumination conditions detectable according to the embodiments described herein. By way of example, optional filters to control the emitted wavelength of light and diffusers 114 to increase the illumination field of the emitter array 115 are illustrated.

[0071] Light emissions output from one or more emitters 115e impinge on and are reflected by one or more targets 150, and the reflected light is detected (e.g., via receiver optics 112) by one or more detectors 110d as optical signals (also referred to herein as return signals, echo signals, or echoes), converted into electrical signal representations (referred to herein as detection signals), and processed (e.g., based on time of flight) to define a three-dimensional point cloud representation 170 of a field of view 190. The operation of a lidar system according to embodiments of the present disclosure as described herein may be controlled by one or more processors or controllers such as Figure 1 The control circuit 105) is executed.

[0072] In some embodiments, receiver / detector module or circuitry 110 includes an array of detector pixels (each including one or more detectors 110d, such as SPADs); receiver optics 112 (e.g., one or more lenses for collecting light above the FoV 190); and receiver electronics (including timing circuitry 106) configured to power, enable, and disable all or part of the detector array 110 and provide timing signals thereto. Detector pixels can be activated or deactivated with at least nanosecond precision and can be individually, group-addressable, and / or globally addressable. Receiver optics 112 may include microlenses configured to collect light from the maximum FoV imaged by the lidar system, microlenses that improve the collection efficiency of the detection pixels, and / or antireflection coatings that reduce or prevent stray light detection. In some embodiments, a spectral filter 111 may be provided to pass or allow "signal" light (i.e., light of a wavelength corresponding to the wavelength of the optical signal output from the transmitter) but substantially reject or prevent the passage of non-signal light (i.e., light of a wavelength different from the optical signal output from the transmitter).

[0073] Detectors 110d of detector array 110 are connected to timing circuit 106. Timing circuit 106 can be phase-locked to driver circuit 116 of emitter array 115. The sensitivity of each detector 110d or group of detectors can be controlled. For example, when the detector elements include reverse-biased photodiodes, avalanche photodiodes (APDs), PIN diodes, and / or Geiger-mode avalanche diodes (SPADs), the reverse bias can be adjusted such that higher overbias results in higher sensitivity.

[0074] In some embodiments, the control circuit 105, such as a microcontroller or microprocessor, provides different emitter control signals to the driver circuits 116 of different emitters 115e and / or provides different signals (e.g., gating signals) to the timing circuits 106 of different detectors 110d to enable / disable different detectors 110d to detect return signals from the target 150. As used herein, "gating" may refer to generating detector control signals (also referred to herein as gating signals or "gating") to control the timing and / or duration of activation (detection or gating window) of one or more detectors 110d of the lidar system 100. The control circuit 105 may also control memory operations to store data indicated by the detection signals in a non-transitory memory or memory array 205.

[0075] Figure 2 Components of a ToF measurement system or circuit 200 for LIDAR applications according to some embodiments described herein are further illustrated. Circuit 200 may include a processor circuit 105' (such as a digital signal processor (DSP)), a timing generator 116' that controls the timing of an illumination source (illustrated by way of example with reference to laser emitter array 115), and a single-photon detector array (illustrated by way of example with reference to single-photon detector array 110). Processor circuit 105' may also include a sequencer circuit configured to coordinate the operation of emitters 115e and detectors 110d.

[0076] Processor circuit 105' and timing generator 116' may implement Figure 1 The control circuit 105 and the driver circuit 116 of FIG. 10 , which are provided by the processor circuit 105, perform some operations. The laser emitter array 115 emits laser pulses 130 at times controlled by the timing generator 116′. Light 135 from the laser pulses 130 reflects off a target (illustrated as object 150) and is sensed by the single-photon detector array 110. The processor circuit 105′ implements a pixel processor that measures the time of flight (ToF) of the laser pulses 130 and their reflected signals 135 over their journey from the emitter array 115 to the object 150 and back to the single-photon detector array 110.

[0077] Processor circuit 105' can provide an analog and / or digital implementation of logic circuitry that provides the necessary timing signals (such as quenching and gating or strobing signals) to control the operation of the single-photon detectors of array 110 and process the detection signals output therefrom. For example, the single-photon detectors of array 110 can generate detection signals in response to incident photons only during a short strobing interval or strobing window defined by the strobing signal. Photons incident outside the strobing window have no effect on the output of the single-photon detectors. More generally, processor circuit 105' can include one or more circuits configured to generate corresponding detector control signals that control the timing and / or duration of activation of detector 110d and / or generate corresponding emitter control signals that control the output of optical signals from emitter 115e.

[0078] In some embodiments, the probability of detection for a photon can vary over time during detector activation or recharging. Thus, a detector can be activated just before the start of a gating window, but the sampling circuitry can only process detection signals output from the detector once the gating window begins. Similarly, a detector can initiate its shutdown or forced discharge after the end of the gating window, but the processing circuitry can disable input from the detector output immediately after the end of the gating window. Thus, a detector can be active for a duration longer than the gating window, but the processing circuitry can only process its output during the gating window—e.g., in response to a sampling cycle or clock cycle that is short enough to allow for the collection of multiple samples of the detector output during the gating window (e.g., sampling the detection signal at a frequency corresponding to multiple memory bins).

[0079] A detection event can be identified by the processor circuit 105′ based on one or more photon counts indicated by a detection signal output from the detector array 110, which can be stored in the memory 205. In some embodiments, the processor circuit 105′ can include a correlation circuit or correlator that identifies a detection event based on photon counts from two or more detectors (referred to herein as correlated photon counts) that are within a predefined time window (referred to herein as a correlation window or correlation time) that are correlated with each other, wherein the detection signal indicates the arrival time of the incident photons within the correlation window. Because photons corresponding to the optical signal output from the emitter array 115 (also referred to as signal photons) may arrive relatively close in time to photons corresponding to ambient light (also referred to as background photons), the correlator is configured to distinguish the signal photons based on their respective arrival times relative to each other within the correlation time. For example, such a correlator is described in U.S. Patent Application Publication No. 2019 / 0250257, entitled “Methods and Systems for High-Resolution Long-Range Flash Lidar,” which is incorporated herein by reference.

[0080] The processor circuit 105′ may be small enough to allow for a three-dimensional stacked implementation, for example, where the detector array 110 is “stacked” on top of the processor circuit 105′ (and / or other associated circuitry, such as memory 205), which is sized to fit within the area or footprint of the array 110. For example, some embodiments may implement the detector array 110 on a first substrate and the transistor array of the circuit 105 / 105′ on a second substrate, with the first and second substrates / wafers bonded in a stacked arrangement, as described, for example, in U.S. Patent Application Publication No. 2020 / 0135776, filed on October 30, 2019, and entitled “High Quantum Efficiency Geiger-Mode Avalanche Diodes Including High Sensitivity Photon Mixing Structures and Arrays Thereof,” the disclosure of which is incorporated herein by reference.

[0081] The pixel processor implemented by the processor circuit 105' is configured to calculate an estimate of the average ToF aggregated over thousands of laser pulses 130 and photon returns in the reflected light 135. The processor circuit 105' can be configured to count incident photons in the reflected light 135 to identify a detection event (e.g., based on one or more SPADs 110 having been triggered) over a laser cycle (or a portion thereof). The timing and duration of the detection window can be determined by a strobe signal (Strobe#x or Strobe#x) as described herein. <x>) control. Many duplicate Strobe <x>are aggregated (e.g., in pixels) to define the <x>Subframes of the image frame may be selected, where subframes 1 to x define an image frame. Each subframe may correspond to a respective distance subrange of the overall imaging distance range, where the frequency of the laser cycles may be selected based on the desired imaging distance range.

[0082] In some embodiments, the detector pixel may include circuitry implementing a memory array (eg, memory 205 ) and a memory controller (eg, control circuitry 105 / processor 105 ′) such as a DRAM controller, collectively referred to herein as memory circuitry. Figure 3 An example configuration of a memory circuit for implementing a memory pixel 300 (eg, a DRAM-based pixel) according to some embodiments of the present disclosure is illustrated. In particular, Figure 3 The memory pixel 300 may represent a lower or bottom layer of a pixel layout, for example, upon which an array of detector pixels 110 may be stacked to define a three-dimensional stacked implementation. Figure 3 The memory pixel 300 may be sized to fit within the area or footprint of the detector array 110 .

[0083] Figure 3 The memory pixel 300 includes: a photodetector interface circuit 310, which is configured to receive detection signals from one or more photodetectors (e.g., SPADs); a sampler circuit 302 (illustrated as a sampler) configured to sample the detection signals output from the photodetectors; a main memory device 303, which is configured to store histogram data (illustrated as an n×k DRAM device, where n refers to the number of histogram bins and k refers to the number of bits per bin); and a controller circuit 305 (illustrated as an arithmetic logic unit (ALU) and a PRMW controller) configured to manage the operation of the interface circuit 310, the sampler 302, and the main memory device 303 to store and integrate data indicated by the detection signals output from the photodetectors into the histogram data.

[0084] In some embodiments, main memory device 300 may be implemented using volatile memory (such as DRAM), which may require refresh operations to retain the data stored therein. The refresh rate of the DRAM cells is controlled by controller circuit 305. In some embodiments, the refresh rate is selected so that the memory refresh operation for all DRAM cells in array 303 can be completed within the time between pulses (or period T) of the lidar transmitter signal. The time between transmitter pulses (which defines the laser cycle, or more generally, the transmitter pulse frequency) can be selected or otherwise correspond to the desired imaging range of the lidar system. For example, in some embodiments, the refresh rate may be once per laser cycle or period Tlaser. In some embodiments, the refresh rate may be less than the laser repetition rate or period Tlaser. In some embodiments, the refresh rate may be equal to the laser repetition rate. In some embodiments, the refresh rate may be some integer multiple R of the laser repetition rate, where for 1 of the R laser cycles, the system can read, modify, and write to all bins, and for the other R-1 cycles, the system will read, modify, and write to a bin only if a photon is present during the bin time. The value of R can be adjusted by the timing system to save power, or as a function of temperature (where more frequent refresh operations may be required at higher temperatures).

[0085] Figure 4A An example memory device implementing an n×k bit DRAM array 303a using gain cell DRAMs in a 3T configuration according to some embodiments of the present disclosure is illustrated. While some embodiments are described herein with reference to NMOS gain cell DRAM configurations, it will be understood that PMOS gain cell DRAM configurations may similarly be used in accordance with the present invention.

[0086] like Figure 4A As shown in FIG, each DRAM cell 400a (0 to k-1) of a bin (0 to n-1) includes three transistors 401, 402, 403. The first and second transistors 401 and 402 are connected in series to an output line or bit line b. o <0:k-1>, and the third transistor 403 is connected to the input line b i <0:k-1> and the gate of the first transistor 401, which acts as a storage node. The read signal Rd<0:n-1> provides a control signal to the gate of the second transistor 402, and the write signal Wr<0:n-1> provides a control signal to the gate of the third transistor 403. When data is to be read from the cell in bin (0 to n-1), the read signal Rd<0:n-1> is asserted and the corresponding bit line b is connected. o <0:k-1> read data. During the read operation, bit line b o <0:k-1> is precharged to the precharge read voltage Prechargeb. When data is to be written, the write signal Wr<0:n-1> is asserted and comes from the input line b. i The data of <0:k-1> is stored in the corresponding DRAM cell 400a. This logic state is maintained through the cyclic refresh operation until a new write operation is initiated.

[0087] Figure 4B FIG. 4 illustrates an example memory device implementing an n×k bit DRAM array 303 b using a 1T1C DRAM cell 400 b according to some embodiments of the present disclosure. Figure 4B As shown in , each DRAM cell (0 to k-1) of a bin (0 to n-1) includes a single transistor 407 (which acts as an access transistor) and a single capacitor 404 (which acts as a storage node), where sense amplifier hardware 406 increments or refreshes the value stored on capacitor 404.

[0088] Each increment and refresh operation for the DRAM-based pixels described herein may include a precharge-read-modify-write (PRMW) operation in which the current contents of a given memory bin 0 to n-1 are read, incremented, or refreshed (depending on the presence or absence of a detection event), and written back to the corresponding memory bin. The retention time of the voltage on the storage node may determine the maximum refresh period required to maintain the stored logic state of each DRAM cell 400a, 400b. In some embodiments, the time to complete the refresh operation may be such that each DRAM cell 400a, 400b of the memory array 303 may be refreshed in the time between pulses of the lidar transmitter signal; however, it will be understood that the period or frequency at which the refresh operations are performed depends on the leakage of the DRAM cells 400a, 400b (also referred to herein as retention time), which may vary, for example, with temperature. Figure 9 An example simulation illustrating leakage as a function of temperature is shown in the graph of FIG, where leakage (indicated by a drop in the memory voltage) occurs faster with increasing temperature (shown by the plotted line). As such, while this document primarily describes a refresh operation being performed once per cycle Tlaser of the emitter signal, it will be understood that in some embodiments, refresh operations may be performed more or less frequently (e.g., once every two cycles (2Tlaser) of the emitter signal), or otherwise as needed to meet the leakage requirements of the DRAM cell under operating conditions.

[0089] Figure 5A 1 illustrates an example circuit 500a configured to perform increment and refresh operations according to some embodiments of the present disclosure. In particular, Figure 5A An example embodiment is illustrated that includes a k-bit linear feedback shift register (LFSR) PRMW and refresh logic circuitry 500a configured to execute a program for detecting the presence or absence of an event during an activation window of a detector pixel in an emitter cycle (e.g., during the time between pulses of an emitter signal). Figure 4A FIG. 3 shows an increment or refresh operation of an example row or bin (shown as row i) of the DRAM array 303 a. An LFSR is a shift register whose input bits are a linear function of their previous state.

[0090] like Figure 5A As shown in , in an increment operation, a signal increment is asserted in response to the presence of a detection event (e.g., when the output of a detector pixel is "high"), and the bit stored in the DRAM cell 400a of a memory bin (shown as bin or row i) is shifted forward one bit using an XNOR (or exclusive OR) LFSR loop feedback. In particular, in Figure 5A In the circuit, the input bit to the leftmost DRAM cell 400a (eg, the least significant bit of bin i) is connected by bit line b. o <fb1> 、b o <fb2>The value on one or more of the bits and the most significant bit line b o <k-1>The value stored in each DRAM cell 400a is therefore shifted to the DRAM cell 400a to its right in response to the increment signal. In a refresh operation, in response to the absence of a detection event (e.g., when the output of the detector pixel is "low"), the refresh signal is asserted, and the bit stored in each DRAM cell 400a of the memory bin is fed back to its own input. That is, for j = 1 to the number of strobe cycles (e.g., the strobe window Strobe <x>cycles or repetitions), and for bins i = 0 to n-1 (in order), if a detection event (e.g., an incident photon) is identified or present in cycle j, the value stored in the appropriate bin i (corresponding to the arrival time during the gating window) is incremented. If a detection event is not identified or present in cycle j, the value stored in bin i may be refreshed (for higher refresh rates, i.e., where a refresh operation is performed every R (≤1) cycles), or no action may be taken for that cycle j (for lower refresh rates, i.e., where a refresh operation is performed every R (>1) cycles).

[0091] Figure 5B 1 illustrates an example circuit 500b configured to perform increment and refresh operations according to some embodiments of the present disclosure. In particular, Figure 5B An example embodiment is illustrated that includes an adder-based pixel that receives input from an array of N detector elements 510 (eg, SPADs). Figure 5B The embodiment includes a logic implementation of a sampler circuit 502 (shown as an edge sampler), a parallel counter circuit 504 (shown as a parallel counter), a latch circuit 506 (shown as k latches), and an adder circuit 507 (shown as a k-bit adder), which is configured to perform a Figure 4A An example row or bin (shown as row i) of the DRAM array 303a is incremented or refreshed. Figure 5B In the example of FIG, in the gating cycle j, for bin i = 0 to n-1, N SPADs 510 are sampled at each bin time. In each bin time, the CorrQ<N-1:0> The states (output from sampler 502) are summed to produce the sum word S<log2(N)-1:0> To determine the number of SPADs 510 that have been excited (by SPAD<N-1:0> This sum is then compared with the b from bin i of the DRAM array. o <k-1:0> The words read in are added to generate the updated histogram word sum<k-1:0> , which is written back into DRAM word I (ie, row i) by the tri-state write driver under the control of the Wr signal.

[0092] Figure 6 An example timing diagram 600 is illustrated for precharge, read, modify (eg, increment or refresh), and write operations for performing increment and refresh operations according to some embodiments of the present disclosure. Figure 6 As shown in FIG, the precharge signal Prechargeb is applied to the output line b o <0:k-1>. Then, the read line Rd<0:n-1> is enabled in response to the signal Rd transitioning to a "high" state, and the data is read. Then, the write line Wr<0:n-1> is enabled in response to the signal Wr transitioning to a "high" state, and the cell is incremented or refreshed. The precharge, read, increment / refresh, and write operations can be completed in sufficient time to prevent leakage of the stored value in each memory cell. Figure 6 In the example of laser Multiple increment or refresh operations are performed within a transmitter cycle of approximately 1000 ms (e.g., on the order of microseconds or nanoseconds, corresponding to an imaging distance range of approximately 400 meters), where each precharge, read, increment / refresh, and write operation is performed at time T integrate Therefore, the number of increment or refresh operations can be expressed as T laser / T integrate .exist Figure 6 In the example of , for an embodiment where the corresponding gating window is measured in the time between each pulse of the transmitter signal, approximately hundreds of DRAM cells may be incremented or refreshed for each gating window.

[0093] Figure 7 1 and 2 illustrate example sampling circuits 702 and increment / refresh circuits 712 according to some embodiments of the present disclosure. Figure 7 As shown in FIG, the sampler circuit 702 includes a configuration of logic circuits 708 (illustrated as D flip-flops) configured to determine whether at least one detection event has occurred during a clock cycle Gclk (e.g., based on a detection signal output from a SPAD indicating detection of a photon). If a detection event has occurred (e.g., the detection signal "photon" is "high"), the increment / refresh circuit 712 responds to the signal Wr ( Figure 6 ) turns to a "high" state and outputs an incrementing signal, the LFSR circuit (for example, Figure 5A The circuit 500a shown in FIG. 5 is forward clocked to perform an increment operation. If no detection event occurs (e.g., the detection signal "photon" is "low"), the increment / refresh circuit 712 outputs a refresh signal in response to the signal Wr transitioning to a "high" state, and the LFSR circuit is backward clocked to perform a refresh operation.

[0094] Figure 8 illustrates an example timing diagram 800 for generating signals for asserting or enabling (for bins i=0 to n-1) a write signal Wr (implemented by logic circuits 812w and 812r, respectively) according to some embodiments of the present disclosure. and read signal Rd To perform incremental and refresh operations. Figure 8 As shown in the example, for a single-photon detector array, the time between pulses of the emitter signal (laser) (or period T laser ), the DRAM cell storing the corresponding bit of each memory bin i can be accessed and either incremented or refreshed (during Figure 8 That is, the number of bins of the array that can be refreshed in a cycle (and the number of bits per bin) may be limited by the time between pulses of the transmitter signal. In some embodiments, an LFSR circuit (such as Figure 5A The circuit 500a shown in FIG. 5 can be used to reduce or minimize the time required for each increment / refresh operation due to its deterministic operation (where each current value is determined by its previous state). Reducing the time required for each increment / refresh operation can allow more increment / refresh operations to be performed (e.g., within the time between pulses of the transmitter signal), thereby increasing the total number of DRAM bits that can be stored (assuming sufficient surface area is available for the DRAM array).

[0095] Still refer to Figure 8 In some embodiments, the increment or refresh operation can be performed sequentially for each row / bin 0 to n-1, with readout performed in a rolling shutter scheme. Figure 8 In the example, there may be z access operations performed between pulses of the transmitter signal laser. <0> To Access <z-1>) (As noted in the above example, it may have T laser Each access operation Access May need T integrate (T laser / z access operation) and may include the duration of the Figure 6 The precharge, read, increment / refresh, and write operations discussed. In some embodiments (e.g., using Figure 5A LFSR 500a shown in FIG), for each access operation Access The duration of can be independent of the bit depth, since read and write operations can be performed in parallel. In other embodiments (e.g., using a binary ALU with a serial carry chain), for each access operation Access The duration of may vary based on the bit depth (the duration may increase with the number of bits k per bin n, e.g., due to a larger number of gates to stabilize).

[0096] As such, some embodiments described herein may allow for operation over a temperature range of approximately -40 degrees Celsius to approximately +125 degrees Celsius based on a period T of each memory cell. laser Similar leakage or holdover times (e.g., for a 400 m laser system) for each transmitter cycle up to T laser / T integrate The increment / refresh operation is performed with 2.6 Mbps, providing more than enough resolution for ToF estimation. However, as noted above, if the leakage or retention time of the memory cells is greater, the frequency of the refresh operation can be reduced (e.g., for a 2.6 Mbps memory cell with 2.6 Mbps). Leakage or hold time of the memory cell, 334 bins can be refreshed once every 2 laser cycles, or 668 bins can be used). That is, the hold time can be highly process dependent and if the hold time is longer than the laser period T laser , then the refresh operation can be performed less frequently to save power.

[0097] In some embodiments, the refresh operation described herein can be performed once per laser cycle, for example, because the retention time of the memory cell can be similar to the period Tlaser even at higher temperatures. For example, the refresh operation can be implemented by performing an increment operation (e.g., once per laser cycle) and then subtracting a known number of laser cycles from the LFSR code, for example, at the end of an exposure. The laser cycles or period Tlaser can be selected to correspond to a maximum or other desired LIDAR imaging distance range.

[0098] Some advantages of embodiments of the present disclosure may include a more compact layout (e.g., by using only a single type of transistor (e.g., NMOS transistor, no N-well)) and lower bitline capacitance (e.g., one drain diffusion per cell because only one transistor per cell can be coupled to the bitline), which may allow for lower power requirements and faster PRMW cycles (e.g., the number of access lines to DRAM is halved compared to SRAM, which may require a pair of bitlines). In addition, for iToF with a high bit depth (e.g., 18 bits), for example, for short-range applications (e.g., indoor applications with a range of approximately 3 m or less), smaller pixel implementations (e.g., having one or more dimensions less than 10 mm) with fewer bins (e.g., 4 bins) may be possible. Due to the shorter ranging distance (and therefore the smaller period of the transmitter signal), such indoor or other short-range applications may require that the increment / refresh operations described herein be completed in shorter time durations and / or at higher frequencies. Some embodiments may allow for short-range direct ToF pixels with a small pixel pitch in the same area as iToF pixels. Furthermore, the lower drive capacitance of Rd and Wr at digital Vdd allows for lower-power, higher-frequency (e.g., on the order of hundreds of MHz) global drive of bin clocks (Gclk). For example, indoor short-range ToF systems may require higher-frequency global Gclk clocks, but the loading of those Gclk clocks needs to be kept low to achieve such frequencies with low power consumption across large arrays. DRAM can provide this capability, as only a single transistor is driven by Rd ​​or Wr. Indoor ToF systems may have lower power requirements because they are typically battery-powered and portable.

[0099] While some embodiments of the present disclosure may require a custom (not existing fab supported) gain cell DRAM layout, the use of a single transistor type (e.g., only NMOS) may allow for a more compact implementation compared to an SRAM cell layout (e.g., due to the absence of PMOS transistors). Embodiments of the present disclosure may utilize sequential or rolling shutter type readout (where a row or bin is read out at a time) such that increment or refresh operations may continue during read operations that may require a time duration greater than the hold time of the storage node (e.g., on the order of milliseconds). The refresh rate in the embodiments described herein is selected to be sufficient to ensure that the DRAM cell does not leak and may depend on operating conditions (e.g., operating temperature). As noted above, in embodiments where one refresh operation is performed per emitter cycle, up to approximately 2.667 The refresh time may be sufficient for operating temperatures up to about 125° C. Furthermore, the embodiments described herein may involve off-chip decoding of the LFSR code into binary (e.g., using a lookup table and associated software operations), which may require overhead in terms of additional power and / or device area.

[0100] Additional embodiments of memory structures (such as DRAM structures) that can be used in memory devices as described herein may include, but are not limited to, the following. In some embodiments, the optical isolation structures between the detector elements (e.g., SPADs) are implemented as deep trench isolation. In some embodiments, the memory structure is located on a separate wafer from the detector elements of the detector array, and the detector array and memory structure on the separate wafer are then electrically interconnected, for example using intra-pixel bump bonding.

[0101] In some embodiments, the memory structure is implemented as a trench capacitor, as in Figure 10 In particular, Figure 10 An implementation of an n×k DRAM array 1003 is illustrated, including access transistors 1001 and storage capacitor structures 1004 in a substrate 1000. Storage capacitor structures 1004 include a conductive layer 1004c (e.g., polysilicon) and a dielectric layer 1004d in trenches 1004d between access transistors 1001. In some embodiments, the DRAM structure is formed by creating trench capacitors and ensuring that those capacitors are sufficiently optically isolated from their surroundings, such as by depositing a sufficiently opaque coating on the sides of the DRAM structure.

[0102] In some embodiments, the memory structure is formed on the detector wafer, such that the memory device and the detector are natively located on the same wafer or substrate. In some embodiments, the DRAM structure also forms an optical and / or electrical barrier between the SPAD structures (e.g., when implemented as a trench capacitor), thereby reducing the die area by using the DRAM structure as both a memory structure and an optical barrier to photons (such as those generated by hot carrier recombination), thereby potentially reducing optical crosstalk effects. Other variations of gain-cell DRAM structures that can be used in accordance with embodiments of the present disclosure may include those described in the publication "Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip" by P. Meinerzhagen et al. (Basel, Switzerland: Springer, 2018), the disclosure of which is incorporated herein by reference.

[0103] The lidar systems and arrays described herein can be applied to ADAS (advanced driver assistance systems), autonomous vehicles, UAVs (unmanned aerial vehicles), industrial automation, robotics, biometrics, modeling, augmented and virtual reality, 3D mapping, and security. In some embodiments, the emitter elements of the emitter array can be vertical cavity surface emitting lasers (VCSELs). In some embodiments, the emitter array can include a non-native substrate having thousands of discrete emitter elements electrically connected in series and / or parallel thereon, wherein the drive circuitry is implemented by driver transistors integrated on the non-native substrate adjacent to corresponding rows and / or columns of the emitter array, as described, for example, in U.S. Patent Application Publication No. 2018 / 0301872 filed by Burroughs et al. with the U.S. Patent and Trademark Office on April 12, 2018, the disclosure of which is incorporated herein by reference.

[0104] Various embodiments have been described herein with reference to the accompanying drawings in which example embodiments are shown. However, these embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete and to fully convey the concepts of the present invention to those skilled in the art. Various modifications to the example embodiments and the general principles and features described herein will be readily apparent. In the accompanying drawings, the sizes and relative sizes of layers and regions are not shown to scale and may be exaggerated in some instances for clarity.

[0105] The example embodiments are described primarily in terms of the specific methods and devices provided in a particular implementation. However, the methods and devices may operate effectively in other implementations. Phrases such as "example embodiment," "one embodiment," and "another embodiment" may refer to the same or different embodiments, as well as to multiple embodiments. The embodiments will be described with respect to systems and / or devices having certain components. However, the systems and / or devices may include fewer or additional components than shown, and variations in the arrangement and types of components may be made without departing from the scope of the inventive concept.

[0106] The example embodiments may be described in the context of a particular method having specific steps or operations. However, the methods and apparatus may operate effectively with other methods having different and / or additional steps / operations, as well as steps / operations in a different order, without conflicting with the example embodiments. Therefore, the inventive concept is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.

[0107] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the exemplary embodiments. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that, as used herein, the terms "include" or "comprise" are open ended and include one or more stated elements, steps, and / or functions without excluding one or more unstated elements, steps, and / or functions. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0108] It will be understood that although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the scope of the present invention, the first element discussed below can be referred to as the second element.

[0109] It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0110] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0111] This document, in conjunction with the above description and accompanying drawings, discloses many different embodiments. It will be understood that literally describing and illustrating every combination and subcombination of these embodiments would be unduly repetitive and obfuscating. Therefore, this specification, including the accompanying drawings, should be construed as constituting a complete written description of all combinations and subcombinations of the embodiments described herein, as well as the manner and process of making and using them, and should support claims to any such combination or subcombination.

[0112] In the drawings and specification, there have been disclosed embodiments of the disclosure, and although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims. < / x> < / fb1> < / x> < / x> < / x> < / x>

Claims

1. A light detection and ranging (LIDAR) detector circuit comprising: a memory device comprising a non-transitory storage medium configured to store the histogram data in respective memory bins; and At least one control circuit configured to: receiving a detection signal from one or more photodetector elements; performing a first memory operation to update histogram data in a corresponding memory bin in response to a detection signal indicating the presence of a detection event during a portion of time between pulses of an emitter signal output from the LIDAR emitter element, wherein the first memory operation comprises an increment operation; and performing a second memory operation to update the histogram data in the corresponding memory bin in response to the detection signal indicating an absence of a detection event during the portion of time between pulses of the transmitter signal, wherein the second memory operation comprises a refresh operation, and Increment operations or refresh operations for updating the histogram data stored in corresponding memory bins of the memory device are completed during the time between pulses of the transmitter signal.

2. The LIDAR detector circuit of claim 1 , wherein: The at least one control circuit is configured to perform a refresh operation at a frequency greater than or less than a pulse frequency of the transmitter signal, optionally wherein the frequency of the refresh operation is temperature dependent.

3. The LIDAR detector circuit of claim 1 , wherein: The at least one control circuit includes a logic-based counter circuit configured to perform an increment operation or a refresh operation.

4. The LIDAR detector circuit of claim 3, wherein: The counter circuit includes a plurality of adder circuits connected in series.

5. The LIDAR detector circuit of claim 3, wherein: The counter circuit includes a linear feedback shift register configured to perform an incrementing operation by shifting bits stored in corresponding memory bins forward using a linear feedback loop.

6. The LIDAR detector circuit of claim 5, wherein: The linear feedback shift register is configured to perform a refresh operation by feeding back bits stored in corresponding memory bins to at least one of its inputs.

7. The LIDAR detector circuit of claim 1 , wherein: The increment or refresh operations are performed sequentially for the corresponding memory bins.

8. The LIDAR detector circuit of claim 7, wherein: The memory device is a memory array comprising corresponding rows or columns of dynamic random access memory (DRAM) cells defining corresponding memory bins, and wherein at least one control circuit is further configured to output a read signal in response to read signals sequentially applied to the corresponding rows or columns.

9. The LIDAR detector circuit of claim 8, wherein: The memory device and the one or more photodetector elements include a DRAM cell and a plurality of photodetector elements that are natively located on the same die or provided on respective dies and electrically connected to each other.

10. The LIDAR detector circuit of claim 8, wherein: The DRAM cells are provided in respective trenches between the photodetector elements and define optical and / or electrical barriers between adjacent ones of the photodetector elements.

11. The LIDAR detector circuit of claim 8, wherein: The readout signal comprises a count signal and / or a time-integrated signal, and wherein the at least one control circuit is configured to calculate an estimated arrival time of a photon incident on the photodetector element based on the readout signal.

12. A LIDAR detector circuit according to any preceding claim, wherein: The portion of time between pulses of the transmitter signal corresponds to a respective distance sub-range, and wherein the respective memory bin includes histogram data corresponding to the respective distance sub-range.

13. The LIDAR detector circuit of claim 12, wherein: The photodetector elements include single photon avalanche detectors (SPADs), and wherein the histogram data includes photon counts indicated by detection signals corresponding to respective distance sub-ranges.

14. The LIDAR detector circuit according to any one of claims 1 to 11, wherein: The at least one control circuit is configured to transmit respective gating signals that activate one or more photodetector elements for respective detection windows that are differently delayed between pulses of the emitter signal.

15. The LIDAR detector circuit of claim 14, wherein: The respective detection windows correspond to respective distance sub-ranges, and wherein the at least one control circuit is configured to transmit respective gating signals to activate the one or more photodetector elements to sequentially cycle through the respective distance sub-ranges.

16. A light detection and ranging (LIDAR) detector circuit comprising: one or more photodetector elements defining a LIDAR detector pixel; a memory device comprising a non-transitory storage medium configured to store data in respective memory bins, wherein the memory bins comprise dynamic random access memory (DRAM) cells; and at least one processor circuit configured to receive a detection signal from the one or more photodetector elements, identify an absence of a detection event indicated by the detection signal during a portion of time between pulses of an emitter signal output from the LIDAR emitter element, and, in response to identifying the absence of the detection event, perform a memory operation to update data in a corresponding memory bin, Therein, the DRAM cells are provided in corresponding trenches between the photodetector elements and define optical and / or electrical barriers between adjacent ones of the photodetector elements.

17. The LIDAR detector circuit of claim 16, wherein: The memory operation is a refresh operation, and wherein the at least one processor circuit is further configured to identify the presence of a detection event indicated by the detection signal during the portion of time between pulses of the transmitter signal, and in response to the identification of the presence of the detection event, perform an increment operation to update data in the corresponding memory bin.

18. The LIDAR detector circuit of claim 17, wherein: The at least one processor circuit is configured to perform a refresh operation at a frequency that is greater than or less than a transmitter signal pulse frequency, optionally wherein the frequency of the refresh operation is temperature dependent.

19. The LIDAR detector circuit of claim 18, wherein: The at least one processor circuit includes a linear feedback shift register configured to perform an increment operation by shifting bits stored in a corresponding memory bin forward using a linear feedback loop, and configured to perform a refresh operation by feeding back bits stored in the corresponding memory bin to at least one of its inputs.

20. The LIDAR detector circuit of claim 17, wherein: Increment operations or refresh operations for updating data stored in corresponding memory bins of the memory device are completed during the time between pulses of the transmitter signal.

21. The LIDAR detector circuit of claim 17, wherein: The portion of time between pulses of the emitter signal corresponds to a corresponding distance sub-range, the corresponding memory bin includes histogram data corresponding to the corresponding distance sub-range, the histogram data includes photon counts indicated by the detection signal, and the memory device includes dynamic random access memory DRAM cells, which define the corresponding memory bin.

22. A method of operating a light detection and ranging (LIDAR) detector circuit, the method comprising: receiving a detection signal from one or more photodetector elements; identifying the presence or absence of a detection event indicated by the detection signal during a portion of time between pulses of an emitter signal output from the LIDAR emitter element; and In response to identifying the presence or absence of a detection event, respectively, one of a first memory operation or a second memory operation is performed to update histogram data stored in a corresponding memory bin of a memory device including a non-transitory storage medium, wherein the first memory operation includes an increment operation and wherein the second memory operation includes a refresh operation, and within a time between transmitter signal pulses, one of the increment operation or the refresh operation is completed to update the histogram data stored in the corresponding memory bin of the memory device.

23. The method according to claim 22, wherein Performing the refresh operation includes performing the refresh operation at a frequency greater than or less than a frequency of the transmitter signal pulses, and wherein the frequency of the refresh operation is temperature dependent.

24. The method according to claim 22, wherein Performing an increment operation includes shifting the bits stored in the corresponding memory bin forward using a linear feedback loop of a linear feedback shift register.

25. The method according to claim 24, wherein Performing a refresh operation includes feeding back the bits stored in the corresponding memory bins to at least one input of the linear feedback shift register.

26. A LIDAR system comprising the detector circuit of claim 1, wherein: The LIDAR system is configured to be coupled to an autonomous vehicle such that the LIDAR transmitter element and the one or more photodetector elements are oriented relative to an intended direction of travel of the autonomous vehicle.

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