Display panel and electronic device

Abstract

The display panel and the electronic equipment provided by the embodiment relate to the technical field of display. In the region corresponding to the anode block, the fourth metal layer forms signal lines, and the orthographic projection of the signal lines on the substrate layer is axially symmetrically distributed relative to the symmetry axis of the orthographic projection of the anode block on the substrate layer, and at least one signal line in the fourth metal layer is connected with a signal line in the first metal layer, the second metal layer or the third metal layer. The above design can make the anode block more flat, and improve the color deviation of the display panel on the opposite side caused by the uneven anode block, on the one hand, by axially symmetrically distributing the signal lines formed by the fourth metal layer relative to the symmetry axis of the orthographic projection of the anode block on the substrate layer. On the other hand, the signal line in the fourth metal layer is connected with the signal line of the other layer, which can increase the area of the signal line, reduce the resistance of the signal line, reduce the loss of the signal in the transmission process, and reduce the influence of the signal transmission distortion on the display effect.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and an electronic device. BACKGROUND

[0002] When a display panel (such as an OLED display panel) is tested for color deviation, the color deviation test for each side (upper side, lower side, left side or right side) of the display panel can pass, but the color deviation test for the opposite two sides (such as upper and lower sides or left and right sides) is difficult to pass. Therefore, how to improve the color deviation of the opposite two sides of the display panel to improve the display effect of the display panel is a technical problem that needs to be solved by those skilled in the art. SUMMARY

[0003] In order to overcome the technical problems mentioned in the above technical background, the embodiments of the present application provide a substrate and a display panel.

[0004] In a first aspect, the present application provides a display panel, comprising:

[0005] an array driving layer and a pixel device layer which are stacked;

[0006] The pixel device layer comprises anode blocks which are arranged in an array;

[0007] The array driving layer comprises a substrate layer, and a first metal layer, a second metal layer, a third metal layer and a fourth metal layer which are stacked on the substrate layer in sequence and used to form signal lines;

[0008] In the region corresponding to the anode block, the signal lines formed by the fourth metal layer are axially symmetrically distributed on the substrate layer with respect to the symmetry axis of the anode block projected on the substrate layer, and at least one signal line in the fourth metal layer is connected with the signal line in the first metal layer, the second metal layer or the third metal layer.

[0009] In a possible embodiment of the present application, the signal lines in the fourth metal layer comprise a first signal line, a second signal line and a third signal line, and the first metal layer, the second metal layer or the third metal layer comprises a fourth signal line connected with the first signal line;

[0010] The first signal line and the fourth signal line extend along the symmetry axis of the anode block projected on the substrate layer, and the symmetry axis of the first signal line projected on the substrate layer and the symmetry axis of the fourth signal line projected on the substrate layer both coincide with the symmetry axis of the anode block projected on the substrate layer;

[0011] A projection of the second signal line on the substrate layer is located within a projection of the anode block on the substrate layer;

[0012] A portion of a projection of the third signal line on the substrate layer that overlaps with a projection of the anode block on the substrate layer is distributed in axial symmetry with respect to an axis of symmetry of a projection of the second signal line on the substrate layer with respect to a projection of the anode block on the substrate layer.

[0013] The second signal line is connected to the fourth signal line.

[0014] In a possible embodiment of the present application, a projection of the first signal line on the substrate layer does not overlap with a projection of the anode block on the substrate layer.

[0015] A projection of the fourth signal line on the substrate layer overlaps with a projection of the anode block on the substrate layer.

[0016] In a possible embodiment of the present application, a projection of the first signal line on the substrate layer overlaps with a projection of the anode block on the substrate layer.

[0017] A projection of the fourth signal line on the substrate layer overlaps with a projection of the anode block on the substrate layer.

[0018] A projection of the first signal line on the substrate layer overlaps with a projection of the fourth signal line on the substrate layer.

[0019] In a possible embodiment of the present application, the display panel further includes a first signal line block disposed in the same layer as the fourth signal line.

[0020] The first signal line block is located on a side of the fourth signal line facing the second signal line, and the first signal line block is connected to the fourth signal line.

[0021] The second signal line is connected to the fourth signal line through the first signal line block.

[0022] Preferably, the fourth signal line and the first signal line block are in an integral structure.

[0023] In a possible embodiment of the present application, a projection of a side of the first signal line block away from the fourth signal line on the substrate layer is flush with a projection of a side of the second signal line away from the fourth signal line on the substrate layer.

[0024] The length of the first signal trace block along the fourth signal trace extension direction is equal to the length of the second signal trace along the fourth signal trace extension direction.

[0025] In a possible embodiment of the present application, the display panel further includes a second signal trace block disposed in the same layer as the fourth signal trace;

[0026] The second signal trace block is symmetrically distributed with the first signal trace block about the fourth signal trace.

[0027] In a possible embodiment of the present application, the first signal trace and the fourth signal trace are connected to a power voltage signal, and the third signal trace is connected to a data voltage signal.

[0028] The fourth signal trace is located in the third metal layer;

[0029] The display panel further includes a planarization layer located between the third metal layer and the fourth metal layer;

[0030] The first signal trace and the fourth signal trace are connected via a via on the planarization layer,

[0031] The second signal trace is connected to the first signal trace block via a via on the planarization layer.

[0032] In a possible embodiment of the present application, the third signal trace extends along the extension direction of the fourth signal trace;

[0033] The first signal trace and the fourth signal trace have the same trace width;

[0034] The first signal trace, the second signal trace, and the third signal trace have the same trace thickness.

[0035] In a second aspect of the present application, an electronic device is provided, and the electronic device includes the display panel in any possible embodiment of the first aspect.

[0036] The display panel and the electronic device provided by the embodiments of the present application are characterized in that, in the region corresponding to the anode block, the orthographic projection of the signal trace formed by the fourth metal layer on the substrate layer is distributed in axial symmetry relative to the symmetry axis of the orthographic projection of the anode block on the substrate layer, and at least one signal trace in the fourth metal layer is connected with the signal trace in the first metal layer, the second metal layer or the third metal layer. The above design can make the anode block more flat, and improve the color deviation of the display panel on the opposite side caused by the uneven anode block, on the one hand, and the signal trace in the fourth metal layer is connected with the signal trace in other layers, which can increase the area of the signal trace, reduce the resistance of the signal trace, reduce the loss of the signal in the transmission process, and reduce the influence of the signal transmission distortion on the display effect. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0038] Figure 1 A data table for testing the color deviation of the display panel on the opposite side is illustrated;

[0039] Figure 2 A schematic diagram illustrating the influence of the part of the film layer under the anode block on the flatness of the anode block is illustrated;

[0040] Figure 3 A position relationship diagram between the anode block and the signal lead of each layer of the display panel in the test is illustrated; Figure 1

[0041] Figure 4 A schematic diagram of a film layer structure of the display panel in the embodiment is illustrated;

[0042] Figure 5 A schematic diagram of the position relationship between the anode block and the signal trace in the display panel in the embodiment is illustrated;

[0043] Figure 6 A data table for testing the color deviation of the display panel on the opposite side is illustrated;

[0044] Figure 7 A schematic diagram of the position relationship between the anode block and the signal trace in the display panel in the embodiment is illustrated;

[0045] Figure 8 A position relationship diagram between the anode block and the signal lead of each layer of the display panel in the test is illustrated; Figure 7 ​A cross-sectional view along the direction of the symmetry axis L;

[0046] Figure 9 A cross-sectional view along the direction of the symmetry axis L is shown in FIG. 10B. Figure 5 A cross-sectional view along the direction of the symmetry axis L is shown in FIG. 10B.

[0047] Figure 10 A cross-sectional view along the direction of the symmetry axis L is shown in FIG. 10B.

[0048] Figure 11 A cross-sectional view along the direction of the symmetry axis L is shown in FIG. 10B. Figure 10 A cross-sectional view along the direction of the symmetry axis L is shown in FIG. 10B.

[0049] Figure 12 A cross-sectional view along the direction of the symmetry axis L is shown in FIG. 10B. Figure 10 A cross-sectional view along the direction of the symmetry axis L is shown in FIG. 10B.

[0050] Figure 13 A cross-sectional view along the direction of the symmetry axis L is shown in FIG. 10B.

[0051] Figure 14 A cross-sectional view along the direction of the symmetry axis L is shown in FIG. 10B. Figure 13 A cross-sectional view along the direction of the symmetry axis L is shown in FIG. 10B.

[0052] FIG. 10: a display panel; 110: an array driving layer; 1101: a substrate layer; 120: a display device layer; 121: an anode block; 1001: an insulating layer; 102: a planarization layer; 1021: a first planarization layer; 1022: a second planarization layer; 1301: a first signal line; 1302: a second signal line; 1303: a third signal line; 1304: a fourth signal line; 1401: a first signal line block; 1402: a second signal line block. DETAILED DESCRIPTION

[0053] In order to make the objectives, technical solutions, and superiorities of the embodiments of the present application clearer, the following will be a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations.

[0054] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0055] It should be noted that similar reference numerals and letters refer to like items throughout the accompanying drawings, and once an item is defined in one drawing, it is not necessary to further define and explain it in the subsequent drawings.

[0056] In the description of the present application, it should be noted that the terms "upper", "lower" and the like indicate the orientation or positional relationship shown in the drawings, or the orientation or positional relationship commonly used when the product of the present application is used, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second" and the like are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0057] It should be noted that the different features in the embodiments of the present application can be combined with each other without conflict.

[0058] Please refer to Figure 1 , Figure 1 The data table for testing the color deviation of the opposite side of the existing display panel is shown, where JNCD(|L-R|) represents the color deviation of the left and right sides of the display panel, JNCD(|T-B|) represents the color deviation of the top and bottom sides of the display panel, 0.5JNCD represents that the color deviation required by the display panel is less than 0.5, 1.0JNCD represents that the color deviation required by the display panel is less than 1.0, and 1.5JNCD represents that the color deviation required by the display panel is less than 1.5. It can be seen that Figure 1 only when the observation angle is large (such as 60°) and the color deviation required by the display panel is less than 1.5, the test can be passed. As can be seen, the color deviation of the opposite side of the existing display panel is difficult to meet the requirement of the display panel for low color deviation.

[0059] The inventors found through analysis that the main reason why the color deviation of the opposite side cannot meet the requirement of the display panel for color deviation is that the light-emitting angles of the pixel light-emitting units located on the opposite sides are different, for example, the light-emitting angle of the pixel light-emitting unit located on one side is A degrees (such as 40 degrees), and the light-emitting angle of the pixel light-emitting unit located on the other side is B degrees (such as 45 degrees), which will cause a relatively obvious color deviation when observing the opposite side at different observation angles. Based on this, the inventors found through disassembling analysis of the structure of the existing display panel that one of the main reasons why the light-emitting angles of the pixel light-emitting units on the opposite sides are different is that the flatness of the anode block in the pixel light-emitting unit is poor, where the flatness can be represented by the angle between the surface of the anode block and the horizontal plane. The larger the angle between the surface of the anode block and the horizontal plane, the poorer the flatness, and vice versa.

[0060] Further, please refer to Figure 2 ,Figure 2 A schematic diagram of the influence of the partial film layer below the anode block 121 on the flatness of the anode block 121 is shown. As shown, the partial film layer can include the insulating layer 1001, the third metal layer M3, the first planarization layer 1021, the fourth metal layer M4, and the second planarization layer 1022 arranged in layers. Because the first planarization layer 1021 and the second planarization layer 1022 exist above the third metal layer M3, the thickness of the two planarization layers can offset the influence of the uneven third metal layer M3 on the flatness of the anode block 121; and because only the second planarization layer 1022 exists above the fourth metal layer M4, the flatness of the anode block 121 is mainly influenced by the underlying fourth metal layer M4.

[0061] Please refer to Figure 3 , Figure 3 A schematic diagram of a possible film layer structure of the display panel is shown. In addition to the third metal layer M3 and the fourth metal layer M4 shown in Figure 2 , the display panel 10 can also include a first metal layer M1 and a second metal layer M2. The first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 can be used to form various layers of signal leads. Please refer to Figure 4 , Figure 4 A position relationship diagram of the anode block 121 of the display panel 10 and various layers of signal leads in Figure 1 is shown. The scan signal leads S1 and S2 can be formed using the first metal layer M1, the reset signal lead REF and the enable signal lead EM can be formed using the second metal layer M2, the power voltage signal lead (VDD) can be formed using the fourth metal layer M4 / M3, and the data voltage signal lead (DATA) can be formed using the fourth metal layer M4. In the above arrangement position diagram of the signal leads, the signal leads formed by the fourth metal layer M4 below the anode block 121 are unevenly distributed, which can cause an inclination angle between the anode block 121 formed on the signal leads formed by the fourth metal layer M4 and the horizontal plane. For example, please refer again to Figure 2 , in Figure 2 , the left side of the anode block 121 will be raised by the signal lead in the fourth metal layer M4, so that the anode block 121 as a whole is in a state of being higher on the left and lower on the right, i.e., the height d1 in the diagram is greater than the height d2.

[0062] To solve the above technical problems, the inventors have innovatively designed the following technical solutions, which will be described in detail below in combination with the accompanying drawings. It should be noted that the defects in the above prior art solutions are the result of the inventors' careful research and practice, and therefore the discovery process of the above technical problems and the solutions proposed by the present embodiment to solve the above problems should be considered as the contribution of the inventors to the present application, and should not be understood as technical content known to those skilled in the art.

[0063] Please refer to Figure 5 , Figure 5 Exemplified Figure 3 The position relationship between the anode block 121 in the display panel 10 and the signal wire is shown in the schematic diagram. The display panel 10 provided by the embodiment will be introduced below in combination with Figure 3 and Figure 5 The display panel 10 provided by the embodiment can include an array driving layer 110 and a pixel device layer 120 which are arranged in a stack. The pixel device layer 120 includes an array of anode blocks 121. Taking the pixel device layer 120 formed by RGB light-emitting pixel units as an example, the anode blocks 121 can be divided into anode blocks 121 corresponding to red light-emitting pixel units, anode blocks 121 corresponding to green light-emitting pixel units, and anode blocks 121 corresponding to blue light-emitting pixel units according to different light-emitting pixel units. The anode blocks 121 corresponding to the red light-emitting pixel units, the anode blocks 121 corresponding to the green light-emitting pixel units, and the anode blocks 121 corresponding to the blue light-emitting pixel units are arranged in an array in the pixel device layer 120. The array driving layer 110 can include a substrate layer 1101, and a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4 which are stacked on the substrate layer 1101 and used to form signal wires.

[0064] In the embodiment, in order to facilitate the description of the scheme, Figure 5 The position relationship between the anode blocks 121 corresponding to the red light-emitting pixel units and the anode blocks 121 corresponding to the blue light-emitting pixel units and the signal wires is exemplarily shown, and the introduction of the scheme of the present application is performed in combination with the accompanying drawings shown in Figure 5 It can be understood that the scheme provided by the present application is also applicable to the anode blocks 121 corresponding to the green light-emitting pixel units.

[0065] The fourth metal layer M4 is formed in the region corresponding to the anode block 121. The signal lines formed by the fourth metal layer M4 are distributed in axial symmetry with respect to the symmetry axis L of the anode block 121 on the substrate layer. At least one signal line in the fourth metal layer M4 is connected to a signal line in the first metal layer M1, the second metal layer M2, or the third metal layer M3. When a signal line in the fourth metal layer M4 is connected to a signal line in the first metal layer M1, the signal line in the fourth metal layer M4 is connected to the signal line in the first metal layer M1 through a via hole in the film layer between the fourth metal layer M4 and the first metal layer M1. When a signal line in the fourth metal layer M4 is connected to a signal line in the second metal layer M2, the signal line in the fourth metal layer M4 is connected to the signal line in the second metal layer M2 through a via hole in the film layer between the fourth metal layer M4 and the second metal layer M2. When a signal line in the fourth metal layer M4 is connected to a signal line in the third metal layer M3, the signal line in the fourth metal layer M4 is connected to the signal line in the third metal layer M3 through a via hole in the film layer between the fourth metal layer M4 and the third metal layer M3. In this embodiment, the region corresponding to the anode block 121 refers to the region where the anode block 121 is located.

[0066] In the above structure, on the one hand, the signal lines in the fourth metal layer M4 are distributed in axial symmetry with respect to the symmetry axis L of the anode block 121 on the substrate layer, which makes the anode block 121 more flat, reduces the difference in light-emitting angle of the light-emitting units on the opposite sides of the pixel caused by the non-flatness of the anode block 121, and improves the color deviation on the opposite sides of the display panel caused by the difference in light-emitting angle. Please refer to Figure 6 , Figure 6 The data table for testing the color deviation on the opposite sides of the display panel 10 is shown in this application. As shown in the table, the color deviation on the opposite sides of the display panel 10 in this embodiment is between 0.3 and 0.5, which is much smaller than the color deviation on the opposite sides of the display panel in Figure 2 . On the other hand, the signal lines formed by the fourth metal layer M4 are connected to the signal lines of other layers, which increases the area of the signal lines, reduces the resistance of the signal lines, reduces the loss of the signal in the transmission process, and reduces the influence of the signal transmission distortion on the display effect.

[0067] Further, please refer to Figure 5In the embodiment, the signal lines formed by the fourth metal layer M4 can include a first signal line 1301, a second signal line 1302, and a third signal line 1303, wherein the fourth metal layer M4, the first metal layer M1, or the second metal layer M2 forms a fourth signal line 1304 connected to the first signal line 1301. The first signal line 1301 and the fourth signal line 1304 extend along the symmetry axis L of the anode block 121 in the orthographic projection of the substrate layer, the orthographic projection of the first signal line 1301 on the substrate layer overlaps the orthographic projection of the fourth signal line 1304 on the substrate layer, and the symmetry axis of the orthographic projection of the first signal line 1301 on the substrate layer and the symmetry axis of the orthographic projection of the fourth signal line 1304 on the substrate layer can coincide with the symmetry axis L of the orthographic projection of the anode block 121 on the substrate layer.

[0068] The second signal line 1302 can be discontinuously distributed in the fourth metal layer M4, the second signal line 1302 can be located only in the region where the anode block 121 is located, and the orthographic projection of the second signal line 1302 on the substrate layer can be located within the orthographic projection of the anode block 121 on the substrate layer. The third signal line 1303 can be continuously distributed in the fourth metal layer M4 for transmitting electrical signals, and the overlapping part of the orthographic projection of the third signal line 1303 on the substrate layer and the orthographic projection of the anode block 121 on the substrate layer can be axially symmetrically distributed with the orthographic projection of the second signal line 1302 on the substrate layer relative to the symmetry axis L of the orthographic projection of the anode block 121 on the substrate layer. The second signal line 1302 can be connected to the fourth signal line 1304, for example, the second signal line 1302 can be connected to the fourth signal line 1304 through a via hole of the film layer and a signal line in the same layer as the fourth signal line 1304, and connected to the fourth signal line 1304 through the signal line in the same layer as the fourth signal line 1304. On the one hand, in the region where the anode block 121 is located, the second signal line 1302 and the third signal line 1303 are symmetrically distributed on opposite sides of the symmetry axis L of the orthographic projection of the anode block 121 on the substrate layer, and the second signal line 1302 can be used as a compensation signal line to make the anode block 121 flat. On the other hand, the second signal line 1302 can be connected to the fourth signal line 1304 to increase the area of the fourth signal line 1304 in the region where the anode block 121 is located, reduce the resistance of the fourth signal line 1304, reduce the loss of signal transmission on the fourth signal line 1304, and reduce the influence of signal transmission distortion on the display effect.

[0069] Please refer to Figure 7In one embodiment of this invention, the first signal trace 1301 can be intermittently distributed on the fourth metal layer M4. The first signal trace 1301 can be distributed in an area outside the anode block 121, meaning that the orthographic projection of the first signal trace 1301 on the substrate layer 1101 does not overlap with the orthographic projection of the anode block 121 on the substrate layer 1101. The fourth signal trace 1304 can be continuously distributed on the first metal layer M1, the second metal layer M2, or the third metal layer M3. The first signal trace 1301 and the fourth signal trace 1304 are connected through film vias between the metal layers. The orthographic projection of the fourth signal trace 1304 on the substrate layer 1101 can overlap with the orthographic projection of the anode block 121 on the substrate layer 1101. Please refer to... Figure 8 , Figure 8 Example Figure 7 A cross-sectional view along the axis of symmetry shows that, outside the anode block 121, the first signal trace 1301 and the fourth signal trace 1304 are connected through vias in the film layer. Specifically, the first signal trace 1301 can be connected to the fourth signal trace 1304 through a via in the film layer between the first signal trace 1301 and the fourth signal trace 1304 at the end near the anode block 121. For example, when the first signal trace 1301 is a signal trace in the fourth metal layer M4 and the fourth signal trace 1304 is a signal trace in the third metal layer M3, the first signal trace 1301 can be connected to the fourth signal trace 1304 through a via in the planarization layer 102 between the fourth metal layer M4 and the third metal layer M3. In this embodiment, since the first signal trace 1301 is distributed in the area outside the anode block 121, the distance between the second signal trace 1302 and the third signal trace 1303 in the area corresponding to the anode block 121 is relatively large. This ensures that the second signal trace 1302 and the third signal trace 1303 can be etched apart when the photolithography process is used to fabricate them, thus avoiding etching residue.

[0070] Please refer to this again. Figure 5 In another embodiment of this invention, the first signal trace 1301 can be continuously distributed on the fourth metal layer M4, and the first signal trace 1301 can overlap with the anode block 121, that is, the orthographic projection of the first signal trace 1301 on the substrate layer 1101 overlaps with the orthographic projection of the anode block 121 on the substrate layer 1101. The fourth signal trace 1304 can be continuously distributed on the first metal layer M1, the second metal layer M2, or the third metal layer M3. The first signal trace 1301 and the fourth signal trace 1304 are connected through film vias between the metal layers, and the orthographic projection of the fourth signal trace 1304 on the substrate layer 1101 can overlap with the orthographic projection of the anode block 121 on the substrate layer 1101. Please refer to... Figure 9 , Figure 9 Example Figure 5The cross-sectional view along the direction of the axis of symmetry shows that the first signal line 1301 and the fourth signal line 1304 are connected through the film layer via hole in the area outside the anode block 121 and the area corresponding to the anode block 121. For example, when the first signal line 1301 is a signal line in the fourth metal layer M4 and the fourth signal line 1304 is a signal line in the third metal layer M3, the first signal line 1301 can be connected with the fourth signal line 1304 through the via hole of the planarization layer 102 between the fourth metal layer M4 and the third metal layer M3 in the area outside the anode block 121 and the area corresponding to the anode block 121. The orthographic projection of the first signal line 1301 on the substrate layer 1101 can overlap with the orthographic projection of the fourth signal line 1304 on the substrate layer 1101. In this way, the first signal line 1301 and the fourth signal line 1304 can be directly connected through the film layer via hole between them. The above embodiment can make the fourth metal layer line in the area corresponding to the anode block 121 axially symmetrically distributed along the axis of symmetry of the orthographic projection of the anode block 121 on the substrate layer 1101, so as to improve the flatness of the anode block 121.

[0071] Next, the first signal line 1301 discontinuously distributed in the fourth metal layer M4 is taken as an example for description. Please refer to Figure 10 In the embodiment, the display panel 10 can further include a first signal line block 1401 arranged in the same layer as the fourth signal line 1304. For example, the fourth signal line 1304 and the first signal line block 1401 can be an integrated structure, that is, the fourth signal line 1304 and the first signal line block 1401 can be formed simultaneously by patterning after the metal layer is made. The first signal line block 1401 can be located on the side of the fourth signal line 1304 facing the second signal line 1302. The first signal line block 1401 extends from the side of the fourth signal line 1304 facing the second signal line 1302 to the direction of the second signal line 1302. The first signal line block 1401 is electrically connected with the fourth signal line 1304, and the second signal line 1302 is connected with the fourth signal line 1304 through the first signal line block 1401. In this way, the line area of the fourth signal line 1304 in the area where the anode block 121 is located can be increased, the resistance of the fourth signal line 1304 can be reduced, the signal transmission loss on the fourth signal line 1304 can be reduced, and the influence of signal transmission distortion on the display effect can be reduced.

[0072] Further, please refer to Figure 11 and Figure 12 , Figure 11 is Figure 10 the cross-sectional view along the direction of A1A2, Figure 12 is Figure 10The cross-sectional view of the A3-A4 direction. The orthographic projection of the first signal trace block 1401 on the substrate layer away from the side of the fourth signal trace 1304 where the second signal trace 1302 is connected to the fourth signal trace 1304 is flush with the orthographic projection of the second signal trace 1302 on the substrate layer away from the side of the fourth signal trace 1304 where the second signal trace 1302 is connected to the fourth signal trace 1304. The length of the first signal trace block 1401 along the extension direction of the fourth signal trace 1304 is equal to the length of the second signal trace 1302 along the extension direction of the fourth signal trace 1304. Please refer to Figure 11 The side of the second signal trace 1302 away from the side of the fourth signal trace 1304 where the second signal trace 1302 is connected to the fourth signal trace 1304 can be connected to the first signal trace block 1401 through a film layer via between them to realize the connection of the second signal trace 1302 to the fourth signal trace 1304 through the first signal trace block 1401. Please refer to Figure 12 When the second signal trace 1302 is a signal trace in the fourth metal layer M4 and the first signal trace block 1401 is a signal trace block in the third metal layer M3, the second signal trace 1302 is connected to the first signal trace block 1401 through a via in the planarization layer 102 between the fourth metal layer M4 and the third metal layer M3. The above design, on the one hand, when the first signal trace 1301 is discontinuously distributed on the fourth metal layer M4, the missing part of the first signal trace 1301 in the area where the anode block 121 is located can be compensated by adding the first signal trace block 1401, so that the interference signal caused by the increase of the signal trace resistance due to the missing of the first signal trace 1301 in the area where the anode block 121 is located can be prevented; on the other hand, by adding the first signal trace block 1401, the width of the entire fourth signal trace 1304 can be increased, and the overlapping area between the orthographic projection of the fourth signal trace 1304 on the substrate layer and the film layer below the fourth signal trace 1304 can be increased, which can stabilize the electrical signal of the film layer below the fourth signal trace 1304.

[0073] Please refer to Figure 13 and Figure 14 In the present embodiment, the display panel 10 can further include a second signal trace block 1402 arranged in the same layer as the fourth signal trace 1304, wherein the second signal trace block 1402 is located on the side of the fourth signal trace 1304 facing the third signal trace 1303, and the second signal trace block 1402 extends in the direction of the third signal trace 1303 from the side of the fourth signal trace 1304 facing the third signal trace 1303. The second signal trace block 1402 and the first signal trace block 1401 are axially symmetrically distributed about the fourth signal trace 1304.

[0074] Further, in the embodiment, the first signal wire 1301 and the fourth signal wire 1304 are connected with the power voltage signal VDD, and the third signal wire 1303 is connected with the data voltage signal DATA. The fourth signal wire layer 1304 is formed by the third metal layer M3, and the display panel 10 can further include a planarization layer 102 between the third metal layer M3 and the fourth metal layer M4, the first signal wire 1301 and the fourth signal wire 1304 are connected via a via on the planarization layer 102, and the second signal wire 1302 is connected with the first signal wire block 1401 via a via on the planarization layer 102.

[0075] In the embodiment, the third signal wire 1303 extends along the extension direction of the fourth signal wire 1304, the first signal wire 1301 and the fourth signal wire 1304 have the same wire width, and the first signal wire 1301, the second signal wire 1302 and the third signal wire 1303 have the same wire thickness.

[0076] On the basis of the above, in another aspect, the embodiment of the present application further provides an electronic device, which includes the display panel described above. The use of the display panel described above can make the opposite sides of the electronic device have smaller color deviation, ensure the display uniformity of the electronic device, thus increasing the user experience and improving the market competitiveness of the product.

[0077] To sum up, the display panel and the electronic device provided by the embodiment have the following advantages. In the region corresponding to the anode block, the orthographic projection of the signal wire formed by the fourth metal layer on the substrate layer is axially symmetrically distributed relative to the symmetry axis of the orthographic projection of the anode block on the substrate layer, and at least one signal wire in the fourth metal layer is connected with the signal wire in the first metal layer, the second metal layer or the third metal layer. The above design, on the one hand, can make the anode block more flat by axially symmetrically distributing the signal wire formed by the fourth metal layer relative to the symmetry axis of the orthographic projection of the anode block on the substrate layer, and improve the color deviation of the opposite sides of the display panel caused by the uneven anode block; on the other hand, the connection of the signal wire in the fourth metal layer with the signal wire in the other layer can increase the area of the signal wire, reduce the resistance of the signal wire, reduce the loss of the signal in the transmission process, and reduce the influence of the signal transmission distortion on the display effect.

[0078] The above only describes the preferred embodiments of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, characterized by, The display panel comprises: an array driving layer and a pixel device layer which are arranged in a stack; the pixel device layer comprises anode blocks which are arranged in an array; the array driving layer comprises a substrate layer, and a first metal layer, a second metal layer, a third metal layer and a fourth metal layer which are sequentially stacked on the substrate layer and used for forming signal lines; in a region corresponding to the anode block, a normal projection of the signal line formed by the fourth metal layer on the substrate layer is distributed in axial symmetry with respect to a symmetry axis of the normal projection of the anode block on the substrate layer, wherein at least one signal line in the fourth metal layer is connected with a signal line in the first metal layer, the second metal layer or the third metal layer; the signal lines in the fourth metal layer comprise a first signal line, a second signal line and a third signal line, and the first metal layer, the second metal layer or the third metal layer comprises a fourth signal line connected with the first signal line; the first signal line and the fourth signal line extend along the symmetry axis of the normal projection of the anode block on the substrate layer, and the symmetry axis of the normal projection of the first signal line on the substrate layer and the symmetry axis of the normal projection of the fourth signal line on the substrate layer both coincide with the symmetry axis of the normal projection of the anode block on the substrate layer; the normal projection of the second signal line on the substrate layer is located within the normal projection of the anode block on the substrate layer; a portion of the normal projection of the third signal line on the substrate layer which overlaps with the normal projection of the anode block on the substrate layer is distributed in axial symmetry with respect to the symmetry axis of the normal projection of the second signal line on the substrate layer with respect to the normal projection of the anode block on the substrate layer; the second signal line is connected with the fourth signal line; the first signal line is discontinuously distributed on the fourth metal layer, and the normal projection of the first signal line on the substrate layer does not overlap with the normal projection of the anode block on the substrate layer, wherein in a region outside the anode block, the first signal line and the fourth signal line are connected through a film layer via hole; the normal projection of the fourth signal line on the substrate layer overlaps with the normal projection of the anode block on the substrate layer; the display panel further comprises a first signal line block which is arranged in the same layer as the fourth signal line; the first signal line block is located on a side of the fourth signal line facing the second signal line, and the first signal line block is connected with the fourth signal line; the second signal line is connected with the fourth signal line through the first signal line block.

2. The display panel of claim 1, wherein the fourth signal line and the first signal line block are an integral structure.

3. The display panel of claim 1, wherein, a normal projection of a side of the first signal line block away from the fourth signal line on the substrate layer is flush with a normal projection of a side of the second signal line away from the fourth signal line on the substrate layer; a length of the first signal line block along an extension direction of the fourth signal line is equal to a length of the second signal line along the extension direction of the fourth signal line.

4. The display panel of claim 3, wherein, The display panel further comprises a second signal trace block disposed in the same layer as the fourth signal trace; The second signal trace block is symmetrically distributed with the first signal trace block about the fourth signal trace.

5. The display panel of claim 1, wherein, The first signal trace and the fourth signal trace are connected with a power voltage signal, and the third signal trace is connected with a data voltage signal; The fourth signal trace is located in the third metal layer; The display panel further comprises a planarization layer located between the third metal layer and the fourth metal layer; The first signal trace and the fourth signal trace are connected via a via on the planarization layer, The second signal trace is connected with the first signal trace block via a via on the planarization layer.

6. The display panel of claim 5, wherein, The third signal trace extends along the extension direction of the fourth signal trace; The first signal trace and the fourth signal trace have the same trace width; The first signal trace, the second signal trace and the third signal trace have the same trace thickness.

7. An electronic device, comprising: The electronic device comprises the display panel of any one of claims 1-6.

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