Method for preparing a photoelectric device

Abstract

The present invention provides a method for preparing a photoelectric device. In the process of preparing a photoelectric device epitaxial wafer using the preparation method, a phosphide protective layer and an arsenide capping layer lattice-matched with the ohmic contact layer are provided on the side of the ohmic contact layer facing away from the substrate. This method can effectively prevent reactant deposition particles on quartz parts and graphite parts in the epitaxial wafer cavity from falling onto the ohmic contact layer after the epitaxial wafer growth is completed. After the epitaxial wafer growth is completed, the phosphide protective layer and the arsenide capping layer are removed to obtain an ohmic contact layer with good film quality, thereby enabling the ohmic contact layer to form better ohmic contact, thereby further improving the performance of the photoelectric device and the yield of the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and more particularly to a method for preparing a photoelectric device. Background Art

[0002] Among optoelectronic devices, solar cells can directly convert solar energy into electrical energy and are the most efficient form of clean energy. Among the current solar cell material systems, III-V compound semiconductor solar cells have the highest conversion efficiency. In addition, III-V compound semiconductor solar cells also have the advantages of good high-temperature resistance and strong radiation resistance. They are recognized as a new generation of high-performance, long-life main power sources. Among them, the triple-junction solar cell with GaInP / InGaAs / Ge lattice-matched structure has been widely used in the aerospace field.

[0003] In the prior art, the epitaxial layer structure of a GaInP / InGaAs / Ge triple-junction solar cell, according to its growth sequence, ends with an ohmic contact layer. This ohmic contact layer can be deposited with metal during the subsequent chip tape-out process to form an ohmic contact. However, after the triple-junction solar cell is prepared using the metal organic chemical vapor deposition (MOCVD) method, reactants are deposited on the quartz and graphite parts in the cavity, so particles inevitably fall onto the surface of the ohmic contact layer, which significantly affects the performance of the solar cell and the chip yield. Summary of the Invention

[0004] In view of this, in order to solve the above problems, the present invention provides a method for preparing a photoelectric device, and the technical solution is as follows:

[0005] The preparation method comprises:

[0006] A substrate is provided during the epitaxial wafer growth stage; an epitaxial layer is formed on one side of the substrate; an ohmic contact layer, a P-type protective layer, and an As-type capping layer are formed in sequence in a first direction on a side of the epitaxial layer facing away from the substrate; the first direction is perpendicular to the substrate and points from the substrate to the ohmic contact layer;

[0007] After the epitaxial wafer growth stage is completed, the As compound capping layer is removed to expose the P compound protection layer; and then the P compound protection layer is removed to expose the ohmic contact layer.

[0008] Optionally, in the above preparation method, the material of the P-compound protective layer is InP material, GaInP material, AlInP material, or AlGaInP material;

[0009] The material of the As compound cap layer is GaAs material, InGaAs material, AlGaAs material or AlInGaAs material.

[0010] Optionally, in the above preparation method, forming the P compound protective layer includes:

[0011] An AlInP layer and a GaInP layer are sequentially formed on a side of the ohmic contact layer facing away from the substrate and in the first direction.

[0012] Optionally, in the above preparation method, the thickness of the AlInP layer is 20 nm-200 nm;

[0013] The thickness of the GaInP layer is 50nm-500nm.

[0014] Optionally, in the above preparation method, the thickness of the As compound capping layer is 20 nm-200 nm.

[0015] Optionally, in the above preparation method, the material of the ohmic contact layer is GaAs material, InGaAs material, AlGaAs material, or AlInGaAs material.

[0016] Optionally, in the above preparation method, forming an epitaxial layer on one side of the substrate includes:

[0017] A first subcell, a first tunnel junction, a DBR reflective layer, a second subcell, a second tunnel junction and a third subcell are sequentially formed on one side of the substrate in the first direction.

[0018] Optionally, in the above preparation method, forming the first sub-cell includes:

[0019] On one side of the substrate, a first sub-cell back surface field layer, a first sub-cell base region, a first sub-cell emitter region and a first sub-cell window layer are sequentially formed in the first direction;

[0020] Forming the second sub-cell includes:

[0021] On a side of the DBR reflective layer away from the substrate, a second subcell back surface field layer, a second subcell base region, a second subcell emitter region and a second subcell window layer are sequentially formed in the first direction;

[0022] Forming the third sub-cell includes:

[0023] A third subcell back surface field layer, a third subcell base region, a third subcell emitter region and a third subcell window layer are formed in sequence on a side of the second tunnel junction away from the substrate and in the first direction.

[0024] Optionally, in the above preparation method, forming an epitaxial layer on one side of the substrate includes:

[0025] On one side of the substrate, an etching stop layer, an N-type ohmic contact layer, a bottom cell, a third tunnel junction, a middle cell, a fourth tunnel junction, a metamorphic buffer layer and a top cell are sequentially formed in the first direction.

[0026] Optionally, in the above preparation method, forming the bottom cell includes:

[0027] On a side of the N-type ohmic contact layer away from the substrate, a bottom cell back field layer, a bottom cell base region, a bottom cell emitter region and a bottom cell window layer are sequentially formed in the first direction;

[0028] Forming the intermediate battery includes:

[0029] On a side of the third tunnel junction away from the substrate, a middle battery back field layer, a middle battery base region, a middle battery emitter region and a middle battery window layer are sequentially formed in the first direction;

[0030] Forming the top cell includes:

[0031] A top cell back surface field layer, a top cell base region, a top cell emitter region and a top cell window layer are sequentially formed on a side of the metamorphic buffer layer away from the substrate and in the first direction.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] The present invention provides a method for preparing a photoelectric device, which comprises: providing a substrate during an epitaxial wafer growth stage; forming an epitaxial layer on one side of the substrate; forming an ohmic contact layer, a P-compound protective layer, and an As-compound cap layer in sequence in a first direction on a side of the epitaxial layer facing away from the substrate; the first direction is perpendicular to the substrate and points from the substrate to the ohmic contact layer; removing the As-compound cap layer after the epitaxial wafer growth stage to expose the P-compound protective layer; and then removing the P-compound protective layer to expose the ohmic contact layer.

[0034] In the process of preparing an epitaxial wafer of an optoelectronic device using this method, a P-compound protective layer and an As-compound capping layer that are lattice-matched to the ohmic contact layer are provided on the side of the ohmic contact layer facing away from the substrate. This can effectively prevent reactant deposition particles on the quartz parts and graphite parts in the epitaxial wafer cavity from falling onto the ohmic contact layer after the epitaxial wafer growth is completed. After the epitaxial wafer growth is completed, the P-compound protective layer and the As-compound capping layer are removed, and an ohmic contact layer with better film quality can be obtained, so that the ohmic contact layer can form better ohmic contact, further improving the performance of the optoelectronic device and the yield of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0036] Figure 1 A schematic flow chart of a method for preparing a photoelectric device according to an embodiment of the present invention;

[0037] Figure 2 for Figure 1 The structural schematic diagram corresponding to the preparation method shown;

[0038] Figure 3 for Figure 1 Another structural schematic diagram corresponding to the preparation method shown;

[0039] Figure 4 for Figure 1 Another structural schematic diagram corresponding to the preparation method shown;

[0040] Figure 5 for Figure 1 Another structural schematic diagram corresponding to the preparation method shown. DETAILED DESCRIPTION

[0041] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0042] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0043] refer to Figure 1 , Figure 1 A schematic diagram of a process for preparing a photoelectric device according to an embodiment of the present invention; Figure 2 , Figure 2 for Figure 1 The structural schematic diagram corresponding to the preparation method shown.

[0044] S101: providing a substrate 01 during the epitaxial wafer growth stage; forming an epitaxial layer 02 on one side of the substrate 01; forming an ohmic contact layer 03, a P-type protective layer 04, and an As-type capping layer 05 in sequence on a side of the epitaxial layer 02 facing away from the substrate 01 and in a first direction M; the first direction M is perpendicular to the substrate 01 and points from the substrate 01 to the ohmic contact layer 03.

[0045] In this step, a metal organic chemical vapor deposition (MOCVD) method is used to prepare a photovoltaic device. In the stage of growing the epitaxial wafer of the photovoltaic device, a substrate 01 is first provided. The substrate 01 can be a Ge substrate or a GaAs substrate, etc. An epitaxial layer 02 is formed on one side of the substrate 01. The epitaxial layer 02 will be described later. It should be noted that the substrate 01 and the epitaxial layer 02 are not specifically limited in the present invention.

[0046] Then, an ohmic contact layer 03 , a P-compound protective layer 04 and an As-compound cap layer 05 are sequentially formed in a first direction M on a side of the epitaxial layer 02 facing away from the substrate 01 .

[0047] It should be noted that the P-compound protection layer 04 and the As-compound cap layer 05 are lattice-matched with the ohmic contact layer 03 .

[0048] Optionally, in another embodiment of the present invention, the material of the ohmic contact layer 03 is GaAs material, InGaAs material, AlGaAs material, or AlInGaAs material.

[0049] Optionally, in another embodiment of the present invention, the material of the P-compound protection layer 04 is InP material, GaInP material, AlInP material, or AlGaInP material.

[0050] The material of the As compound cap layer 05 is GaAs material, InGaAs material, AlGaAs material or AlInGaAs material.

[0051] Specifically, the material of the ohmic contact layer 03 is GaAs material, InGaAs material, AlGaAs material, AlInGaAs material, etc.; the P-compound protective layer 04 can be InP material, GaInP material, AlInP material, AlGaInP material, etc.; the As-compound cap layer 05 can be GaAs material, InGaAs material, AlGaAs material, AlInGaAs material, etc.; it should be noted that there is no specific limitation on the materials of the ohmic contact layer 03, the P-compound protective layer 04, and the As-compound cap layer 05, and they can be determined according to actual conditions.

[0052] Optionally, in another embodiment of the present invention, the thickness of the As compound capping layer 05 is 20 nm-200 nm.

[0053] Specifically, the thickness of the As compound capping layer 05 can range from 20 nm to 200 nm; for example, the thickness of the As compound capping layer 05 can be 20 nm, 100 nm, or 190 nm, including endpoint values; it should be noted that this embodiment does not specifically limit the thickness of the As compound capping layer 05, and it can be determined according to actual conditions.

[0054] Optional, reference Figure 3 , Figure 3 for Figure 1 Another structural schematic diagram corresponding to the preparation method shown, in another embodiment of the present invention, forming the P-compound protection layer 04 includes: forming an AlInP layer 041 and a GaInP layer 042 in sequence on the side of the ohmic contact layer 03 away from the substrate 01 and in the first direction M.

[0055] Optionally, in another embodiment of the present invention, the thickness of the AlInP layer 041 is 20 nm-200 nm.

[0056] The thickness of the GaInP layer 042 is 50 nm-500 nm.

[0057] Specifically, the thickness range of the AlInP layer 041 can be 20nm-200nm; for example, the thickness of the AlInP layer 041 can be 60nm or 120nm or 200nm, etc., including endpoint values; the thickness range of the GaInP layer 042 can be 50nm-500nm; for example, the thickness of the GaInP layer 042 can be 60nm or 300nm or 450nm, etc., including endpoint values; it should be noted that this embodiment does not specifically limit the thickness of the AlInP layer 041 and the GaInP layer 042, and can be determined according to actual conditions.

[0058] S102 : After the epitaxial wafer growth stage is completed, the As compound capping layer 05 is removed to expose the P compound protection layer 04 ; and the P compound protection layer 04 is then removed to expose the ohmic contact layer 03 .

[0059] In this step, after the epitaxial wafer of the optoelectronic device is grown, the As compound capping layer 05 is removed first, and then the P compound protective layer 04 is removed. It should be noted that the P compound protective layer 04 and the As compound capping layer 05 have selective corrosiveness to different chemical solutions, so different removers can be selected to remove them.

[0060] HCl:H3PO4 remover is used to remove the GaInP layer 042 in the P-compound protection layer 04. When the HCl:H3PO4 remover is used to remove the GaInP layer 042, the HCl:H3PO4 remover will affect the ohmic contact layer 03. Therefore, the AlInP layer 041 is provided to protect the ohmic contact layer 03. That is to say, if the AlInP layer 041 is not provided, HCl:H3PO4 will slowly etch the ohmic contact layer 03, and the AlInP layer 041 can better protect the ohmic contact layer 03.

[0061] It should be noted that there is no specific limitation on the remover for removing the As compound cap layer 05 and the P compound protection layer 04 , and the remover can be determined according to actual conditions.

[0062] In the embodiment of the present invention, a P-compound protective layer 04 and an As-compound cap layer 05 that are lattice-matched to the ohmic contact layer 03 are provided on the side of the ohmic contact layer 03 facing away from the substrate 01. This can effectively prevent reactant deposition particles on the quartz parts and graphite parts in the epitaxial wafer cavity from falling onto the ohmic contact layer 03 after the epitaxial wafer growth is completed. By removing the P-compound protective layer 04 and the As-compound cap layer 05 after the epitaxial wafer growth is completed, an ohmic contact layer 03 with better film quality can be obtained, thereby enabling the ohmic contact layer 03 to form a better ohmic contact, thereby further improving the performance of the optoelectronic device and the yield of the chip.

[0063] The above embodiments can be applied to a variety of optoelectronic devices based on GaAs and InP systems. Based on the contents of the above embodiments, the present invention also provides two different embodiments, Example 1 and Example 2, to illustrate the present invention. It should be noted that the optoelectronic devices in Example 1 and Example 2 are multi-junction solar cells.

[0064] Example 1, reference Figure 4 , Figure 4 for Figure 1 Another structural schematic diagram corresponding to the preparation method shown.

[0065] A multi-junction solar cell is prepared by using a metal organic chemical vapor deposition (MOCVD) method. This embodiment is described by taking a forward triple-junction solar cell as an example.

[0066] First, a substrate 01 is provided, which may be a Ge substrate, and then an epitaxial layer 02 is formed on one side of the substrate 01 .

[0067] Optionally, in another embodiment of the present invention, forming the epitaxial layer 02 on one side of the substrate 01 includes:

[0068] On one side of the substrate 01 , and in the first direction M, a first sub-cell 021 , a first tunnel junction 023 , a DBR reflective layer 023 , a second sub-cell 024 , a second tunnel junction 025 and a third sub-cell 026 are sequentially formed.

[0069] Specifically, the first sub-battery 021 is a Ge battery, and the second sub-battery 024 is an In battery. x GaAs cell, the third sub-cell 026 is an AlGaInP cell; the first tunnel junction 023 is used to connect the first sub-cell 021 and the second sub-cell 024.

[0070] Optionally, in another embodiment of the present invention, forming the first sub-cell 021 includes:

[0071] On one side of the substrate 01 , and in the first direction M, a first sub-cell back surface field layer, a first sub-cell base region, a first sub-cell emitter region, and a first sub-cell window layer are sequentially formed.

[0072] Forming the second sub-cell 024 includes:

[0073] On the side of the DBR reflective layer 023 away from the substrate 01 , a second subcell back surface field layer, a second subcell base region, a second subcell emitter region and a second subcell window layer are sequentially formed in the first direction M.

[0074] Forming the third sub-cell 026 includes:

[0075] On the side of the second tunnel junction 025 away from the substrate 01 , and in the first direction M, a third sub-cell back surface field layer, a third sub-cell base region, a third sub-cell emitter region and a third sub-cell window layer are sequentially formed.

[0076] Specifically, a GaInP nucleation layer is grown on one side of the Ge substrate as the first sub-cell window layer of the first sub-cell 021 .

[0077] After the third sub-cell 026 is grown, the ohmic contact layer 03 is further grown on the side of the third sub-cell 026 facing away from the substrate 01 . The ohmic contact layer 03 can be evaporated with metal to form an ohmic contact in the subsequent chip fabrication process.

[0078] Then, on the side of the ohmic contact layer 03 facing away from the substrate 01, an AlInP layer 041 and a GaInP layer 042 lattice-matched to the ohmic contact layer 03 are grown in sequence in the first direction M as a P-compound protective layer 04, and then an As-compound cap layer 05 is grown. Then, the growth of the epitaxial wafer is terminated. The As-compound cap layer 05 can be a GaAs cap layer, an InGaAs cap layer, an AlGaAs cap layer, or an AlInGaAs cap layer, etc. This embodiment takes the AlInGaAs cap layer as an example.

[0079] After the epitaxial wafer is grown, reactant deposited particles on the quartz and graphite parts in the epitaxial wafer cavity will fall onto the surface of the epitaxial wafer. The grown AlInP layer 041, GaInP layer 042, and AlInGaAs cap layer block the reactant deposited particles on the quartz and graphite parts that fall after the epitaxial wafer growth is completed. In other words, the AlInP layer 041, GaInP layer 042, and AlInGaAs cap layer block the reactant deposited particles on the quartz and graphite parts from falling onto the ohmic contact layer 03, thereby improving the film quality of the ohmic contact layer 03.

[0080] The AlInP layer 041, the GaInP layer 042 and the AlInGaAs cap layer are then removed to obtain an epitaxial wafer of a forward triple-junction solar cell. The AlInGaAs cap layer is first removed, and then the GaInP layer 042 is removed using an HCl:H3PO4 remover. When the GaInP layer 042 is removed using the HCl:H3PO4 remover, the AlInP layer 041 protects the ohmic contact layer 03 from being etched. The AlInP layer 041 is then removed to obtain an ohmic contact layer 03 with higher film quality. At this point, an epitaxial wafer of a forward triple-junction solar cell is obtained, and subsequent process steps are performed on the epitaxial wafer to form a forward triple-junction solar cell.

[0081] Example 2, reference Figure 5 , Figure 5 for Figure 1 Another structural schematic diagram corresponding to the preparation method shown.

[0082] A multi-junction solar cell is prepared by a metal organic chemical vapor deposition (MOCVD) method. This embodiment is described by taking an inverted triple-junction solar cell as an example.

[0083] First, a substrate 01 is provided, which may be a GaAs substrate, and then an epitaxial layer 02 is formed on one side of the substrate 01 .

[0084] Optionally, in another embodiment of the present invention, forming the epitaxial layer 02 on one side of the substrate 01 includes:

[0085] On one side of the substrate 01, an etching stop layer 02a, an N-type ohmic contact layer 02b, a bottom cell 02c, a third tunnel junction 02d, a middle cell 02e, a fourth tunnel junction 02f, a metamorphic buffer layer 02g and a top cell 02h are sequentially formed in the first direction M.

[0086] Specifically, the bottom cell 02c is an AlGaInP bottom cell, the middle cell 02e is a GaAs middle cell, and the top cell 02h is an InGaAs top cell.

[0087] Optionally, in another embodiment of the present invention, forming the bottom cell 02c includes:

[0088] On the side of the N-type ohmic contact layer 02 b away from the substrate 01 , a bottom cell back surface field layer, a bottom cell base region, a bottom cell emitter region and a bottom cell window layer are sequentially formed in the first direction M.

[0089] Forming the intermediate battery 02e includes:

[0090] On the side of the third tunnel junction 02d away from the substrate 01, and in the first direction M, a middle battery back surface field layer, a middle battery base region, a middle battery emitter region and a middle battery window layer are sequentially formed.

[0091] Forming the top cell 02h includes:

[0092] On the side of the metamorphic buffer layer 02g away from the substrate 01 and in the first direction M, a top cell back surface field layer, a top cell base region, a top cell emitter region and a top cell window layer are sequentially formed.

[0093] After the top cell 02h is grown, the ohmic contact layer 03 continues to grow on the side of the top cell 02h facing away from the substrate 01. It should be noted that the ohmic contact layer 03 is a P-type ohmic contact layer, and the material can be GaAs material, InGaAs material, AlGaAs material, or AlInGaAs material. The ohmic contact layer 03 can be evaporated with metal to form an ohmic contact in the subsequent chip flow process.

[0094] Then, on the side of the ohmic contact layer 03 facing away from the substrate 01, an AlInP layer 041 and a GaInP layer 042 lattice-matched to the ohmic contact layer 03 are grown in sequence in the first direction M as a P-compound protective layer 04, and then an AlInGaAs cap layer is grown. After that, the epitaxial wafer growth is terminated. The As-compound cap layer 05 can be a GaAs cap layer, an InGaAs cap layer, an AlGaAs cap layer, or an AlInGaAs cap layer, etc. This embodiment takes the AlInGaAs cap layer as an example.

[0095] After the epitaxial wafer is grown, the reactant deposited particles on the quartz and graphite parts in the epitaxial wafer cavity will fall onto the surface of the epitaxial wafer. The grown AlInP layer 041, GaInP layer 042, and AlInGaAs cap layer block the reactant deposited particles on the quartz and graphite parts that fall after the epitaxial wafer growth is completed. In other words, the AlInP layer 041, GaInP layer 042, and InGaAs cap layer block the reactant deposited particles on the quartz and graphite parts from falling onto the ohmic contact layer 03, thereby improving the film quality of the ohmic contact layer 03.

[0096] The AlInP layer 041, the GaInP layer 042 and the AlInGaAs cap layer are then removed to obtain an epitaxial wafer of an inverted triple junction solar cell. The AlInGaAs cap layer is first removed, and then the GaInP layer 042 is removed using an HCl:H3PO4 remover. When the GaInP layer 042 is removed using the HCl:H3PO4 remover, the AlInP layer 041 protects the ohmic contact layer 03 from being etched. The AlInP layer 041 is then removed to obtain an ohmic contact layer 03 with higher film quality. At this point, an epitaxial wafer of an inverted triple junction solar cell is obtained, and subsequent process steps are performed on the epitaxial wafer to form an inverted triple junction solar cell.

[0097] The above is a detailed introduction to the preparation method of a photoelectric device provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

[0098] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0099] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that the process, method, article, or apparatus comprising a series of elements inherent to the elements, or also including elements inherent to these processes, methods, articles, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0100] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for preparing a photoelectric device, characterized in that: The preparation method comprises: A substrate is provided during the epitaxial wafer growth stage; an epitaxial layer is formed on one side of the substrate; an ohmic contact layer, a P-type protective layer, and an As-type capping layer are sequentially formed in a first direction on a side of the epitaxial layer facing away from the substrate to prevent reactant deposited particles on the quartz and graphite parts in the epitaxial wafer cavity from falling onto the ohmic contact layer after the epitaxial wafer growth is completed; the first direction is perpendicular to the substrate and points from the substrate to the ohmic contact layer; After the epitaxial wafer growth stage is completed, the As compound capping layer is removed to expose the P compound protection layer; and then the P compound protection layer is removed to expose the ohmic contact layer.

2. The preparation method according to claim 1, characterized in that The material of the P-compound protective layer is InP material, GaInP material, AlInP material or AlGaInP material; The material of the As compound cap layer is GaAs material, InGaAs material, AlGaAs material or AlInGaAs material.

3. The preparation method according to claim 1, characterized in that Forming the P compound protection layer includes: An AlInP layer and a GaInP layer are sequentially formed on a side of the ohmic contact layer facing away from the substrate and in the first direction.

4. The preparation method according to claim 3, characterized in that The thickness of the AlInP layer is 20nm-200nm; The thickness of the GaInP layer is 50nm-500nm.

5. The preparation method according to claim 1, characterized in that The thickness of the As compound capping layer is 20nm-200nm.

6. The preparation method according to claim 1, characterized in that The material of the ohmic contact layer is GaAs material, InGaAs material, AlGaAs material or AlInGaAs material.

7. The preparation method according to claim 1, characterized in that The forming of an epitaxial layer on one side of the substrate comprises: A first subcell, a first tunnel junction, a DBR reflective layer, a second subcell, a second tunnel junction and a third subcell are sequentially formed on one side of the substrate in the first direction.

8. The preparation method according to claim 7, characterized in that Forming the first sub-cell includes: On one side of the substrate, a first sub-cell back surface field layer, a first sub-cell base region, a first sub-cell emitter region and a first sub-cell window layer are sequentially formed in the first direction; Forming the second sub-cell includes: On a side of the DBR reflective layer away from the substrate, a second subcell back surface field layer, a second subcell base region, a second subcell emitter region and a second subcell window layer are sequentially formed in the first direction; Forming the third sub-cell includes: A third subcell back surface field layer, a third subcell base region, a third subcell emitter region and a third subcell window layer are formed in sequence on a side of the second tunnel junction away from the substrate and in the first direction.

9. The preparation method according to claim 1, characterized in that The forming of an epitaxial layer on one side of the substrate comprises: On one side of the substrate, an etching stop layer, an N-type ohmic contact layer, a bottom cell, a third tunnel junction, a middle cell, a fourth tunnel junction, a metamorphic buffer layer and a top cell are sequentially formed in the first direction.

10. The preparation method according to claim 9, characterized in that Forming the bottom cell includes: On a side of the N-type ohmic contact layer away from the substrate, a bottom cell back field layer, a bottom cell base region, a bottom cell emitter region and a bottom cell window layer are sequentially formed in the first direction; Forming the intermediate battery includes: On a side of the third tunnel junction away from the substrate, a middle battery back field layer, a middle battery base region, a middle battery emitter region and a middle battery window layer are sequentially formed in the first direction; Forming the top cell includes: A top cell back surface field layer, a top cell base region, a top cell emitter region and a top cell window layer are sequentially formed on a side of the metamorphic buffer layer away from the substrate and in the first direction.

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