Semiconductor structure and its preparation method

Abstract

This invention relates to a semiconductor structure and its fabrication method. The semiconductor structure includes: a substrate; a transistor structure located on the substrate, the transistor structure including a gate structure and source and drain electrodes located on both sides of the gate structure; an interlayer oxide layer located on the substrate and covering the surface of the transistor structure; a contact plug penetrating the interlayer oxide layer and electrically connected to the source or drain electrode; and a sidewall structure located between the contact plug and the gate structure and covering the sidewall of the gate structure. The sidewall structure includes a first nitrided sidewall, a second nitrided sidewall, an oxide sidewall, and an air gap. The first nitrided sidewall, the oxide sidewall, and the second nitrided sidewall are sequentially stacked on the sidewall of the gate structure in a direction away from the gate structure. The air gap is located within the oxide sidewall, and the oxide sidewall communicates with the interlayer oxide layer. This invention can reduce the parasitic capacitance generated between the gate and the adjacent contact plug.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that primarily works by using the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0.

[0003] As DRAM size shrinks, parasitic capacitance in devices becomes increasingly severe, significantly impacting device response speed. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problem that parasitic capacitance affects the response speed of devices in the prior art.

[0005] This invention provides a semiconductor structure, the semiconductor structure comprising:

[0006] Substrate;

[0007] A transistor structure is located on the substrate, the transistor structure including a gate structure and a source and a drain located on both sides of the gate structure;

[0008] An interlayer oxide layer is located on the substrate and covers the surface of the transistor structure;

[0009] A contact plug penetrates the interlayer oxide layer and is electrically connected to the source or the drain.

[0010] A sidewall structure is located between the contact plug and the gate structure and covers the sidewall of the gate structure. The sidewall structure includes a first nitrided sidewall, a second nitrided sidewall, an oxide sidewall, and an air gap. The first nitrided sidewall, the oxide sidewall, and the second nitrided sidewall are sequentially stacked on the sidewall of the gate structure in a direction away from the gate structure. The air gap is located inside the oxide sidewall, and the oxide sidewall is in communication with the interlayer oxide layer.

[0011] In one embodiment, the gate structure includes a gate dielectric layer, a first conductive layer, a second conductive layer and an insulating cap layer sequentially stacked on the substrate in a direction away from the substrate, wherein the second conductive layer is disposed opposite to the air gap.

[0012] In one embodiment, the gate dielectric layer includes a gate oxide layer and a high dielectric constant layer sequentially stacked on the substrate in a direction away from the substrate.

[0013] In one embodiment, the bottom of the air gap is higher than the top surface of the gate oxide layer.

[0014] In one embodiment, the first conductive layer includes a first metal layer, a first barrier layer, and a polysilicon layer sequentially stacked on the gate dielectric layer in a direction away from the substrate, wherein the polysilicon layer is at least partially disposed opposite to the air gap.

[0015] In one embodiment, the second conductive layer includes a second barrier layer and a second metal layer sequentially stacked on the first conductive layer in a direction away from the substrate.

[0016] The present invention also provides a method for preparing a semiconductor structure, the method comprising:

[0017] A substrate is provided, on which a gate structure is disposed;

[0018] A sidewall structure and an interlayer oxide layer are formed on the substrate. A source and a drain are formed on both sides of the gate structure. The sidewall structure covers the sidewall of the gate structure. The source, the drain, and the gate structure constitute a transistor structure. The interlayer oxide layer covers the surface of the transistor structure. The sidewall structure includes a first nitride sidewall, a second nitride sidewall, an oxide sidewall, and an air gap. The first nitride sidewall, the oxide sidewall, and the second nitride sidewall are sequentially stacked on the sidewall of the gate structure in a direction away from the gate structure. The air gap is located inside the oxide sidewall, and the oxide sidewall is connected to the interlayer oxide layer.

[0019] A contact plug is formed on the side of the sidewall structure away from the gate structure. The contact plug penetrates the interlayer oxide layer and is electrically connected to the source or the drain.

[0020] In one embodiment, forming a sidewall structure on the substrate includes:

[0021] A first nitrided sidewall, a first oxide layer, and a second nitrided sidewall are sequentially formed on the sidewall of the gate structure;

[0022] The first oxide layer is etched back, and the top surface height of the first oxide layer is lower than the first nitrided sidewall and the second nitrided sidewall;

[0023] A second oxide layer with a deposition rate greater than that of the first oxide layer is formed on the first oxide layer, an air gap is formed between the first oxide layer and the second oxide layer, and the first oxide layer and the second oxide layer constitute an oxide sidewall.

[0024] In one embodiment, the material of the first oxide layer is the same as the material of the second oxide layer.

[0025] In one embodiment, the gate structure includes a gate dielectric layer, a first conductive layer, a second conductive layer, and an insulating cap layer sequentially stacked on the substrate in a direction away from the substrate, wherein the height of the top surface of the first oxide layer after etch-back is lower than the height of the bottom surface of the second conductive layer.

[0026] In one embodiment, the gate dielectric layer includes a gate oxide layer and a high dielectric constant layer sequentially stacked on the substrate in a direction away from the substrate, wherein the top surface height of the first oxide layer after etch-back is higher than the top surface of the gate oxide layer.

[0027] In one embodiment, forming a first nitrided sidewall, a first oxide layer, and a second nitrided sidewall sequentially on the sidewall of the gate structure includes:

[0028] A first nitride layer is deposited on the top surface and sidewalls of the gate structure and on the exposed surface of the substrate, and at least the first nitride layer on the substrate is removed, wherein the first nitride layer on the sidewalls of the gate structure forms a first nitride sidewall.

[0029] A first oxide layer is deposited on the top and side surfaces of the first nitride layer and on the exposed surface of the substrate, and at least the top surface of the first nitride layer and the first oxide layer on the substrate are removed;

[0030] A second nitride layer is deposited on the top surface of the first nitride layer, the top and side surfaces of the first oxide layer, and the exposed surface of the substrate. The second nitride layer on the top surface of the first nitride layer and the top surface of the first oxide layer is removed. The second nitride layer on the side surface of the first oxide layer forms a second nitride sidewall.

[0031] In one embodiment, the exposed surface of the substrate and the top surface of the gate structure are sequentially covered with the second nitride layer and the second oxide layer; forming an interlayer oxide layer on the substrate includes:

[0032] A third oxide layer with a deposition rate lower than that of the second oxide layer is formed on the second oxide layer, and the third oxide layer is planarized. The second oxide layer and the third oxide layer covering the exposed surface of the substrate and the top surface of the gate structure constitute an interlayer oxide layer.

[0033] In one embodiment, forming a source and a drain on both sides of the gate structure includes:

[0034] After removing at least the top surface of the first nitride layer and the first oxide layer on the substrate, ions are implanted into the source and drain regions in the substrate to form the source and drain electrodes, which are located on both sides of the gate structure.

[0035] In one embodiment, the preparation method further includes:

[0036] After at least the first nitride layer on the substrate is removed, ions are implanted into lightly doped regions in the substrate, the lightly doped regions being located between the source region and the gate structure, and between the drain region and the gate structure.

[0037] The semiconductor structure and its preparation method of the present invention have the following beneficial effects:

[0038] The semiconductor structure of this invention includes a substrate, a transistor structure, an interlayer oxide contact plug, and a sidewall structure. The transistor structure is located on the substrate and includes a gate structure and source and drain electrodes located on both sides of the gate structure. The interlayer oxide layer is located on the substrate and covers the surface of the transistor structure. The contact plug is located on the substrate, penetrates the interlayer oxide layer, and is electrically connected to the source or drain electrode. Therefore, there is a parasitic capacitance between the contact plug and the gate structure. The sidewall structure covers the sidewall of the gate structure and is located between the contact plug and the gate structure. It includes a first nitrided sidewall, a second nitrided sidewall, an oxide sidewall, and an air gap. The first nitrided sidewall, the oxide sidewall, and the second nitrided sidewall are sequentially stacked on the sidewall of the gate structure in a direction away from the gate structure. The air gap is located inside the oxide sidewall, and the oxide sidewall is connected to the interlayer oxide layer. Therefore, the first nitrided sidewall, the oxide sidewall, and the second nitrided sidewall form a non-non ... The sidewall structure, which combines the final air gap with the NON sandwich structure, can effectively improve the parasitic capacitance between the gate and the adjacent contact plug caused by the miniaturization of DRAM size, improve the response speed of the device, and thus improve the overall performance of the device.

[0039] The semiconductor structure fabrication method of the present invention first provides a substrate with a gate structure, then forms a sidewall structure and an interlayer oxide layer on the substrate, and forms source and drain electrodes on both sides of the gate structure. The sidewall structure covers the sidewalls of the gate structure, and the source, drain, and gate form a transistor structure. The interlayer oxide layer covers the surface of the transistor structure. Finally, a contact plug is formed on the substrate on the side of the sidewall structure away from the gate structure. The contact plug penetrates the interlayer oxide layer and is electrically connected to the source or drain electrode. Therefore, there is a parasitic capacitance between the contact plug and the gate structure. The sidewall structure includes a first nitrided sidewall, a second nitrided sidewall, an oxide sidewall, and an air gap. The first nitrided sidewall, the oxide sidewall, and the second nitrided sidewall are sequentially stacked on the sidewalls of the gate structure in a direction away from the gate structure to form a non-non sandwich structure, which can effectively reduce the parasitic capacitance between the contact plug and the gate structure. In addition, the more insulating air gap is located inside the oxide sidewall, which can further reduce the parasitic capacitance between the contact plug and the gate structure based on the non-non sandwich structure. The combination of the final air gap and the NON sandwich structure can effectively improve the parasitic capacitance between the gate and the adjacent contact plug caused by the miniaturization of DRAM size, improve the response speed of the device, and thus improve the overall performance of the device. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 A schematic diagram of a semiconductor structure provided in related technologies;

[0042] Figure 2 This is a schematic diagram of a semiconductor structure provided in one embodiment;

[0043] Figure 3 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment;

[0044] Figure 4 This is a cross-sectional view of the structure obtained in step S301 of the semiconductor structure fabrication method provided in one embodiment;

[0045] Figure 5 This is a cross-sectional view of the structure obtained in step S302 of the semiconductor structure fabrication method provided in one embodiment;

[0046] Figure 6 This is a cross-sectional view of the structure obtained in step S303 of the semiconductor structure fabrication method provided in one embodiment;

[0047] Figure 7 This is a flowchart of step S302 in a method for fabricating a semiconductor structure provided in one embodiment;

[0048] Figure 8 This is a cross-sectional view of the structure obtained in step S701 of the semiconductor structure fabrication method provided in one embodiment;

[0049] Figure 9 This is a cross-sectional view of the structure obtained in step S702 of the semiconductor structure fabrication method provided in one embodiment;

[0050] Figure 10 This is a cross-sectional view of the structure obtained in step S704 of the semiconductor structure fabrication method provided in one embodiment;

[0051] Figure 11 This is a cross-sectional view of the structure obtained in step S705 of the semiconductor structure fabrication method provided in one embodiment;

[0052] Figure 12 This is a flowchart of step S701 in a method for fabricating a semiconductor structure provided in one embodiment;

[0053] Figure 13 This is a cross-sectional view of the structure obtained in step S1201 of the semiconductor structure fabrication method provided in one embodiment;

[0054] Figure 14 This is a cross-sectional view of the structure obtained in step S1202 of the semiconductor structure fabrication method provided in one embodiment;

[0055] Figure 15 This is a cross-sectional view of the structure obtained in step S1203 of the semiconductor structure fabrication method provided in one embodiment;

[0056] Figure 16 This is a cross-sectional view of the structure obtained in step S1204 of the semiconductor structure fabrication method provided in one embodiment;

[0057] Figure 17 This is a cross-sectional view of the structure obtained in step S1205 of the semiconductor structure fabrication method provided in one embodiment;

[0058] Figure 18 This is a cross-sectional view of the structure obtained in step S1206 of the semiconductor structure fabrication method provided in one embodiment;

[0059] Figure 19 This is a flowchart of step S303 in a method for preparing a semiconductor structure provided in one embodiment.

[0060] Explanation of reference numerals in the attached figures:

[0061] 110, Substrate; 120, Gate structure; 130, Sidewall; 140, Lightly doped region; 150, Source region; 160, Drain region;

[0062] 210. Substrate;

[0063] 220. Gate structure;

[0064] 221, gate dielectric layer; 2211, gate oxide layer; 2212, high dielectric constant layer;

[0065] 222, First conductive layer; 2221, First metal layer; 2222, First barrier layer; 2223, Polycrystalline silicon layer;

[0066] 223, second conductive layer; 2231, second barrier layer; 2232, second metal layer;

[0067] 224. Insulating cover layer;

[0068] 230. Interlayer oxide layer;

[0069] 240. Contact plug;

[0070] 250. Sidewall structure; 251. First nitrided sidewall; 252. Second nitrided sidewall; 253. Oxidized sidewall; 254. Air gap. Detailed Implementation

[0071] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0072] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0073] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0074] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0075] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0076] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0077] DRAM consists of an array area composed of multiple memory cells and an outer area surrounding the array area. A DRAM memory cell typically has a 1T1C structure, consisting of a transistor and a capacitor. The capacitor stores data, while the transistor controls the capacitor's access to that data.

[0078] Figure 1 This is a schematic diagram of a semiconductor structure provided in related technologies. Please refer to [link / reference]. Figure 1 The semiconductor structure includes a substrate 110, a gate structure 120, a sidewall 130, a lightly doped region 140, a source region 150, and a drain region 160. The gate structure 120 is disposed on the substrate 110. The source region 150 and the drain region 160 are disposed in the substrate 110 and located on opposite sides of the gate structure 120. The lightly doped region 140 is disposed in the substrate 110 and located between the gate structure 120 and the source region 150, and between the gate structure 120 and the drain region 160. The sidewall 130 is disposed on the sidewall of the gate structure 120 and located on the lightly doped region 140.

[0079] In practical applications, contact plugs are provided on the source region 150 and the drain region 160, respectively, and there is a parasitic capacitance between the contact plugs and the gate structure 120. The sidewall 130 is located between the contact plugs and the gate structure 120, which can reduce the parasitic capacitance between the contact plugs and the gate structure 120.

[0080] However, as DRAM size shrinks, the parasitic capacitance between the gate structure and the contact plug becomes larger and larger. Existing sidewall structures cannot effectively reduce the parasitic capacitance between the gate structure and the contact plug, which seriously affects the response speed of the device and thus reduces the overall performance of the device.

[0081] Based on the above reasons, the present invention provides a semiconductor structure and its fabrication method, wherein a first nitrided sidewall, an oxide sidewall, and a second nitrided sidewall are sequentially stacked on the sidewall of the gate structure, and an air gap is provided in the oxide sidewall. By combining the NON sandwich structure and the air gap, the parasitic capacitance between the gate and the adjacent contact plug caused by the miniaturization of DRAM size is effectively improved, the response speed of the device is improved, and the overall performance of the device is improved.

[0082] Figure 2 This is a schematic diagram of a semiconductor structure provided in one embodiment. Please refer to [link / reference]. Figure 2 This invention provides a semiconductor structure comprising a substrate 210, a transistor structure, an interlayer oxide layer 230, a contact plug 240, and a sidewall structure 250. The transistor structure is located on the substrate 210 and includes a gate structure 220 and source and drain electrodes (not shown) located on either side of the gate structure 220. The interlayer oxide layer 230 is located on the substrate 210 and covers the surface of the transistor structure. The contact plug 240 penetrates the interlayer oxide layer 230 and is electrically connected to the source or drain electrode. The sidewall structure 250 is located between the contact plug 240 and the gate structure 220 and covers the sidewall of the gate structure 220. The sidewall structure 250 includes a first nitrided sidewall 251, a second nitrided sidewall 252, an oxide sidewall 253 and an air gap 254. The first nitrided sidewall 251, the oxide sidewall 253 and the second nitrided sidewall 252 are stacked sequentially on the sidewall of the gate structure 220 in a direction away from the gate structure 220. The air gap 254 is located inside the oxide sidewall 253. The oxide sidewall 253 is connected to the interlayer oxide layer 230.

[0083] The aforementioned semiconductor structure includes a substrate, a transistor structure, an interlayer oxide contact plug, and a sidewall structure. The transistor structure is located on the substrate and includes a gate structure and source and drain electrodes located on both sides of the gate structure. The interlayer oxide layer is located on the substrate and covers the surface of the transistor structure. The contact plug is located on the substrate, penetrates the interlayer oxide layer, and is electrically connected to the source or drain electrode. Therefore, there is a parasitic capacitance between the contact plug and the gate structure. The sidewall structure covers the sidewall of the gate structure and is located between the contact plug and the gate structure. It includes a first nitrided sidewall, a second nitrided sidewall, an oxide sidewall, and an air gap. The first nitrided sidewall, oxide sidewall, and second nitrided sidewall are sequentially stacked on the sidewall of the gate structure in a direction away from the gate structure. The air gap is located inside the oxide sidewall, and the oxide sidewall is connected to the interlayer oxide layer. Therefore, the first nitrided sidewall, oxide sidewall, and second nitrided sidewall form a non-non ... The sidewall structure, which combines the final air gap with the NON sandwich structure, can effectively improve the parasitic capacitance between the gate and the adjacent contact plug caused by the miniaturization of DRAM size, improve the response speed of the device, and thus improve the overall performance of the device.

[0084] Specifically, the substrate 210 can be constructed from semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate 210 can be a single-layer structure or a multi-layer structure. For example, the substrate 210 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, the substrate can be a layered substrate comprising materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of substrate should not limit the scope of this disclosure.

[0085] Shallow trench isolation (STI) can be formed within the substrate 210, isolating several spaced-apart active areas (AAs) within the substrate 210. These active areas can be P-type or N-type. P-type active areas can form N-type metal-oxide-semiconductor (NMOS) devices, and N-type active areas can form P-type metal-oxide-semiconductor (PMOS) devices.

[0086] In embodiments where the substrate includes a P-type substrate, the source and drain can be formed by implanting N-type ions; correspondingly, in embodiments where the substrate includes an N-type substrate, the source and drain can be formed by implanting P-type ions. Contact plug 240 is located on the source or drain. Ions can also be implanted into the substrate between the source or drain and the gate structure 220 to form a lightly doped region. Understandably, when the substrate 210 is N-type, the implanted ions are P-type; when the substrate 210 is P-type, the implanted ions are N-type.

[0087] This disclosure does not specifically limit the types of P-type ions. As an example, P-type ions may include, but are not limited to, any one or more of boron (B) ions, magnesium (Mg) ions, or indium (In) ions. Similarly, this disclosure does not specifically limit the types of N-type ions. As an example, N-type ions may include, but are not limited to, any one or more of phosphorus (P) ions, arsenic (As) ions, or antimony (Sb) ions.

[0088] In some embodiments, such as Figure 2 As shown, the gate structure 220 includes a gate dielectric layer 221, a first conductive layer 222, a second conductive layer 223 and an insulating capping layer 224 sequentially stacked on the substrate 210 in a direction away from the substrate 210, with the second conductive layer 223 disposed opposite to the air gap 254.

[0089] Parasitic capacitance is typically formed between conductors. The gate structure includes a gate dielectric layer, a first conductive layer, a second conductive layer, and an insulating cap layer, which are sequentially stacked on the substrate in a direction away from the substrate. The second conductive layer is disposed opposite to the air gap, which can effectively reduce the parasitic capacitance generated between the gate and the adjacent contact plug.

[0090] In some embodiments, such as Figure 2As shown, the gate dielectric layer 221 includes a gate oxide layer 2211 and a high dielectric constant layer 2212 sequentially stacked on the substrate 210 in a direction away from the substrate 210.

[0091] The gate dielectric layer includes a gate oxide layer and a high dielectric constant layer sequentially stacked on the substrate in a direction away from the substrate. The gate oxide layer and the high dielectric constant layer work together to effectively prevent direct electron tunneling and gate leakage current, which is beneficial to reducing the thickness of the gate dielectric layer and meeting the requirements of process size reduction.

[0092] For example, the gate oxide layer 2111 may be formed using silicon dioxide (SiO2).

[0093] For example, the high dielectric constant layer 2112 can be formed using a material with a high k dielectric constant. For instance, the material of the gate dielectric layer 2112 includes hafnium silicon oxide (HfSiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3). When the high dielectric constant layer 2112 is made of HfSiO2, it has a higher matching degree with the gate oxide layer (SiO2), which is beneficial for forming a better interface layer and improving the device performance of the transistor structure.

[0094] In some embodiments, such as Figure 2 As shown, the first conductive layer 222 includes a first metal layer 2221, a first barrier layer 2222 and a polysilicon layer 2223 sequentially stacked on the gate dielectric layer 221 in a direction away from the substrate 210. The polysilicon layer 2223 is at least partially disposed opposite to the air gap 254.

[0095] The polysilicon layer is the closest to the second conductive layer in the first conductive layer. The polysilicon layer is at least partially positioned opposite the air gap, which is beneficial for the orthogonal projection of the air gap on the sidewall of the gate structure to completely cover the second conductive layer, thereby effectively reducing the parasitic capacitance generated between the gate and the adjacent contact plug.

[0096] For example, when the transistor structure is NMOS, the first metal layer 2221 can be formed of lanthanum (La), and the first barrier layer 2222 can be formed of lanthanum oxide (La2O3).

[0097] When the transistor structure is PMOS, the first metal layer 2221 can be formed of aluminum (Al), and the first barrier layer 2222 can be formed of aluminum oxide (Al2O3).

[0098] The non-metallic layer 2223 can be formed using doped polycrystalline silicon (poly-Si).

[0099] The first metal layer, as a work function adjustment layer, can diffuse metal ions to the interface between the high dielectric constant layer 2212 and the gate oxide layer 2211 through annealing or other methods to adjust the performance of the transistor structure.

[0100] For example, the bottom of the air gap 254 is higher than the top surface of the gate oxide layer 2211.

[0101] In some embodiments, such as Figure 2 As shown, the second conductive layer 223 includes a second barrier layer 2231 and a second metal layer 2232 sequentially stacked on the first conductive layer 222 in a direction away from the substrate 210.

[0102] For example, the second barrier layer 2231 can be formed using metal silicides, such as titanium silicon nitride (TiSiN), cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), etc., or it can be formed using metal nitrides, such as titanium nitride (TiN), tungsten nitride (WN), etc. The second metal layer 2232 can be formed using tungsten (W). The second barrier layer being formed using metal silicides can, on the one hand, block tungsten diffusion, and on the other hand, reduce the interface resistance.

[0103] The material of the second metal layer 2232 may include metals such as cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), tantalum titanate (TaTi), and aluminum (Al).

[0104] In some embodiments, such as Figure 2 As shown, the insulating cover layer 224 is at least partially disposed opposite to the air gap 254.

[0105] Located on the second conductive layer is an insulating capping layer, which is at least partially positioned opposite the air gap. This allows the orthogonal projection of the air gap onto the sidewall of the gate structure to completely cover the second conductive layer, thereby effectively reducing the parasitic capacitance generated between the gate and the adjacent contact plug.

[0106] For example, the insulating capping layer 224 may be formed of silicon nitride (SiN). In other embodiments, the material of the insulating capping layer 224 may also include, but is not limited to, silicon oxide (SiO2) or silicon oxynitride (SiON).

[0107] For example, the material of the first nitride sidewall 251 can be the same as that of the insulating capping layer 224, namely silicon nitride. The insulating capping layer is the top layer of the gate structure, and the first nitride layer forming the first nitride sidewall covers the gate structure, which can be merged with the insulating capping layer into one layer.

[0108] For example, the material of the second nitrided sidewall 252 can be the same as that of the first nitrided sidewall 251, namely silicon nitride.

[0109] For example, the material of the oxide sidewall 253 can be the same as that of the gate oxide layer 2111, namely silicon dioxide.

[0110] For example, the contact plug 240 may be formed of tungsten.

[0111] Based on the same inventive concept, this invention also provides a method for fabricating a semiconductor structure. Please refer to [link to relevant documentation]. Figure 3 The preparation method includes the following steps:

[0112] S301 provides a substrate on which a gate structure is provided.

[0113] Figure 4 This is a cross-sectional view of the structure obtained in step S301 of the semiconductor structure fabrication method provided in one embodiment. For example... Figure 4 As shown, a gate structure 220 is disposed on a substrate 210. The gate structure 220 includes a gate dielectric layer 221, a first conductive layer 222, a second conductive layer 223, and an insulating capping layer 224 stacked sequentially. The gate dielectric layer 221 includes a gate oxide layer 2211 and a high dielectric constant layer 2212 stacked sequentially. The first conductive layer 222 includes a first metal layer 2221, a first barrier layer 2222, and a polysilicon layer 2223 stacked sequentially. The second conductive layer 223 includes a second barrier layer 2231 and a second metal layer 2232 stacked sequentially.

[0114] S302 has a sidewall structure and an interlayer oxide layer formed on a substrate. The source and drain are formed on both sides of the gate structure. The sidewall structure covers the sidewall of the gate structure. The source, drain and gate structures form a transistor structure. The interlayer oxide layer covers the surface of the transistor structure.

[0115] The sidewall structure includes a first nitrided sidewall, a second nitrided sidewall, an oxide sidewall, and an air gap. The first nitrided sidewall, the oxide sidewall, and the second nitrided sidewall are sequentially stacked on the sidewall of the gate structure in a direction away from the gate structure. The air gap is located inside the oxide sidewall, and the oxide sidewall is connected to the interlayer oxide layer.

[0116] Figure 5 This is a cross-sectional view of the structure obtained in step S302 of the semiconductor structure fabrication method provided in one embodiment. For example... Figure 5 As shown, a sidewall structure 250 is disposed on the sidewall of the gate structure 220, and an interlayer oxide layer 230 covers the surfaces of the gate structure 220 and the sidewall structure 250. The sidewall structure 250 includes a first nitrided sidewall 251, a second nitrided sidewall 252, an oxide sidewall 253, and an air gap 254. The first nitrided sidewall 251, the oxide sidewall 253, and the second nitrided sidewall 252 are stacked sequentially, and the air gap 254 is located within the oxide sidewall 253. The oxide sidewall 253 communicates with the interlayer oxide layer 230.

[0117] S303 forms a contact plug on the side of the sidewall structure away from the gate structure. The contact plug penetrates the interlayer oxide layer and is electrically connected to the source or drain.

[0118] Figure 6 This is a cross-sectional view of the structure obtained in step S303 of the semiconductor structure fabrication method provided in one embodiment. For example... Figure 6 As shown, the contact plug 240 is disposed on the substrate 210, the gate structure 220 is located between the two contact plugs 240, and the sidewall structure 250 is located between the contact plug 240 and the gate structure 220.

[0119] The above-described semiconductor structure fabrication method first provides a substrate with a gate structure, then forms a sidewall structure and an interlayer oxide layer on the substrate. Source and drain electrodes are formed on both sides of the gate structure. The sidewall structure covers the sidewalls of the gate structure. The source, drain, and gate form a transistor structure. The interlayer oxide layer covers the surface of the transistor structure. Finally, a contact plug is formed on the substrate on the side of the sidewall structure away from the gate structure. The contact plug penetrates the interlayer oxide layer and is electrically connected to the source or drain. Therefore, parasitic capacitance exists between the contact plug and the gate structure. The sidewall structure includes a first nitrided sidewall, a second nitrided sidewall, an oxide sidewall, and an air gap. The first nitrided sidewall, oxide sidewall, and second nitrided sidewall are sequentially stacked on the sidewalls of the gate structure in a direction away from the gate structure, forming a non-non sandwich structure. This effectively reduces the parasitic capacitance between the contact plug and the gate structure. Furthermore, the more insulating air gap located within the oxide sidewall further reduces the parasitic capacitance between the contact plug and the gate structure based on the non-non sandwich structure. The combination of the final air gap and the NON sandwich structure can effectively improve the parasitic capacitance between the gate and the adjacent contact plug caused by the miniaturization of DRAM size, improve the response speed of the device, and thus improve the overall performance of the device.

[0120] In some embodiments, please refer to Figure 7 The formation of sidewall structures and interlayer oxide layers on a substrate includes the following steps:

[0121] S701, a first nitrided sidewall, a first oxide layer and a second nitrided sidewall are sequentially formed on the sidewall of the gate structure.

[0122] Figure 8 This is a cross-sectional view of the structure obtained in step S701 of the semiconductor structure fabrication method provided in one embodiment. For example... Figure 8 As shown, a first nitrided sidewall 251, a first oxide layer forming an oxide sidewall 253, and a second nitrided sidewall 252 are sequentially stacked on the sidewall of the gate structure 220. The top surface of the first oxide layer is flush with the height of the first nitrided sidewall 251 and the second nitrided sidewall 252, and the second nitrided layer forming the second nitrided sidewall 252 is also located on the exposed surface of the substrate 210.

[0123] S702, the first oxide layer is etched back, and the top surface height of the first oxide layer is lower than the first nitrided sidewall and the second nitrided sidewall.

[0124] Figure 9 This is a cross-sectional view of the structure obtained in step S702 of the semiconductor structure fabrication method provided in one embodiment. For example... Figure 9 As shown, the upper half of the first oxide layer is removed, leaving the lower half, and the top surface height is lower than the first nitrided sidewall 251 and the second nitrided sidewall 252.

[0125] For example, the gate structure includes a gate dielectric layer, a first conductive layer, a second conductive layer and an insulating cap layer sequentially stacked on the substrate in a direction away from the substrate, wherein the height of the top surface of the first oxide layer after etch-back is lower than the height of the bottom surface of the second conductive layer.

[0126] For example, the gate dielectric layer includes a gate oxide layer and a high dielectric constant layer sequentially stacked on the substrate in a direction away from the substrate, and the top surface height of the first oxide layer after etch-back is higher than the top surface of the gate oxide layer.

[0127] S703, a second oxide layer with a deposition rate greater than that of the first oxide layer is formed on the first oxide layer, an air gap is formed between the first oxide layer and the second oxide layer, and the first oxide layer and the second oxide layer constitute an oxide sidewall.

[0128] For example, the material of the second oxide layer is the same as that of the first oxide layer, and the second oxide layer and the first oxide layer are merged into one layer. The second oxide layer between the first nitrided sidewall and the second nitrided sidewall forms an oxide sidewall with the first oxide layer. Because the deposition rate of the second oxide layer is faster, an air gap is formed between the first oxide layer and the second oxide layer. Furthermore, because the top surface height of the first oxide layer after etching back is lower than the bottom surface height of the second conductive layer, the bottom surface height of the air gap is lower than the bottom surface height of the second conductive layer, so that the second conductive layer and the air gap are positioned opposite each other.

[0129] S704, a third oxide layer is formed on the second oxide layer with a deposition rate lower than that of the second oxide layer, and the bottom surface height of the third oxide layer is higher than the top surface height of the second conductive layer.

[0130] S704 is an optional step.

[0131] For example, the material of the third oxide layer is the same as that of the second oxide layer. The third oxide layer, the second oxide layer, and the first oxide layer are merged into one layer. The second oxide layer and the third oxide layer covering the exposed surface of the substrate and the top surface of the gate structure form an interlayer oxide layer. The deposition rate of the third oxide layer is slower, which can avoid the formation of air gaps, so that the air gap terminates between the second oxide layer and the third oxide layer.

[0132] For example, the lowest height of the top surface of the third oxide layer is higher than that of the second nitride layer and the first nitride layer, and the interlayer oxide layer can cover the gate structure and the sidewall structure.

[0133] Figure 10 This is a cross-sectional view of the structure obtained in step S704 of the semiconductor structure fabrication method provided in one embodiment. For example... Figure 10 As shown, an air gap 254 is formed in the oxide sidewall 253 (including the first oxide layer and the second oxide layer) between the first nitrided sidewall 251 and the second nitrided sidewall 252. An interlayer oxide layer 230 (including the second oxide layer and the third oxide layer) is covered on the exposed surfaces of the gate structure 220, the sidewall structure 250 and the substrate 210.

[0134] S705 is used to planarize the third oxide layer.

[0135] Figure 11 This is a cross-sectional view of the structure obtained in step S705 of the semiconductor structure fabrication method provided in one embodiment. For example... Figure 11 As shown, after planarization, the top surface of the interlayer oxide layer 230 is a plane, and the height of the top surface of the interlayer oxide layer 230 is still higher than the first nitrided sidewall 251 and the second nitrided sidewall 252, completely covering the gate structure 220 and the sidewall structure 250.

[0136] In some embodiments, please refer to Figure 12 The process of sequentially forming a first nitrided sidewall, a first oxide layer, and a second nitrided sidewall on the sidewall of the gate structure includes the following steps:

[0137] S1201, deposit a first nitride layer on the top surface and sidewalls of the gate structure, as well as on the exposed surface of the substrate.

[0138] Figure 13 This is a cross-sectional view of the structure obtained in step S1201 of the semiconductor structure fabrication method provided in one embodiment. For example... Figure 13 As shown, the first nitride layer forming the first nitride sidewall 251 covers the top surface and sidewalls of the gate structure 220, as well as the exposed surface of the substrate 210.

[0139] For example, S1201 includes the step of depositing a first nitride layer on the top surface and sidewalls of the gate structure and on the exposed surface of the substrate using a deposition process.

[0140] Specifically, the deposition process may include, but is not limited to, one or more of the following processes: Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP), Plasma Enhanced Deposition (PDE), and Spin-on Dielectric (SOD).

[0141] S1202, at least the first nitride layer on the substrate is removed, and the first nitride layer on the sidewall of the gate structure forms a first nitride sidewall.

[0142] Figure 14 This is a cross-sectional view of the structure obtained in step S1202 of the semiconductor structure fabrication method provided in one embodiment. For example... Figure 14 As shown, the first nitride layer on the substrate 210 is removed, leaving the first nitride layer on the top surface and sidewalls of the gate structure 220, forming the first nitride sidewall 251. Since the material of the first nitride layer is the same as the material of the top layer of the gate structure 220, the first nitride layer on the top surface of the gate structure 220 and the top layer of the gate structure 220 can be merged into one layer, without the need to remove the first nitride layer on the top surface of the gate structure 220.

[0143] In other embodiments, step S1202 also removes the first nitride layer on the top surface of the gate structure, leaving only the first nitride layer on the sidewall of the gate structure. This is particularly suitable for cases where the material of the first nitride layer is different from that of the top layer of the gate structure.

[0144] For example, S1202 includes the following steps: etching back the first nitride layer to remove the first nitride layer on the top surface of the gate structure and the substrate.

[0145] S1203, depositing a first oxide layer on the top and side surfaces of the first nitride layer and on the exposed surface of the substrate.

[0146] Figure 15 This is a cross-sectional view of the structure obtained in step S1203 of the semiconductor structure fabrication method provided in one embodiment. For example... Figure 15 As shown, the first oxide layer forming the oxide sidewall 253 covers the top and side surfaces of the first nitride layer 251, as well as the exposed surface of the substrate 210. If the first nitride layer does not cover the top surface of the gate structure 220, the first oxide layer also covers the top surface of the gate structure 220.

[0147] For example, S1203 includes the following steps: depositing a first oxide layer on the top and side surfaces of the first nitride layer and on the exposed surface of the substrate using an etching process.

[0148] S1204, at least the top surface of the first nitride layer and the first oxide layer on the substrate are removed.

[0149] Figure 16 This is a cross-sectional view of the structure obtained in step S1204 of the semiconductor structure fabrication method provided in one embodiment. Figure 16 As shown, the first oxide layer on the top surface of the first nitride layer and on the substrate 210 is removed, leaving the first oxide layer on the side surface of the first nitride layer. If there is no first nitride layer on the top surface of the gate structure 220, and the first oxide layer directly covers the top surface of the gate structure 220, then the first oxide layer on the top surface of the gate structure 220 is also removed.

[0150] For example, S1204 includes the following steps: etching back the first oxide layer to remove at least the top surface of the first nitride layer and the first oxide layer on the substrate.

[0151] S1205, deposit a second nitride layer on the top surface of the first nitride layer, the top and side surfaces of the first oxide layer, and the exposed surface of the substrate.

[0152] Figure 17 This is a cross-sectional view of the structure obtained in step S1205 of the semiconductor structure fabrication method provided in one embodiment. Figure 17 As shown, the second nitride layer forming the second nitride sidewall 252 covers the top surface of the first nitride layer, the top and side surfaces of the first oxide layer, and the exposed surface of the substrate 210. If the first nitride layer does not cover the top surface of the gate structure 220, the second nitride layer also covers the top surface of the gate structure 220.

[0153] For example, S1205 includes the following steps: depositing a second nitride layer on the top surface of the first nitride layer, the top and side surfaces of the first oxide layer, and the exposed surface of the substrate using a deposition process.

[0154] S1206, remove the second nitriding layer on the top surface of the first nitriding layer and the top surface of the first oxide layer, and the second nitriding layer on the side surface of the first oxide layer forms a second nitriding sidewall.

[0155] Figure 18 This is a cross-sectional view of the structure obtained in step S1206 of the semiconductor structure fabrication method provided in one embodiment. For example... Figure 18As shown, the second nitride layer on the top surface of the first nitride layer and the top surface of the first oxide layer is removed, leaving the second nitride layer on the side surface of the first oxide layer and on the substrate 210, forming the second nitride sidewall 252. If there is no first nitride layer on the top surface of the gate structure 220, and the second nitride layer directly covers the top surface of the gate structure 220, then the second nitride layer on the top surface of the gate structure 220 can be retained (the material of the second nitride layer is the same as that of the top layer of the gate structure 220, and they can be merged into one layer), or it can be removed (especially applicable when the material of the second nitride layer is different from that of the top layer of the gate structure 220).

[0156] For example, S1206 includes the following step: removing the second nitride layer using a planarization process until the first oxide layer is exposed.

[0157] In some embodiments, please refer to Figure 19 Forming a contact plug on the side of the sidewall structure away from the gate structure includes the following steps:

[0158] S1901, a first via extending to the source and a second via extending to the drain are formed in the interlayer oxide layer and the second nitride layer.

[0159] S1902, a contact plug is formed in the first through hole and the second through hole.

[0160] In one embodiment, forming a source and a drain on both sides of the gate structure includes the following steps: after removing at least the top surface of the first nitride layer and the first oxide layer on the substrate, ions are implanted into the source and drain regions in the substrate to form the source and drain regions, which are located on both sides of the gate structure.

[0161] The source region is the area in the substrate where the source electrode is formed, and the drain region is the area in the substrate where the drain electrode is formed.

[0162] After removing the top surface of the first nitride layer and the first oxide layer on the substrate, ion implantation is performed on the source and drain regions in the substrate. Ions are implanted without any obstruction on the substrate. The gate structure has a first oxide layer and a first nitride layer on its sidewalls to prevent ion implantation into the gate structure.

[0163] In one embodiment, the fabrication method further includes the following steps: after removing at least the first nitride layer on the substrate, implanting ions into a lightly doped region in the substrate, the lightly doped region being located between the source region and the gate structure, and between the drain region and the gate structure.

[0164] After removing the first nitride layer on the substrate, ion implantation is performed on the lightly doped region in the substrate. Ions are implanted without any obstruction on the substrate. The first nitride layer on the sidewall of the gate structure prevents ion implantation into the gate structure.

[0165] It should be understood that, although Figure 3 , Figure 7, Figure 12 , Figure 19 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 3 , Figure 7 , Figure 12 , Figure 19 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0166] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0167] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure includes: Substrate; A transistor structure is located on the substrate, the transistor structure including a gate structure and a source and a drain located on both sides of the gate structure; An interlayer oxide layer is located on the substrate and covers the surface of the transistor structure; A contact plug penetrates the interlayer oxide layer and is electrically connected to the source or the drain. A sidewall structure is located between the contact plug and the gate structure and covers the sidewall of the gate structure. The sidewall structure includes a first nitrided sidewall, a second nitrided sidewall, an oxide sidewall, and an air gap. The first nitrided sidewall, the oxide sidewall, and the second nitrided sidewall are sequentially stacked on the sidewall of the gate structure in a direction away from the gate structure. The air gap is located inside the oxide sidewall, and the oxide sidewall communicates with the interlayer oxide layer. The gate structure includes a gate dielectric layer, a first conductive layer, a second conductive layer, and an insulating cap layer sequentially stacked on the substrate in a direction away from the substrate. The second conductive layer is disposed opposite to the air gap, and the orthogonal projection of the air gap on the sidewall of the gate structure completely covers the second conductive layer. The first conductive layer includes a first metal layer, a first barrier layer, and a polysilicon layer sequentially stacked on the gate dielectric layer in a direction away from the substrate. The polysilicon layer is at least partially disposed opposite to the air gap. The second conductive layer includes a second barrier layer and a second metal layer sequentially stacked on the first conductive layer in a direction away from the substrate.

2. The semiconductor structure of claim 1, wherein, The gate dielectric layer includes a gate oxide layer and a high dielectric constant layer sequentially stacked on the substrate in a direction away from the substrate.

3. The semiconductor structure of claim 2, wherein, The bottom of the air gap is higher than the top surface of the gate oxide layer.

4. A method for fabricating a semiconductor structure, characterized in that, The preparation method includes: A substrate is provided, on which a gate structure is disposed; the gate structure includes a gate dielectric layer, a first conductive layer, a second conductive layer and an insulating cap layer sequentially stacked on the substrate in a direction away from the substrate, the first conductive layer including a first metal layer, a first barrier layer and a polysilicon layer sequentially stacked on the gate dielectric layer in a direction away from the substrate, and the second conductive layer including a second barrier layer and a second metal layer sequentially stacked on the first conductive layer in a direction away from the substrate; A sidewall structure and an interlayer oxide layer are formed on the substrate. A source and a drain are formed on both sides of the gate structure. The sidewall structure covers the sidewall of the gate structure. The source, the drain, and the gate structure constitute a transistor structure. The interlayer oxide layer covers the surface of the transistor structure. The sidewall structure includes a first nitride sidewall, a second nitride sidewall, an oxide sidewall, and an air gap. The first nitride sidewall, the oxide sidewall, and the second nitride sidewall are sequentially stacked on the sidewall of the gate structure in a direction away from the gate structure. The air gap is located inside the oxide sidewall, and the oxide sidewall is connected to the interlayer oxide layer. A contact plug is formed on the side of the sidewall structure away from the gate structure. The contact plug penetrates the interlayer oxide layer and is electrically connected to the source or the drain. The formation of the sidewall structure on the substrate includes: A first nitrided sidewall, a first oxide layer, and a second nitrided sidewall are sequentially formed on the sidewall of the gate structure; The first oxide layer is etched back, and the height of the top surface of the first oxide layer is lower than the height of the first nitrided sidewall and the second nitrided sidewall, and the height of the top surface of the first oxide layer after etching back is lower than the height of the bottom surface of the second conductive layer. A second oxide layer is formed on the first oxide layer at a deposition rate greater than that of the first oxide layer, an air gap is formed between the first oxide layer and the second oxide layer, and the first oxide layer and the second oxide layer constitute an oxide sidewall; the second conductive layer is disposed opposite to the air gap and the polysilicon layer is at least partially disposed opposite to the air gap, and the orthogonal projection of the air gap on the sidewall of the gate structure completely covers the second conductive layer.

5. The preparation method according to claim 4, characterized in that, The material of the first oxide layer is the same as the material of the second oxide layer.

6. The preparation method according to claim 4, characterized in that, The gate dielectric layer includes a gate oxide layer and a high dielectric constant layer sequentially stacked on the substrate in a direction away from the substrate, wherein the top surface height of the first oxide layer after etch-back is higher than the top surface of the gate oxide layer.

7. The preparation method according to any one of claims 4-6, characterized in that, The formation of a first nitrided sidewall, a first oxide layer, and a second nitrided sidewall sequentially on the sidewall of the gate structure includes: A first nitride layer is deposited on the top surface and sidewalls of the gate structure and on the exposed surface of the substrate, and at least the first nitride layer on the substrate is removed, wherein the first nitride layer on the sidewalls of the gate structure forms a first nitride sidewall. A first oxide layer is deposited on the top and side surfaces of the first nitride layer and on the exposed surface of the substrate, and at least the top surface of the first nitride layer and the first oxide layer on the substrate are removed; A second nitride layer is deposited on the top surface of the first nitride layer, the top and side surfaces of the first oxide layer, and the exposed surface of the substrate. The second nitride layer on the top surface of the first nitride layer and the top surface of the first oxide layer is removed. The second nitride layer on the side surface of the first oxide layer forms a second nitride sidewall.

8. The preparation method according to claim 7, characterized in that, The exposed surface of the substrate and the top surface of the gate structure are sequentially covered with the second nitride layer and the second oxide layer; forming an interlayer oxide layer on the substrate includes: A third oxide layer with a deposition rate lower than that of the second oxide layer is formed on the second oxide layer, and the third oxide layer is planarized. The second oxide layer and the third oxide layer covering the exposed surface of the substrate and the top surface of the gate structure constitute an interlayer oxide layer.

9. The preparation method according to claim 7, characterized in that, Forming source and drain electrodes on both sides of the gate structure includes: After removing at least the top surface of the first nitride layer and the first oxide layer on the substrate, ions are implanted into the source and drain regions in the substrate to form the source and drain electrodes, which are located on both sides of the gate structure.

10. The preparation method according to claim 9, characterized in that, The preparation method further includes: After at least the first nitride layer on the substrate is removed, ions are implanted into lightly doped regions in the substrate, the lightly doped regions being located between the source region and the gate structure, and between the drain region and the gate structure.

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