A method and system for optimizing a layout of a quad-core CPU chip

Abstract

The application discloses a four-core CPU chip layout optimization method and system, which comprises the following steps: configuring a command to close a useful skew environment in an IC design system, controlling chip size, placing memory and pin position through overall layout of a floorplan, setting parameters including cell spacing, timing, area and power consumption through a place mode, and placing standard cells; adjusting memory in the overall layout stage of the floorplan through a debug net method according to a place result; repeating the place method and the debug net method, and judging an optimal chip layout strategy according to timing slack, a drv violation and a 'congestion' condition in a timing report, and re-executing the optimal chip layout strategy in a useful skew opening environment.

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