A control substrate and a preparation method thereof, and a light-emitting panel

Abstract

The disclosed embodiment provides a control substrate and a preparation method thereof, and a light-emitting panel. The control substrate includes: a first metal layer, located on the side of the active layer, the gate electrode and the first insulating layer away from the substrate, including a source electrode, a drain electrode and a first metal wiring; a first passivation layer and a first organic layer, which are located on the side of the first metal layer away from the substrate in sequence, the first organic layer is provided with a first via hole and a second via hole, the first via hole at least partially intersects with the positive projection of the drain electrode on the substrate, and the second via hole at least partially intersects with the positive projection of the first metal wiring on the substrate; a second passivation layer, located on the side of the first organic layer away from the substrate, is provided with a third via hole located at the position of the first via hole and a fourth via hole located at the position of the second via hole, the third via hole penetrates the second passivation layer and the first passivation layer to expose a portion of the surface of the drain electrode, and the fourth via hole penetrates the second passivation layer and the first passivation layer to expose a portion of the surface of the first metal wiring.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a control substrate and a preparation method thereof, and a light-emitting panel. Background Art

[0002] Light-emitting diode chips (LEDs) are a new technology with broad market prospects and are receiving more and more attention. In LED panels in the prior art, such as passive matrix LED panels (PM-LED panels), the spacing between LEDs cannot be further reduced while ensuring the cost. However, as the performance of LED panels, such as resolution, improves, more LEDs need to be set on the LED panels, and accordingly, the LED panels require more sets of driver ICs. When the spacing between LEDs is smaller and the number of LEDs on the same area is greater, more driver ICs are required, resulting in a limited layout area for the driver ICs. In order to solve the problem of limited driver IC area, a driver IC with a smaller area is required, which is bound to increase the cost of the driver IC, thereby greatly increasing the cost of the LED panel. Summary of the invention

[0003] The embodiments of the present disclosure provide a control substrate and a method for preparing the same, and a light-emitting panel to solve or alleviate one or more technical problems in the prior art.

[0004] As a first aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a control substrate, including:

[0005] substrate;

[0006] The active layer, the gate electrode and the first insulating layer are located on one side of the substrate;

[0007] A first metal layer, located on a side of the active layer, the gate electrode and the first insulating layer away from the substrate, the first metal layer comprising a source electrode, a drain electrode and a first metal wiring;

[0008] A first passivation layer is located on a side of the first metal layer facing away from the substrate;

[0009] A first organic layer is located on a side of the first passivation layer away from the substrate, the first organic layer is provided with a first via hole and a second via hole, an orthographic projection of the first via hole on the substrate at least partially intersects with an orthographic projection of the drain electrode on the substrate, and an orthographic projection of the second via hole on the substrate at least partially intersects with an orthographic projection of the first metal trace on the substrate;

[0010] The second passivation layer is located on the side of the first organic layer away from the substrate. The second passivation layer is provided with a third via and a fourth via. The third via is located at the first via. The third via penetrates the second passivation layer and the first passivation layer to expose a portion of the surface of the drain electrode. The fourth via is located at the second via. The fourth via penetrates the second passivation layer and the first passivation layer to expose a portion of the surface of the first metal trace.

[0011] In some embodiments, the control substrate further comprises a reflective layer, wherein the reflective layer is located between the first organic layer and the second passivation layer;

[0012] The reflective layer includes a shielding pattern, and an orthographic projection of the shielding pattern on the substrate includes an orthographic projection of the active layer on the substrate; and / or,

[0013] The reflective layer includes a first reflective ring, and the first reflective ring is arranged on a side wall of the first via hole; and / or,

[0014] The reflective layer includes a second reflective ring, and the second reflective ring is arranged on a side wall of the second via hole.

[0015] In some embodiments, the reflective layer includes a first sub-film layer, a second sub-film layer, and a third sub-film layer stacked in sequence. The material of the first sub-film layer and the third sub-film layer is a transparent material. The material of the first sub-film layer and the third sub-film layer both includes oxide, and the material of the second sub-film layer includes silver or aluminum.

[0016] In some embodiments,

[0017] The reflective layer comprises a first reflective ring, and the angle between the side wall of the first reflective ring and the plane parallel to the substrate is 45° to 75°; and / or,

[0018] The reflective layer comprises a second reflective ring, and an angle between a side wall of the second reflective ring and a plane parallel to the substrate is 45° to 75°.

[0019] In some embodiments, the control substrate further includes a shielding layer, the shielding layer is located between the first organic layer and the second passivation layer, and the orthographic projection of the shielding layer on the substrate includes the orthographic projection of the active layer on the substrate.

[0020] In some embodiments, the material of the first organic layer includes a black organic material.

[0021] In some embodiments, the control substrate also includes a second organic layer, which is located on the side of the second passivation layer facing away from the substrate, and the second organic layer is provided with a fifth via and a sixth via, and the orthographic projection of the third via on the substrate falls within the orthographic projection of the fifth via on the substrate, and the orthographic projection of the fourth via on the substrate falls within the orthographic projection of the sixth via on the substrate.

[0022] In some embodiments, the orthographic projection of the third via on the substrate falls within the orthographic projection of the first via on the substrate, and the orthographic projection of the fourth via on the substrate falls within the orthographic projection of the second via on the substrate.

[0023] In some embodiments, the first metal layer includes three stacked sub-metal layers, the middle sub-metal layer in the first metal layer is made of copper, the exposed surface of the drain electrode is made of copper, and the exposed surface of the first metal trace is made of copper.

[0024] In some embodiments,

[0025] The first insulating layer includes a first sub-insulating layer and a second sub-insulating layer which are stacked, the material of the first sub-insulating layer includes silicon nitride, the material of the second sub-insulating layer includes silicon oxide, and the second sub-insulating layer is close to the active layer; and / or,

[0026] The first passivation layer includes a first sub-passivation layer and a second sub-passivation layer which are stacked. The material of the first sub-passivation layer includes silicon oxide, the material of the second sub-passivation layer includes silicon nitride, and the first sub-passivation layer is close to the active layer.

[0027] In some embodiments, the material of the second passivation layer includes silicon nitride, and / or the thickness of the second passivation layer is greater than 8000 angstroms.

[0028] In some embodiments, the gate electrode is located on one side of the substrate, the first insulating layer is located on the side of the gate electrode away from the substrate, the active layer is located on the side of the first insulating layer away from the substrate, and the first metal layer is located on the side of the active layer away from the substrate.

[0029] In some embodiments, the control substrate also includes an etch stop layer, which is located between the first metal layer and the active layer. The orthographic projection of the etch stop layer on the substrate includes the orthographic projection of the channel region of the active layer on the substrate, and the channel region of the active layer is the active layer region between the source electrode and the drain electrode.

[0030] As a second aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a method for preparing a control substrate, comprising:

[0031] forming an active layer, a gate electrode and a first insulating layer on one side of the substrate;

[0032] Forming a first metal layer on the side of the active layer, the gate electrode and the first insulating layer away from the substrate, the first metal layer comprising a source electrode, a drain electrode and a first metal wiring;

[0033] depositing a first passivation layer on a side of the first metal layer facing away from the substrate;

[0034] Coating a first organic layer on a side of the first passivation layer facing away from the substrate, exposing and developing the first organic layer to form a first via hole and a second via hole, wherein an orthographic projection of the first via hole on the substrate at least partially intersects with an orthographic projection of the drain electrode on the substrate, and an orthographic projection of the second via hole on the substrate at least partially intersects with an orthographic projection of the first metal trace on the substrate;

[0035] depositing a second passivation layer on a side of the first organic layer facing away from the substrate;

[0036] The second passivation layer is etched to form a third via and a fourth via, wherein the third via is located in the first via, and the third via penetrates the second passivation layer and the first passivation layer to expose a portion of the surface of the drain electrode, and the fourth via is located in the second via, and the fourth via penetrates the second passivation layer and the first passivation layer to expose a portion of the surface of the first metal trace.

[0037] In some embodiments, before depositing the second passivation layer, the method further comprises:

[0038] forming a reflective layer on a side of the first organic layer facing away from the substrate,

[0039] Wherein, the reflective layer includes a shielding pattern, and the orthographic projection of the shielding pattern on the substrate includes the orthographic projection of the active layer on the substrate; and / or, the reflective layer includes a first reflective ring, and the first reflective ring is arranged on the side wall of the first via hole; and / or, the reflective layer includes a second reflective ring, and the second reflective ring is arranged on the side wall of the second via hole.

[0040] In some embodiments, etching the second passivation layer to form a third via hole and a fourth via hole includes:

[0041] Coating a second organic layer on a side of the second passivation layer facing away from the substrate, exposing and developing the second organic layer to form a fifth via hole and a sixth via hole, wherein the fifth via hole is located at the first via hole and the sixth via hole is located at the second via hole;

[0042] The second organic layer is used as a mask, and a dry etching process is used to etch the area exposed by the fifth via hole and the sixth via hole to form a third via hole and a fourth via hole.

[0043] As a third aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a light-emitting panel, characterized in that it includes the control substrate in any embodiment of the present disclosure, and the light-emitting panel device also includes a light-emitting diode chip, the light-emitting diode chip is coupled to the drain electrode exposed through the third via hole, and the light-emitting diode chip is also coupled to the first metal trace exposed through the fourth via hole.

[0044] The control substrate of the disclosed embodiment can be applied to the field of LED chips, and the exposed surface of the drain electrode and the exposed surface of the first metal trace can be used to bind and connect with the LED chip. The area of ​​the thin film transistor is much smaller than the area of ​​the driver IC, so the control substrate can be provided with more thin film transistors, which can drive more LED chips, reduce the spacing between LEDs, improve the resolution of the product, and meet the market demand for product resolution. In addition, the preparation process of thin film transistors is relatively mature, so the control substrate of the disclosed embodiment ensures a lower production cost while meeting a higher resolution.

[0045] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present disclosure will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments according to the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0047] Figure 1 is a cross-sectional schematic diagram of a control substrate in an embodiment of the present disclosure;

[0048] Figure 2 is a cross-sectional schematic diagram of a control substrate in another embodiment of the present disclosure;

[0049] Figure 3 is a cross-sectional schematic diagram of a control substrate in another embodiment of the present disclosure;

[0050] Figure 4 is a cross-sectional schematic diagram of a control substrate in another embodiment of the present disclosure;

[0051] Figure 5 is a cross-sectional schematic diagram of a control substrate in another embodiment of the present disclosure;

[0052] Figure 6 is a cross-sectional schematic diagram of a control substrate in another embodiment of the present disclosure;

[0053] Figure 7 is a schematic cross-sectional structure diagram of a control substrate in another embodiment of the present disclosure;

[0054] Figure 8a It is a schematic diagram of a control substrate after an active layer is formed in an embodiment of the present disclosure;

[0055] Figure 8bThis is a schematic diagram of a control substrate after a first metal layer is formed in an embodiment of the present disclosure;

[0056] Figure 8c This is a schematic diagram of a control substrate after forming a first organic layer according to an embodiment of the present disclosure;

[0057] Figure 8d This is a schematic diagram of a control substrate after a reflective layer is formed in an embodiment of the present disclosure;

[0058] Figure 8e This is a schematic diagram of a control substrate after a second passivation layer is formed in an embodiment of the present disclosure;

[0059] Figure 8f FIG. 1 is a schematic diagram of a control substrate after forming a second organic layer according to an embodiment of the present disclosure.

[0060] Description of reference numerals:

[0061] 11. substrate; 12. first insulating layer; 13. first passivation layer; 14. first organic layer; 141. first via; 142. second via; 151. reflection pattern / reflection layer; 152. first reflection ring; 153. second reflection ring; 16. second passivation layer; 161. third via; 162. fourth via; 17. second organic layer; 171. fifth via; 172. sixth via; 18. etching stop layer; 19. second insulating layer; 211. gate electrode; 22. active layer; 231. source electrode; 232. drain electrode; 233. first metal trace. DETAILED DESCRIPTION

[0062] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure, and different embodiments may be combined arbitrarily without conflict. Therefore, the drawings and descriptions are considered to be illustrative in nature and not restrictive.

[0063] The light emitting diode chip (LED chip) in the present disclosure may be a sub-millimeter light emitting diode (Mini Light Emitting Diode, referred to as Mini LED) chip, or may be a micro light emitting diode (Micro Light Emitting Diode, referred to as Micro LED) chip.

[0064] Herein, the source electrode and the drain electrode are used only to distinguish the two electrodes of the thin film transistor. It can be understood by those skilled in the art that the names of the source electrode and the drain electrode of the thin film transistor can be interchanged. For example, 231 refers to the source electrode, and 232 refers to the drain electrode; or, 231 refers to the drain electrode, and 232 refers to the source electrode.

[0065] Figure 1 is a cross-sectional schematic diagram of a control substrate in an embodiment of the present disclosure; Figure 2 is a cross-sectional schematic diagram of a control substrate in another embodiment of the present disclosure; Figure 3 is a cross-sectional schematic diagram of a control substrate in another embodiment of the present disclosure; Figure 4 is a cross-sectional schematic diagram of a control substrate in another embodiment of the present disclosure; Figure 5 is a cross-sectional schematic diagram of a control substrate in another embodiment of the present disclosure; Figure 6 FIG. 1 is a cross-sectional schematic diagram of a control substrate in another embodiment of the present disclosure. In one embodiment, Figure 1 to Figure 6 As shown, the control substrate may include a substrate 11 , an active layer 22 , a gate electrode 211 , a source electrode 231 , a drain electrode 232 , a first metal trace 233 , a first insulating layer 12 , a first passivation layer 13 , a first organic layer 14 and a second passivation layer 16 .

[0066] like Figure 1 to Figure 6 As shown, the active layer 22, the gate electrode 211 and the first insulating layer 12 are located on one side of the substrate 11. The first metal layer is located on the side of the active layer 22, the gate electrode 211 and the first insulating layer 12 that is away from the substrate 11, and the first metal layer includes a source electrode 231, a drain electrode 232 and a first metal wiring 233. The first passivation layer 13 is located on the side of the first metal wiring 233 that is away from the substrate 11.

[0067] The first organic layer 14 is located on the side of the first passivation layer 13 facing away from the substrate 11. The first organic layer 14 is provided with a first via 141 and a second via 142. The orthographic projection of the first via 141 on the substrate 11 at least partially intersects with the orthographic projection of the drain electrode 232 on the substrate 11, and the orthographic projection of the second via 142 on the substrate 11 at least partially intersects with the orthographic projection of the first metal trace 233 on the substrate 11.

[0068] The second passivation layer 16 is located on the side of the first organic layer 14 facing away from the substrate 11. The second passivation layer 16 is provided with a third via hole 161 and a fourth via hole 162. The third via hole 161 is located at the first via hole 141, and the third via hole 161 penetrates the second passivation layer 16 and the first passivation layer 13 to expose a portion of the surface of the drain electrode 232. The fourth via hole 162 is located at the second via hole 142, and the fourth via hole 162 penetrates the second passivation layer 16 and the first passivation layer 13 to expose a portion of the surface of the first metal trace 233.

[0069] Exemplarily, the thin film transistor may include an active layer 22 , a gate electrode 211 , a source electrode 231 , and a drain electrode 232 .

[0070] It should be noted that the control substrate in the embodiment of the present disclosure can be applied to the field of LED chips. In the control substrate, the partial surface of the drain electrode 232 exposed through the third via 161 and the partial surface of the first metal trace 233 exposed through the fourth via 162 can be used to bind and connect with the LED chip. For example, the partial surface of the drain electrode 232 exposed through the third via 161 can be bound and connected with the first pin of the LED chip, and the partial surface of the first metal trace 233 exposed through the fourth via 162 can be bound and connected with the second pin of the LED chip.

[0071] The control substrate of the disclosed embodiment uses a thin film transistor driving circuit to drive the LED chip, and no longer uses a driver IC. The area of ​​the thin film transistor is much smaller than the area of ​​the driver IC, so the control substrate can be provided with more thin film transistors, which can drive more LED chips, reduce the spacing between LEDs, improve the resolution of the product, and meet the market demand for product resolution. In addition, the preparation process of thin film transistors is relatively mature, so the control substrate of the disclosed embodiment will not lead to cost increases, and while meeting higher resolution, it ensures lower production costs.

[0072] Exemplarily, the material of the substrate 11 may include glass, for example, the material of the substrate 11 is glass.

[0073] In one embodiment, the second metal layer may include a gate electrode 211. The material of the second metal layer includes copper. Copper can reduce the resistance of the second metal layer. Exemplarily, the second metal layer includes a fourth sub-metal layer, a fifth sub-metal layer and a sixth sub-metal layer stacked in sequence. The material of the middle sub-metal layer, i.e., the fifth sub-metal layer, may include copper. For example, the material of the fifth sub-metal layer may be copper. The fourth sub-metal layer is close to the substrate 11.

[0074] Exemplarily, the material of the fourth sub-metal layer may include molybdenum, titanium, and nickel. For example, the fourth sub-metal layer may be MTD (molybdenum-titanium-nickel alloy). Exemplarily, the material of the sixth sub-metal layer may include molybdenum, titanium, and nickel. For example, the sixth sub-metal layer may be MTD (molybdenum-titanium-nickel alloy). Exemplarily, the second metal layer may be a three-layer structure of MTD / Cu / MTD.

[0075] Exemplarily, the material of the fourth sub-metal layer may include molybdenum (Mo) and niobium (Nb), for example, the fourth sub-metal layer may be a molybdenum-niobium alloy (MoNb). Exemplarily, the material of the sixth sub-metal layer may include molybdenum (Mo) and niobium (Nb), for example, the sixth sub-metal layer may be a molybdenum-niobium alloy (MoNb). Exemplarily, the second metal layer may be a three-layer structure of MoNb / Cu / MoNb.

[0076] The second metal layer adopts a laminated structure, and the copper metal layer is sandwiched between the fourth sub-metal layer and the fifth sub-metal layer, which can improve the adhesion between the second metal layer and the substrate 11, avoid copper diffusion, and avoid copper surface oxidation.

[0077] In one embodiment, the thickness of the fourth sub-metal layer may be in a range of 250 angstroms to 350 angstroms (including end values). For example, the thickness of the fourth sub-metal layer may be 300 angstroms.

[0078] In one embodiment, the thickness of the fifth sub-metal layer may range from 2800 angstroms to 3200 angstroms (including end points). For example, the thickness of the fifth sub-metal layer may be 3000 angstroms.

[0079] In one embodiment, the thickness of the sixth sub-metal layer may be in a range of 150 angstroms to 250 angstroms (including end values). Exemplarily, the thickness of the sixth sub-metal layer may be 200 angstroms.

[0080] In one embodiment, the material of the first insulating layer 12 may include at least one of silicon nitride (SiNx), silicon oxide (SiOx) and silicon oxynitride (SiON). Exemplarily, the first insulating layer 12 may be a three-layer structure of SiOx / SiON / SiNx or a two-layer structure of SiOx / SiNx. The SiN layer is close to the substrate 11, and the SiO layer is close to the active layer 22, so that SiO can supplement oxygen for the active layer 22. This can optimize the device structure.

[0081] Exemplarily, the first insulating layer 12 includes a first sub-insulating layer and a second sub-insulating layer which are stacked, the material of the first sub-insulating layer includes silicon nitride (SiNx), and the material of the second sub-insulating layer includes silicon oxide (SiOx). The second sub-insulating layer is close to the active layer 22. The thickness of the first sub-insulating layer may range from 2800 angstroms to 3200 angstroms (including the endpoint values). For example, the thickness of the first sub-insulating layer may be 3000 angstroms. Exemplarily, the thickness of the second sub-insulating layer ranges from 800 angstroms to 1200 angstroms (including the endpoint values). For example, the thickness of the second sub-insulating layer is 1000 angstroms.

[0082] In one embodiment, the material of the active layer 22 may include an oxide semiconductor or low temperature polysilicon (LTPS). For example, the material of the active layer 22 may be indium gallium zinc oxide (IGZO). The thickness of the active layer 22 may range from 500 angstroms to 700 angstroms (including the end values). For example, the thickness of the active layer 22 may be 600 angstroms.

[0083] Exemplarily, the material of the active layer 22 may be doped with tungsten (W), Ta or rare earth elements to improve the mobility of the device and thus improve product performance.

[0084] In one embodiment, the material of the first metal layer includes copper. The first metal layer may include a source electrode 231, a drain electrode 232, and a first metal trace 233. Copper can reduce the resistance of the trace in the first metal layer. Exemplarily, the first metal layer includes three sub-metal layers arranged in a stacked manner, and the material of the sub-metal layer in the middle includes copper. For example, the first metal layer includes a first sub-metal layer, a second sub-metal layer, and a third sub-metal layer arranged in a stacked manner. The material of the second sub-metal layer can be copper. The first sub-metal layer is close to the substrate 11.

[0085] Exemplarily, the material of the first sub-metal layer may include molybdenum, titanium, and nickel. For example, the first sub-metal layer may be MTD (molybdenum-titanium-nickel alloy). Exemplarily, the material of the third sub-metal layer may include molybdenum, titanium, and nickel. For example, the third sub-metal layer may be MTD (molybdenum-titanium-nickel alloy). Exemplarily, the first metal layer may be a three-layer structure of MTD / Cu / MTD.

[0086] Exemplarily, the material of the first sub-metal layer may include molybdenum (Mo) and niobium (Nb), for example, the first sub-metal layer may be a molybdenum-niobium alloy (MoNb). Exemplarily, the material of the third sub-metal layer may include molybdenum (Mo) and niobium (Nb), for example, the third sub-metal layer may be a molybdenum-niobium alloy (MoNb). Exemplarily, the first metal layer may be a two-layer structure of MoNb / Cu / MoNb.

[0087] The first metal layer adopts a laminated structure, and the copper metal layer is sandwiched between the first sub-metal layer and the second sub-metal layer, which can improve the adhesion between the first metal layer and the substrate 11, avoid copper diffusion, and avoid copper surface oxidation.

[0088] In one embodiment, the exposed surface of the drain electrode 232 is made of copper, and the exposed surface of the first metal wiring 233 is made of copper. That is, when the third via 161 and the fourth via 162 are formed by an etching process, over-etching can be performed, and the third sub-metal layer in the first metal layer can be etched away to expose the second sub-metal layer. As a result, the exposed surface of the drain electrode 232 is made of copper, and the exposed surface of the first metal wiring 233 is made of copper. This can reduce the binding resistance and improve the binding yield.

[0089] In one embodiment, the thickness of the first sub-metal layer may be in a range of 250 angstroms to 350 angstroms (including end values). Exemplarily, the thickness of the first sub-metal layer may be 300 angstroms.

[0090] In one embodiment, the second sub-metal layer may have a thickness ranging from 2500 angstroms to 3500 angstroms (including end points). For example, the second sub-metal layer may have a thickness of 3000 angstroms.

[0091] In one embodiment, the thickness of the third sub-metal layer may be in a range of 150 angstroms to 250 angstroms (including end values). Exemplarily, the thickness of the third sub-metal layer may be 200 angstroms.

[0092] In one embodiment, the material of the first passivation layer 13 may include at least one of silicon nitride (SiNx), silicon oxide (SiOx) and silicon oxynitride (SiON).

[0093] In one embodiment, the first passivation layer 13 may include a first sub-passivation layer and a second sub-passivation layer in a stacked arrangement. Exemplarily, the material of the first sub-passivation layer may include SiOx, and the material of the second sub-passivation layer may include SiNx. The first sub-passivation layer is close to the active layer 22, so that the SiOx in the first sub-passivation layer can supplement oxygen for the active layer 22.

[0094] In the case where the second sub-passivation layer includes SiNx, ammonia (NH 3 ), which is convenient for benchmarking the mass production lines in the existing technology and realizing mass production.

[0095] The first passivation layer 13 is made of SiNx instead of SiON. SiNx has better compactness, which is beneficial to improving the uniformity of the characteristics of the thin film transistor device.

[0096] For example, during the deposition of the first passivation layer 13 , the temperature is 230° C. to 290° C. Such a temperature can prevent bubbling of copper metal in the metal layer.

[0097] Exemplarily, the thickness of the first sub-passivation layer ranges from 2000 angstroms to 2800 angstroms (including the end values), for example, the thickness of the first sub-passivation layer can be 2400 angstroms. The thickness of the second sub-passivation layer can range from 300 angstroms to 700 angstroms (including the end values), for example, the thickness of the second sub-passivation layer can be 500 angstroms.

[0098] The material of the first organic layer 14 may be an organic resin, for example, the material of the first organic layer 14 may be JEM-608-SS. The thickness of the first organic layer 14 may range from 20,000 angstroms to 30,000 angstroms (including end values). For example, the thickness of the first organic layer 14 may be 25,000 angstroms. The first organic layer 14 may play a role in flattening and reducing parasitic capacitance. The first organic layer 14 may also effectively block the influence of external water vapor on device performance, thereby ensuring device characteristics.

[0099] In one embodiment, the material of the second passivation layer 16 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride. Exemplarily, the material of the second passivation layer 16 may include SiNx. SiNx material is relatively dense, which can protect the thin film transistor device from the influence of the external environment such as water and oxygen, and improve the stability of the thin film transistor device.

[0100] In one embodiment, if Figure 1 and Figure 3 As shown, the thickness of the second passivation layer 16 can be greater than 8000 angstroms. Therefore, the second passivation layer 16 can play a role of buffering and protection, and can prevent external water vapor from entering the substrate, thereby ensuring the performance of the thin film transistor device.

[0101] In one embodiment, if Figure 1 and Figure 2 As shown, the material of the first organic layer 14 includes black organic material. Such a first organic layer 14 can absorb stray light of the LED chip, prevent the light of the LED chip from irradiating the active layer 22 and affecting the malfunction of the thin film transistor, and ensure the device reliability of the thin film transistor.

[0102] In one embodiment, if Figure 4 As shown, the control substrate may further include a shielding layer 151, and the shielding layer 151 is located between the first organic layer 14 and the second passivation layer 16. The orthographic projection of the shielding layer 151 on the substrate 11 may include the orthographic projection of the active layer 22 on the substrate 11.

[0103] It should be noted that when the LED chip is bound and connected to the control substrate, the upper side of the control substrate is the light emitting side. The shielding layer 151 can shield the light emitted by the LED chip to prevent the light from the LED chip from irradiating the active layer 22 and causing the thin film transistor to malfunction. The material of the shielding layer 151 can be a metal with light shielding properties, or the material of the shielding layer 151 can be a metal with reflective properties. The material of the shielding layer 151 can be selected as needed, as long as it can prevent the light emitted by the LED chip from irradiating the active layer 22.

[0104] In one embodiment, if Figure 3 , Figure 5 and Figure 6 As shown, the control substrate may further include a reflective layer, and the reflective layer is located between the first organic layer 14 and the second passivation layer 16 .

[0105] Exemplarily, the reflective layer may include a shielding pattern 151 , and an orthographic projection of the shielding pattern 151 on the substrate 11 includes an orthographic projection of the active layer 22 on the substrate 11 .

[0106] It should be noted that when the LED chip is bound and connected to the control substrate, the upper side of the control substrate is the light emitting side. By setting the shielding pattern 151, the shielding pattern 151 can shield the active layer 22 of the thin film transistor to prevent the light of the LED chip from irradiating the active layer 22 and causing the thin film transistor to malfunction.

[0107] Exemplarily, the reflective layer may include a first reflective ring 152 , and the first reflective ring 152 is disposed on a sidewall of the first via hole 141 . For example, the reflective layer disposed on the sidewall of the first via hole 141 constitutes the first reflective ring 152 .

[0108] Exemplarily, the reflective layer may include a second reflective ring 153 , and the second reflective ring 153 is disposed on a sidewall of the second via hole 142 . For example, the reflective ring disposed on the sidewall of the second via hole 142 constitutes the second reflective ring 153 .

[0109] The first reflection ring 152 and the second reflection ring 153 can reflect the light generated by the LED to improve the light extraction efficiency of the LED.

[0110] In one embodiment, the angle between the side wall of the first via 141 and the plane parallel to the substrate 11 is 45° to 75° (including the endpoint values). Thus, the angle β between the side wall of the first reflection ring 152 and the plane parallel to the substrate 11 is 45° to 75° (including the endpoint values). The first reflection cup can reflect the light of the LED chip to improve the light extraction efficiency. By setting β to 45° to 75°, better light extraction efficiency can be obtained. Exemplarily, β can be one of 45°, 60°, 65°, 70°, and 75°.

[0111] After testing and verification, when β is 45°, the light collection efficiency of the first reflector cup is about 29.59%; when β is 60°, the light collection efficiency of the first reflector cup is about 31.02%; when β is 65°, the light collection efficiency of the first reflector cup is about 31.15%; when β is 70°, the light collection efficiency of the first reflector cup is about 31.18%; when β is 75°, the light collection efficiency of the first reflector cup is about 30.76%. The higher the light collection efficiency, the better the light output efficiency.

[0112] In one embodiment, the angle between the side wall of the second via 142 and the plane parallel to the substrate 11 is 45° to 75° (including the endpoint values). Thus, the angle β between the side wall of the second reflection ring 153 and the plane parallel to the substrate 11 is 45° to 75° (including the endpoint values). The second reflection cup can reflect the light of the LED chip to improve the light extraction efficiency. By setting β to 45° to 75°, better light extraction efficiency can be obtained. Exemplarily, β can be one of 45°, 60°, 65°, 70°, and 75°.

[0113] In one embodiment, the material of the reflective layer includes a material with high reflectivity such as silver (Ag) or aluminum (Al). Exemplarily, the reflective layer may include a first sub-film layer, a second sub-film layer, and a third sub-film layer stacked in sequence, the materials of the first sub-film layer and the third sub-film layer are transparent materials, the materials of the first sub-film layer and the third sub-film layer both include oxides, and the material of the second sub-film layer includes a material with high reflectivity such as silver (Ag) or aluminum (Al). Exemplarily, the materials of the first sub-film layer and the second sub-film layer include at least one of indium tin oxide (ITO) and indium zinc oxide (IZO). The material of the second sub-film layer includes silver or aluminum. In the reflective layer of this structure, the second sub-film layer is sandwiched between the first sub-film layer and the third sub-film layer, and the first sub-film layer and the third sub-film layer can protect the second sub-film layer, avoid oxidation of the second sub-film layer material, improve the adhesion between the reflective layer and the adjacent film layer, and avoid peeling problems caused by insufficient adhesion.

[0114] In one embodiment, the thickness of the first sub-layer may be in a range of 70 angstroms to 90 angstroms (including end points). For example, the thickness of the first sub-layer may be 80 angstroms.

[0115] In one embodiment, the thickness of the second sub-film layer may range from 900 angstroms to 1100 angstroms (including end points). For example, the thickness of the second sub-film layer may be 1000 angstroms.

[0116] In one embodiment, the thickness of the third sub-layer may be in a range of 70 angstroms to 90 angstroms (including end points). For example, the thickness of the third sub-layer may be 80 angstroms.

[0117] In one embodiment, if Figure 2 , Figures 4 to 6 As shown, the thickness of the second passivation layer 16 may range from 1300 angstroms to 1900 angstroms (including end values). For example, the thickness of the second passivation layer 16 may be 1600 angstroms.

[0118] In one embodiment, if Figure 2 , Figures 4 to 6 As shown, the control substrate may further include a second organic layer 17, and the second organic layer 17 is located on the side of the second passivation layer 16 facing away from the substrate 11. The second organic layer 17 is provided with a fifth via hole 171 and a sixth via hole 172. The orthographic projection of the third via hole 161 on the substrate 11 falls within the orthographic projection of the fifth via hole 171 on the substrate 11, and the orthographic projection of the fourth via hole 162 on the substrate 11 falls within the orthographic projection of the sixth via hole 172 on the substrate 11.

[0119] When the second passivation layer 16 is relatively thin, a second organic layer 17 may be provided. The second organic layer 17 is made of organic material and can play a role of buffering and protection. It can effectively block external water vapor, ensure the device characteristics of the thin film transistor, and help improve the bonding yield.

[0120] In one embodiment, the thickness of the second organic layer 17 is in the range of 20,000 angstroms to 30,000 angstroms (including end points). For example, the thickness of the second organic layer 17 may be 25,000 angstroms.

[0121] In one embodiment, the orthographic projection of the third via hole 161 on the substrate 11 falls within the orthographic projection of the first via hole 141 on the substrate 11, and the orthographic projection of the fourth via hole 162 on the substrate 11 falls within the orthographic projection of the second via hole 142 on the substrate 11. Thus, a portion of the second passivation layer 16 is retained between the sidewall of the third via hole 161 and the sidewall of the first via hole 141, and between the sidewall of the fourth via hole 162 and the sidewall of the second via hole 142, as shown in FIG. Figure 1 to Figure 6 As shown, the retained second passivation layer 16 can prevent external water and oxygen from entering the substrate through the side wall, which is beneficial to improving the stability of the thin film transistor device.

[0122] In one embodiment, if Figure 1 to Figure 6 As shown, the thin film transistor in the control substrate can be a bottom-gate thin film transistor. Among them, the gate electrode 211 is located on one side of the substrate 11, and the first insulating layer 12 (which can be called a gate insulating layer) is located on the side of the gate electrode 211 away from the substrate 11. The active layer 22 is located on the side of the first insulating layer 12 away from the substrate 11, and the first metal layer is located on the side of the active layer 22 and the first insulating layer 12 away from the substrate 11. The use of a bottom-gate thin film transistor can reduce the process steps of the control substrate and reduce costs.

[0123] Figure 7 FIG. 1 is a schematic diagram of a cross-sectional structure of a control substrate in another embodiment of the present disclosure. Figure 7 As shown, the thin film transistor in the control substrate may also be a top-gate thin film transistor. The control substrate further includes a second insulating layer 19, and the active layer 22 may be located on one side of the substrate 11, and the second insulating layer 19 is located on the side of the active layer 22 away from the substrate 11. The gate electrode 211 is located on the side of the second insulating layer 19 away from the substrate 11, the first insulating layer 12 is located on the side of the gate electrode 211 away from the substrate 11, and the first metal layer is located on the side of the first insulating layer 12 away from the substrate 11. The source electrode 231 and the drain electrode 232 are connected to the active layer 22 through vias penetrating the first insulating layer 12 and the second insulating layer 19, respectively.

[0124] In one embodiment, if Figure 6As shown, the control substrate may further include an etch stop layer 18, and the etch stop layer 18 is located between the first metal layer and the active layer 22. The orthographic projection of the etch stop layer 18 on the substrate 11 includes the orthographic projection of the channel region of the active layer 22 on the substrate 11, and the channel region of the active layer 22 is the region of the active layer 22 between the source electrode 231 and the drain electrode 232.

[0125] It should be noted that during the etching process of forming the source electrode 231 and the drain electrode 232 , since the source electrode 231 and the drain electrode 232 are respectively overlapped with the active layer 22 , in order to prevent the etching from damaging the active layer 22 , a wet etching process is required to pattern the first metal layer. Figure 6 In the illustrated embodiment, an etching stopper layer 18 is provided, and the orthographic projection of the etching stopper layer 18 on the substrate 11 includes the orthographic projection of the channel region of the active layer 22 on the substrate 11, so that when the source electrode 231 and the drain electrode 232 are formed by an etching process, the active layer 22 will not be etched due to the blocking of the etching stopper layer 18. Therefore, a dry etching process can be used to etch the first metal layer and pattern the first metal layer. The dry etching process can reduce the size of the thin film transistor and further improve the resolution of the product.

[0126] The present disclosure also provides a method for preparing a control substrate, comprising:

[0127] An active layer 22, a gate electrode 211 and a first insulating layer 12 are formed on one side of the substrate 11;

[0128] A first metal layer is formed on the side of the active layer 22, the gate electrode 211 and the first insulating layer 12 facing away from the substrate 11, and the first metal layer includes a source electrode 231, a drain electrode 232 and a first metal wiring 233;

[0129] Depositing a first passivation layer 13 on the side of the first metal layer facing away from the substrate 11;

[0130] A first organic layer 14 is coated on a side of the first passivation layer 13 facing away from the substrate 11, and the first organic layer 14 is exposed and developed to form a first via hole 141 and a second via hole 142, wherein an orthographic projection of the first via hole 141 on the substrate 11 at least partially intersects with an orthographic projection of the drain electrode 232 on the substrate 11, and an orthographic projection of the second via hole 142 on the substrate 11 at least partially intersects with an orthographic projection of the first metal trace 233 on the substrate 11;

[0131] Depositing a second passivation layer 16 on the side of the first organic layer 14 facing away from the substrate 11;

[0132] The second passivation layer 16 is etched to form a third via 161 and a fourth via 162. The third via 161 is located in the first via 141. The third via 161 penetrates the second passivation layer 16 and the first passivation layer 13 to expose a portion of the surface of the drain electrode 232. The fourth via 162 is located in the second via 142. The fourth via 162 penetrates the second passivation layer 16 and the first passivation layer 13 to expose a portion of the surface of the first metal trace 233.

[0133] In one embodiment, before depositing the second passivation layer 16, the method further comprises:

[0134] A reflective layer is formed on the side of the first organic layer 14 facing away from the substrate 11.

[0135] The reflective layer includes a shielding pattern 151, and the orthographic projection of the shielding pattern 151 on the substrate 11 includes the orthographic projection of the active layer 22 on the substrate 11; and / or, the reflective layer includes a first reflective ring 152, and the first reflective ring 152 is arranged on the side wall of the first via hole 141; and / or, the reflective layer includes a second reflective ring 153, and the second reflective ring 153 is arranged on the side wall of the second via hole 142.

[0136] In one embodiment, etching the second passivation layer 16 to form the third via hole 161 and the fourth via hole 162 includes:

[0137] A second organic layer 17 is coated on a side of the second passivation layer 16 facing away from the substrate 11, and the second organic layer 17 is exposed and developed to form a fifth via hole 171 and a sixth via hole 172, wherein the fifth via hole 171 is located at the first via hole 141, and the sixth via hole 172 is located at the second via hole 142;

[0138] The second organic layer 17 is used as a mask, and a dry etching process is used to etch the areas exposed by the fifth via hole 171 and the sixth via hole 172 to form the third via hole 161 and the fourth via hole 162 .

[0139] In one embodiment, the control substrate further includes an etching stop layer 18, and an active layer 22, a gate electrode 211 and a first insulating layer 12 are formed on one side of the substrate 11, including:

[0140] A gate electrode 211 is formed on one side of the substrate 11;

[0141] forming a first insulating layer 12 on a side of the gate electrode 211 facing away from the substrate 11;

[0142] An active layer 22 is formed on a side of the first insulating layer 12 facing away from the substrate 11;

[0143] An etch stop layer 18 is formed on the side of the active layer 22 facing away from the substrate 11 , and the orthographic projection of the etch stop layer 18 on the substrate 11 includes the orthographic projection of the channel region of the active layer 22 on the substrate 11 . The channel region of the active layer 22 is the region of the active layer 22 between the source electrode 231 and the drain electrode 232 .

[0144] Below through Figure 5 The preparation process of the control substrate of the illustrated embodiment further illustrates the technical solution of the disclosed embodiment. It is understandable that the "patterning" mentioned herein includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist when the patterned material is an inorganic material or metal, and includes processes such as mask exposure and development when the patterned material is an organic material. The evaporation, deposition, coating, and coating mentioned herein are all mature preparation processes in the relevant technology.

[0145] An active layer 22, a gate electrode 211, and a first insulating layer 12 are formed on one side of the substrate 11. Exemplarily, this step may include: depositing a second metal film on one side of the substrate 11, patterning the second metal film to form the gate electrode 211; depositing a first insulating film on a side of the gate electrode 211 facing away from the substrate 11, patterning the first insulating film to form the first insulating layer 12; depositing an active film on a side of the first insulating layer 12 facing away from the substrate 11, patterning the active film to form the active layer 22, such as Figure 8a As shown, Figure 8a This is a schematic diagram of a control substrate after an active layer is formed according to an embodiment of the present disclosure.

[0146] A first metal layer is formed on the side of the active layer 22, the gate electrode 211 and the first insulating layer 12 facing away from the substrate 11, and the first metal layer includes a source electrode 231, a drain electrode 232 and a first metal wiring 233. This step may include: depositing a first metal film on the side of the active layer 22 facing away from the substrate 11, patterning the first metal film, and forming a first metal layer, the first metal layer including a source electrode 231, a drain electrode 232 and a first metal wiring 233, such as Figure 8b As shown, Figure 8b This is a schematic diagram of a control substrate after forming a first metal layer in an embodiment of the present disclosure. In this embodiment, before depositing the first metal film, the substrate does not need to be pre-cleaned, thereby avoiding residual water vapor during the tape-out process and avoiding copper bubbling problems when depositing the first metal film.

[0147] The first passivation layer 13 is deposited on the side of the first metal layer facing away from the substrate 11. For example, the first passivation layer 13 may be a first sub-passivation layer and a second sub-passivation layer arranged in a stacked manner, wherein the material of the first sub-passivation layer includes silicon oxide, and the material of the second sub-passivation layer includes silicon nitride. In the process of depositing the first passivation layer 13, a silicon oxide film is first deposited as the first sub-passivation layer, and then a silicon nitride film is deposited on the silicon oxide film as the second sub-passivation layer. Ammonia NH is added during the deposition of the silicon nitride film. 3 The temperature during the deposition of the first passivation layer 13 is 230°C to 290°C.

[0148] A first organic layer 14 is coated on a side of the first passivation layer 13 facing away from the substrate 11, and the first organic layer 14 is exposed and developed to form a first via hole 141 and a second via hole 142, wherein the orthographic projection of the first via hole 141 on the substrate 11 at least partially intersects with the orthographic projection of the drain electrode 232 on the substrate 11, and the orthographic projection of the second via hole 142 on the substrate 11 at least partially intersects with the orthographic projection of the first metal trace 233 on the substrate 11, as shown in FIG. Figure 8c As shown, Figure 8c It is a schematic diagram of a control substrate after forming a first organic layer according to an embodiment of the present disclosure.

[0149] A reflective layer is formed on the side of the first organic layer 14 facing away from the substrate 11. This step may include: depositing a reflective film on the side of the first organic layer 14 facing away from the substrate 11, and patterning the reflective film to form a reflective layer. The reflective layer includes a shielding pattern 151, a first reflective ring 152, and a second reflective ring 153. The orthographic projection of the shielding pattern 151 on the substrate 11 includes the orthographic projection of the active layer 22 on the substrate 11. The first reflective ring 152 is disposed on the side wall of the first via hole 141. The second reflective ring 153 is disposed on the side wall of the second via hole 142. Figure 8d As shown, Figure 8d It is a schematic diagram of a control substrate after a reflective layer is formed according to an embodiment of the present disclosure.

[0150] A second passivation film is deposited on the side of the reflective layer away from the substrate 11 as the second passivation layer 16. Figure 8e As shown, Figure 8e This is a schematic diagram of a control substrate after a second passivation layer is formed according to an embodiment of the present disclosure.

[0151] The second passivation layer 16 is etched to form a third via hole 161 and a fourth via hole 162. This step may include:

[0152] A second organic layer 17 is coated on the side of the second passivation layer 16 facing away from the substrate 11, and the second organic layer 17 is exposed and developed to form a fifth via hole 171 and a sixth via hole 172. The fifth via hole 171 is located at the first via hole 141, and the sixth via hole 172 is located at the second via hole 142. Figure 8f As shown, Figure 8f FIG. 1 is a schematic diagram of a control substrate after forming a second organic layer according to an embodiment of the present disclosure.

[0153] The second organic layer 17 is used as a mask, and the area exposed by the fifth via hole 171 and the sixth via hole 172 is etched by a dry etching process to form a third via hole 161 and a fourth via hole 162. The third via hole 161 penetrates the second passivation layer 16 and the first passivation layer 13 to expose a portion of the surface of the drain electrode 232. The fourth via hole 162 penetrates the second passivation layer 16 and the first passivation layer 13 to expose a portion of the surface of the first metal trace 233, as shown in FIG. Figure 5 shown.

[0154] It should be noted that when the film layer includes a plurality of stacked sub-film layers, each sub-film layer can be deposited sequentially during the deposition process.

[0155] In one embodiment, the control substrate further includes an etching stopper layer 18. Before forming the first metal layer, the method for preparing the control substrate may further include: forming the etching stopper layer 18 on the side of the active layer 22 facing away from the substrate 11. Specifically, depositing an etching stopper film on the side of the active layer 22 facing away from the substrate 11, and patterning the etching stopper film to form the etching stopper layer 18. Figure 6 As shown, the orthographic projection of the etch stop layer 18 on the substrate 11 includes the orthographic projection of the channel region of the active layer 22 on the substrate 11 , and the channel region of the active layer 22 is the region of the active layer 22 between the source electrode 231 and the drain electrode 232 .

[0156] In one embodiment, the method for preparing the control substrate may further include: performing nickel-gold plating on the exposed surface of the drain electrode 232 and the exposed surface of the first metal wiring 233, or depositing CuNi or a nickel alloy on the exposed surface of the drain electrode 232 and the exposed surface of the first metal wiring 233. The nickel-gold layer or the nickel-copper layer or the nickel alloy on the exposed surface of the drain electrode 232 and the exposed surface of the first metal wiring 233 can play an anti-oxidation role and improve the bonding yield.

[0157] In one embodiment, the method for preparing the control substrate may further include: coating white ink on the surface of the control substrate. The white ink can improve light extraction efficiency and protect each film layer.

[0158] The LED chip is placed on the control substrate through a die bonding process, and two pins of the LED chip are respectively bound and connected to the exposed surface of the drain electrode 232 and the exposed surface of the first metal trace 233. Then, the LED chip is sealed and protected.

[0159] The embodiment of the present disclosure also provides a light-emitting panel, including the control substrate in any embodiment of the present disclosure, and also including a light-emitting diode chip. The light-emitting diode chip is coupled to the drain electrode 232 exposed through the third via hole 161, and the light-emitting diode chip is also coupled to the first metal trace 233 exposed through the fourth via hole 162.

[0160] The light-emitting panel in the embodiment of the present disclosure can be assembled in a display device as a display panel, or can be assembled in a display device as a light source. The display device can be: electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigators, wearable display devices, and any other products or components with display functions.

[0161] The light-emitting panel in the embodiment of the present disclosure can also be used as a light source in lighting products.

[0162] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0163] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0164] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0165] In the present disclosure, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being “above”, “above”, and “above” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0166] The disclosure above provides many different embodiments or examples to implement different structures of the present disclosure. In order to simplify the present disclosure, the components and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present disclosure. In addition, the present disclosure can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0167] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of various changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A control substrate, characterized in that: include: substrate; An active layer, a gate electrode and a first insulating layer are located on one side of the substrate; A first metal layer, located on a side of the active layer, the gate electrode and the first insulating layer away from the substrate, the first metal layer comprising a source electrode, a drain electrode and a first metal wiring; A first passivation layer, located on a side of the first metal layer away from the substrate; a first organic layer, located on a side of the first passivation layer away from the substrate, the first organic layer being provided with a first via hole and a second via hole, the orthographic projection of the first via hole on the substrate at least partially intersecting with the orthographic projection of the drain electrode on the substrate, and the orthographic projection of the second via hole on the substrate at least partially intersecting with the orthographic projection of the first metal trace on the substrate; a second passivation layer, located on a side of the first organic layer away from the substrate, the second passivation layer being provided with a third via hole and a fourth via hole, the third via hole being located at the first via hole, the third via hole penetrating the second passivation layer and the first passivation layer to expose a portion of the surface of the drain electrode, the fourth via hole being located at the second via hole, the fourth via hole penetrating the second passivation layer and the first passivation layer to expose a portion of the surface of the first metal wiring; The control substrate further includes a reflective layer, which is located between the first organic layer and the second passivation layer; the reflective layer includes a first reflective ring, which is arranged on the side wall of the first via hole; and / or the reflective layer includes a second reflective ring, which is arranged on the side wall of the second via hole.

2. The control substrate according to claim 1, characterized in that: The reflective layer includes a shielding pattern, and an orthographic projection of the shielding pattern on the substrate includes an orthographic projection of the active layer on the substrate.

3. The control substrate according to claim 2, characterized in that: The reflective layer includes a first sub-film layer, a second sub-film layer and a third sub-film layer which are stacked in sequence. The first sub-film layer and the third sub-film layer are made of transparent materials. The first sub-film layer and the third sub-film layer both include oxides. The second sub-film layer includes silver or aluminum.

4. The control substrate according to claim 2, characterized in that: The reflective layer comprises a first reflective ring, wherein the angle between the side wall of the first reflective ring and a plane parallel to the substrate is 45° to 75°; and / or, The reflective layer includes a second reflective ring, and an angle between a side wall of the second reflective ring and a plane parallel to the substrate is 45° to 75°.

5. The control substrate according to claim 1, characterized in that: The control substrate further includes a shielding layer, wherein the shielding layer is located between the first organic layer and the second passivation layer, and an orthographic projection of the shielding layer on the substrate includes an orthographic projection of the active layer on the substrate.

6. The control substrate according to claim 1, characterized in that: The material of the first organic layer includes black organic material.

7. The control substrate according to claim 1, characterized in that: The control substrate also includes a second organic layer, which is located on the side of the second passivation layer away from the substrate. The second organic layer is provided with a fifth via and a sixth via. The orthographic projection of the third via on the substrate falls within the orthographic projection of the fifth via on the substrate, and the orthographic projection of the fourth via on the substrate falls within the orthographic projection of the sixth via on the substrate.

8. The control substrate according to claim 1, characterized in that: The orthographic projection of the third via hole on the substrate falls within the orthographic projection of the first via hole on the substrate, and the orthographic projection of the fourth via hole on the substrate falls within the orthographic projection of the second via hole on the substrate.

9. The control substrate according to claim 1, characterized in that: The first metal layer includes three stacked sub-metal layers, the middle sub-metal layer in the first metal layer is made of copper, the exposed surface of the drain electrode is made of copper, and the exposed surface of the first metal trace is made of copper.

10. The control substrate according to claim 1, characterized in that: The first insulating layer includes a first sub-insulating layer and a second sub-insulating layer which are stacked, the first sub-insulating layer is made of silicon nitride, the second sub-insulating layer is made of silicon oxide, and the second sub-insulating layer is close to the active layer; and / or, The first passivation layer includes a first sub-passivation layer and a second sub-passivation layer which are stacked. The material of the first sub-passivation layer includes silicon oxide, the material of the second sub-passivation layer includes silicon nitride, and the first sub-passivation layer is close to the active layer.

11. The control substrate according to claim 1, characterized in that: The material of the second passivation layer includes silicon nitride, and / or the thickness of the second passivation layer is greater than 8000 angstroms.

12. The control substrate according to any one of claims 1 to 11, characterized in that: The gate electrode is located on one side of the substrate, the first insulating layer is located on a side of the gate electrode away from the substrate, the active layer is located on a side of the first insulating layer away from the substrate, and the first metal layer is located on a side of the active layer away from the substrate.

13. The control substrate according to claim 12, characterized in that: The control substrate also includes an etch stop layer, which is located between the first metal layer and the active layer. The orthographic projection of the etch stop layer on the substrate includes the orthographic projection of the channel region of the active layer on the substrate, and the channel region of the active layer is the active layer region between the source electrode and the drain electrode.

14. A method for preparing a control substrate, characterized in that: include: forming an active layer, a gate electrode and a first insulating layer on one side of the substrate; Forming a first metal layer on a side of the active layer, the gate electrode and the first insulating layer away from the substrate, wherein the first metal layer includes a source electrode, a drain electrode and a first metal wiring; Depositing a first passivation layer on a side of the first metal layer facing away from the substrate; Coating a first organic layer on a side of the first passivation layer facing away from the substrate, exposing and developing the first organic layer to form a first via hole and a second via hole, wherein an orthographic projection of the first via hole on the substrate at least partially intersects with an orthographic projection of the drain electrode on the substrate, and an orthographic projection of the second via hole on the substrate at least partially intersects with an orthographic projection of the first metal trace on the substrate; depositing a second passivation layer on a side of the first organic layer facing away from the substrate; Etching the second passivation layer to form a third via hole and a fourth via hole, wherein the third via hole is located in the first via hole, the third via hole penetrates the second passivation layer and the first passivation layer to expose a portion of the surface of the drain electrode, and the fourth via hole is located in the second via hole, the fourth via hole penetrates the second passivation layer and the first passivation layer to expose a portion of the surface of the first metal trace; Before depositing the second passivation layer, the method further includes: forming a reflective layer on a side of the first organic layer facing away from the substrate, wherein the reflective layer includes a first reflective ring, and the first reflective ring is arranged on the side wall of the first via hole; and / or the reflective layer includes a second reflective ring, and the second reflective ring is arranged on the side wall of the second via hole.

15. The method according to claim 14, characterized in that The reflective layer includes a shielding pattern, and an orthographic projection of the shielding pattern on the substrate includes an orthographic projection of the active layer on the substrate.

16. The preparation method according to claim 14, characterized in that: The second passivation layer is etched to form a third via hole and a fourth via hole, comprising: Coating a second organic layer on a side of the second passivation layer away from the substrate, exposing and developing the second organic layer to form a fifth via hole and a sixth via hole, wherein the fifth via hole is located in the first via hole, and the sixth via hole is located in the second via hole; The second organic layer is used as a mask, and a dry etching process is used to etch the area exposed by the fifth via hole and the sixth via hole to form the third via hole and the fourth via hole.

17. A light-emitting panel, characterized in that: The light-emitting panel device comprises a control substrate as described in any one of claims 1 to 13, wherein the light-emitting panel device further comprises a light-emitting diode chip, wherein the light-emitting diode chip is coupled to the drain electrode exposed through the third via hole, and the light-emitting diode chip is also coupled to the first metal trace exposed through the fourth via hole.

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