A supercapacitor management circuit

Abstract

This invention relates to a supercapacitor management circuit. The input terminal is connected to port J1 of a charging device and ground port J2. The circuit includes a charging management circuit, a discharging management circuit, and a capacitor protection circuit. The charging management circuit and the discharging management circuit are respectively connected to port J1. The output terminal of the charging management circuit and the input terminal of the discharging management circuit are respectively connected to the capacitor protection circuit. The charging management circuit includes an ideal diode U4 and a voltage regulator U1. The ideal diode U4 and the voltage regulator U1 form a capacitor charging path. The voltage regulator U1 is connected to a resistor R26, and the two constitute a constant current source. The resistor R26 is connected to the capacitor protection circuit. The supercapacitor protection circuit includes multiple parallel capacitor protection units. Each capacitor protection unit includes a capacitor protection chip, a supercapacitor, and a power resistor. Compared with the prior art, this invention has advantages such as low voltage drop, low power consumption, and the ability to select two specifications of supercapacitors for charging protection.

Description

Technical Field

[0001] The present invention relates to the technical field of charge and discharge circuits, and in particular to a supercapacitor management circuit. Background Art

[0002] Typically, lower-power devices use lithium batteries as backup power sources. However, due to the complex operating environments of power equipment, supercapacitors are often used as backup power sources. In devices using supercapacitors as backup power sources, lithium batteries are significantly affected by temperature, and high-rate charge and discharge have a significant impact on battery life. Furthermore, the use of ordinary diodes or RGBTs in the circuit results in a large voltage drop, high power consumption, and a tendency to affect capacitor performance. Summary of the Invention

[0003] The purpose of the present invention is to provide a supercapacitor management circuit in order to overcome the above-mentioned defects in the prior art.

[0004] The purpose of the present invention can be achieved by the following technical solutions:

[0005] A supercapacitor management circuit, the input end of which is connected to the port J1 of the charging device and the ground port J2. The management circuit includes a charging management circuit, a discharge management circuit and a capacitor protection circuit. The charging management circuit and the discharge management circuit are respectively connected to the port J1, and the output end of the charging management circuit and the input end of the discharge management circuit are respectively connected to the capacitor protection circuit. The charging management circuit includes an ideal diode U4 and a voltage regulator U1. The ideal diode U4 and the voltage regulator U1 form a capacitor charging path. The voltage regulator U1 is connected to a resistor R26, and the two form a constant current source. The resistor R26 is connected to the capacitor protection circuit. The supercapacitor protection circuit includes multiple parallel capacitor protection units, each of which is provided with a capacitor protection chip, a supercapacitor and a power resistor.

[0006] The input pin of the ideal diode U4 is connected to port J1, and the drain pin, output pin, and VDD pin of the ideal diode U4 are respectively connected to the input pin and Vcon pin of the voltage regulator U1. The output pin of the voltage regulator U1 is connected in series with a resistor R26, and the input pin of the voltage regulator U1 is connected to a capacitor protection circuit.

[0007] The ideal diode U4 uses LTC4358, and the voltage regulator U1 uses LT3080 positive linear regulator. The input pins 1, 2, 3, and 4 of the ideal diode U4 are connected to port J1. The drain pin 15, output pin 9, and VDD pin 8 of the ideal diode U4 are respectively connected to the input pin and Vcon pin of the voltage regulator U1. The SET pin of the voltage regulator U1 is connected to the resistor R29, and the resistor R26 is connected in parallel with the resistor R29. A capacitor C1 is connected between the input pin and the output pin of the voltage regulator U1.

[0008] The discharge management circuit includes a low-power comparator U3, a diode controller IC9, a field-effect transistor Q3 and a field-effect transistor Q2. The low-power comparator U3 and the diode controller IC9 constitute a capacitor discharge path. The gate of the diode controller IC9 is connected to the gates of the field-effect transistor Q3 and the field-effect transistor Q2, respectively. The source of the field-effect transistor Q3 is connected to the source of the field-effect transistor Q2, and the source of IC9 is connected between the two. The input pin of IC9 is connected to the capacitor protection circuit. The input pin of the low-power comparator U3 is connected to the resistor R26 through the resistor R33 and is grounded through the resistor R31.

[0009] The low-power comparator U3 turns on or off the diode controller IC9 according to the voltage of port J1 and port J2. The diode controller IC9 and field-effect transistors Q3 and Q2 form an ideal diode unit. When the voltage between port J1 and port J2 or the voltage of the capacitor module is lower than the set value, the low-power comparator U3 cuts off the ideal diode composed of the diode controller IC9 and field-effect transistors Q3 and Q2. When the voltage between port J1 and port J2 or the voltage of the capacitor module is higher than the set value, the ideal diode U4 is enabled. The set voltage value is determined by the voltage divider of resistors R33 and R31.

[0010] The low-power comparator U3 adopts LTC1540, and the diode controller IC9 adopts LTC4359 diode controller. The Vss pin of the diode controller IC9 is connected to the drain of the field-effect transistor Q2 through the capacitor C23. The input pin IN+ of the low-power comparator U3 is connected to the resistor R26 through the resistor R33 and is grounded through the resistor R31. The output pin of the low-power comparator U3 is connected to the shutdown control pin SHDN of the diode controller IC9. The power pin V+ of the low-power comparator U3 is connected to the resistor R32, and the power pin V+ is also grounded through the capacitor C22 and the Zener diode D2 respectively; the input pin IN of the diode controller IC9 is connected to the capacitor protection circuit, and the Vss pin of the diode controller IC9 is connected to the drain of Q2 through the capacitor C23.

[0011] The input pin IN of the diode controller IC9 in the discharge management circuit is respectively connected to the capacitor protection chip of each capacitor protection unit, and the output pin of each capacitor protection chip is respectively connected to the power resistor. Each capacitor protection chip is also connected to a supercapacitor and a jumper resistor. The capacitor protection chip monitors the voltage across the corresponding supercapacitor in real time. When the voltage across the supercapacitor exceeds the safe value, discharge is performed through the power resistor.

[0012] Furthermore, the capacitor protection chip adopts the BW6101 capacitor protection chip.

[0013] Furthermore, a first jumper resistor is connected between the GND pin and the SEL pin of each BW6101 capacitor protection chip, the SEL pin of each BW6101 capacitor protection chip is connected to the VDD pin through a second jumper resistor, a supercapacitor is provided between the VDD pin and the GND pin of each BW6101 capacitor protection chip, and the LED pin of each BW6101 capacitor protection chip is connected to a light-emitting diode.

[0014] Furthermore, each BW6101 capacitor protection chip selects two specifications of supercapacitors for charging protection through the external pin SEL. When SEL is selected as a high level, the corresponding protection point is 2.65V. When the SEL level is selected as a low level, the corresponding protection point is 2.45V. When SEL is connected to a jumper resistor, the protection voltage is 2.65V. When this voltage is exceeded, the IOUT leakage of the BW6101 capacitor protection chip is connected to the port of the supercapacitor, and the supercapacitors are discharged through their respective power resistors. The discharge current is adjusted according to the resistance value of each resistor, and the corresponding light-emitting diodes are lit.

[0015] The supercapacitor management circuit provided by the present invention has at least the following advantages compared to the prior art:

[0016] 1) The switch of the present invention uses an ideal diode, which has a lower voltage drop and lower power consumption than ordinary diodes or RGBT tubes. The ideal diode is single-phase conductive, which can prevent the capacitor from self-discharging into the external circuit through the voltage regulator. By using the voltage regulator and resistor to form a constant current source, the current is limited by the resistance value of the resistor, which can achieve adjustable charging current and thus reduce power consumption.

[0017] 2) The design of the charge management circuit, discharge management circuit and capacitor protection circuit can actively implement capacitor charging overvoltage protection. The supercapacitor has a high discharge rate, a long life, and the ambient temperature has little effect on the capacitor performance, which can improve the battery life. In addition, two specifications of supercapacitors can be selected for charging protection. The charging protection voltage of supercapacitors of different specifications can be achieved through the level on the SEL pin of the BW6101 and can be expanded according to the voltage range.

[0018] 3) Using an ideal diode as a switch, the capacitor can be automatically charged and discharged without the need for a CPU. The circuit is simple and reliable, and the device cost is low.

[0019] 4) Charging current and voltage can be set by resistors for flexible application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of the structure of the supercapacitor management circuit in the embodiment;

[0021] Figure 2 Schematic diagram of the structure of the charging management circuit in the supercapacitor management circuit in the embodiment;

[0022] Figure 3 Schematic diagram of the structure of the discharge management circuit in the supercapacitor management circuit in the embodiment;

[0023] Figure 4 Schematic diagram of the structure of the capacitor protection circuit in the supercapacitor management circuit in the embodiment. DETAILED DESCRIPTION

[0024] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments described are only a portion of the embodiments of the present invention, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort should fall within the scope of protection of the present invention.

[0025] Example

[0026] The present invention relates to a supercapacitor management circuit, including a charging management circuit for charging a supercapacitor module, a discharge management circuit and a capacitor protection circuit. Figure 1 As shown in the figure, J1 is the port for connecting to the charging device, and J2 is the ground port. J1 connects the charging management circuit and the discharge management circuit, which are respectively connected to the capacitor protection circuit.

[0027] Specifically, the charging management circuit includes an ideal diode U4 and a voltage regulator U1. U1 and U4 form a capacitor charging path. As a preferred solution, U4 uses LTC4358 and U1 uses LT3080 positive linear regulator. The circuit is as follows: Figure 2As shown, U4's input pins 1, 2, 3, and 4 are connected to port J1. U4's drain pin 15, output pin 9, and VDD pin 8 are connected to U1's input pin IN and Vcon pin, respectively. Resistor R26 is connected in series with U1's output pin, and U1's SET pin is connected to resistor R29. Resistor R26 and resistor R29 are connected in parallel. Capacitor C1 is connected between U1's input and output pins. Furthermore, capacitor C1 is 10μF / 25V; resistor R29 has a resistance of 100kΩ. U4 is an ideal diode, conducting in one phase, to prevent the capacitor from self-discharge into the external circuit through U1. Voltage regulator U1 and resistor R26 form a constant current source, with the current limited by the resistance of resistor R26. A larger resistance reduces the current, while a reverse current increases.

[0028] The discharge management circuit includes a low-power comparator U3 and a diode controller IC9. U3 and IC9 form the capacitor discharge path. As a preferred solution, U3 uses LTC1540 and IC9 uses LTC4359 diode controller. The circuit is as follows Figure 3 As shown, U3's input pin IN+ is connected to resistor R26 via resistor R33 and to ground via resistor R31. U3's output pin OUT is connected to IC9's shutdown control pin SHDN. U3's power pin V+ is connected to resistor R32 and is also connected to ground via capacitor C22 and Zener diode D2. The gate of diode controller IC9 is connected to the gates of field-effect transistors Q3 and Q2, respectively. The source of field-effect transistor Q3 is connected to the source of field-effect transistor Q2, with the source of IC9 connected between them. IC9's input pin IN is connected to the capacitor protection circuit. IC9's Vss pin is connected to the drain of Q2 via capacitor C23. U3 turns IC9 on or off based on the port voltage. IC9, Q3, and Q2 form an ideal diode unit. When the port voltage or the capacitor module voltage falls below a set value, U3 shuts off the ideal diode formed by IC9, Q3, and Q2. When the voltage exceeds a set value, the ideal diode is enabled. The set voltage value is determined by the voltage divider between resistors R33 and R31.

[0029] The supercapacitor protection circuit includes six capacitors connected in parallel. Figure 4 As shown in the figure, the supercapacitor protection circuit mainly consists of multiple capacitor protection chips, supercapacitors, and power resistors. C12, C13, C14, C15, C16, and C17 are supercapacitors. IC2, IC3, IC4, IC5, IC6, and IC7 are capacitor protection chips (model BW6101). R19, R20, R21, R22, R23, and R24 are power resistors. R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, and R12 are jumper resistors (zero-ohm resistors).

[0030] The input pins IN of IC9 in the discharge management circuit are connected to the respective BW6101 capacitor protection chips, and the IOUT pins of each BW6101 capacitor protection chip are connected to power resistors. A jumper resistor (R1, R2, R3, R4, R5, R6) is connected between the GND and SEL pins of each BW6101 capacitor protection chip. The SEL pin of each BW6101 capacitor protection chip is also connected to the VDD pin via another jumper resistor (R7, R8, R9, R10, R11, R12). A supercapacitor is installed between the VDD and GND pins of each BW6101 capacitor protection chip. The LED pins of each BW6101 capacitor protection chip are connected to light-emitting diodes via 50-ohm resistors.

[0031] BW6101 monitors the voltage across the supercapacitor in real time. When the voltage across the capacitor exceeds the safe value, it discharges through the power resistor. R1, R2, R3, R4, R5, R6, R19, R20, R21, R22, R23, and R24 set the capacitor protection voltage value.

[0032] The BW6101 can be used to select two sizes of supercapacitors for charging protection via the external SEL pin. When SEL is selected as a high level, the corresponding protection point is 2.65V; when SEL is selected as a low level, the corresponding protection point is 2.45V. When SEL is connected to R7, R8, R9, R10, R11, and R12 respectively, the protection voltage is 2.65V. When this voltage is exceeded, the IOUT leakage of the BW6101 is connected to the supercapacitor port, and the supercapacitor is discharged through its respective discharge resistors R19, R20, R21, R22, R23, and R24. The discharge current is adjusted according to the resistance value of each resistor, and the corresponding LED is illuminated. When connected to R1, R2, R3, R4, R5, and R6, the protection voltage is set to 2.45V.

[0033] According to the connection relationship between the above-mentioned charging management circuit, discharge management circuit and capacitor protection circuit, when the voltage at the ports at both ends of J1 and J2 is higher than the voltage of the supercapacitor, the ports charge the supercapacitor; when it is lower than or close to the voltage of the supercapacitor module, the supercapacitor replenishes the power to the ports, thereby improving the transient response of the system.

[0034] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and such modifications or substitutions are intended to be within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A supercapacitor management circuit, characterized in that: The input end of the management circuit is connected to the port J1 of the charging device and the ground port J2. The management circuit includes a charging management circuit, a discharging management circuit and a capacitor protection circuit. The charging management circuit and the discharging management circuit are respectively connected to the port J1. The output end of the charging management circuit and the input end of the discharging management circuit are respectively connected to the capacitor protection circuit. The charging management circuit includes an ideal diode U4 and a voltage regulator U1. The ideal diode U4 and the voltage regulator U1 form a capacitor charging path. The voltage regulator U1 is connected to a resistor R26, and the two form a constant current source. The resistor R26 is connected to the capacitor protection circuit. The supercapacitor protection circuit includes a plurality of capacitor protection units connected in parallel, and each capacitor protection unit is provided with a capacitor protection chip, a supercapacitor and a power resistor. The discharge management circuit includes a low-power comparator U3, a diode controller IC9, a field effect transistor Q3 and a field effect transistor Q2. The low-power comparator U3 and the diode controller IC9 form a capacitor discharge path. The gate of the diode controller IC9 is respectively connected to the gates of the field effect transistor Q3 and the field effect transistor Q2. The source of the field effect transistor Q3 is connected to the source of the field effect transistor Q2, and the source of IC9 is connected between the two. The input pin of IC9 is connected to the capacitor protection circuit. The input pin of the low-power comparator U3 is connected to the resistor R26 through the resistor R33 and is grounded through the resistor R31. The low-power comparator U3 turns on or off the diode controller IC9 according to the voltage of the port J1 and the port J2. The diode controller IC9 and the field effect transistors Q3 and Q2 form an ideal diode unit. When the voltage between the port J1 and the port J2 or the super capacitor voltage is lower than the set value, the low-power comparator U3 cuts off the ideal diode formed by the diode controller IC9 and the field effect transistors Q3 and Q2. When the voltage between the port J1 and the port J2 or the super capacitor voltage is higher than the set value, the ideal diode U4 is enabled. The set value of the voltage is determined by the voltage division of the resistors R33 and R31. The low-power comparator U3 adopts LTC1540, and the diode controller IC9 adopts LTC4359 diode controller. The Vss pin of the diode controller IC9 is connected to the drain of the field effect tube Q2 through the capacitor C23. The input pin IN+ of the low-power comparator U3 is connected to the resistor R26 through the resistor R33 and is grounded through the resistor R31. The output pin of the low-power comparator U3 is connected to the shutdown control pin SHDN of the diode controller IC9. The power pin V+ of the low-power comparator U3 is connected to the resistor R32, and the power pin V+ is also grounded through the capacitor C22 and the voltage-stabilizing diode D2 respectively; the input pin IN of the diode controller IC9 is connected to the capacitor protection circuit, and the Vss pin of the diode controller IC9 is connected to the drain of Q2 through the capacitor C23; The input pin IN of the diode controller IC9 in the discharge management circuit is respectively connected to the capacitor protection chip of each capacitor protection unit, and the output pin of each capacitor protection chip is respectively connected to the power resistor. Each capacitor protection chip is also respectively connected to a supercapacitor and a jumper resistor. The capacitor protection chip monitors the voltage across the corresponding supercapacitor in real time. When the voltage across the supercapacitor exceeds the safety value, discharge is performed through the power resistor.

2. The supercapacitor management circuit according to claim 1, characterized in that: The input pin of the ideal diode U4 is connected to port J1, the drain pin, output pin and VDD pin of the ideal diode U4 are respectively connected to the input pin and Vcon pin of the voltage regulator U1, the output pin of the voltage regulator U1 is connected in series with resistor R26, and the input pin of the voltage regulator U1 is connected to a capacitor protection circuit.

3. The supercapacitor management circuit according to claim 2, characterized in that: The ideal diode U4 adopts LTC4358, the voltage regulator U1 adopts LT3080 positive linear regulator, the input pin of the ideal diode U4 is connected to port J1, the drain pin, output pin and VDD pin of the ideal diode U4 are respectively connected to the input pin and Vcon pin of the voltage regulator U1, the SET pin of the voltage regulator U1 is connected to resistor R29, resistor R26 is connected in parallel with resistor R29, and a capacitor C1 is connected between the input pin and the output pin of the voltage regulator U1.

4. The supercapacitor management circuit according to claim 1, characterized in that: The capacitor protection chip adopts the BW6101 capacitor protection chip.

5. The supercapacitor management circuit according to claim 4, characterized in that: A first jumper resistor is connected between the GND pin and the SEL pin of each BW6101 capacitor protection chip, the SEL pin of each BW6101 capacitor protection chip is connected to the VDD pin through a second jumper resistor, a super capacitor is provided between the VDD pin and the GND pin of each BW6101 capacitor protection chip, and the LED pin of each BW6101 capacitor protection chip is connected to a light emitting diode.

6. The supercapacitor management circuit according to claim 5, characterized in that: Each BW6101 capacitor protection chip selects two specifications of supercapacitors for charging protection through the external pin SEL. When SEL is selected as a high level, the corresponding protection point is 2.65V. When the SEL level is selected as a low level, the corresponding protection point is 2.45V. When SEL is connected to a jumper resistor, the protection voltage is 2.65v. When this voltage is exceeded, the IOUT leakage of the BW6101 capacitor protection chip is connected to the port of the supercapacitor, and the supercapacitors are discharged through their respective power resistors. The discharge current is adjusted according to the resistance value of each resistor, and the corresponding light-emitting diodes are lit.

Images