A clock data recovery circuit for half-rate data re-timing

Abstract

The application discloses a clock data recovery circuit for half-rate data re-timing, comprising a switched capacitor module, a filter capacitor, a two-stage differential ring oscillator, a clock buffer, a four same OR gate module and a re-timer module, wherein the switched capacitor module controls a sampling period and a sampling frequency by using input binary random data, samples a clock signal and outputs a sampling voltage signal; the filter capacitor filters the sampling voltage signal and outputs a control voltage; the two-stage differential ring oscillator generates four clock signals according to the control voltage; the clock buffer obtains the four square wave clock signals; the four same OR gate module outputs a double frequency clock signal and feeds back to the switched capacitor module; and the re-timer module samples binary random data according to two square wave clock signals. The application can significantly reduce power consumption, reduce area, save cost, and has good jitter performance of recovered clock and jitter tolerance performance of recovered data.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuit design, and particularly relates to a clock data recovery circuit for half-rate data retiming. BACKGROUND

[0002] At present, science and technology develop rapidly, and data throughput increases dramatically. In a data-driven world, the number of devices connected to the central system increases explosively, and the number of devices connected to the central system increases explosively, which will unprecedentedly increase the requirements for data throughput and communication bandwidth. At the same time, video data accounts for the highest proportion of total data, and the growth rate of video data is much higher than that of the number of devices. This undoubtedly puts forward requirements for data transmission rate, and the demand for a bandwidth improvement technology for a server system input / output interface transceiver is imminent. The clock data recovery (CDR) circuit located at the receiving end of the link is a key module for determining the bit error rate of the high-speed data interface system, which can recover the required clock signal from the data stream processed by the equalizer, and retime the data stream signal according to the recovered clock signal.

[0003] Multi-link wired transceivers must handle the clock distribution problem caused by the large chip module area when working in long interconnection, so it is necessary to avoid using inductors and capacitors and other devices in circuit design. At the same time, the energy efficiency of the wired transceiver is also a very important performance indicator. However, the CDR circuit usually needs to rely on an inductor-capacitor oscillator to achieve low clock jitter and a large-area loop filter to limit jitter. In addition, the traditional CDR circuit architecture also faces the contradiction between the recovery clock jitter performance and the recovery data jitter tolerance. SUMMARY

[0004] In order to solve the above problems in the prior art, the application provides a clock data recovery circuit for half-rate data retiming. The technical problems to be solved by the application are solved by the following technical scheme:

[0005] The application provides a clock data recovery circuit for half-rate data retiming, which comprises a switched capacitor module, a filter capacitor C2, a two-stage differential ring oscillator, a clock buffer, a four same OR gate module and a retimer module, wherein,

[0006] The switched capacitor module is connected to the four same OR gate module, and is used for controlling the sampling period and the sampling frequency by using the input binary random data, so as to sample the voltage of the clock signal fed back by the four same OR gate module and output a sampling voltage signal;

[0007] The filter capacitor C2 is connected to the output end of the switched capacitor module, and is used for filtering the sampling voltage signal and outputting a control voltage;

[0008] The two-stage differential ring oscillator is connected to the filter capacitor C2, and is used for generating four clock signals with a phase difference of 90° according to the control voltage;

[0009] The clock buffer is used for adjusting the duty cycle of the four clock signals, and obtaining four square wave clock signals with a phase difference of 90°;

[0010] The four same or gate modules are connected to the clock buffer, and are used for performing a same or operation on the four square wave clock signals, outputting a double-frequency clock signal and feeding back to the switched capacitor module;

[0011] The re-timer module is connected to the clock buffer, and is used for sampling input binary random data according to two square wave clock signals with a phase difference of 180° from the clock buffer, and outputting two recovered data.

[0012] In an embodiment of the present application, the switched capacitor module comprises a first switch S1, a sampling switch capacitor C1 and a second switch S2, wherein,

[0013] The first control end of the first switch S1 is connected to a first binary random data input end Din, and the second control end of the first switch S1 is connected to a second binary random data input end The input end of the first switch S1 is connected to the output end of the four same or gate modules;

[0014] The first end of the sampling switch capacitor C1 is connected to the output end of the first switch S1, and the second end of the sampling switch capacitor C1 is connected to a ground end;

[0015] The input end of the second switch S2 is connected to the output end of the first switch S1, the first control end of the second switch S2 is connected to the first binary random data input end Din, and the second control end of the second switch S2 is connected to the second binary random data input end The output end of the second switch S2 is connected to the filter capacitor C2;

[0016] The first binary random data Din and the second binary random data input end The output binary random data is a reverse signal.

[0017] In an embodiment of the present application, the first switch S1 comprises an NMOS transistor Mn1 and a PMOS transistor Mp1, wherein,

[0018] The drain of the NMOS transistor Mn1 and the source of the PMOS transistor Mp1 are connected to the output of the four same OR gate module, the gate of the PMOS transistor Mp1 is connected to the first binary random data input Din, and the gate of the NMOS transistor Mn1 is connected to the second binary random data input The source of the NMOS transistor Mn1 and the drain of the PMOS transistor Mp1 are both connected to the input of the second switch S2.

[0019] In an embodiment of the present application, the second switch S2 comprises an NMOS transistor Mn2 and a PMOS transistor Mp2, wherein,

[0020] The drain of the NMOS transistor Mn2 and the source of the PMOS transistor Mp2 are connected to the output of the first switch S1, the gate of the PMOS transistor Mp2 is connected to the second binary random data input The gate of the NMOS transistor Mn2 is connected to the first binary random data input Din, and the source of the NMOS transistor Mn2 and the drain of the PMOS transistor Mp2 are both connected to the filter capacitor C2.

[0021] In an embodiment of the present application, the filter capacitor C2 is connected between the output of the second switch S2 and the ground.

[0022] In an embodiment of the present application, the capacitance value of the sampling switch capacitor C1 is 20 fF, and the capacitance value of the filter capacitor C2 is 10 fF.

[0023] In an embodiment of the present application, the four same OR gate module comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, and a sixteenth MOS transistor M16, wherein,

[0024] The gate of the fourth MOS M4, the gate of the seventh MOS M7, the gate of the tenth MOS M10 and the gate of the thirteenth MOS M13 are connected to the first clock output end A1 of the clock buffer 103; the gate of the first MOS M1, the gate of the sixth MOS M6, the gate of the ninth MOS M9 and the gate of the fourteenth MOS M14 are connected to the second clock output end A2 of the clock buffer 103; the gate of the second MOS M2, the gate of the fifth MOS M5, the gate of the twelfth MOS M12 and the gate of the fifteenth MOS M15 are connected to the third clock output end A3 of the clock buffer 103; the gate of the third MOS M3, the gate of the eighth MOS M8, the gate of the eleventh MOS M11 and the gate of the sixteenth MOS M16 are connected to the third clock output end A4 of the clock buffer 103;

[0025] The source of the fifth MOS M5, the source of the sixth MOS M6, the source of the seventh MOS M7 and the source of the eighth MOS M8 are connected to the ground end, the drain of the fifth MOS M5 is connected to the source of the first MOS M1, the drain of the sixth MOS M6 is connected to the source of the second MOS M2, the drain of the seventh MOS M7 is connected to the source of the third MOS M3, and the drain of the eighth MOS M8 is connected to the source of the fourth MOS M4;

[0026] The source of the ninth MOS M9, the source of the tenth MOS M10, the source of the eleventh MOS M11 and the source of the twelfth MOS M12 are connected to the power supply end, the drain of the ninth MOS M9 is connected to the source of the thirteenth MOS M13, the drain of the tenth MOS M10 is connected to the source of the fourteenth MOS M14, the drain of the eleventh MOS M11 is connected to the source of the fifteenth MOS M15, and the drain of the twelfth MOS M12 is connected to the source of the sixteenth MOS M16;

[0027] The first MOS M1, the second MOS M2, the third MOS M3, the fourth MOS M4, the thirteenth MOS M13, the fourteenth MOS M14, the fifteenth MOS M15 and the sixteenth MOS M16 are connected to the output end VOUT of the four same AND gates.

[0028] In an embodiment of the present application, the re-timer module comprises a first re-timer DFF0 and a second re-timer DFF1, wherein,

[0029] The D input end of the first re-timer DFF0 is connected with the first binary random data input end Din, the clock negative phase input end of the first re-timer DFF0 is used for inputting the first square wave clock signal output by the clock buffer, the clock positive phase input end of the first re-timer DFF0 is used for inputting the third square wave clock signal output by the clock buffer, and the output end of the first re-timer DFF0 outputs the first half-rate random data Deven.

[0030] The D input end of the second re-timer DFF1 is connected with the first binary random data input end Din, the clock positive phase input end of the second re-timer DFF1 is used for inputting the first square wave clock signal output by the clock buffer, the clock negative phase input end of the second re-timer DFF1 is used for inputting the third square wave clock signal output by the clock buffer, and the output end of the second re-timer DFF1 outputs the second half-rate random data Dodd.

[0031] Compared with the prior art, the beneficial effects of the present application are that:

[0032] 1、The half-rate data re-timing clock data recovery circuit of the present application does not use the frequency discriminator loop, voltage-current converter and large-area filtering capacitor in the traditional phase-locked loop type clock data recovery circuit, so that the power consumption and noise area of the CDR circuit are effectively improved. The frequency discriminator in the present application uses a switched capacitor module to achieve, which can effectively reduce the power consumption and area of the frequency discriminator. At the same time, the switched capacitor module plays the role of frequency discriminator and equivalent resistance, and can obtain a large loop bandwidth independent of process voltage temperature (PVT). The multi-phase clock of the two-stage differential ring oscillator can compensate for the fixed phase shift for data re-timing. The clock frequency of this architecture is half of the data rate, which saves the frequency divider module and saves the additional demultiplexing power consumption. At the same time, using the switched capacitor module instead of the phase discriminator relieves the compromise between the recovered clock jitter performance and the recovered data jitter margin in the traditional phase-locked loop type CDR circuit.

[0033] 2、The present application proposes a four same XNOR gate structure, compared with the traditional XNOR gate structure, the four same XNOR gate structure of the present application considers the factor of clock matching, suppresses the influence of clock feedthrough, and at the same working frequency, compared with the traditional XNOR gate structure, the power consumption is obviously reduced, and a stable control voltage can be output.

[0034] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 is a structural schematic diagram of a half-rate data re-timing clock data recovery circuit provided by an embodiment of the present application;

[0036] Figure 2 is a circuit structure schematic diagram of a switched capacitor module provided by an embodiment of the present application;

[0037] Figure 3 is a specific circuit implementation schematic diagram of an XNOR gate in a clock data recovery circuit provided by an embodiment of the present application;

[0038] Figure 4 is an input and output frequency waveform schematic diagram of an XNOR gate in a clock data recovery circuit provided by an embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to further illustrate the technical means and effects taken by the present application to achieve the predetermined purposes, a half-rate data re-timing clock data recovery circuit according to the present application is described in detail below in combination with the accompanying drawings and specific embodiments.

[0040] The foregoing and other technical contents, features and effects of the present application can be clearly presented in the following detailed description of specific embodiments in combination with the accompanying drawings. Through the description of specific embodiments, the technical means and effects taken by the present application to achieve the predetermined purposes can be understood more deeply and specifically. However, the accompanying drawings are provided for reference and illustration only, and are not intended to limit the technical solutions of the present application.

[0041] It should be noted that in this document, relational terms such as first and second and the like can only be used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that the items or devices including a series of elements not only include those elements, but also include other elements not explicitly listed. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the item or device including the element.

[0042] Please refer to Figure 1 , Figure 1A structure diagram of a clock data recovery circuit for half-rate data re-timing is provided by an embodiment of the present application. The clock data recovery circuit comprises a switched capacitor module 101, a filter capacitor C2, a two-stage differential ring oscillator 102, a clock buffer 103, a four same OR gate module 104 and a re-timer module 105, wherein the switched capacitor module 101 is connected to the four same OR gate module 104, for controlling a sampling period and a sampling frequency by using input binary random data, sampling a clock signal fed back by the four same OR gate module 104 to output a sampling voltage signal; the filter capacitor C2 is connected to an output end of the switched capacitor module 101, for filtering the sampling voltage signal and outputting a control voltage; the two-stage differential ring oscillator 102 is connected to the filter capacitor C2, for generating four clock signals according to the control voltage, and each clock signal has a phase difference of 90°; the clock buffer 103 is used for adjusting a duty cycle of the four clock signals to obtain four square wave clock signals with a phase difference of 90°; the four same OR gate module 104 is connected to the clock buffer 103, for performing two-by-two same OR processing on the four square wave clock signals to output a double-frequency clock signal and feed it back to the switched capacitor module 101, specifically, the first square wave clock signal is subjected to same OR processing with the second square wave clock signal, and the third square wave clock signal is subjected to same OR processing with the fourth square wave clock signal; the re-timer module 105 is connected to the clock buffer 103, for sampling the input binary random data according to two square wave clock signals with a phase difference of 180° from the clock buffer 103 to output two recovered data.

[0043] Specifically, the switch capacitor module 101 is connected with four same or gate modules 104, for voltage sampling of the clock signal fed back by the four same or gate modules 104, and outputting the sampled voltage signal value to the filter capacitor C2. The filter capacitor C2 receives the sampled voltage signal from the switch capacitor module 101, and forms an RC low-pass filter with the equivalent resistance of the switch capacitor module 101, thereby achieving the function of filtering the input sampled voltage signal, and outputting a control voltage with smaller ripple to the two-stage differential ring oscillator 102. The two-stage differential ring oscillator 102 receives the control voltage output by the filter capacitor C2, and generates four clock signals with corresponding frequencies according to the control voltage, wherein each clock signal has a phase difference of 90°. The clock buffer 103 is connected with the two-stage differential ring oscillator 102, for providing a direct current bias voltage for the four clock signals and adjusting the duty cycle of the four clock signals, so as to adjust the four clock signals to have a duty cycle of 50%, i.e., output the four clock signals in the form of square waves, and maintain the phase difference of the four square wave clock signals to be 90°, and output the four square wave clock signals to the four same or gate modules 104. Among them, the two clock signals with a phase difference of 180° are simultaneously sent to the two re-timer modules for sampling the two binary random data in the re-timer module, and two recovered data are output.

[0044] The four square wave signals with a phase difference of 90° are sent to the four same or gate modules 104, and after four-phase quadrature input and exclusive or processing, the clock feedthrough phenomenon is suppressed, and a double-frequency clock signal is output and fed back to the switch capacitor module 101. The half-rate clock signal is recovered, and the power consumption is greatly reduced. The clock recovery circuit for half-rate data re-timing realizes the functions of recovering the clock of the input random data signal at half rate and obtaining two recovered data.

[0045] Further, the switch capacitor module 101 of the embodiment includes a first switch S1, a sampling switch capacitor C1, and a second switch S2, wherein a first control end of the first switch S1 is connected with a first binary random data input end Din, a second control end of the first switch S1 is connected with a second binary random data input end Din, an input end of the first switch S1 is connected with an output end of the four same or gate modules (104), a first end of the sampling switch capacitor C1 is connected with an output end of the first switch S1, a second end of the sampling switch capacitor C1 is connected with a ground end, an input end of the second switch S2 is connected with the output end of the first switch S1, a first control end of the second switch S2 is connected with the first binary random data input end Din, and a second control end of the second switch S2 is connected with the second binary random data input end Din. Further, the switch capacitor module 101 of the embodiment includes a first switch S1, a sampling switch capacitor C1, and a second switch S2, wherein a first control end of the first switch S1 is connected with a first binary random data input end Din, a second control end of the first switch S1 is connected with a second binary random data input end Din, an input end of the first switch S1 is connected with an output end of the four same or gate modules (104), a first end of the sampling switch capacitor C1 is connected with an output end of the first switch S1, a second end of the sampling switch capacitor C1 is connected with a ground end, an input end of the second switch S2 is connected with the output end of the first switch S1, a first control end of the second switch S2 is connected with the first binary random data input end Din, and a second control end of the second switch S2 is connected with the second binary random data input end Din. The output end of the second switch S2 is connected with a filter capacitor C2; a first binary random data Din and a second binary random data The emitted binary random data is a reverse signal.

[0046] Further, please refer to Figure 2 , Figure 2 is a circuit structure schematic diagram of a switch capacitor module provided by an embodiment of the present application. The first switch S1 includes an NMOS tube Mn1 and a PMOS tube Mp1, wherein the drain of the NMOS tube Mn1 and the source of the PMOS tube Mp1 are connected with the output end of the four same or gate module 104, the gate of the PMOS tube Mp1 is connected with the first binary random data input end Din, and the gate of the NMOS tube Mn1 is connected with the second binary random data input end The source of the NMOS tube Mn1 and the drain of the PMOS tube Mp1 are both connected with the input end of the second switch S2.

[0047] The second switch S2 includes an NMOS tube Mn2 and a PMOS tube Mp2, wherein the drain of the NMOS tube Mn2 and the source of the PMOS tube Mp2 are connected with the output end of the first switch S1, the gate of the PMOS tube Mp2 is connected with the second binary random data input end The gate of the NMOS tube Mn2 is connected with the first binary random data input end Din, and the source of the NMOS tube Mn2 and the drain of the PMOS tube Mp2 are both connected with the filter capacitor C2. The filter capacitor C2 is connected between the output end of the second switch S2 and the ground end.

[0048] In other embodiments, the switch capacitor module 101 can also be a gate voltage bootstrap switch or other appropriate switch.

[0049] Specifically, the clock data recovery circuit of the embodiment can effectively reduce the power consumption and parasitic effects of ring oscillation, buffer and data retiming, etc. Replacing the phase detector with the switch capacitor module 101 of the embodiment can achieve a large loop bandwidth. The capture range of the filter capacitor is large, the use of the frequency discriminator is eliminated, and the area and power consumption are reduced.

[0050] The -3dB loop bandwidth of the clock data recovery circuit of the embodiment is irrelevant to PVT, and only related to the ratio of the switch capacitor C1 and the filter capacitor C2. The switch is implemented by using a transmission gate, and the on-resistance thereof is about 700Ω. The sampling switch capacitor C1 is 20fF, and the filter capacitor C2 is 10fF, so that a larger bandwidth is obtained to suppress the jitter of the voltage-controlled oscillator (VCO) and the NOR gate. The large loop bandwidth can not only achieve a higher jitter tolerance, but also suppress the jitter performance of the low-power two-stage differential ring oscillator. The large loop bandwidth alleviates the contradiction between the recovered clock jitter and the recovered data jitter tolerance in the traditional CDR structure, so that the lock-in time is shorter. The power consumption of the sampling switch capacitor is mainly related to the power supply voltage VDD, the parasitic gate capacitance and the clock frequency (i.e. the random data rate of Din and Compared with the traditional current mode logic (CML), D-type flip-flop (DFF) and phase detector (PD), the power consumption can be obviously reduced. Moreover, due to the large loop bandwidth and the low-pass filter composed of the equivalent switch resistance and the filter capacitor C2, the clock jitter caused by the non-ideal factors such as leakage current, charge injection, clock feedthrough and KT / C noise is small, and the phase noise of the low-power loop oscillator is suppressed. Therefore, by using the switch capacitor-based frequency discriminator, the power consumption can be effectively reduced, the area can be reduced, and the loop bandwidth irrelevant to PVT can be obtained.

[0051] The two-stage differential ring oscillator 102 of the embodiment is composed of the differential delay unit of the two-stage inverter latch. The clock buffer 103 is an ac-coupled resistance feedback self-biased inverter, which provides the direct current level and duty cycle correction, and is followed by a one-stage inverter to further improve the gain. The quadrature clock output has four buffers.

[0052] Further, the re-timer module 105 of the embodiment includes a first re-timer DFF0 and a second re-timer DFF1. The D input end of the first re-timer DFF0 is used to input the binary random data, the clock negative phase input end of the first re-timer DFF0 is connected to the first square wave clock signal output by the clock buffer 103, the clock positive phase input end of the first re-timer DFF0 is connected to the third square wave clock signal output by the clock buffer 103, and the output end of the first re-timer DFF0 outputs the first half-rate random data Deven. The D input end of the second re-timer DFF1 is used to input the binary random data, the clock positive phase input end of the second re-timer DFF1 is connected to the first square wave clock signal output by the clock buffer 103, the clock negative phase input end of the second re-timer DFF1 is connected to the third square wave clock signal output by the clock buffer 103, and the output end of the second re-timer DFF1 outputs the second half-rate random data Dodd.

[0053] The retiming module 105 of the embodiment can meet the needs of high speed and low power consumption, and can complete the data retiming function of the half-rate CDR. At a working frequency of 10GHz, the proposed retiming module 105 only consumes an average current of 40uA, and is suitable for various sub-rate data retiming structures.

[0054] Further, referring to Figure 3 , Figure 3 is a specific circuit implementation schematic diagram of the four same AND gate in the clock data recovery circuit provided by the embodiment of the application. The four same AND gate includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, and a sixteenth MOS transistor M16.

[0055] The gate of the fourth MOS transistor M4, the gate of the seventh MOS transistor M7, the gate of the tenth MOS transistor M10, and the gate of the thirteenth MOS transistor M13 are all connected to the first clock output end A1 of the clock buffer 103; the gate of the first MOS transistor M1, the gate of the sixth MOS transistor M6, the gate of the ninth MOS transistor M9, and the gate of the fourteenth MOS transistor M14 are all connected to the second clock output end A2 of the clock buffer 103; the gate of the second MOS transistor M2, the gate of the fifth MOS transistor M5, the gate of the twelfth MOS transistor M12, and the gate of the fifteenth MOS transistor M15 are all connected to the third clock output end A3 of the clock buffer 103; and the gate of the third MOS transistor M3, the gate of the eighth MOS transistor M8, the gate of the eleventh MOS transistor M11, and the gate of the sixteenth MOS transistor M16 are all connected to the fourth clock output end A4 of the clock buffer 103.

[0056] The sources of the fifth MOS transistor M5, the sixth MOS transistor M6, the seventh MOS transistor M7, and the eighth MOS transistor M8 are all connected to a ground end, the drain of the fifth MOS transistor M5 is connected to the source of the first MOS transistor M1, the drain of the sixth MOS transistor M6 is connected to the source of the second MOS transistor M2, the drain of the seventh MOS transistor M7 is connected to the source of the third MOS transistor M3, and the drain of the eighth MOS transistor M8 is connected to the source of the fourth MOS transistor M4.

[0057] The source of the ninth MOS M9, the source of the tenth MOS M10, the source of the eleventh MOS M11 and the source of the twelfth MOS M12 are connected to the power supply end, the drain of the ninth MOS M9 is connected to the source of the thirteenth MOS M13, the drain of the tenth MOS M10 is connected to the source of the fourteenth MOS M14, the drain of the eleventh MOS M11 is connected to the source of the fifteenth MOS M15, and the drain of the twelfth MOS M12 is connected to the source of the sixteenth MOS M16.

[0058] The first MOS M1, the second MOS M2, the third MOS M3, the fourth MOS M4, the thirteenth MOS M13, the fourteenth MOS M14, the fifteenth MOS M15 and the sixteenth MOS M16 are commonly connected to the output end VOUT of the four same or gates.

[0059] Specifically, the four-phase quadrature clock input or gate considers clock matching. Please refer to Figure 4 , Figure 4 is the schematic diagram of the input and output frequency waveforms of the or gate in the clock data recovery circuit provided by the embodiment of the application. The clock signals output by the A1, A2, A3 and A4 clock output ends are respectively pulse signal sources with a phase difference of 90°. In the conventional two-phase input or gate, when the rising or falling edge of the input signal comes, the gate of all the MOS tubes in the four or gate will have clock feedthrough effect, and the input signal is directly fed through to the VOUT node, which is obviously disadvantageous to the design of the overall clock data recovery circuit. Considering clock matching, the four-phase input or gate is proposed based on the conventional two-phase input or gate. The input signals of the four-phase input or gate are A1, A2, A3 and A4, A1 and A2 have a phase difference of 90°, A2 and A3 have a phase difference of 90°, A3 and A4 have a phase difference of 90°, and A4 and A1 have a phase difference of 90°. A1 and A2 are subjected to or logic processing, and A3 and A4 are subjected to or logic processing. Although the or logic processing of the two is the same, the influence of clock feedthrough can be eliminated.

[0060] As shown in Figure 3 , the left upper part A1 and A2 signal sources are orthogonally input to the gate end of the MOS tube. Even if clock feedthrough phenomenon occurs, when the rising and falling edge of the signal source comes, since the period of the signal sources A1 and A2 has a phase difference of 90°, the feedthrough voltage of the A1 and A2 signal sources to the output signal VOUT will offset each other, so that the output is stable and is not affected. This orthogonal input four or gate obviously reduces power consumption relative to the conventional or gate structure, and can output a stable control voltage VOUT, as shown in Figure 4The period of the output signal VOUT is half of the input signal source A1, A2, A3, A4, realizing the innovation of the half-rate clock recovery circuit architecture. The clock recovery circuit at half rate is greatly reduced in power consumption compared with the full-rate clock recovery circuit, and can effectively recover the clock and data.

[0061] The half-rate clock data recovery circuit of the embodiment of the present application does not use the frequency discriminator loop, voltage current converter and large area filter capacitor in the traditional phase-locked loop type clock data recovery circuit, so that the power consumption and noise area of the CDR circuit are effectively improved. The frequency discriminator in the present application is realized using a switched capacitor, which can effectively reduce the power consumption and area of the frequency discriminator. At the same time, the switched capacitor plays the role of the frequency discriminator and the equivalent resistance, and can obtain a large loop bandwidth independent of the process voltage temperature (PVT). The multi-phase clock of the two-stage differential ring oscillator can compensate for the fixed phase shift and be used for data re-timing. The clock frequency of this architecture is half of the data rate, which saves the frequency divider module and saves the additional demultiplexing power consumption. At the same time, the use of the switched capacitor instead of the phase discriminator alleviates the compromise between the recovered clock jitter performance and the recovered data jitter margin in the traditional phase-locked loop type CDR circuit. The embodiment of the present application proposes a four XNOR gate structure for half-rate data re-timing. Compared with the traditional XNOR gate structure, the four XNOR gate structure of the present application considers the clock matching factor, suppresses the influence of clock feedthrough, and significantly reduces the power consumption compared with the traditional XNOR gate structure at the same operating frequency, and can output a stable control voltage.

[0062] In summary, the clock data recovery circuit architecture of the half-rate data re-timing of the embodiment of the present application can significantly reduce the power consumption, reduce the area, save the cost, and has good jitter performance of the recovered clock and jitter margin performance of the recovered data.

[0063] In several embodiments provided by the present application, it should be understood that the apparatus and method disclosed by the present application can be implemented by other manners. For example, the apparatus embodiment described above is only schematic, for example, the division of the modules is only a logical function division, and actual implementation can have another division manner, for example, a plurality of modules or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0064] In addition, each function module in each embodiment of the present application can be integrated in a processing module, or each module can exist physically, or two or more modules can be integrated in one module. The above integrated module can be realized in the form of hardware or in the form of hardware plus software function module.

[0065] The above is further detailed description of the present application in combination with specific preferred embodiments, and cannot be deemed as limitation of the specific implementation of the present application to these descriptions. For those skilled in the art to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, and all should be deemed as falling within the protection scope of the present application.

Claims

1. A clock data recovery circuit for half-rate data re-timing, comprising: The switch capacitor module (101), the filter capacitor C2, the two-stage differential ring oscillator (102), the clock buffer (103), the four same or gate module (104) and the re-timer module (105) are connected, wherein, The switch capacitor module (101) is connected with the four same or gate module (104), and is used for controlling the sampling period and the sampling frequency by using the input binary random data, so as to sample the clock signal fed back by the four same or gate module (104) and output a sampling voltage signal; The filter capacitor C2 is connected at the output end of the switch capacitor module (101), and is used for filtering the sampling voltage signal and outputting a control voltage; The two-stage differential ring oscillator (102) is connected with the filter capacitor C2, and is used for generating four clock signals according to the control voltage, and the phase difference of each clock signal is 90°; The clock buffer (103) is used for adjusting the duty cycle of the four clock signals, and obtaining four square wave clock signals with the phase difference of 90°; The four same or gate module (104) is connected with the clock buffer (103), and is used for performing two-by-two same or processing on the four square wave clock signals, outputting a double-frequency clock signal and feeding back to the switch capacitor module (101); The re-timer module (105) is connected with the clock buffer (103), and is used for sampling the input binary random data according to the two square wave clock signals with the phase difference of 180° from the clock buffer (103), and outputting two recovered data; The switch capacitor module (101) comprises a first switch S1, a sampling switch capacitor C1 and a second switch S2, wherein, The first control end of the first switch S1 is connected with the first binary random data input end Din, the second control end of the first switch S1 is connected with the second binary random data input end Din, and the input end of the first switch S1 is connected with the output end of the four same OR gate module (104). , the first control end of the first switch S1 is connected with the first binary random data input end Din, the second control end of the first switch S1 is connected with the second binary random data input end Din, and the input end of the first switch S1 is connected with the output end of the four same OR gate module (104). The first end of the sampling switch capacitor C1 is connected at the output end of the first switch S1, and the second end of the sampling switch capacitor C1 is connected with the ground end; The input end of the second switch S2 is connected with the output end of the first switch S1, the first control end of the second switch S2 is connected with the first binary random data input end Din, the second control end of the second switch S2 is connected with the second binary random data input end Din, and the output end of the second switch S2 is connected with the filter capacitor C2. , the output end of the second switch S2 is connected with the filter capacitor C2. said first binary random data Din and said second binary random data input The emitted binary random data is an inverted signal. The four same or gate module (104) comprises a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M9, a tenth MOS tube M10, an eleventh MOS tube M11, a twelfth MOS tube M12, a thirteenth MOS tube M13, a fourteenth MOS tube M14, a fifteenth MOS tube M15 and a sixteenth MOS tube M16, wherein, The gate of the fourth MOS transistor M4, the gate of the seventh MOS transistor M7, the gate of the tenth MOS transistor M10 and the gate of the thirteenth MOS transistor M13 are all connected to the first clock output end A1 of the clock buffer 103; the gate of the first MOS transistor M1, the gate of the sixth MOS transistor M6, the gate of the ninth MOS transistor M9 and the gate of the fourteenth MOS transistor M14 are all connected to the second clock output end A2 of the clock buffer 103; the gate of the second MOS transistor M2, the gate of the fifth MOS transistor M5, the gate of the twelfth MOS transistor M12 and the gate of the fifteenth MOS transistor M15 are all connected to the third clock output end A3 of the clock buffer 103; the gate of the third MOS transistor M3, the gate of the eighth MOS transistor M8, the gate of the eleventh MOS transistor M11 and the gate of the sixteenth MOS transistor M16 are all connected to the third clock output end A4 of the clock buffer 103; The source of the fifth MOS transistor M5, the source of the sixth MOS transistor M6, the source of the seventh MOS transistor M7 and the source of the eighth MOS transistor M8 are all connected to the ground end, the drain of the fifth MOS transistor M5 is connected to the source of the first MOS transistor M1, the drain of the sixth MOS transistor M6 is connected to the source of the second MOS transistor M2, the drain of the seventh MOS transistor M7 is connected to the source of the third MOS transistor M3, and the drain of the eighth MOS transistor M8 is connected to the source of the fourth MOS transistor M4; The source of the ninth MOS transistor M9, the source of the tenth MOS transistor M10, the source of the eleventh MOS transistor M11 and the source of the twelfth MOS transistor M12 are all connected to the power supply end, the drain of the ninth MOS transistor M9 is connected to the source of the thirteenth MOS transistor M13, the drain of the tenth MOS transistor M10 is connected to the source of the fourteenth MOS transistor M14, the drain of the eleventh MOS transistor M11 is connected to the source of the fifteenth MOS transistor M15, and the drain of the twelfth MOS transistor M12 is connected to the source of the sixteenth MOS transistor M16; The first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, the thirteenth MOS transistor M13, the fourteenth MOS transistor M14, the fifteenth MOS transistor M15 and the sixteenth MOS transistor M16 are collectively connected to the output end VOUT of the four same AND gates.

2. The half-rate data re-timing clock data recovery circuit of claim 1, wherein, The first switch S1 includes an NMOS transistor Mn1 and a PMOS transistor Mp1, wherein, The drain of the NMOS transistor Mn1 and the source of the PMOS transistor Mp1 are connected to the output of the four same OR gate module (104), the gate of the PMOS transistor Mp1 is connected to the first binary random data input Din, the gate of the NMOS transistor Mn1 is connected to the second binary random data input Din The source of the NMOS transistor Mn1 and the drain of the PMOS transistor Mp1 are both connected to the input of the second switch S2.

3. The half-rate data re-timing clock data recovery circuit of claim 2, wherein, The second switch S2 includes an NMOS transistor Mn2 and a PMOS transistor Mp2, wherein, The drain of the NMOS transistor Mn2 and the source of the PMOS transistor Mp2 are connected to the output of the first switch S1, and the gate of the PMOS transistor Mp2 is connected to the second binary random data input The gate of the NMOS transistor Mn2 is connected to the first binary random data input Din, and the source of the NMOS transistor Mn2 and the drain of the PMOS transistor Mp2 are both connected to the filter capacitor C2.

4. The half-rate data retiming clock data recovery circuit of claim 1, wherein, The filter capacitor C2 is connected between the output end of the second switch S2 and the ground end.

5. The half-rate data retiming clock data recovery circuit of claim 1, wherein, The capacitance value of the sampling switch capacitor C1 is 20fF, and the capacitance value of the filter capacitor C2 is 10fF.

6. The half-rate data retiming clock data recovery circuit of any of claims 1 to 5, wherein, The re-timer module (105) includes a first re-timer DFF0 and a second re-timer DFF1, wherein, The first switch S1 includes an NMOS transistor Mn1 and a PMOS transistor Mp1, wherein, The second switch S2 includes an NMOS transistor Mn2 and a PMOS transistor Mp2, wherein, The filter capacitor C2 is connected between the output end of the second switch S2 and the ground end. The capacitance value of the sampling switch capacitor C1 is 20fF, and the capacitance value of the filter capacitor C2 is 10fF. The re-timer module (105) includes a first re-timer DFF0 and a second re-timer DFF1, wherein, The D input end of the first re-timer DFF0 is connected with the first binary random data input end Din, the clock negative phase input end of the first re-timer DFF0 is used for inputting the first square wave clock signal output by the clock buffer (103), the clock positive phase input end of the first re-timer DFF0 is used for inputting the third square wave clock signal output by the clock buffer (103), and the output end of the first re-timer DFF0 outputs the first half-rate random data Deven; The D input end of the second re-timer DFF1 is connected with the first binary random data input end Din, the clock positive phase input end of the second re-timer DFF1 is used for inputting the first square wave clock signal output by the clock buffer (103), the clock negative phase input end of the second re-timer DFF1 is used for inputting the third square wave clock signal output by the clock buffer (103), and the output end of the second re-timer DFF1 outputs the second half-rate random data Dodd.

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