Waveform digitizing analog front-end circuit suitable for low power supply voltage

Abstract

This invention provides a waveform digitization analog front-end circuit suitable for low power supply voltages. Its unit circuit includes a switched capacitor circuit, a buffer amplifier, and a comparator. The buffer amplifier consists of an amplifying transistor Mnt and a current source Ib. The input voltage signal Vin is connected to the gate of the sampling capacitor Cs via a sampling switch SW, and simultaneously connected to the gate of the amplifying transistor Mnt in the buffer amplifier. The other end of the sampling capacitor Cs is connected to signal ground. The drain of the buffer amplifier is connected to the power supply voltage VDD, and the source of the buffer amplifier is connected to the current source Ib and the negative input terminal of the comparator. The positive input terminal of the comparator is connected to the ramp voltage VRamp. This invention solves the problem of obtaining a large input dynamic range under low power supply voltage conditions, effectively alleviating the contradictions between power supply voltage, input dynamic range, linearity, accuracy, noise, and area.

Description

Technical Field

[0001] This invention belongs to the field of high-precision time measurement integrated circuits, specifically relating to a waveform digitization analog front-end circuit suitable for low power supply voltage. Background Technology

[0002] In applications such as 3D recognition, automotive LiDAR, nuclear medicine imaging, and particle physics, the requirements for the temporal resolution performance of detector systems are becoming increasingly stringent. Currently, the temporal resolution performance of high-performance detector systems has reached the picosecond level and is showing a further technological evolution trend towards the sub-picosecond level.

[0003] Compared to commonly used timing techniques such as single-threshold leading-edge timing, multi-threshold leading-edge timing, and constant-ratio timing, waveform sampling timing technology is generally considered to have superior time resolution performance. With the reduction in feature size of bulk silicon complementary metal-oxide-semiconductor (CMOS) processes, on the one hand, the intrinsic speed of devices becomes increasingly faster, which is highly beneficial for improving time resolution performance. However, on the other hand, the supply voltage also decreases accordingly, reducing the dynamic range that the detector system can handle. This lowers the achievable signal-to-noise ratio and severely limits further improvements in time resolution performance.

[0004] Waveform sampling techniques all feature a key analog front-end circuit, the core of which consists of a switched capacitor array, a buffer amplifier, and a comparator. This circuit enables high-speed signal acquisition and threshold comparison, thereby providing trigger signals for the back-end digital circuitry to perform signal over-comparison and quantization. Specifically, the switched capacitor array is used for high-speed signal acquisition, and the buffer amplifier transfers and amplifies the charge from each sampling capacitor, driving the comparator in voltage form for threshold comparison.

[0005] Existing waveform sampling techniques can be categorized into two types of analog front-end circuits: one is the shared buffer amplifier and comparator type, such as... Figure 1a As shown. Another type is the unitized buffer amplifier and comparator type, such as... Figure 1b As shown.

[0006] In a shared buffer amplifier and comparator type, all sampling capacitors (Cs) in a switched capacitor array (SCA) share a buffer amplifier (OPA) and a comparator (CMP). The output of the buffer amplifier is simultaneously connected to an analog-to-digital converter (ADC) for signal quantization. The comparator's output signal STOP is used to start the ADC, i.e., when the threshold voltage V... THWhen the output voltage of the buffer amplifier exceeds the voltage, the STOP signal becomes high, thus triggering the analog-to-digital converter as a trigger signal. This type occupies a small area, but generally requires an additional clock phase for resetting the buffer amplifier on the current buffer to avoid the interference of the charge on the sampling capacitor to be buffered in the next phase on the charge on the sampling capacitor to be buffered, thus reducing the signal readout speed and increasing the complexity of the control signal. In addition, since the distance of the buffer amplifier in each sampling capacitor is inconsistent, there is a large wiring parasitic capacitance at the virtual ground of the buffer amplifier, and the farther the distance from the buffer amplifier, the longer the wiring, and the larger the parasitic capacitance, thus requiring a larger bandwidth and greater power consumption of the buffer amplifier.

[0007] The unit buffer amplifier and comparator type, i.e., each sampling capacitor in the switched capacitor array has an independent buffer amplifier and a comparator. This type does not have the problems of the shared buffer amplifier and comparator type described above, but has the problem of occupying a relatively large area. Compared with the shared buffer amplifier and comparator type, this type can achieve better overall performance, and is therefore the mainstream direction of the development of waveform sampling technology.

[0008] Figure 2 For a typical unit buffer amplifier and comparator type currently available, a 1.2V power supply voltage can be used for power supply, and a 1V input dynamic range can be achieved. The circuit combines the buffer amplifier and the comparator into one by using a differential structure (the core of which is composed of a pair of differential pair tubes M1 and M2 and a tail current source Ib), and all functions of the analog front-end circuit are achieved by using a simple circuit. Moreover, compared with the shared buffer amplifier and comparator type, the additional area overhead is smaller, and it is a relatively ingenious design.

[0009] The working principle of the circuit is as follows:

[0010] When the sampling clock Φ WR，n is high, the sampling switch SW is turned on, and the voltage V in，SH on the sampling capacitor Cs changes with the input signal Vin, which is the sampling phase. When the sampling clock Φ WR，n is low, the sampling switch SW is turned off, and the sampling capacitor Cs maintains the voltage V′ in，SH at the moment when the switch is turned off, and the ramp voltage V Ramp begins to change linearly from its lower limit value V Ramp，L to its upper limit value V Ramp，H , which is the holding phase. When V Ramp exceeds V′ in，SH , the STOPn becomes low, which is a trigger signal for the subsequent circuit, used for latching the digital code and completing the quantization of V′ in，SH . It should be noted that V Ramp，LV Ramp，H V

[0011] Figure 2 The disadvantages of the circuit are as follows:

[0012] (1) The requirement for the process is strict: the sampling capacitor Cs of the circuit is realized by a metal-insulator-metal (MIM) capacitor, so the linearity of the capacitor is good. However, many CMOS processes do not provide MIM capacitors, in which case it is difficult to realize a large dynamic range of 1V under the condition of a 1.2V power supply voltage, and even if it can be realized, the linearity cannot be guaranteed.

[0013] (2) V Ramp，L The V Ramp，L is at least the sum of the threshold voltage of one M2 transistor and the overdrive voltage of one tail current source. It is difficult to realize a large dynamic range of 1V under the condition of a 1.2V power supply voltage.

[0014] (3) The comparator gain is small, the offset is large, and the offset is related to the input signal.

[0015] (4) The noise performance is poor. SUMMARY

[0016] To solve the above technical problems, improve the input signal dynamic range that can be processed by the waveform sampling technology under the condition of a low power supply voltage, and further improve the time resolution performance under the condition, thereby relieving the contradiction between the power supply voltage, the dynamic range, the sampling speed, the time resolution performance and the power consumption, the present application provides a waveform digitization analog front-end circuit suitable for a low power supply voltage, solves the problem of obtaining a large input dynamic range under the condition of a low power supply voltage, and well relieves the contradiction between the power supply voltage, the input dynamic range, the linearity, the precision, the noise and the area.

[0017] To achieve the above object, the technical scheme adopted by the present application is as follows:

[0018] The application discloses a waveform digitizing analog front-end circuit suitable for low power voltage, which is a unit buffer amplifier and comparator type, and a unit circuit of the application comprises a switch capacitor circuit, a buffer amplifier and a comparator; the buffer amplifier is composed of an amplifying tube Mnt and a current source Ib; an input voltage signal Vin is connected to a gate of a sampling capacitor Cs through a sampling switch SW, and is also connected to a gate of the amplifying tube Mnt of the buffer amplifier; the sampling switch SW is controlled by a sampling clock signal ΦWR,n, that is, when the signal is high, the sampling switch SW is closed; otherwise, the sampling switch SW is opened; the other end of the sampling capacitor Cs is connected to a signal ground; a drain of the buffer amplifier is connected to a power voltage VDD, a source of the buffer amplifier is connected to the current source Ib and a negative phase input end of the comparator, and a positive phase input end of the comparator is connected to a ramp voltage VRamp.

[0019] After the input voltage signal Vin is sampled through the sampling switch SW, a sampled voltage signal Vin,SH is formed at the gate of the sampling capacitor Cs, the sampled voltage signal Vin,SH is buffered and amplified by the amplifying tube Mnt of the buffer amplifier, and then an output voltage signal Vout,SF is output, and the output voltage signal Vout,SF is compared with the ramp voltage VRamp of the comparator, and finally a threshold-crossing logic signal STOPn of the unit circuit is output.

[0020] Further, the sampling capacitor Cs is an intrinsic MOS tube.

[0021] Further, the amplifying tube Mnt of the buffer amplifier is an intrinsic MOS tube, and is configured in the form of a source follower amplifier.

[0022] Further, the comparator is a rail-to-rail comparator, comprising two 5-tube operational amplifiers, wherein an N-type input 5-tube operational amplifier is composed of five MOS tubes M1, M2, M5, M6 and M7; a P-type input 5-tube operational amplifier is composed of five MOS tubes M3, M4, M8, M9 and M10; the output ends of the P-type input 5-tube operational amplifier and the N-type input 5-tube operational amplifier are connected at the gate of a MOS tube M12, the P-type input 5-tube operational amplifier and the N-type input 5-tube operational amplifier constitute a first stage, and a second stage is composed of the MOS tube M12 and a MOS tube M11; an output signal Vo1 of the P-type input 5-tube operational amplifier and the N-type input 5-tube operational amplifier is shaped by two inverters composed of M13-M16, and finally an output signal Vout is output.

[0023] Further, the sampling capacitor Cs is replaced by a gate parasitic capacitor of the amplifying tube Mnt.

[0024] Further, the sampling capacitor Cs, the amplification tube Mnt and the current source Ib are removed; the input voltage signal Vin is directly connected with the negative phase input end of the comparator through the sampling switch SW, and the parasitic capacitor of the negative phase input end of the comparator is used as the sampling capacitor Cs.

[0025] Further, the positive phase input end and the negative phase input end of the comparator can be interchanged.

[0026] Beneficial effects:

[0027] The present application has solved the problems of the prior art, and solved the problem of obtaining a large input dynamic range under the condition of low power supply voltage, and well relieved the contradiction between the power supply voltage, the input dynamic range, the linearity, the precision, the noise and the area.

[0028] In particular, the present application can realize a higher signal-to-noise ratio than the traditional technology under the condition of low power supply voltage, and effectively improve the time resolution performance, and effectively solve the contradiction between the high time resolution performance and the low power supply voltage, which is the most remarkable advantage of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1a Figure 1b It is an analog front-end circuit of two waveform sampling technologies in the prior art; wherein, Figure 1a It is a shared buffer amplifier and comparator type; Figure 1b It is a unit buffer amplifier and comparator type (only contains one unit circuit, and the subscript n represents the nth unit);

[0030] Figure 2 It is a specific circuit of an existing unit buffer amplifier and comparator type (only contains one unit circuit);

[0031] Figure 3 It is a schematic diagram of the unit circuit of the present application;

[0032] Figure 4 It is a possible implementation circuit of the comparator involved in the present application;

[0033] Figure 5a Figure 5b It is two expansion circuits of the present application; wherein, Figure 5a It is an expansion form 1; Figure 5b It is an expansion form 2. DETAILED DESCRIPTION

[0034] ​​In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application. In addition, the technical features involved in each embodiment of the present application described below can be combined with each other as long as they do not conflict with each other.

[0035] As shown in Figure 3 , the waveform digitizing analog front-end circuit suitable for low power supply voltage of the present application belongs to the type of unitized buffer amplifier and comparator, and the unit circuit thereof comprises a switched capacitor circuit, a buffer amplifier and a comparator (CMP). The buffer amplifier is composed of an amplifying tube Mnt and a current source Ib. The input voltage signal Vin is connected to the gate of the sampling capacitor Cs through the sampling switch SW, and is also connected to the gate of the amplifying tube Mnt of the buffer amplifier. The sampling switch SW is controlled by the sampling clock signal ΦWR,n, that is, when the signal is at a high level, the sampling switch SW is closed; otherwise, the sampling switch SW is opened. The other end of the sampling capacitor Cs is connected to the signal ground. The drain of the buffer amplifier is connected to the power supply voltage VDD, and the source of the buffer amplifier is connected to the current source Ib and the negative phase input end of the comparator, that is Figure 4 the Vinn end as shown. The positive phase input end of the comparator, that is Figure 4 the Vinp end, is connected to the ramp voltage VRamp.

[0036] After the input voltage signal Vin is sampled through the sampling switch SW, the sampled voltage signal Vin,SH is formed at the gate of the sampling capacitor Cs (which is also the gate of the amplifying tube Mnt of the buffer amplifier), and the sampled voltage signal Vin,SH is outputted as the voltage signal Vout,SF after being buffered and amplified by the amplifying tube Mnt of the buffer amplifier. The voltage signal Vout,SF is compared with the ramp voltage VRamp of the comparator, and finally the over-threshold logic signal STOPn of the present unit circuit is outputted. In the connection relationship, the positive phase input end and the negative phase input end of the comparator can be interchanged, and similar interchanges can be made in all the following circuit connection relationships involving the comparator.

[0037] Among them, the sampling capacitor Cs and the amplifying tube Mnt are realized by intrinsic MOS tubes, and the comparator is a rail-to-rail comparator. The amplifying tube Mnt is configured in the form of a source follower amplifier. A possible implementation circuit of the comparator of the present application is as shown in Figure 4As shown, this circuit includes two 5-transistor operational amplifiers. The N-type input 5-transistor operational amplifier consists of 5 MOS transistors (M1, M2, M5, M6, and M7); the P-type input 5-transistor operational amplifier consists of 5 MOS transistors (M3, M4, M8, M9, and M10). The outputs of these two operational amplifiers are connected to the gate of M12. In essence, this is a voltage comparator with a two-stage operational amplifier structure. The two 5-transistor operational amplifiers form the first stage, and the second stage consists of MOS transistors M12 and M11. The output signal Vo1 of this two-stage operational amplifier is shaped by two inverters (M13 to M16) to finally output the signal Vout. Under large input dynamic range conditions, this comparator circuit suffers from gain fluctuations.

[0038] The working principle of the waveform digitization analog front-end circuit of the present invention, suitable for low power supply voltage, is as follows:

[0039] At the sampling clock signal Φ WR，n When the voltage level is high, the sampled voltage signal V on the sampling capacitor Cs is... in，SH Following the input voltage signal Vin, the output voltage signal V of the buffer amplifier changes accordingly due to the use of intrinsic MOS. out，SF With V in，SH Consistent. At the sampling clock signal Φ WR，n When the voltage is low, the sampling capacitor Cs maintains the voltage V′ at the moment the sampling switch SW is open. in_SH Correspondingly, when the sampling switch SW is open, the output voltage of the buffer amplifier is V′. out，SF , and V′ out，SF With V′ in，SH Basically the same. At the same time, the ramp voltage V Ramp Start from its lower limit value V Ramp，L up to its upper limit V Ramp，H Linear change. When V Ramp More than V′ out，SF When STOPn goes high, it serves as a trigger signal for subsequent circuits, used to latch the digital code and complete the latching of V′. out，SF That is, for V′ in，SH Quantification.

[0040] The circuit features of the present invention for waveform digitization analog front-end circuits applicable to low power supply voltages include:

[0041] (1) The sampling capacitor Cs uses an intrinsic MOS transistor, which not only reduces the requirements for the process but also takes into account the linearity of the capacitor. The reason is that current CMOS processes generally use intrinsic MOS transistors. The characteristic of this type of transistor is that the active region is not heavily doped, and the intrinsic doping of the substrate is directly used as the active region. Therefore, the threshold voltage of the transistor is about 0V. Since the operating region of the intrinsic MOS transistor remains stable throughout the entire dynamic range, the capacitance value changes relatively stably with the gate voltage, thereby improving the linearity.

[0042] (2) The buffer amplifier uses intrinsic MOSFETs, which not only improves the driving capability and enhances the isolation effect, but also allows V to be... out，SF With V inSH The results are basically the same, which minimizes the drain on voltage margin caused by the amplifier tube.

[0043] (3) The comparator uses a rail-to-rail comparator, and uses the rail-to-rail voltage as part of the quantization circuit to compare V. out，SF Digital quantization is performed. Because the buffer amplifier uses intrinsic MOSFETs, it is possible to use a rail-to-rail comparator. That is, a rail-to-rail comparator can be constructed using a simple 5-transistor operational amplifier, such as... Figure 4 As shown, this makes the comparator threshold upper limit V Ramp，H Approaching the supply voltage, i.e., the upper limit of the supply voltage, and the lower threshold V. Ramp，L It is close to the power supply ground, that is, the lower rail of the supply voltage.

[0044] Because an intrinsic MOSFET is used as both the sampling capacitor and the amplifying transistor in the buffer amplifier, compared to existing circuits, such as... Figure 2 As shown, the leakage current phenomenon of this invention is more severe. The leakage current is mainly due to the small sampling capacitor and the long holding time, causing the charge on the sampling capacitor to gradually dissipate while maintaining the phase. This is a common problem in the analog front-end circuits of existing waveform sampling technologies. This invention also suffers from some adverse effects because the intrinsic MOSFET used cannot be turned off effectively.

[0045] Since existing waveform sampling techniques generally require calibration to improve linearity and accuracy, simple amplitude calibration can eliminate the leakage current problem caused by using intrinsic MOSFETs, and can also eliminate the gain fluctuation problem of comparators under large input dynamic range conditions.

[0046] like Figure 5a , Figure 5b As shown, the present invention can have the following two extended forms:

[0047] (1) Extended Form 1:

[0048] like Figure 5a As shown, compared toFigure 3 The expanded form 1 removes the sampling capacitor Cs and uses the gate parasitic capacitor of the amplifier Mnt as the sampling capacitor. Compared with the circuit shown in Figure 3 The expanded form 1 has the disadvantage of poor linearity. The expanded form 1 can be used in applications where the linearity is not very high.

[0049] (2) Expanded form 2:

[0050] As shown in Figure 5b Compared with the circuit shown in Figure 3 The expanded form 2 not only removes the sampling capacitor Cs but also removes the amplifier Mnt and the current source Ib of the buffer amplifier. The input signal Vin is directly connected to the negative phase input terminal of the comparator through a switch, and the parasitic capacitor of the negative phase input terminal of the comparator is used as the sampling capacitor Cs. Compared with the circuit shown in Figure 3 The expanded form 2 has the disadvantage of large absolute value of the sampling capacitor and large variation with the input voltage, thus poor linearity of the circuit, and the noise of the comparison deteriorates the sampling accuracy. More importantly, this circuit structure limits the analog bandwidth. The expanded form 2 can be used in applications where the analog bandwidth, linearity and accuracy are not very high.

[0051] Those skilled in the art will easily understand that the above description is only the preferred embodiment of the present application and is not intended to limit the present application. Any modification, equivalent replacement and improvement within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A waveform digitizing analog front end circuit suitable for low power supply voltage, characterized by: It is a single unit buffer amplifier and comparator type, which single unit circuit includes a switched capacitor circuit, a buffer amplifier and a comparator; the buffer amplifier is composed of an amplifying tube Mnt and a current source Ib; the input voltage signal Vin is connected to the gate of the sampling capacitor Cs through the sampling switch SW, and is also connected to the gate of the amplifying tube Mnt of the buffer amplifier; the sampling switch SW is controlled by the sampling clock signal ΦWR,n, that is, when the signal is high, the sampling switch SW is closed; otherwise, the sampling switch SW is opened; the other end of the sampling capacitor Cs is connected to the signal ground; the drain of the buffer amplifier is connected to the power supply voltage VDD, and the source of the buffer amplifier is connected to the current source Ib and the negative phase input end of the comparator, and the positive phase input end of the comparator is connected to the ramp voltage VRamp; After the input voltage signal Vin is sampled through the sampling switch SW, the sampled voltage signal Vin,SH is formed at the gate of the sampling capacitor Cs, and after the sampled voltage signal Vin,SH is buffered and amplified by the amplifying tube Mnt of the buffer amplifier, the output voltage signal Vout,SF is output, which is compared with the ramp voltage VRamp of the comparator, and finally the threshold crossing logic signal STOPn of the single unit circuit is output. The comparator is a rail-to-rail comparator, which includes two 5-tube operational amplifiers, wherein the N-type input 5-tube operational amplifier is composed of five MOS tubes M1, M2, M5, M6 and M7; the P-type input 5-tube operational amplifier is composed of five MOS tubes M3, M4, M8, M9 and M10; the output ends of the P-type input 5-tube operational amplifier and the N-type input 5-tube operational amplifier are connected at the gate of MOS tube M12, and the P-type input 5-tube operational amplifier and the N-type input 5-tube operational amplifier constitute the first stage, and the second stage is composed of MOS tube M12 and MOS tube M11; the output signal Vo1 of the P-type input 5-tube operational amplifier and the N-type input 5-tube operational amplifier is shaped by two inverters composed of M13-M16, and finally the output signal Vout is output.

2. The waveform digitizing analog front-end circuit suitable for low power supply voltage according to claim 1, characterized in that: The sampling capacitor Cs adopts an intrinsic MOS tube.

3. The waveform digitizing analog front-end circuit suitable for low power supply voltage according to claim 1, characterized in that: The amplifying tube Mnt of the buffer amplifier adopts an intrinsic MOS tube and is configured in the form of a source follower amplifier.

4. The waveform digitizing analog front-end circuit suitable for low power supply voltage according to claim 1, characterized in that: The gate parasitic capacitor of the amplifying tube Mnt is used to replace the sampling capacitor Cs.

5. The waveform digitizing analog front-end circuit suitable for low power supply voltage according to claim 1, characterized in that: The sampling capacitor Cs, the amplifying tube Mnt and the current source Ib are removed; the input voltage signal Vin is directly connected to the negative phase input end of the comparator through the sampling switch SW, and the parasitic capacitor of the negative phase input end of the comparator is used as the sampling capacitor Cs.

6. The waveform digitizing analog front-end circuit suitable for low power supply voltage according to claim 1, characterized in that: The positive phase input end and the negative phase input end of the comparator can be interchanged.

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