A memory testing method, device and computer equipment

Abstract

The application provides a memory test method applied to a processor, and the method comprises the following steps: determining a first virtual address of a breakpoint of a memory to be tested; resolving a physical address of the breakpoint according to the first virtual address of the breakpoint; saving the physical address of the breakpoint to a third-party memory; reading the physical address of the breakpoint from the third-party memory in the case of resuming the test; mapping a second virtual address according to the physical address of the breakpoint; starting the test from the second virtual address; and completing the test of the memory. The application saves the test progress in real time during the test, and the last memory test progress can be obtained after power-off and power-on again, so that the memory resuming test is realized. In the case that the test progress of each memory is inconsistent in the face of multiple parallel memory tests, the memory breakpoint resuming test is realized, and the resource waste and low test efficiency caused by the secondary test of the fault-free memory due to the empty test progress are avoided.

Description

Technical Field

[0001] This application relates to the field of memory testing technology, and in particular to a method, apparatus and computer device for memory testing. Background Technology

[0002] To meet the ever-increasing performance demands of processors, more and more memory is being configured, with ever-expanding capacities. As memory technology continues to advance and memory capacity increases, processors require memory stress testing throughout the supply chain to ensure stability at the time of shipment. The more memory and the larger the capacity, the longer the memory stress testing time becomes. Therefore, how to reduce memory stress testing time is a pressing issue that needs to be addressed. Summary of the Invention

[0003] To address the aforementioned problems, embodiments of this application provide a method, apparatus, and system computer device for memory testing.

[0004] Firstly, embodiments of this application provide a memory testing method applied to a processor. The method involves determining a first virtual address of the interrupt point of the memory under test; resolving the physical address of the interrupt point from the first virtual address; saving the physical address of the interrupt point to a third-party memory; in the case of continued testing, reading the physical address of the interrupt point from the third-party memory; mapping a second virtual address based on the physical address of the interrupt point; and starting the test from the second virtual address to complete the memory test. This application saves the test progress in real time during the test, allowing the previous memory test progress to be retrieved even after power-down and power-on, thus enabling continued memory testing. When facing multiple parallel memory tests with inconsistent test progress for each memory module, this method of resuming memory tests after an interrupt point avoids resource waste and low test efficiency caused by clearing the test progress during a second, fault-free memory test.

[0005] In some embodiments, determining the first virtual address of the interrupt point of the memory under test includes: determining the first virtual address of the current interrupt point of the memory under test in the event of a current test interruption, wherein the test interruption includes one of the following: operating system abnormality, memory error checking and correction (ECC) alarm, or processor processing failure. This allows the current test progress to be recorded after the CPU detects a memory fault or other faults during the memory test, such as abnormal restart or abnormal test interruption.

[0006] In some embodiments, memory testing includes multiple parallel memory tests, generating an address file based on the serial number (SN) information of the multiple memory modules. The SN information is used to identify each of the multiple memory modules. This allows for the labeling of each memory module when facing multiple parallel memory tests.

[0007] In some embodiments, the memory under test includes multiple memory modules. Determining the first virtual address of the breakpoint of the memory under test includes: acquiring the test address of each memory module in the multiple memory modules in real time; recording the test address of each memory module in an address file; and, in the event of a test interruption, obtaining the first virtual address of the breakpoint of each memory module based on the test address currently recorded in the address file. This allows for real-time acquisition of the current test address and recording of the test progress of each memory module when facing multiple parallel memory tests.

[0008] In some embodiments, the memory under test includes multiple memory modules. Determining the first virtual address of the breakpoint of the memory under test includes: identifying the memory modules that have completed the test among the multiple memory modules; and marking the first virtual addresses of all the memory modules that have completed the test as test completion identifiers. This allows for real-time acquisition of the current test address when facing multiple parallel memory tests, recording the test progress of each completed memory module, and avoiding resource waste and low test efficiency caused by secondary tests during continuation testing.

[0009] In some embodiments, resolving the physical address of an interrupt point from its first virtual address includes: obtaining the physical address of the interrupt point corresponding to the first virtual address based on a mapping table of first memory addresses; the mapping table of first memory addresses is used to record the mapping relationship between the physical address of the interrupt point and the first virtual address. In this way, the current test address Y can be obtained in real time and converted into a physical address through the memory address mapping table and stored in a third-party memory, achieving the purpose of recording the memory test address in real time.

[0010] In some embodiments, in the case of continued testing, reading the physical address of the interrupt point from a third-party storage includes: determining that the memory is in the case of continued testing based on the memory's serial number (SN) information matched through the address file; and in the case of continued testing, reading the physical address of the interrupt point from the third-party storage according to the memory's SN information. This ensures that the testing progress of each memory module can still be obtained during parallel memory testing, taking into account situations where new memory is replaced on the retested machine. It ensures that each memory module has been tested from start to finish, and covers various system failure scenarios including common errors, abnormal restarts, and test interruptions, ensuring that the corresponding memory test progress is saved.

[0011] In some embodiments, obtaining the second virtual address based on the physical address mapping of the interrupt point includes: obtaining the second virtual address corresponding to the physical address of the interrupt point according to a mapping table of second memory addresses; the mapping table of second memory addresses is used to record the mapping relationship between the physical address of the interrupt point and the second virtual address. This allows the physical address stored in a third-party memory to be processed into the virtual address required by the test script process during testing, and the content of the specified test start address X set in the test script to be replaced, so that the test process starts execution from the previous test interrupt address.

[0012] In some embodiments, if the memory's serial number (SN) information is not matched in the address file, it is determined that the memory is being tested anew. In the case of memory being tested anew, the test begins from the memory's entry address. This can accommodate situations where the machine being retested has had its memory replaced, ensuring that each memory module has been tested from start to finish.

[0013] Secondly, embodiments of this application provide a memory testing apparatus, comprising: a test progress saving module, used to determine a first virtual address of an interrupt point in the memory under test; resolve the physical address of the interrupt point based on the first virtual address; and save the physical address of the interrupt point to a third-party storage device. A test progress acquiring module, used to, in the event of continued testing, read the physical address of the interrupt point from the third-party storage device; map a second virtual address based on the physical address of the interrupt point; and start testing from the second virtual address to complete the memory test. Its beneficial effects are as described in the first aspect and will not be repeated here.

[0014] Thirdly, embodiments of this application provide an electronic device including a processor and a memory; the processor is configured to execute instructions stored in the memory to cause the electronic device to perform a method as described in any of the first aspects.

[0015] Fourthly, embodiments of this application provide a computer-readable storage medium including computer program instructions, which, when executed by a computer, enable the computer to perform the method as described in any of the first aspects.

[0016] Fifthly, embodiments of this application provide a computer program product containing instructions that, when executed by a computing device, cause the computing device to perform the method as described in any of the first aspects. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the various embodiments disclosed in this specification, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only a few embodiments disclosed in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] The accompanying drawings used in the description of the embodiments or prior art are briefly introduced below.

[0019] Figure 1 A system architecture diagram of the memory testing method provided in the embodiments of this application;

[0020] Figure 2 An interactive principle diagram of the memory testing method provided in the embodiments of this application;

[0021] Figure 3 A flowchart illustrating the memory testing method provided in this application embodiment;

[0022] Figure 4 This is a flowchart illustrating the memory testing method provided in Embodiment 1 of this application.

[0023] Figure 5 This is a flowchart of the interrupt point address resolution provided in Embodiment 2 of this application;

[0024] Figure 6 A flowchart of the memory testing method provided in Embodiment 3 of this application;

[0025] Figure 7 This is a schematic diagram of multiple memory parallel tests provided in Embodiment 4 of this application;

[0026] Figure 8 This is a schematic diagram illustrating the specific test progress of multiple memory units at the moment of memory failure, provided in Embodiment 4 of this application.

[0027] Figure 9 This is a schematic diagram of the test progress of each memory segment obtained from a third-party storage device, provided in Embodiment 4 of this application.

[0028] Figure 10 This is a schematic diagram of the test start address for each memory segment when resuming testing after a test interruption caused by a memory fault, as provided in Embodiment 4 of this application.

[0029] Figure 11 This is a schematic diagram of the test start address for each memory segment when resuming testing after a test interruption caused by a non-memory fault, as provided in Embodiment 4 of this application. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings.

[0031] In the description of the embodiments of this application, the words "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the words "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a specific manner.

[0032] In the description of the embodiments in this application, the term "and / or" is merely a description of the association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, B existing alone, and A and B existing simultaneously. Furthermore, unless otherwise stated, the term "multiple" means two or more. For example, multiple systems refer to two or more systems, and multiple terminals refer to two or more terminals.

[0033] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and their variations all mean "including but not limited to," unless otherwise specifically emphasized.

[0034] In the description of the embodiments in this application, "some embodiments" are mentioned, which describe a subset of all possible embodiments. However, it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0035] In the description of the embodiments of this application, the terms "first, second, third, etc." or module A, module B, module C, etc. are used only to distinguish similar objects and do not represent a specific ordering of objects. It is understood that, where permitted, a specific order or sequence can be interchanged so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0036] In the description of the embodiments of this application, the reference numerals for the steps, such as S110, S120, etc., do not necessarily indicate that the steps will be executed in this manner. Where permissible, the order of the steps can be interchanged or executed simultaneously.

[0037] In the description of the embodiments of this application:

[0038] Memory mapping is a mechanism that maps a file to a block of memory, mapping a part or the entire file of a file on disk to a range of addresses within the application's address space. The application can then access the file on disk in the same way as it accesses dynamic memory.

[0039] Virtual memory is a system memory management technique that makes applications believe they have a contiguous block of available memory—a single, complete address space. In reality, programs are typically fragmented into multiple physical memory segments, with some parts temporarily stored on external disk storage, and data swapped in as needed. Programs operate within a virtual address space, and their content can be viewed as running in this virtual address space, ultimately mapping the virtual address space to the physical address space. The mapping table between virtual and physical addresses (Memory Management Unit, MMU) is stored in Dynamic Random Access Memory (DRAM).

[0040] The swap space is actually a disk space (hard disk space). When virtual memory is mapped to physical memory, the code in the virtual memory is placed in the swap space. When the CPU wants to execute related instructions or data, if it does not exist in physical memory, it first maps the required instructions and data from the swap space to physical memory, and then the CPU executes them.

[0041] A physical address is the memory address used by the CPU to access data in memory. When the CPU accesses memory, it must provide the address of the memory location. Each memory location has a unique physical address. For example, for the 8086 CPU, the physical address = segment address x 16 + offset address. The segment address refers to the 16-bit address bus of the 8086 CPU, and the offset address also refers to the 16-bit address bus.

[0042] A script is a computer language that consists of program code.

[0043] Memory test scripts are program code used to detect memory faults.

[0044] The SN information of the memory is the product serial number (SN) of the memory, which is used to identify each of the multiple memory modules. The SN information includes model, version number, capacity, year, month, day, etc.

[0045] Integrated Memory Controller (IMC).

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0047] The first approach provides a memory testing technique. The operating system (OS) obtains the zero-starting address of the memory entry point by running a memory test script or a third-party testing tool. The memory test program then runs from this zero-starting address to perform comprehensive tests on memory performance and stability. If the CPU detects a memory fault or other faults during the test, including abnormal restarts, abnormal test interruptions, or processor processing failures, and the fault is repaired by replacing the memory or other means, re-running the memory test script or third-party testing tool under the operating system will cause the memory test to restart from the zero-starting address of the memory entry point.

[0048] In the current memory testing process, after replacing the memory or handling other faults that cause the test to be interrupted, when the test is restarted, the previous memory test progress is cleared, which leads to an extension of the overall test time.

[0049] In actual supply chain production testing, processor systems frequently encounter issues such as memory error correcting code (ECC) alarms or abnormal OS restarts during stress testing. Regarding memory ECC alarms, since memory is tested in parallel across multiple rank and chip layers, the following two scenarios often occur:

[0050] Scenario 1: After the processor issues a memory ECC alarm, it doesn't immediately power down to terminate the test. Instead, it completes one round of memory stress testing before replacing the faulty component. After powering down and replacing the memory component, the test progress is reset to zero. Memory modules that passed the first round of stress testing, regardless of the result, must be retested in the second round. With technological advancements and increasing memory capacity, the impact on test duration under full-capacity configurations will become increasingly significant.

[0051] Scenario 2: After the processor detects a memory ECC alarm, it immediately reports the fault information and terminates the test. At the time of termination, the test progress of each memory module is different. After powering on and off and replacing the memory components, the test progress of all memory modules is also reset to zero.

[0052] If the test stops due to other faults encountered during processor testing, such as abnormal processor restart, processor power cycle, or replacement of faulty components, the memory needs to be tested from scratch, which will also lead to a decrease in test efficiency.

[0053] The memory testing method provided in this application changes the handling mechanism when memory testing encounters faults or test interruptions, thereby saving the memory test progress and resuming testing at a specified interruption address, thus reducing retest time and improving testing efficiency.

[0054] Figure 1 A system architecture diagram of the memory testing method provided in the embodiments of this application. (See diagram below.) Figure 1 As shown, the embodiments of this application are mainly implemented through the cooperation of a memory test script 11 set in the operating system and a third-party storage device 12.

[0055] The memory test script 11 runs using virtual addresses of memory in the operating system to obtain a larger running space. At the same time, the address that the processor obtains in real time through the memory test script 11 is a virtual address.

[0056] After the processor is powered on and off or restarted, the memory addresses will be remapped, the virtual addresses will be updated, while the physical addresses will remain unchanged. In this embodiment, the physical address of the memory interrupt point is used as the interrupt point marker address and stored in a third-party memory.

[0057] In some embodiments, the memory test script 11 includes an address resolution module 111, an address determination module 112, and an address mapping module 113.

[0058] The address resolution module 111 is used to resolve the physical address Y of the interrupt point based on the virtual address y1; save the physical address Y of the interrupt point to a third-party memory, and the virtual address y1 is a mapping of the physical address Y before the test interrupt.

[0059] In the case of continued testing, the address determination module 112 reads the physical address Y of the interrupt point from a third-party memory; and maps the virtual address y2 according to the physical address Y of the interrupt point.

[0060] The memory test script 11 starts testing from virtual address y2, which is the mapping of physical address Y after the retest.

[0061] The address mapping module 113 is used to determine the mapping relationship between the physical address Y of the interrupt point and the virtual addresses y1 and y2.

[0062] Figure 2 This is a schematic diagram illustrating the interaction principle of the memory testing method provided in an embodiment of this application. Figure 2 As shown, the memory address is marked through the following steps to enable interrupt point continuation testing.

[0063] S21, when the test script runs after the processor powers on, it retrieves mapping table 1 from the OS to determine the mapping relationship between physical and virtual memory addresses. This mapping table 1 can be referred to as the first mapping table.

[0064] S22, In the event of a memory test interruption, obtain the virtual address y1 of the memory interruption point, convert the virtual address y1 of the interruption point to the physical address Y of the interruption point according to the mapping table 1, and write it to the third-party memory. The virtual address y1 of the interruption point at this time can be recorded as the first virtual address.

[0065] S23, when the processor re-tests the memory, it retrieves the updated mapping table 2 from the OS; mapping table 2 is denoted as the second mapping table.

[0066] S24: Obtain the physical address Y of the interrupt point from the third-party memory, convert it into a virtual address y2 through the mapping table 2, obtain the second virtual address of the interrupt point, and continue the test from the virtual address y2.

[0067] In the memory testing method provided in this application embodiment, a page table mapping virtual addresses and physical addresses is stored in physical memory DRAM. The OS is responsible for maintaining the contents of the mapping table and transferring the page table back and forth between the disk and physical memory. The processor uses the mapping page table to convert physical addresses into the virtual addresses of the corresponding interrupt points, and refreshes the value of the test start X to be equal to the virtual address y of the interrupt point. The processor executes the test process, finds the memory unit corresponding to the interrupt point, and starts the test. The processor continuously obtains the current virtual address of the memory test, performs mapping and translation, and stores it in a third-party storage device, forming an address file named by the corresponding SN. The address file contains the memory SN information and test address information.

[0068] Figure 3 A flowchart illustrating a memory testing method provided in an embodiment of this application. Figure 3 As shown, the process includes the following steps: S31, determining the first virtual address of the interrupt point of the memory being tested; S32, resolving the physical address of the interrupt point from the first virtual address; S33, saving the physical address of the interrupt point to a third-party memory; S34, in the case of continued testing, reading the physical address of the interrupt point from the third-party memory; S35, mapping the physical address of the interrupt point to a second virtual address; S36, starting the test from the second virtual address to complete the memory test.

[0069] The memory testing method provided in this application embodiment will be described in detail below for each of the above steps.

[0070] S31, determine the first virtual address of the breakpoint of the memory being tested.

[0071] In some embodiments, step S31 can be achieved by performing the following steps S311-S314.

[0072] S311: Upon power-up, the processor runs a memory test script to establish a mapping relationship between physical and virtual memory addresses, resulting in memory address mapping table 1. This memory address mapping table 1 is designated as the first mapping table.

[0073] For example, when the test script is run after the processor is powered on, the memory address mapping table 1 is obtained from the OS to obtain the correspondence between physical memory addresses and virtual addresses.

[0074] In some embodiments, the test includes parallel testing of multiple memory locations. When the test script is run after the processor is powered on, the memory address mapping table 1 is obtained from the OS to obtain the correspondence between the physical address and virtual address of each memory location in the multiple memory locations.

[0075] S312 generates an address file based on the memory's serial number (SN) information, which is used to identify each memory segment; the address file is then stored in a third-party storage device.

[0076] In some embodiments, memory testing includes parallel testing of multiple memory locations, and multiple address files named after the memory's serial number (SN) can be generated based on the SN information of each memory location. Each address file contains the memory's SN information and the test address.

[0077] S313 records the current test address y of the memory in real time in the address file during memory testing. The current test address y is a virtual address.

[0078] In some embodiments, the address return value of the current test function can be obtained in real time to determine the current test address y in memory.

[0079] In some embodiments, the memory to be tested includes multiple memory locations, and the SN information of each memory location and the test address information of each memory location can be recorded in an address file, with the file named after the SN of each memory location.

[0080] In some embodiments, the information of the test address y for each memory location can be recorded or updated at intervals. For example, the test address y can be refreshed every 5 minutes to ensure the real-time nature of the address information.

[0081] S314, in the event of a test interruption, can obtain the virtual address y1 of the current interruption point in memory based on the real-time recorded current test address.

[0082] In some embodiments, the virtual address y1 of the current breakpoint in each of the multiple memory locations can be obtained based on the current test address recorded in the address file.

[0083] Among them, memory test interruptions include test interruptions caused by non-memory faults and test interruptions caused by memory faults.

[0084] For example, test interruptions caused by non-memory failures include operating system anomalies, processor processing failures, abnormal power outages, or abnormal restarts.

[0085] For example, test interruptions caused by memory failures include memory error checking and correction (ECC) alarms, etc.

[0086] For test interruptions not caused by memory faults, the virtual address y1 of the last recorded update is used as the interrupt point. For example, if the last recorded update test address is 53H, then the virtual address of the interrupt point is y1 = 53H.

[0087] For test interruptions caused by memory failures, it is necessary to replace the memory with a new one or perform other procedures such as reseating it. The zero address of the memory entry point can be used as the virtual address y1. For example, if the zero address of the original / new memory is 00H, then the virtual address of the interruption point y1 = 00H.

[0088] In some embodiments, the memory to be tested includes multiple memory locations. In the event of a test interruption, the memory locations that have completed the test are identified from among the multiple memory locations. The virtual address y1 of each of the multiple memory locations that have completed the test is marked as a test completion identifier.

[0089] For example, the virtual address y1 of the memory interrupt point where the test is completed can be set to y1 = Z, where Z is the test completion identifier.

[0090] For example, the virtual address y1 of the memory interrupt point where the test is completed can be set to y1 = 0FFH, where 0FFH is the test completion identifier.

[0091] S32, the physical address of the interrupt point is obtained by resolving the first virtual address of the interrupt point.

[0092] In some embodiments, step S32 determines the physical address of the interrupt point through the following step S321.

[0093] S321, obtain the physical address Y of the interrupt point corresponding to the virtual address y1 according to the memory address mapping table 1; the memory address mapping table 1 is used to record the mapping relationship between the physical address and the virtual address y1 of the interrupt point.

[0094] For example, the virtual address of the interrupt point is y1 = 53H, and the corresponding physical address Y = 0B153H is obtained according to the memory address mapping table 1.

[0095] In some embodiments, if multiple memory interruptions occur, the physical address of each interruption point corresponding to the virtual address y1 of the multiple memory can be obtained according to the memory address mapping table 1.

[0096] For example, among multiple memory locations, memory 1 is interrupted due to a non-memory fault, with a virtual address of y1 = 53H, and the corresponding physical address Y1 = 0B153H is obtained according to the memory address mapping table 1; memory 2 is interrupted due to a memory fault, with a virtual address of y1 = 00H, and the corresponding physical address Y1 = 0B000H is obtained according to the memory address mapping table 1; memory 3 completes the test, with a virtual address of y1 = 0FFH, and the corresponding physical address Y1 = 0FFFFH or Y1 = Z is obtained according to the memory address mapping table 1.

[0097] S33 saves the physical address of the interrupt point to a third-party memory.

[0098] In some embodiments, the physical address of each interrupt point corresponding to multiple memory locations can be saved to a third-party storage device.

[0099] It should be noted that if the processor cannot operate normally, it cannot record the current state and the physical address of the interrupt point. In this case, the physical address Y of the interrupt point that was last stored in a third-party memory will be used.

[0100] For test interruptions caused by memory failures, the processor's basic input / output system (BIOS) can pinpoint the specific memory fault. For this type of fault, the memory must be replaced. After powering on and resuming testing, the SN information of the memory saved in the historical records can be used to determine where to start the test for that memory.

[0101] S34, in the case of continued testing, reads the physical address of the interrupt point from a third-party memory.

[0102] In some embodiments, step S34 determines the current memory status as a continuous test case through the following steps S341-S342.

[0103] S341, after power-on, the processor retrieves the updated mapping table 2 from the OS. Mapping table 2 is used to record the mapping relationship between the physical address Y and the virtual address y2 of the interrupt point.

[0104] S342 determines the continuation of memory testing based on the memory's serial number (SN) information.

[0105] In some embodiments, the processor is configured with multiple memory modules. After power-on, the processor will call the historical records saved in the address file to obtain the serial number (SN) information of the multiple memory modules. The processor can determine the continuation of the memory test by matching the SN information of the memory modules with the address file.

[0106] If the memory SN information is found by matching the address file, and the case is determined to be a continued memory test, then S343 is executed.

[0107] If no memory SN information is found in the address file, it indicates that the memory is newly installed. This can be determined as a test of the new memory, and S35 is executed.

[0108] S343, in the case of continuous memory testing, reads the physical address Y of the corresponding memory interrupt point from a third-party storage device based on the memory's SN information.

[0109] In some embodiments, when resuming memory testing, the physical address Y of the interrupt point of the corresponding memory is read from a third-party storage device based on the memory's SN information. If the value of the physical address Y is a memory test completion flag, it indicates that the memory has completed the test and will no longer be tested.

[0110] For example, the physical address Y = 0B153H of the corresponding memory interrupt point is read from a third-party storage device based on the memory's SN information.

[0111] For example, the memory test completion flag can be set to Z or 0FFFFH. If the physical address of the corresponding memory interrupt point is read from the third-party storage, Y = Z or Y = 0FFFFH, it means that the memory has completed the test and no further testing is needed.

[0112] In some embodiments, the processor is configured with multiple memory locations, and the third-party memory stores the interrupt point information of the multiple memory locations. The physical address of the corresponding interrupt point of the multiple memory locations can be read from the third-party memory according to the memory's serial number (SN) information.

[0113] For example, the physical address Y1 = 0B153H of the interrupt point of memory 1 is read from the third-party memory based on the SN information of memory 1; the physical address Y2 = 0FFFFH of the interrupt point of memory 2 is read from the third-party memory based on the SN information of memory 2.

[0114] S35, obtain the virtual address y2 based on the physical address mapping of the interrupt point.

[0115] In some embodiments, the virtual address y2 corresponding to the physical address of the interrupt point can be obtained according to the mapping table 2; the memory address mapping table 2 is used to record the mapping relationship between the physical address Y and the virtual address y2 of the interrupt point.

[0116] For example, the physical address of the corresponding interrupt point in memory is read from the third-party storage according to the memory's SN information as Y = 0B153H, and the virtual address of the corresponding interrupt point is obtained according to the memory address mapping table 2 as y2 = 10H.

[0117] In some embodiments, when the memory is being tested for the first time, the default entry address of that memory is used as the test starting address X.

[0118] For example, the virtual address of the memory breakpoint can be set to y2 = 00H, and the test can start from the beginning.

[0119] In some embodiments, if multiple memory interruptions occur, the virtual address y2 corresponding to the physical address of the interruption point in each of the multiple memory locations can be obtained according to the memory address mapping table 2.

[0120] For example, in multiple memory locations, the physical address of memory 1 is Y1 = 0B153H, and the virtual address of the corresponding interrupt point is obtained as y2 = 10H according to the mapping table 2; the physical address of memory 2 is Y2 = 0FFFFH or Y1 = Z, and the virtual address of the corresponding interrupt point is obtained as y2 = 0FFH according to the memory address mapping table 2.

[0121] S36, starting the test from the second virtual address, completes the memory test.

[0122] For example, if memory 1 was interrupted due to a non-memory fault, and its virtual address y2 = 10H, then the test will begin at address 10H and continue until the memory test is complete. If memory 2 is the new memory that was replaced after the test was interrupted due to a memory fault, and its virtual address y2 = 00H, then the test will begin at the entry address of memory 2 and continue until the memory test is complete. If memory 3 is the memory that has already been tested, and its virtual address y2 = 0FFH, then no further testing is needed.

[0123] The memory testing method provided in this application saves the memory testing progress in real time during the testing process. Even after a power outage and subsequent power-on, the previous memory testing progress can still be retrieved, enabling memory testing to resume. When dealing with multiple parallel memory tests where the testing progress of each memory module is inconsistent, this application avoids resource waste and low testing efficiency caused by clearing the test progress and resulting in a second, fault-free memory test. The memory testing method provided in this application can achieve efficient and seamless testing of the entire memory area.

[0124] Example 1

[0125] Figure 4 This is a flowchart illustrating the memory testing method provided in Embodiment 1 of this application. Figure 4As shown, determining the interrupt point address in a memory test involves the following steps:

[0126] S41, power on and run the memory test script.

[0127] S42, set the starting address of the test for each memory segment to X, where X is the starting address of the memory test.

[0128] S43: Determine if the current memory is a continuing test memory. If it is, proceed to S44. If the result is that it is not a continuing test memory, proceed to S45.

[0129] For example, the memory's serial number (SN) information can be matched with the historical records stored in the address file. If the SN information of the memory is stored in the historical records, the current memory is the memory to be tested again. If the SN information of the memory is not stored in the historical records, the current memory is the memory to be tested again or the new memory.

[0130] S44 specifies the physical address Y of the breakpoint in the current memory to be retrieved from a third-party storage device.

[0131] Specifically, the physical address Y of the interrupt point corresponding to the current memory can be obtained from a third-party storage device using the memory's SN information.

[0132] S45 converts the physical address Y of the interrupt point to a virtual address y through a mapping table.

[0133] S46, starting at address X = y, uses the Integrated Memory Controller (IMC) to locate the virtual address y corresponding to the physical address Y of the memory interrupt point.

[0134] S47, the test script continues execution from virtual address y.

[0135] S48, start testing the memory from the beginning, with the test starting address X being the default entry address of the memory.

[0136] The memory test was completed using S41-S48 as described above.

[0137] The memory is tested in parallel, and in actual operation, the interrupt point address Y corresponding to each memory memory in the machine configuration will be refreshed.

[0138] Example 2

[0139] Figure 5 This is a flowchart illustrating the interrupt point address resolution process provided in Embodiment 2 of this application. When the processor executes the memory test script to test the memory, it obtains the current test address y in real time and converts it into a physical address through the mapping module 113, storing it in the address file. This achieves the purpose of recording the test address of the memory module in real time. Figure 5 As shown. Includes the following steps:

[0140] S51, start testing, which means recording the current test address Y in real time every 5 minutes.

[0141] S52, determine whether a test interruption has occurred. If the result is "yes", proceed to step S53; if the result is "no", execute the test script until the test ends.

[0142] Specifically, test interruptions include either test interruptions caused by non-memory faults or test interruptions caused by memory faults.

[0143] S53: Determine if the processor is running normally. If the result is "yes", then execute S54; if the result is "no", then execute S56.

[0144] S54, determine whether to continue the memory test. If the result is "yes", then execute S55; if the result is "no", then execute S57.

[0145] S55, test the memory normally until completion, and record the test address y of each memory at the last test completion time. If the entire memory has been tested, record the physical address Y=Z in the address file of the third-party storage device, where Z is a marker that the memory has been tested.

[0146] S56, test ends, record the test address y of the most recent interruption point, and execute S58-S59.

[0147] S57, test ends, record the test address y of the interrupt point in the current abnormal memory, and execute S58-S59.

[0148] S58, converts the test address y to the physical address Y according to the memory address mapping table 2.

[0149] S59, store the physical address Y in a third-party memory.

[0150] In some embodiments, if a test interruption occurs due to a non-memory fault, the following steps S521-S522 can be performed respectively.

[0151] S521: With the machine processor running normally and memory testing continuing until the test ends, record the test address y of each memory stick at the last moment of test completion. When the entire memory stick has completed the test, record the test address y = Z, indicating that the memory has completed the test.

[0152] S522: When the machine processor is running and the memory test is interrupted, record the test address y of each memory interruption point at the current test interruption time. If the entire memory module has been tested, record the test address y = Z, indicating that the memory has been tested.

[0153] S522, if the machine processor malfunctions and the test ends, and the processor cannot run normally, the current test address y in memory cannot be recorded. In this case, the physical address y of the interrupt point stored in the third-party memory will be used.

[0154] In some embodiments, if a memory failure occurs during the test, such as a memory ECC failure, the following steps S523-S525 are executed respectively.

[0155] S523, under the condition that the processor is running normally and the memory continues to be tested until the test ends, for multiple memory, the test address y of each memory at the current moment is recorded. If the memory space of memory 1 has been fully tested, the test address y of memory 1 is recorded as Z, indicating that memory 1 has completed the test. For memory 2 that has failed, since it is necessary to replace the new memory or re-insert and test it, the entry address of memory 2 can be set as the test address y of the interrupt point.

[0156] S524: When the processor is running normally, but the memory test is interrupted and the test process ends, for multiple memory modules, record the test address y of each memory module at the time of the current interruption. If memory 1 is currently normal and has not failed, record the test address y of the interrupt point of memory 1 at the time of the current interruption. For memory 2 that has failed, since it is necessary to replace the memory or re-insert it for testing, the entry address of memory 2 can be set as the test address y of the interrupt point.

[0157] In the case of S525, if the processor malfunctions, memory test is interrupted, or the test ends, for multiple memory modules, because the processor cannot run normally and cannot record the current test status and interrupt point address, the test address y of the interrupt point of memory 1 is determined based on the physical address Y of the interrupt point of memory 1 that was last stored on a third-party storage device; if the processor cannot run normally due to a fault in memory 2, the BIOS will locate the specific memory fault, and memory 2 will need to be replaced for this type of fault.

[0158] In some embodiments, when the processor runs the test script to test the memory, it can obtain the address return value of the current test function in real time, that is, the current test address y of the memory. During memory testing, the SN information of each memory and the test address y of each memory are recorded in the address file. The address file is named after the SN of each memory. The test address y of each memory is refreshed once every certain period of time to ensure the real-time nature of the address information.

[0159] Example 3

[0160] Figure 6 This is a flowchart of the memory testing method according to Embodiment 3 of this application. Figure 6 As shown, after the processor powers on and starts the memory test script, the following steps are executed:

[0161] S61, after the processor powers on and starts up, it establishes a mapping table between physical memory addresses and virtual memory addresses, resulting in memory address mapping table 1.

[0162] S62, determine if the current memory is the memory to be tested. If the result is "no", execute S63. If the result is "yes", then the current memory is the memory to be tested, and execute S64.

[0163] S63, testing starts from memory address X.

[0164] S64, the processor continues the test, refreshing the memory test start address X=Y. This includes the following steps S641-S644:

[0165] S641 reads the physical address Y of the interrupt point from a third-party memory.

[0166] S642 determines the physical address Y of the interrupt point of each memory based on the SN information of the memory, and refreshes the test start address X=Y of each memory.

[0167] S643, each memory is tested starting from the second virtual address corresponding to the physical address Y of the break point.

[0168] S644: If a test is interrupted during the test, the test address y will continue to be updated. If the test is completed normally, the memory test completion flag Z will be updated, thus completing the entire test process.

[0169] S65 obtains the current memory test address y in real time during memory testing.

[0170] S66, determine whether a test interruption has occurred. If the result is "yes", execute S67; if the result is "no", execute S67.

[0171] S67 records the current test address y in the event of a test interruption or memory error, maps the test address y to a physical address Y, and stores it on a third-party memory.

[0172] S68. If no test interruption or memory error occurs until the end of the test, a normal test is completed, and the test address y in memory is updated to the test completion flag Z. The physical address Y of the interruption point is updated to the test completion flag Z.

[0173] Example 4

[0174] The memory testing method of Embodiment 4 of this application performs the following steps S71-S74 to achieve parallel testing of multiple memory samples.

[0175] The S71 performs parallel testing starting from the entry address of each memory location after the processor is first powered on.

[0176] like Figure 7 As shown, the processor is configured with DIMM1 to DIMM8, a total of 8 memory locations, with X being the default starting address.

[0177] In the S72, during parallel testing, if a test interruption is caused by a memory failure, the physical address Y of the interruption point is recorded in a third-party memory to obtain the test progress at the time of the interruption.

[0178] like Figure 8 As shown, at the moment a memory failure occurs, the specific test progress of each memory segment is different. The test progress is marked by gray blocks, and the position reached by the gray blocks indicates the virtual address of each memory interruption point.

[0179] For example, at the moment a memory failure occurs, the specific test progress of each memory in DIMM1-DIMM8 is Y1-Y8 respectively. If the processor is running normally, the physical addresses Y1-Y8 of the interrupt points of DIMM1-DIMM8 at the moment of the memory failure can be saved in a third-party memory. Among them, DIMM5 is the memory that has completed the test normally, DIMM7 is the memory that has experienced the memory failure, and DIMM8 is the memory that has been tested from the beginning.

[0180] After reseating the faulty memory DIMM7 (S73), the processor powers on again and obtains the updated memory address mapping table 2 from the OS. The processor then retrieves the initial test address for each memory module from third-party storage based on its memory serial number (SN) information.

[0181] like Figure 9 As shown, based on the test progress of each memory segment obtained from the third-party storage, the test start addresses for each memory segment in DIMM1-DIMM8 are X1-X8, respectively. X1-X8 are the virtual addresses mapped to the physical addresses Y1-Y8 of DIMM1-DIMM8 stored in the third-party storage. Among them, DIMM7 is the memory segment that experienced a memory failure, and its test start address X is the entry address.

[0182] It should be noted that for faulty DIMM7 memory modules, replacing them with new memory or performing other procedures such as reseating or swapping, the testing process restarts from the beginning by default. For other memory modules whose testing was interrupted during normal operation, the testing resumes from the interruption point address X=Y. For memory modules at X=Z, the testing has already been completed and does not need to be repeated. This improves the efficiency of memory testing through the memory testing method provided in this application.

[0183] In some embodiments, memory fault handling, such as memory replacement or reseatment, can be performed after the test is completed.

[0184] like Figure 10 As shown, memory fault handling was performed after the test was completed. DIMM1-DIMM6 and DIMM8 were all tested, with breakpoint addresses of X=Z. The processor was powered on and tested again, and only the faulty memory DIMM7 was tested starting from the entry address.

[0185] S74, test interruption caused by non-memory faults, such as abnormal processor power loss or abnormal restart, since the processor cannot record the state at that time in time, uses the physical address Y of the most recent test stored in third-party memory as the interrupt point address.

[0186] like Figure 11 As shown, after the processor is powered on again for testing, the physical address Y of the interrupt point recorded at the previous moment is read from the third-party memory. The test address X corresponding to each memory module is refreshed according to address mapping table 2, and the test continues from the starting address X of the interrupt point. For example...

[0187] The memory testing method provided in this application does not limit or control the amount of memory. It can resume memory testing from interruption points for both parallel and serial testing.

[0188] The memory testing method provided in this application continuously saves the memory testing progress during the testing process. Even after power-off and power-on, the previous memory testing progress can still be obtained, thus enabling memory testing to continue.

[0189] The memory testing method provided in this application addresses the challenge of parallel testing across multiple memory ranks, where the testing progress of each memory module is inconsistent. By implementing memory interruption point continuation testing, it avoids resource waste and reduced testing efficiency caused by clearing the test progress and resulting in non-faulty memory modules undergoing secondary testing. Compared to testing from the beginning, the memory testing method provided in this application has no difference in fault initiation, and both methods can achieve full-area memory testing.

[0190] This application's embodiments establish a mechanism for real-time reading and saving of test addresses during memory testing. In the next test, the saved physical address is processed into the virtual address required by the test script process, and the content of the specified test start address X set in the test script is replaced, causing the test process to resume execution from the address where the previous test was interrupted. This method solves the problem that memory test progress cannot be stored on the machine itself or in the system, thereby enabling the execution of test content in a specified memory region.

[0191] This application provides a memory testing apparatus, comprising: a test progress saving module, configured to determine a first virtual address of an interrupt point of the memory under test; resolve the physical address of the interrupt point based on the first virtual address of the interrupt point; save the physical address of the interrupt point to a third-party storage device; and a test progress acquiring module, configured to read the physical address of the interrupt point from the third-party storage device when testing continues; map a second virtual address based on the physical address of the interrupt point; and start testing from the second virtual address to complete the memory test.

[0192] This application provides an electronic device, including a processor and a memory; the processor is configured to execute instructions stored in the memory to cause the electronic device to perform the method described in any of the above embodiments.

[0193] This application provides a computer-readable storage medium including computer program instructions, which, when executed by a computer, perform the method described in any of the above embodiments.

[0194] This application provides a computer program product containing instructions that, when executed by a computing device, cause the computing device to perform the method described in any of the above embodiments.

[0195] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0196] Furthermore, various aspects or features of the embodiments of this application can be implemented as methods, apparatus, or articles of manufacture using standard programming and / or engineering techniques. The term "article of manufacture" as used in this application encompasses a computer program accessible from any computer-readable device, carrier, or medium. For example, computer-readable media may include, but are not limited to: magnetic storage devices (e.g., hard disks, floppy disks, or magnetic tapes), optical discs (e.g., compact discs (CDs), digital versatile discs (DVDs), etc.), smart cards, and flash memory devices (e.g., erasable programmable read-only memory (EPROMs), cards, sticks, or key drives, etc.). Additionally, the various storage media described herein may represent one or more devices and / or other machine-readable media for storing information. The term "machine-readable medium" may include, but is not limited to, wireless channels and various other media capable of storing, containing, and / or carrying instructions and / or data.

[0197] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application.

[0198] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0199] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0200] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0201] If the aforementioned function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application embodiment, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a server, or an access network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0202] The above description is merely a specific implementation of the embodiments of this application, but the protection scope of the embodiments of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be covered within the protection scope of the embodiments of this application.

Claims

1. A method for memory testing, applied to a processor, characterized in that, The method includes: Determine the first virtual address of the breakpoint in the memory being tested; The physical address of the interrupt point is resolved from the first virtual address of the interrupt point; Save the physical address of the interrupt point to a third-party memory; In the case of continued testing, the physical address of the interruption point is read from the third-party memory; The second virtual address is obtained by mapping the physical address of the interrupt point; The test begins at the second virtual address, completing the memory test.

2. The method according to claim 1, characterized in that, The first virtual address for determining the breakpoint of the memory being tested includes: In the event of a current test interruption, determine the first virtual address of the current interruption point of the memory under test, wherein the test interruption is one of the following: operating system exception, memory error check and correction (ECC) alarm, or processor processing failure.

3. The method according to claim 1 or 2, characterized in that, The memory test includes multiple parallel memory tests, and an address file is generated based on the SN information of the multiple memory locations. The SN information is used to identify each of the multiple memory locations.

4. The method according to claim 3, characterized in that, The memory being tested includes multiple memory locations, and the first virtual address for determining the breakpoint of the memory being tested includes: The test address of each of the multiple memory locations is obtained in real time; The test address of each memory location is recorded in the address file; In the event of a test interruption, the first virtual address of the interruption point for each of the plurality of memory locations is obtained based on the test address currently recorded in the address file.

5. The method according to claim 1 or 2, characterized in that, The memory being tested includes multiple memory locations, and the first virtual address for determining the breakpoint of the memory being tested includes: Determine which memory from the plurality of memory locations was used for the test; The first virtual addresses of the multiple memory locations that have completed the test are all marked as test completion identifiers.

6. The method according to claim 1 or 2, characterized in that, The process of resolving the physical address of the interrupt point based on the first virtual address of the interrupt point includes: The physical address of the interrupt point corresponding to the first virtual address is obtained according to the mapping table of the first memory address; the mapping table of the first memory address is used to record the mapping relationship between the physical address of the interrupt point and the first virtual address.

7. The method according to claim 1 or 2, characterized in that, In the case of continued testing, reading the physical address of the interrupt point from the third-party memory includes: Based on the SN information of the memory obtained by matching the address file, it is determined that the memory is a case of continued testing; In the case of continued testing, the physical address of the interrupt point is read from the third-party memory based on the SN information of the memory.

8. The method according to claim 1 or 2, characterized in that, The second virtual address is obtained based on the physical address mapping of the interrupt point, including: The second virtual address corresponding to the physical address of the interrupt point is obtained according to the mapping table of the second memory address; the mapping table of the second memory address is used to record the mapping relationship between the physical address and the second virtual address of the interrupt point.

9. The method according to claim 7, characterized in that, include: If the SN information of the memory is not matched in the address file, the memory is determined to be a newly measured case. If the memory is being tested for the first time, the test begins from the memory's entry address.

10. A memory testing apparatus, characterized in that, The device includes: The test progress saving module is used to determine the first virtual address of the interrupt point of the memory being tested; resolve the physical address of the interrupt point based on the first virtual address of the interrupt point; and save the physical address of the interrupt point to a third-party storage device. The test progress acquisition module is used to read the physical address of the interruption point from the third-party memory when the test continues; to obtain a second virtual address based on the physical address of the interruption point; and to start the test from the second virtual address to complete the memory test.

11. An electronic device comprising a processor and a memory; the processor being configured to execute instructions stored in the memory to cause the electronic device to perform the method as claimed in any one of claims 1-9.

12. A computer-readable storage medium, characterized in that, It includes computer program instructions, which, when executed by a computer, cause the computer to perform the method as described in any one of claims 1-9.

13. A computer program product containing instructions, characterized in that, When the instruction is executed by the computing device, the computing device performs the method as described in any one of claims 1-9.

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