Method and System for Verifying Schedulability of Microprograms in Embedded Systems

Abstract

The present application relates to a method and a system for verifying the schedulability of microprograms in an embedded system, which belongs to the technical field of embedded systems. The method includes obtaining a test microprogram set and a control microprogram set; sequentially scheduling the test microprogram set and the control microprogram set by using the EDFI scheduling rule to obtain test scheduling information; sequentially scheduling the test microprogram set and the control microprogram set by using the EDF scheduling rule to obtain control scheduling information; and obtaining result information according to the test scheduling information and the control scheduling information. The present application has the effect of improving the accuracy of the result of judging the schedulability of microprograms.

Description

Technical Field

[0001] The present application relates to the technical field of embedded systems, and in particular to a method and system for verifying the schedulability of microprograms in embedded systems. Background Art

[0002] A distributed embedded system is a system composed of a group of embedded computing nodes that communicate through a network and coordinate to complete common tasks. Also, due to the coordination of the distributed embedded system, the functions implemented by a single computing node are limited. Therefore, in order to save resources, less hardware resources are allocated to the computing node when deploying it.

[0003] In order to enable the embedded computing node to fully schedule the held hardware resources to cooperate with other embedded computing nodes to complete high-real-time tasks, a microprogram is proposed in the operating system of the embedded computing node, and a scheduling policy is configured for the microprogram. The operating system implements the scheduling of the microprogram according to the scheduling policy. However, there is a lack of verification means for the feasibility of the scheduling policy configured for the microprogram, which increases the difficulty of deploying the embedded system. Summary of the Invention

[0004] The present application provides a method and system for verifying the schedulability of microprograms in an embedded system, which has the characteristic of improving the accuracy of the schedulability result of the microprogram.

[0005] A first object of the present application is to provide a method for verifying the schedulability of microprograms in an embedded system.

[0006] The above first object of the present application is achieved by the following technical solutions:

[0007] A method for verifying the schedulability of microprograms in an embedded system includes:

[0008] Obtaining a test microprogram set and a control microprogram set;

[0009] Successively scheduling the test microprogram set and the control microprogram set using the EDFI scheduling rule to obtain test scheduling information;

[0010] Successively scheduling the test microprogram set and the control microprogram set using the EDF scheduling rule to obtain control scheduling information;

[0011] Obtaining result information according to the test scheduling information and the control scheduling information.

[0012] By adopting the above technical solution, the present application sets two sets of data as the data sources for verification, then verifies the verification data using the EDFI scheduling strategy and the EDF scheduling strategy respectively, and finally compares the test scheduling information obtained using the EDFI scheduling strategy with the control scheduling information obtained using the EDF scheduling strategy, and generates result information according to the comparison result. It can be seen that the present application sets two sets of data, then uses two different scheduling strategies to schedule the test microprogram set and the control microprogram set, so as to obtain various intermediate information (including test scheduling information and control scheduling information), and then generates the final result information according to each intermediate information, so as to ensure the accuracy of the schedulability result of the obtained microprogram.

[0013] In a preferred example, the present application can be further configured as follows: Before obtaining the test microprogram, it includes:

[0014] Obtain a target microprogram set, the target microprogram set includes a plurality of target microprograms, and the target microprograms include Wsn_TimerFiber microprogram, Wsn_AppFiber microprogram, Wsn_DemoFiber microprogram and Wsn_EdfiFiber microprogram;

[0015] Extract the theoretical deadline and the minimum inheritance time of the target microprogram, and generate an inheritance deadline schedule according to the minimum inheritance time;

[0016] Establish a ready scheduling queue and a running scheduling queue;

[0017] The ready scheduling queue is used to receive the target microprograms and arrange the target microprograms in ascending order of the theoretical deadline;

[0018] The running scheduling queue is used to receive the inheritance deadline schedule and the target microprograms released by the ready scheduling queue, and execute the target microprograms according to the inheritance deadline schedule to obtain the actual deadline; the running scheduling queue is also used to arrange the executed target microprograms in ascending order of the actual deadline, and release them to the ready scheduling queue when the target microprograms reach the next execution cycle;

[0019] Input the microprogram amount of each target microprogram, the actual deadline of each target microprogram obtained by the running scheduling queue when traversing the target microprograms in the ready scheduling queue, and the running cycle of each target microprogram into the W(t) function, H(t) function and CB(t) function;

[0020] Establish a linear function with a coefficient of 1, put the W(t) function, H(t) function and CB(t) function into the linear function with a coefficient of 1, and judge whether the W(t) function intersects with the diagonal line before the H(t) function and the CB(t) function; if so, mark the target microprogram set as the test microprogram set;

[0021] If not, mark the target micro program set as the control micro program set.

[0022] By adopting the above technical solution, the target micro program set is divided into a test micro program set and a control micro program set, thereby providing a data source for subsequent verification.

[0023] In a preferred example, the present application can be further configured that: the test scheduling information includes real-time test, priority inversion test, deadlock test, and micro program segment scheduling test of the micro program.

[0024] By adopting the above technical solution, based on the setting of two groups of data, multiple groups of tests are respectively performed on the two groups of data, ensuring the accuracy of the schedulability result of the obtained micro program.

[0025] In a preferred example, the present application can be further configured that: the real-time test includes:

[0026] Adopt the EDFI scheduling strategy to schedule the test micro program set to obtain the actual deadline;

[0027] Subtract the theoretical deadline of the test micro program set from the actual deadline to obtain the first early time of the test;

[0028] Adopt the EDFI scheduling strategy to retrieve the control micro program set to obtain the actual deadline;

[0029] Subtract the theoretical deadline of the control micro program set from the actual deadline to obtain the first early time of the control.

[0030] In a preferred example, the present application can be further configured that: the priority inversion test includes:

[0031] Extract the Wsn_AppFiber micro program, Wsn_DemoFiber micro program, and Wsn_EdfiFiber micro program;

[0032] Set the Wsn_AppFiber micro program and the Wsn_EdfiFiber micro program to simultaneously access the same shared hardware resource R, and set the Wsn_DemoFiber micro program to not access any hardware resources;

[0033] Release the Wsn_EdfiFiber micro program, Wsn_DemoFiber micro program, and Wsn_AppFiber micro program in sequence, and adopt the EDFI scheduling strategy to schedule the sequentially released Wsn_EdfiFiber micro program, Wsn_DemoFiber micro program, and Wsn_AppFiber micro program;

[0034] Determine whether priority inversion of the micro - processes occurs in the scheduling of the Wsn_EdfiFiber micro - process, the Wsn_DemoFiber micro - process, and the Wsn_AppFiber micro - process, and generate the first scheduling information.

[0035] In a preferred example, this application can be further configured as: The deadlock test includes:

[0036] Extract the Wsn_AppFiber micro - process and the Wsn_EdfiFiber micro - process;

[0037] Set the Wsn_AppFiber micro - process and the Wsn_EdfiFiber micro - process to access the hardware resource R1 simultaneously;

[0038] Adopt the EDFI scheduling strategy to schedule the Wsn_AppFiber micro - process first. After the Wsn_AppFiber micro - process holds the hardware resource R1, let the Wsn_EdfiFiber micro - process preempt the Wsn_AppFiber micro - process after a certain time delay;

[0039] Determine whether the Wsn_AppFiber micro - process and the Wsn_EdfiFiber micro - process are deadlocked, and generate the first execution information.

[0040] In a preferred example, this application can be further configured as: The micro - process micro - program segment scheduling test includes:

[0041] Extract the Wsn_TimerFiber micro - process, the Wsn_AppFiber micro - process, the Wsn_DemoFiber micro - process, and the Wsn_EdfiFiber micro - process;

[0042] Add an array to each of the Wsn_TimerFiber micro - process, the Wsn_AppFiber micro - process, the Wsn_DemoFiber micro - process, and the Wsn_EdfiFiber micro - process;

[0043] Adopt the EDFI scheduling strategy to schedule the Wsn_TimerFiber micro - process, the Wsn_AppFiber micro - process, the Wsn_DemoFiber micro - process, and the Wsn_EdfiFiber micro - process after adding the arrays;

[0044] Record the names and deadlines of the relevant program segments according to the scheduling results, and generate the first - order information.

[0045] In a preferred example, this application can be further configured as: The obtaining the result information according to the test scheduling information and the control scheduling information includes:

[0046] Perform real-time verification, priority inversion verification, deadlock verification, and microprogram segment scheduling verification on the test scheduling information and the control scheduling information respectively to obtain result information.

[0047] By adopting the above technical solution, based on the real-time testing, priority inversion testing, deadlock testing, and microprogram segment scheduling testing of the test microprogram set and the control microprogram set, and then giving corresponding verifications to each test respectively, the accuracy of the schedulability result of the obtained microprogram is guaranteed.

[0048] The second object of this application is to provide a schedulability verification system for microprograms in an embedded system.

[0049] The above second object of this application is achieved through the following technical solution:

[0050] A schedulability verification system for microprograms in an embedded system includes an analysis module and a verification module;

[0051] The analysis module includes a microprogram data analysis unit, a scheduling feasibility analysis unit, and an analysis result data unit connected in sequence;

[0052] The verification module includes a data receiving unit, a first processing unit, a second processing unit, and a result generating unit;

[0053] The data receiving unit is used to obtain a test microprogram set and a control microprogram set;

[0054] The first processing unit is used to schedule the test microprogram set and the control microprogram set in sequence using the EDFI scheduling rule to obtain test scheduling information;

[0055] The second processing unit is used to schedule the test microprogram set and the control microprogram set in sequence using the EDF scheduling rule to obtain control scheduling information;

[0056] The result generating unit is used to obtain result information according to the test scheduling information and the control scheduling information.

[0057] In summary, this application includes at least one of the following beneficial technical effects:

[0058] 1. By setting two groups of data in this application, and then using two different scheduling strategies to schedule the test microprogram set and the control microprogram set, a variety of intermediate information (including test scheduling information and control scheduling information) is obtained, and then the final result information is generated according to each piece of intermediate information. Therefore, the accuracy of the schedulability result of the obtained microprogram can be guaranteed;

[0059] 2. Based on the real-time test, priority inversion test, deadlock test, and microprogram segment scheduling test of the test microprogram set and the control microprogram set, corresponding verifications are given for each test respectively, ensuring the accuracy of the schedulability results of the obtained microprograms. Description of the Drawings

[0060] Figure 1 It is a system diagram of the schedulability verification of microprograms in the embedded system of the present application.

[0061] Figure 2 It is a flowchart of the method applied to the verification module in the verification method of the present application.

[0062] Figure 3 It is a flowchart of the method applied to the analysis module in the verification method of the present application.

[0063] Figure 4 It is an example diagram of the representation method for multiple target microprograms accessing different hardware resources in the verification method of the present application.

[0064] Figure 5 It is an example diagram of the representation of the inheritance deadline schedule when multiple target microprograms access different hardware resources in the verification method of the present application.

[0065] Figure 6 It is an example diagram of the coordinates of a linear function with a coefficient of 1 in the verification method of the present application.

[0066] Figure 7 It is an example diagram of the priority test in the verification method of the present application.

[0067] Description of the Reference Numerals: 1. Analysis module; 11. Microprogram data analysis unit; 12. Scheduling feasibility analysis unit; 13. Analysis result data unit; 2. Verification module; 21. Data receiving unit; 22. First processing unit; 23. Second processing unit; 24. Result generating unit. Detailed Embodiment

[0068] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0069] Due to the limited hardware resources of the embedded computing node and to ensure the high real-time performance of the operating system of the embedded computing node, a new technical means is needed to analyze the schedulability of the microprograms running in the operating system and to verify the feasibility of the scheduling strategy of the microprograms in the operating system.

[0070] First, for the means of verifying the feasibility of the scheduling strategy of the microprograms in the operating system, it is necessary to build a simulation system with the same working principle as the embedded system. In a specific example, the simulation system is the senHopen operating system, which can run on the ARM platform and the AVR platform. The ARM platform uses a development board with a main processor of S3C2410 chip, and this development board serves as the convergence node of the embedded system. The AVR platform uses the wireless sensor development kit GAINZ, which serves as a wireless sensor node and also as an embedded computing node. By running the SenHopen operating system and the ZigBee protocol stack on these two platforms, a small wireless sensor network is formed, that is, the purpose of building a simulation system is achieved.

[0071] To further disclose the composition structure of the above simulation system, this application proposes a schedulability verification system for microprograms in an embedded system, and this verification system is located in the AVR platform. Refer to Figure 1 , the verification system includes an analysis module 1 and a verification module 2.

[0072] Among them, the analysis module 1 is used to judge whether the scheduling of the microprogram set is the EDFI scheduling strategy. When the scheduling of the microprogram set is the EDFI scheduling strategy, the microprogram set is marked as the test microprogram set; otherwise, when the scheduling of the microprogram set is not the EDFI scheduling strategy, the microprogram set is marked as the control microprogram set. In this embodiment, the microprogram set to be judged whether to use the EDFI scheduling strategy for scheduling is used as the target microprogram set, and after being judged by the analysis module 1, the target microprogram set is transformed into the test microprogram set and the control microprogram set, and the obtained test microprogram set and control microprogram set are used as the data sources for the verification module 2 to verify.

[0073] Specifically, the analysis module 1 includes a microprogram data analysis unit 11, a scheduling feasibility analysis unit 12, and an analysis result data unit 13. The microprogram data analysis unit 11, the scheduling feasibility analysis unit 12, and the analysis result data unit 13 are connected in sequence. Among them, the microprogram data analysis unit 11 is used to receive the target microprogram set, the scheduling feasibility analysis unit 12 is used to analyze whether the scheduling of the target microprogram set is the EDF scheduling strategy, and the analysis result data unit 13 is used to display the analysis result of the scheduling feasibility analysis unit 12.

[0074] The above EDFI scheduling policy is an extended and optimized earliest deadline scheduling policy. The Earliest Deadline First with Deadline Inheritance (EDFI) scheduling policy is a real-time scheduling protocol that combines the deadline inheritance of shared resources on the basis of the EDF scheduling policy. Technicians only need to specify the time limit and resource requirements of a microprogram, and the EDFI scheduling policy can automatically handle transactions such as the loading, scheduling, distribution, and resource synchronization of microprograms, avoiding unnecessary microprogram switches during the operation of microprograms and solving the problems caused by preemptive priorities and competing for shared hardware resources.

[0075] The above EDF scheduling policy is to ensure the real-time performance of microprogram scheduling. The Earliest Deadline First (EDF) scheduling policy judges the microprograms in the ready state and selects the microprogram with the shortest deadline for scheduling when each new microprogram enters the ready state. Therefore, if the deadline of the new microprogram is earlier than the deadline of the interrupted microprogram, the new microprogram will be immediately scheduled, that is, the currently running microprogram will be preempted. It can be seen that EDF scheduling will cause high-priority microprograms to preempt the execution of low-priority microprograms, and the preemption of microprograms will cause two problems, one is the inversion of priorities in scheduling, and the other is deadlock caused by accessing shared resources.

[0076] Therefore, in order to ensure that no problems such as priority inversion and deadlock caused by accessing shared hardware resources occur during the scheduling of the microprogram set, it is necessary to judge whether the microprogram scheduling is the EDFI scheduling policy and verify the feasibility of the EDFI scheduling policy of microprograms in the operating system.

[0077] That is to say, the verification module 2 is used to verify the feasibility of the EDFI scheduling policy of the microprogram set. Specifically, the verification module 2 includes a data receiving unit 21, a first processing unit 22, a second processing unit 23, and a result generating unit 24. The first processing unit 22 and the second processing unit 23 are in parallel, and the input ends of the first processing unit 22 and the second processing unit 23 are both connected to the data receiving unit 21, while the output ends of the first processing unit 22 and the second processing unit 23 are both connected to the result generating unit 24. The data receiving unit 21, the first processing unit 22, the second processing unit 23, and the result generating unit 24 cooperate together to verify the feasibility of the EDFI scheduling policy of the microprogram set.

[0078] To further illustrate the working principle of the verification system, this application also proposes a method for verifying the schedulability of microprograms in an embedded system, and this verification method is run by the verification module 2. Refer to Figure 2, the main process of this verification method is described as follows.

[0079] Step S1: Obtain the test microprogram set and the control microprogram set.

[0080] According to some embodiments of the verification system, the test microprogram set and the control microprogram set are output by the analysis module 1. Specifically, the analysis module 1 divides them according to whether the scheduling used by the target microprogram set is the EDFI scheduling policy. Refer to Figure 3 , the process of the analysis module 1 generating the test microprogram set and the control microprogram set is shown in steps S01 to S05:

[0081] Step S01: Obtain the target microprogram set, which includes multiple target microprograms.

[0082] The target microprogram is a microprogram set to be judged whether it uses the EDFI scheduling policy. The microprogram set refers to a concurrent model using event-driven and is used to complete transactions that frequently occur, have a high degree of concurrency, and a short execution process in the embedded computing node. Each event or task is also called a microprogram. Therefore, the target microprogram set includes multiple target microprograms.

[0083] In this embodiment, for the convenience of subsequent verification by the verification module 2, the target microprogram set consists of Wsn_TimerFiber microprogram, Wsn_AppFiber microprogram, Wsn_DemoFiber microprogram, and Wsn_EdfiFiber microprogram.

[0084] Step S02: Extract the theoretical deadline and the minimum inheritance time of the target microprogram, and generate an inheritance deadline schedule based on the minimum inheritance time.

[0085] The target microprogram has a theoretical deadline and a minimum inheritance time. The theoretical deadline refers to the time expected to be spent for the target microprogram to run one cycle, while the minimum inheritance time refers to the smallest time period among the time periods when the target microprogram accesses shared hardware resources.

[0086] After extracting the minimum inheritance time of the target microprogram, an inheritance deadline schedule is established according to the minimum inheritance time of each target microprogram. When establishing the inheritance deadline schedule, for the hardware resources accessed by the target microprogram, it is necessary to represent the access time of the target microprogram to each hardware resource. At the same time, for the situation where multiple target microprograms hold multiple hardware resources simultaneously, the access times of holding multiple hardware resources simultaneously are represented respectively. For example, Figure 4 as shown, 0.4{A0.2{B}} represents the access method of a certain target microprogram to hardware resource A and hardware resource B. However, if the access method of the target microprogram to hardware resource A and hardware resource B is as Figure 5 shown, the representation method as Figure 4 shown will not be able to represent it correctly. Therefore, for such asFigure 5 The access mode shown has a representation of 0.4{A}0.2{B}0.1{AB}. In fact, when establishing the inheritance deadline schedule, the following access mode is adopted, as shown in Figure 5 the access mode shown. This is because during the feasibility analysis of target microprogram scheduling, only the access time of each hardware resource is required, and the situation where multiple resources are held simultaneously does not need to be analyzed. When presenting the inheritance deadline schedule, the access times held by multiple hardware resources need to be presented. Therefore, using the second representation method above will be more intuitive.

[0087] The processes in the above steps S01 and S02 are all carried out in the microprogram data analysis unit 11. After the microprogram data analysis unit 11 extracts the theoretical deadline of the target microprogram and generates the inheritance deadline schedule, it proceeds to the next step.

[0088] Step S03: Establish a ready scheduling queue and a running scheduling queue.

[0089] To simulate the scheduling process of the target microprogram, a ready scheduling queue and a running scheduling queue are established within the scheduling feasibility analysis unit 12, and the ready scheduling queue and the running scheduling queue are interconnected.

[0090] Among them, the ready scheduling queue is used to receive the target microprograms and arrange the target microprograms in ascending order of theoretical deadline.

[0091] The running scheduling queue is used to receive the inheritance deadline schedule, and is also used to schedule the head target microprogram from the ready scheduling queue, and after obtaining the head target microprogram, execute the target microprogram according to the inheritance deadline schedule, that is, arrange the access time of the hardware resources for the head target microprogram. The running scheduling queue can obtain the actual deadline based on the execution end time of the target microprogram.

[0092] The running scheduling queue schedules the microprograms in the target microprogram set in turn in the way of retrieving the head microprogram of the ready scheduling queue, and after traversing the target microprograms in the target microprogram set, arranges the target microprogram set in ascending order of actual deadline, so as to release it to the ready scheduling queue when the target microprogram reaches the next execution cycle, thereby achieving the purpose of simulating the periodic scheduling of the target microprogram.

[0093] Step S04: Input the microprogram amount of each target microprogram, the actual deadline of each target microprogram obtained by the running scheduling queue when traversing the target microprograms in the ready scheduling queue, and the running cycle of each target microprogram into the W(t) function, H(t) function, and CB(t) function.

[0094] Specifically, Among them, W(t) represents the amount of micro - processes submitted at time t, Ti is the execution period of target micro - process i, and Ci is the amount of micro - processes of target micro - process i.

[0095] Among them, H(t) represents the amount of micro - processes that must be completed at time t, Di is the actual deadline of target micro - process i, Ti is the execution period of target micro - process i, and Ci is the amount of micro - processes of target micro - process i;

[0096] CB(t) = maxΩ{CτΔτ′≤t<Dτ}, where CB(t) is the actual deadline of the head micro - process τ currently scheduled in the running scheduling queue, Ω is the set of target micro - processes, Δτ′ is the inherited deadline of the head micro - process τ currently scheduled in the running scheduling queue, which is also the time to access hardware resources, and Dτ is the theoretical deadline of the head micro - process τ currently scheduled in the running scheduling queue.

[0097] In order to establish a connection among the W(t) function, H(t) function, and CB(t) function, a linear function with a coefficient of 1 is also established, and this linear function represents the performance of the operating system. Then, the W(t) function, H(t) function, and CB(t) function are put into the linear function with a coefficient of 1.

[0098] Step S05: Determine whether the W(t) function intersects with the diagonal line before the H(t) function and the CB(t) function.

[0099] The analysis result data unit is used to display the coordinates of the W(t) function, H(t) function, and CB(t) function in the linear function with a coefficient of 1 after inputting the amount of micro - processes, actual deadline, and running period of each target micro - process into the W(t) function, H(t) function, and CB(t) function.

[0100] As Figure 6 shown, the distance between the W(t) curve and the diagonal line represents the amount of micro - processes submitted at time t;

[0101] The height of the H(t) curve represents the amount of micro - processes that must be completed at time t;

[0102] The CB(t) curve is the time by which the target micro - process is advanced, that is, the actual deadline.

[0103] If the W(t) curve intersects with the diagonal line before the H(t) curve and the CB(t) curve, it means that the set of target micro - processes is schedulable; otherwise, it is non - schedulable.

[0104] Finally, mark the schedulable set of target micro - processes as the test micro - process set, and mark the non - schedulable set of target micro - processes as the control micro - process set.

[0105] It can be seen from this that the analysis module 1 outputs a test micro-program set and a control micro-program set as the data sources for the verification module 2.

[0106] Step S2: Use the EDFI scheduling rule to schedule the test micro-program set and the control micro-program set in sequence to obtain test scheduling information.

[0107] As can be seen from step S1, the target micro-programs are the Wsn_TimerFiber micro-program, the Wsn_AppFiber micro-program, the Wsn_DemoFiber micro-program, and the Wsn_EdfiFiber micro-program respectively. Therefore, the test micro-program set and the control micro-program set obtained also both include the Wsn_TimerFiber micro-program, the Wsn_AppFiber micro-program, the Wsn_DemoFiber micro-program, and the Wsn_EdfiFiber micro-program.

[0108] Among them, the Wsn_TimerFiber micro-program is used to check whether there is a timer timeout in the operating system. If there is a timer timeout, the specified timeout function is executed. There is a tick (mark number) set in the operating system, and the Wsn_TimerFiber micro-program is executed once every time a tick is encountered. It is the most frequently executed micro-program in the operating system.

[0109] The Wsn_AppFiber micro-program is a micro-program that is periodically executed through a timer. Each time the timer times out, the execution of this micro-program is started. And the timeout check of the timer is completed by the above Wsn_TimerFiber micro-program.

[0110] The Wsn_DemoFiber micro-program is an example showing a component-based application program of the micro-program operating system. The Wsn_DemoFiber micro-program is just a function of a certain component in the application program. The component uses it to control the flashing of LED lights of different colors on the AVR platform development board to represent different states during the operation of the application program.

[0111] The Wsn_EdfiFiber micro-program is mainly used to test the execution of micro-programs with multiple program segments, as well as the feasibility and correctness of the EDFI scheduling strategy when there is competition for hardware resource access.

[0112] Specifically, the test scheduling information includes real-time test, priority inversion test, deadlock test, and micro-program segment scheduling test. The test micro-program set and the control micro-program set are used in the real-time test, and only the test micro-program set is used in other groups of tests. The principles of these four tests are described below through steps S21 to S24 respectively.

[0113] Step S21: Real-time test: First, the micro-programs in the test micro-program set and the control micro-program set are scheduled in turn using the EDFI scheduling policy. Then, the theoretical deadline of the test micro-program set obtained after scheduling is subtracted from the actual deadline to obtain the first advance time of the test. Next, the theoretical deadline of the control micro-program set obtained after scheduling is subtracted from the actual deadline to obtain the first advance time of the control.

[0114] Step S22: Priority test: Different theoretical deadlines are set for the Wsn_AppFiber micro-program, the Wsn_DemoFiber micro-program, and the Wsn_EdfiFiber micro-program. Among them, the theoretical deadline value of the Wsn_AppFiber micro-program is the smallest, that is, the highest priority. The theoretical deadline value of the Wsn_DemoFiber micro-program is the second, and the theoretical deadline value of the Wsn_EdfiFiber micro-program is the largest, that is, the lowest priority. Two micro-programs with the highest and lowest priorities access the same shared hardware resource R, and the Wsn_DemoFiber micro-program does not access any hardware resources. Then, release the three micro-programs in the time sequence shown below, and the release process uses the EDFI scheduling policy. Finally, judge whether there is a problem of priority inversion of the micro-programs in the micro-program scheduling according to the scheduling result, and generate the first scheduling information. Figure 7 As shown below, the release process uses the EDFI scheduling policy. Finally, judge whether there is a problem of priority inversion of the micro-programs in the micro-program scheduling according to the scheduling result, and generate the first scheduling information.

[0115] Step S23: Deadlock test: The Wsn_AppFiber micro-program and the Wsn_EdfiFiber micro-program access two different resources R1 and R2 in the reverse order. The low-priority Wsn_AppFiber micro-program is executed first. Then, after the Wsn_AppFiber micro-program holds the resource R1, let the Wsn_EdfiFiber micro-program preempt the Wsn_AppFiber micro-program after a certain time delay. In this case, the EDFI scheduling policy is adopted, and the first execution information is obtained according to the final execution results of the Wsn_AppFiber micro-program and the Wsn_EdfiFiber micro-program.

[0116] Step S24: Micro-program segment scheduling test: The Wsn_TimerFiber micro-program, the Wsn_AppFiber micro-program, the Wsn_DemoFiber micro-program, and the Wsn_EdfiFiber micro-program all have multiple program segments. During the micro-program scheduling process, an array is added to each micro-program to record the names and deadlines of the relevant program segments in the order of completion of the program segments, so as to generate the first order information.

[0117] After step S2 generates the first advance time for testing, the first advance time for control, the first scheduling information, the first execution information, and the first sequence information, it packs the first advance time for testing, the first advance time for control, the first scheduling information, the first execution information, and the first sequence information into test scheduling information and inputs it into step S4.

[0118] Step S3: Use the EDF scheduling rule to schedule the test microprogram set and the control microprogram set in sequence to obtain control scheduling information.

[0119] The test design in step S3 is the same as that in step S2, except that the EDFI scheduling strategy is used in step S2, while the EDF scheduling strategy is used in step S3. To facilitate the distinction of the information obtained in steps S3 and S4:

[0120] First, in the real-time test, subtract the theoretical deadline of the test microprogram set obtained after using the EDF scheduling from the actual deadline to obtain the second advance time for testing, and then subtract the theoretical deadline of the control microprogram set obtained after scheduling from the actual deadline to obtain the second advance time for control;

[0121] Second, in the priority test, use the EDFI scheduling strategy to schedule Figure 7 the three microprograms shown, and determine whether there is a problem of microprogram priority inversion in the microprogram scheduling according to the scheduling result, and generate the second scheduling information;

[0122] Then, in the deadlock test, use the EDF scheduling strategy to schedule the Wsn_AppFiber microprogram and the Wsn_EdfiFiber microprogram, and obtain the second execution information according to the execution result;

[0123] Finally, in the microprogram segment scheduling test, use the EDF scheduling strategy to schedule the Wsn_TimerFiber microprogram, the Wsn_AppFiber microprogram, the Wsn_DemoFiber microprogram, and the Wsn_EdfiFiber microprogram. At the same time, during the microprogram scheduling process, an array is added to each microprogram, and the names and deadlines of the relevant program segments are recorded according to the order in which the program segments are executed to generate the second sequence information.

[0124] After step S3 generates the second advance time for testing, the second advance time for control, the second scheduling information, the second execution information, and the second sequence information, it packs the second advance time for testing, the second advance time for control, the second scheduling information, the second execution information, and the second sequence information into control scheduling information and inputs it into step S4.

[0125] Step S4: Obtain the result information according to the test scheduling information and the control scheduling information.

[0126] After obtaining the test scheduling information and the control scheduling information, it is also necessary to formulate the final verification rules. Specifically:

[0127] For real-time verification, if the first lead time of the test is less than the first lead time of the control, the second lead time of the test, and the second lead time of the control, it indicates that the microprogram using the EDFI scheduling strategy has real-time guarantee.

[0128] For priority inversion verification, if the first scheduling information indicates that there is no priority inversion among the Wsn_AppFiber microprogram, the Wsn_DemoFiber microprogram, and the Wsn_EdfiFiber microprogram, it indicates that the EDFI scheduling strategy solves the problem of priority inversion in the microprogram scheduling process. If the second scheduling information indicates that there is priority inversion among the Wsn_AppFiber microprogram, the Wsn_DemoFiber microprogram, and the Wsn_EdfiFiber microprogram, it indicates that the EDF scheduling strategy has a priority inversion problem, and the EDFI scheduling strategy can solve this problem.

[0129] For deadlock verification, if the first execution information indicates that when the Wsn_EdfiFiber microprogram is executing, the Wsn_AppFiber microprogram stops executing until the Wsn_EdfiFiber microprogram finishes executing and then the Wsn_AppFiber microprogram continues to execute, it indicates that the EDFI scheduling strategy will not have a deadlock problem. If the second execution information indicates that when the Wsn_EdfiFiber microprogram is executing, the Wsn_AppFiber microprogram does not stop executing, and the Wsn_EdfiFiber microprogram and the Wsn_AppFiber microprogram maintain the state of simultaneously accessing hardware resources, resulting in both the Wsn_EdfiFiber microprogram and the Wsn_AppFiber microprogram being unable to continue executing, it indicates that the EDF scheduling strategy will have a deadlock problem.

[0130] For the verification of the microprogram segment scheduling, if the first order information indicates that the order of the completion of the program segments of the Wsn_TimerFiber microprogram, the Wsn_AppFiber microprogram, the Wsn_DemoFiber microprogram, and the Wsn_EdfiFiber microprogram is opposite to the order of their actual deadline sizes, that is, it is consistent with the order of priorities, it indicates that it is correct to schedule the program segments of the microprogram using the EDFI scheduling strategy. When the second order information indicates that the order of the completion of the program segments of the Wsn_TimerFiber microprogram, the Wsn_AppFiber microprogram, the Wsn_DemoFiber microprogram, and the Wsn_EdfiFiber microprogram is not opposite to the order of their actual deadline sizes, that is, it is not consistent with the order of priorities, it indicates that it is incorrect to schedule the program segments of the microprogram using the EDF scheduling strategy.

[0131] Generate result information for the above four verification results, so that technicians or users can understand the feasibility of scheduling the microprogram set using the EDFI scheduling strategy based on the result information, thereby facilitating technicians to deploy the actual embedded system according to the simulation results.

[0132] The implementation principle of the method for verifying the schedulability of microprograms in the embedded system of the embodiment of the present application is as follows: First, set two sets of data, one set is the test microprogram set, and the other set is the control microprogram set; then, perform real-time tests on the test microprogram set and the control microprogram set, and then use the test microprogram set to perform priority tests, deadlock tests, and microprogram segment scheduling tests, and use the EDFI scheduling strategy and the EDF scheduling strategy to schedule the microprograms respectively in the real-time test, priority test, deadlock test, and microprogram segment scheduling test. Finally, compare the test scheduling information generated using the EDFI scheduling strategy and the control scheduling information generated using the EDF scheduling strategy, and verify the feasibility of scheduling the microprogram using the EDFI scheduling strategy according to the comparison result. It can be seen that the present application ensures the accuracy of the obtained schedulability results of the microprogram by setting two sets of data and setting multiple sets of tests on the basis of the two sets of data.

[0133] The above description is only a preferred embodiment of the present application and an explanation of the applied technical principle. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solutions formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the foregoing disclosure concept. For example, the technical solutions formed by mutually replacing the above features with the (but not limited to) technical features with similar functions disclosed in the present application.

Claims

1. A method for verifying the schedulability of microprograms in an embedded system, characterized in that Including: Obtain a test micro-program set and a control micro-program set; Use the EDFI scheduling rule to schedule the test micro-program set and the control micro-program set in sequence to obtain test scheduling information; Use the EDF scheduling rule to schedule the test micro-program set and the control micro-program set in sequence to obtain control scheduling information; Obtain result information according to the test scheduling information and the control scheduling information; Before obtaining the test micro-program, it includes: Obtain a target micro-program set, the target micro-program set includes multiple target micro-programs, and the target micro-programs include Wsn_TimerFiber micro-program, Wsn_AppFiber micro-program, Wsn_DemoFiber micro-program, and Wsn_EdfiFiber micro-program; Extract the theoretical deadline and minimum inheritance time of the target micro-program, and generate an inheritance deadline schedule according to the minimum inheritance time; Establish a ready scheduling queue and a running scheduling queue; The ready scheduling queue is used to receive the target micro-programs and arrange the target micro-programs in ascending order of theoretical deadline; The running scheduling queue is used to receive the inheritance deadline schedule and the target micro-programs released by the ready scheduling queue, and execute the target micro-programs according to the inheritance deadline schedule to obtain the actual deadline; the running scheduling queue is also used to arrange the executed target micro-programs in ascending order of actual deadline and release them to the ready scheduling queue when the target micro-program reaches the next execution cycle; Input the micro-program volume of each target micro-program, the actual deadline of each target micro-program obtained when the running scheduling queue traverses the target micro-programs in the ready scheduling queue, and the running cycle of each target micro-program into the W(t) function, H(t) function, and CB(t) function; Establish a linear function with a coefficient of 1, put the W(t) function, H(t) function, and CB(t) function into the linear function with a coefficient of 1, and determine whether the W(t) function intersects the diagonal line before the H(t) function and the CB(t) function; If so, mark the target micro-program set as the test micro-program set; If not, mark the target micro-program set as the control micro-program set; The obtaining result information according to the test scheduling information and the control scheduling information includes: Perform real-time verification, priority inversion verification, deadlock verification, and micro-program segment scheduling verification on the test scheduling information and the control scheduling information respectively to obtain result information.

2. The schedulability verification method for microprograms in the embedded system according to claim 1, wherein The test scheduling information includes real-time test, priority inversion test, deadlock test, and micro-program micro-program segment scheduling test.

3. The schedulability verification method for microprograms in the embedded system according to claim 2, characterized in that, The real-time test includes: Use the EDFI scheduling strategy to schedule the test micro-program set to obtain the actual deadline; Subtract the theoretical deadline of the test micro-program set from the actual deadline to obtain the first advance time of the test; Use the EDFI scheduling strategy to retrieve the control micro-program set to obtain the actual deadline; Subtract the theoretical deadline of the control micro-program set from the actual deadline to obtain the first advance time of the control.

4. The schedulability verification method of the microprogram in the embedded system according to claim 2, characterized in that The priority inversion test includes: Extract the Wsn_AppFiber micro-program, Wsn_DemoFiber micro-program, and Wsn_EdfiFiber micro-program; Set the Wsn_AppFiber microprogram and the Wsn_EdfiFiber microprogram to access the same shared hardware resource R simultaneously, and set the Wsn_DemoFiber microprogram to not access any hardware resources; Release the Wsn_EdfiFiber microprogram, the Wsn_DemoFiber microprogram, and the Wsn_AppFiber microprogram in sequence, and use the EDFI scheduling policy to schedule the released Wsn_EdfiFiber microprogram, Wsn_DemoFiber microprogram, and Wsn_AppFiber microprogram in sequence; Determine whether priority inversion of the microprogram occurs during the scheduling of the Wsn_EdfiFiber microprogram, the Wsn_DemoFiber microprogram, and the Wsn_AppFiber microprogram, and generate first scheduling information.

5. The schedulability verification method for microprograms in the embedded system according to claim 2, characterized in that, The deadlock test includes: Extract the Wsn_AppFiber microprogram and the Wsn_EdfiFiber microprogram; Set the Wsn_AppFiber microprogram and the Wsn_EdfiFiber microprogram to access the hardware resource R1 simultaneously; Use the EDFI scheduling policy to schedule the Wsn_AppFiber microprogram first. After the Wsn_AppFiber microprogram holds the hardware resource R1, let the Wsn_EdfiFiber microprogram preempt the Wsn_AppFiber microprogram after a certain time delay; Determine whether the Wsn_AppFiber microprogram and the Wsn_EdfiFiber microprogram are deadlocked, and generate first execution information.

6. The schedulability verification method of the microprogram in the embedded system according to claim 2, characterized in that, The microprogram segment scheduling test includes: Extract the Wsn_TimerFiber microprogram, the Wsn_AppFiber microprogram, the Wsn_DemoFiber microprogram, and the Wsn_EdfiFiber microprogram; Add an array to each of the Wsn_TimerFiber microprogram, the Wsn_AppFiber microprogram, the Wsn_DemoFiber microprogram, and the Wsn_EdfiFiber microprogram; Use the EDFI scheduling policy to schedule the Wsn_TimerFiber microprogram, the Wsn_AppFiber microprogram, the Wsn_DemoFiber microprogram, and the Wsn_EdfiFiber microprogram after adding the array; Record the names and deadlines of relevant program segments according to the scheduling results, and generate first-order information.

7. A schedulability verification system for microprograms in an embedded system, characterized in that Including an analysis module (1) for running the method described in claim 1 and a verification module (2) for running the method described in any one of claims 1-6; The analysis module (1) includes a microprogram data analysis unit (11), a scheduling feasibility analysis unit (12), and an analysis result data unit (13) connected in sequence; The verification module (2) includes a data receiving unit (21), a first processing unit (22), a second processing unit (23), and a result generating unit (24); The data receiving unit (21) is used to obtain a test microprogram set and a control microprogram set; The first processing unit (22) is configured to sequentially schedule the test microprogram set and the control microprogram set according to the EDFI scheduling rule to obtain test scheduling information; The second processing unit (23) is configured to sequentially schedule the test microprogram set and the control microprogram set according to the EDF scheduling rule to obtain control scheduling information; The result generation unit (24) is configured to obtain result information based on the test scheduling information and the control scheduling information.

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