Voltage sampling circuit for multi-cell battery management chip

Abstract

The present invention discloses a voltage sampling circuit for a multi-cell battery management chip. A unity-gain operational amplifier is added to the positive-end battery voltage in the sampling circuit of the first cell. This ensures that, while the voltage sampling result remains unchanged, the current consumed by the sampling circuit is provided by a low-voltage voltage source in the chip, i.e., all cells in the battery pack are simultaneously provided, not by the first cell alone. The current consumed by the sampling circuit of the highest cell is provided by the voltage of the highest cell, requiring no modification. Positive-end voltage preprocessing circuits and negative-end voltage preprocessing circuits are added to the remaining cells, ensuring that no additional current flows out of the sampling cell itself. The current flowing through each cell in the battery pack during the sampling process is consistent. Furthermore, the connection method of the operational amplifier in the sampling circuit is modified, avoiding the use of a large number of high-voltage MOS transistors in the operational amplifier and improving voltage sampling accuracy.

Description

Technical Field

[0001] The invention belongs to the technical field of analog battery management and relates to a voltage sampling circuit applied to a multi-cell battery management chip. Background Art

[0002] New energy vehicles and smart home products are becoming increasingly popular in our lives, and lithium batteries play an indispensable role in them. Usually, multiple lithium batteries are connected in series to power the products. However, if the lithium battery is over-voltage or under-voltage during use, it will cause chemical reactions inside the lithium battery, seriously affecting the performance and life of the lithium battery. Therefore, a battery protection chip is needed to monitor the battery voltage of each lithium battery in time and protect the lithium battery. The voltage of a normal battery is 2-5V. Multiple lithium batteries connected in series will generate a high voltage to the ground, making it difficult to sample the voltage of each battery. The traditional voltage sampling circuit using an operational amplifier solves the problem of high-voltage sampling, but there are two problems (1) When sampling the voltage of each battery, there is a current path from the positive terminal voltage of the battery to the ground, causing current to flow out of a single battery. Due to the connection relationship of the series battery group, when sampling the first battery, the first battery flows out the sampling current; when sampling the second battery, the first and second batteries flow out the sampling current at the same time; when sampling the third battery, the first, second and third batteries flow out the sampling current at the same time. After sampling the entire battery pack, the current flowing out of each cell will vary greatly, causing battery imbalance and subsequently damaging the battery pack. (2) The upper end of the operational amplifier is connected to the highest cell voltage, and the lower end is grounded, resulting in a large voltage difference between the upper and lower ends of the operational amplifier, requiring the use of multiple high-voltage MOS transistors, which reduces sampling accuracy. Summary of the Invention

[0003] The purpose of the present invention is to provide a voltage sampling circuit for a multi-cell battery management chip, which solves the problem of imbalance between cells caused by unequal outflow current from each cell during the sampling process of a traditional voltage sampling circuit, which in turn leads to a short battery life. At the same time, it solves the problem of low sampling accuracy caused by excessive use of high-voltage tubes in operational amplifiers in existing voltage sampling circuits.

[0004] The technical solution adopted by the present invention is a voltage sampling circuit applied to a multi-cell battery management chip, including a first-cell battery sampling circuit, several middle-cell battery sampling circuits and a highest-cell battery sampling circuit connected in parallel; the first-cell battery sampling circuit is provided with an operational amplifier OP1 at the positive terminal battery voltage.

[0005] The present invention is also characterized in that:

[0006] The middle battery sampling circuit includes an operational amplifier OP, the upper end of the operational amplifier OP is connected to the positive terminal voltage preprocessing circuit, the lower end of the operational amplifier OP is connected to the upper end of the resistor R, the lower end of the resistor R is connected to the drain end of the MOS tube M, the source end of the MOS tube M is connected to the upper end of the current source I, the lower end of the current source I is grounded, and the positive end of the operational amplifier OP is connected to the resistor R 32 The output of the operational amplifier OP is connected to the MOS tube M 34 The gate of the operational amplifier OP is connected to the negative terminal voltage pre-processing circuit, and the MOS tube M 34 The drain termination resistor R 32 The lower end of the MOS tube M 34 The source termination resistor R 31 The upper end of the output V OUT .

[0007] The negative terminal voltage pre-processing circuit includes a current source I 31 , current source I 31 The lower end is connected to the MOS tube M 31 The source end of MOS tube M 31 The gate terminal is connected to the negative terminal of the battery, and the MOS tube M 31 The drain terminal is grounded, and the MOS tube M 31 The source end of the current source is input to the negative terminal of the operational amplifier OP, and the current source I 31 The upper end is connected to the highest battery voltage V CC3 .

[0008] The positive terminal voltage pre-processing circuit includes a current source I 33 , current source I 33 The lower end is connected to the PMOS tube M 32 , PMOS tube M 32 The gate terminal is connected to the positive terminal of the battery, and the PMOS tube M 32 The drain terminal is connected to the NMOS tube M 33 The gate terminal is connected to the current source I 32 The upper end of the PMOS tube M 32 The source terminal is connected to the NMOS tube M 33 The drain end of NMOS tube M 33 The source end of the current source I 33 The upper end is connected to V CC3 .

[0009] The current flowing through each battery during the battery sampling process is consistent, specifically including the following process: the positive terminal of the first battery is connected to the positive input of the operational amplifier OP1, and the output voltage is equal to the positive terminal voltage of the battery;

[0010] The positive terminal of the middle battery is connected to the positive terminal voltage pre-processing circuit, and the output voltage of the positive terminal voltage pre-processing circuit is V + +V GS, the negative terminal voltage of the battery is connected to the negative terminal voltage preprocessing circuit, and the output of the negative terminal voltage preprocessing circuit is V-+V GS , where V GS MOS tube M 31 and M 32 The absolute value of the gate-source voltage.

[0011] The beneficial effect of the present invention is that, compared to conventional voltage sampling circuits for multi-cell battery protection chips, the present invention solves the problem of inconsistent current flowing out of each battery during battery voltage sampling. By adding a voltage preprocessing circuit to the voltage sampling circuits of all batteries except the highest battery, the current consumed during sampling of each battery is not provided by the battery itself, but by all batteries together, that is, the current flowing through each battery during the sampling process is consistent. When sampling the voltage of the highest battery, the current itself is provided by all batteries together, so no optimization is required. Furthermore, the connection method of the operational amplifier in the sampling circuit is changed, avoiding the use of a large number of high-voltage MOS transistors in the operational amplifier, thereby improving the voltage sampling accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a schematic diagram of the structure of the voltage sampling circuit of the present invention applied to a multi-cell battery management chip (taking 4 batteries as an example);

[0013] Figure 2 The present invention is applied to the voltage sampling circuit of a multi-cell battery management chip for the voltage sampling circuit of other cells except the first cell and the last cell;

[0014] Figure 3 This is a simulation diagram of the battery positive terminal current during the voltage sampling process in the voltage sampling circuit of the multi-cell battery management chip applied to the present invention;

[0015] Figure 4 This is a simulation diagram of the negative terminal current of the battery during the voltage sampling process in the voltage sampling circuit of the multi-cell battery management chip applied to the present invention;

[0016] Figure 5 The present invention is applied to the sampling voltage simulation of battery voltage sampling in the voltage sampling circuit of a multi-cell battery management chip. DETAILED DESCRIPTION

[0017] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0018] The present invention is applied to the voltage sampling circuit of a multi-cell battery management chip, such as Figure 1 As shown, taking 4 batteries in series as an example (for more battery packs, the voltage sampling circuits of 2 and 3 batteries are repeated), the voltage sampling circuit of the first battery includes an operational amplifier OP1, a MOS tube M11 , current source I 11 And sampling resistors R1 and R2; the voltage sampling circuit of the second battery includes a battery positive terminal voltage preprocessing circuit, a battery negative terminal voltage preprocessing circuit, an operational amplifier OP2, a resistor R 21 , MOS tube M 21 , current source I 21 , sampling resistors R3, R4 and isolation MOS tube M5; the voltage sampling circuit of the third battery includes a battery positive terminal voltage preprocessing circuit, a battery negative terminal voltage preprocessing circuit, an operational amplifier OP3, a resistor R 31 , MOS tube M 31 , current source I 31 , sampling resistors R5, R6 and isolation MOS tube M9; the voltage sampling circuit of the fourth battery includes operational amplifier OP4, resistor R 41 , MOS tube M 41 , current source I 41 , sampling resistors R7, R8 and isolation MOS tube M 10 .

[0019] The positive terminal of the battery is connected to the positive input of the operational amplifier OP1. Since the operational amplifier OP1 is connected in the form of a unity gain amplifier, the output voltage is equal to the positive terminal voltage of the battery. The output terminal of the operational amplifier is connected to the upper end of the resistor R2, and the lower end of the resistor R2 is connected to the upper end of the resistor R1. The lower end of the resistor R1 is grounded. Since the negative terminal voltage of the battery is grounded, the output voltage is The upper terminal of the operational amplifier OP1 is connected to V DD5 , V DD5 The 5V stable voltage provided by the LDO in the chip, that is, the current flowing through the operational amplifier and the current flowing through the resistors R1 and R2 is V DD5 Provided, that is, all batteries are provided together. The lower end of the operational amplifier OP1 is connected to the MOS tube M 11 The drain end of MOS tube M 11 The source terminal passes through the current source I 11 Ground, M 11 The gate terminal is connected to the EN1 signal, and the MOS tube M 11 and current source I 11 The tail current source and switch are provided for the operational amplifier OP1. The positive terminal of the battery is connected to the positive terminal of the operational amplifier OP1, which is the gate terminal of the input MOS tube of the operational amplifier OP1. The gate terminal resistance of the MOS tube is infinite, so no independent current flows out of the first battery, ensuring battery balance during the sampling process.

[0020] The positive terminal of the battery in Section 2 is connected to the positive terminal voltage pre-processing circuit, which is composed of a super source follower. The positive terminal of the battery is input to the gate terminal of the MOS tube M2, and the current flowing through the MOS tube M2 is provided by I2, thereby obtaining the gate-source voltage of the MOS tube M2, which is recorded as V GS , so the output voltage of the source end of MOS tube M2 is V 2+ +V GS The source terminal of MOS tube M2 is connected to the drain terminal of MOS tube M4, the gate terminal of MOS tube M4 is connected to the drain terminal of MOS tube M2, and the source terminal of MOS tube M4 is connected to the lower end of current source I2, so that MOS tubes M4 and M2 form a negative feedback structure. Current source I3 is used to provide current flowing through MOS tubes M2 and M4 and the load, and finally the output of the positive terminal voltage preprocessing circuit is V 2+ +V GS The negative terminal voltage of the battery is connected to the negative terminal voltage pre-processing circuit, which is composed of an ordinary source follower. The negative terminal of the battery is input to the gate of the MOS tube M1. Since the output of the negative terminal voltage pre-processing circuit is connected to the gate of the operational amplifier input pair, no current flows out. The current flowing through the MOS tube M1 is determined by the current source I1. By controlling the current sources I1 and I2 to be equal, the two PMOS tubes M1 and M2 are consistent, so that the gate-source voltage of the MOS tube M1 is equal to the gate-source voltage of the MOS tube M2. V GS , ultimately making the output of the negative terminal voltage pre-processing circuit V 2- +V GS The output of the negative voltage pre-processing circuit is connected to the negative terminal of the operational amplifier OP2. Through the virtual short characteristic of the operational amplifier OP2, the voltage at the lower end of the resistor R4 is equal to V 2- +V GS The output of the positive terminal voltage pre-processing circuit provides power to the operational amplifier OP2, while making the upper terminal voltage of the resistor R4 equal to V 2+ +V GS , thus generating a current of magnitude of The isolation MOS tube M5 can not only ensure that the high voltage at the drain end does not affect the negative voltage at the source end, but also make the current flowing through the resistor R4 equal to the current flowing through the resistor R3. At the same time, it forms a negative feedback structure with the operational amplifier OP1, and finally outputs a voltage at the output end. The voltage at the top of current source I3 is V CC , so the current flowing through the operational amplifier, the currents of resistors R3, R4, and the current sources I1, I2, and I3 are all V CC The positive and negative terminals of the battery are connected to the gate terminals of the MOS tube, and no current flows out, thus ensuring the battery balance during the sampling process. In addition, the upper terminal of the operational amplifier OP2 is connected to the output V 2+ +V GS , the lower terminal resistor R 21The upper end of the resistor R 21 The lower end is connected to the MOS tube M 21 The drain end of MOS tube M 21 The source terminal passes through the current source I 21 Ground, M 21 The gate terminal is connected to the EN2 signal, and the MOS tube M 21 and current source I 21 Provide tail current source and switch for operational amplifier OP2. Design operational amplifier OP2 as a five-tube operational amplifier with NMOS input pair tubes. Then MOS tube M 21 At the same time, it ensures that the lower end voltage of the operational amplifier is determined by the gate voltage of the operational amplifier OP2 input pair tube. The gate terminal of the operational amplifier OP2 input pair tube is connected to the output V of the negative terminal voltage preprocessing circuit. 2- +V GS , the voltage difference between the upper end and the input pair of the operational amplifier OP2 is the voltage of one battery, and the voltage difference between the upper and lower ends of the operational amplifier OP2 is the voltage of one battery plus the gate-source voltage of the input pair of the operational amplifier OP2, which ensures that the voltage difference between the upper and lower ends of the operational amplifier is low, avoids the use of high-voltage MOS tubes in the operational amplifier OP2, and improves the accuracy of the voltage sampling circuit.

[0021] The positive terminal of the battery in Section 3 is connected to the positive terminal voltage pre-processing circuit, which is composed of a super source follower. The positive terminal of the battery is input to the gate terminal of the MOS tube M7, and the current flowing through the MOS tube M7 is provided by the current source I5, thereby obtaining the gate-source voltage of the MOS tube M7, which is recorded as V GS , so that the source output voltage of MOS tube M7 is V 3+ +V GS The source terminal of MOS tube M7 is connected to the drain terminal of MOS tube M8, the gate terminal of MOS tube M8 is connected to the drain terminal of MOS tube M7, and the source terminal of MOS tube M8 is connected to the lower end of current source I5, so that MOS tubes M8 and M7 form a negative feedback structure. Current source I6 is used to provide current flowing through MOS tubes M7 and M8 and the load, and finally the output of the positive terminal voltage preprocessing circuit is V 3+ +V GS The negative terminal voltage of the battery is connected to the negative terminal voltage pre-processing circuit, which is composed of an ordinary source follower. The negative terminal of the battery is input to the gate of the MOS tube M6. Since the output of the negative terminal voltage pre-processing circuit is connected to the gate of the operational amplifier input pair, no current flows out. The current flowing through the MOS tube M6 is determined by the current source I4. By controlling the current sources I4 and I5 to be equal, the two PMOS tubes M6 and M7 are consistent, so that the gate-source voltage of the MOS tube M6 is equal to the gate-source voltage of the MOS tube M7. GS , ultimately making the output of the negative terminal voltage pre-processing circuit V 3- +V GSThe output of the negative voltage pre-processing circuit is connected to the negative terminal of the operational amplifier OP3. Through the virtual short characteristic of the operational amplifier OP3, the voltage at the lower end of the resistor R6 is equal to V 3- +V GS The output of the positive terminal voltage pre-processing circuit provides power to the operational amplifier OP3, while making the upper terminal voltage of the resistor R6 equal to V 3+ +V GS , thus generating a current of magnitude of The isolation MOS tube M9 can not only ensure that the high voltage at the drain end does not affect the negative voltage at the source end, but also make the current flowing through the resistor R6 equal to the current flowing through the resistor R5. At the same time, it forms a negative feedback structure with the operational amplifier, and finally outputs a voltage at the output end. The voltage at the top of current source I6 is V CC , so the current flowing through the operational amplifier OP3, the currents of resistors R5, R6, and the current sources I4, I5, I6 are all V CC The positive and negative terminals of the battery are connected to the gate terminals of the MOS tube, and no current flows out, thus ensuring the battery balance during the sampling process. In addition, the upper terminal of the operational amplifier OP3 is connected to the output V 3+ +V GS , the lower terminal resistor R 31 The upper end of the resistor R 31 The lower end is connected to the MOS tube M 31 The drain end of MOS tube M 31 The source terminal passes through the current source I 31 Ground, M 31 The gate terminal is connected to the EN3 signal, and the MOS tube M 31 and current source I 31 Provide tail current source and switch for operational amplifier OP3. Design operational amplifier OP3 as a five-tube operational amplifier with NMOS input pair tubes. Then MOS tube M 31 At the same time, it ensures that the lower end voltage of the operational amplifier is determined by the gate voltage of the operational amplifier OP3 input pair tube, and the gate terminal of the operational amplifier input pair tube is connected to the output V of the negative terminal voltage preprocessing circuit. 3- +V GS , the voltage between the upper end and the input pair of the operational amplifier OP3 is the voltage of a battery, and the voltage difference between the upper and lower ends of the operational amplifier OP3 is the voltage of a battery plus the gate-source voltage of the input pair of the operational amplifier OP3, which ensures that the voltage difference between the upper and lower ends of the operational amplifier is low, avoids the use of high-voltage MOS tubes in the operational amplifier OP3, and improves the accuracy of the voltage sampling circuit.

[0022] The negative terminal of the fourth battery is connected to the negative terminal of the operational amplifier OP4, and the positive terminal of the operational amplifier OP4 is connected to the lower end of the resistor R8 and the MOS tube M 10The drain end of the output is connected to the MOS tube M 10 The gate terminal of the operational amplifier OP4 and the MOS tube M 10 A negative feedback structure is formed, and the virtual short characteristic of the operational amplifier OP4 is used to make the voltage at the lower end of the resistor R8 equal to the negative terminal voltage of the battery. The positive terminal of the battery is connected to the upper end of the operational amplifier OP4 to provide power for OP4, and is also connected to the upper end of the resistor R8, thereby generating a voltage of The current of the isolation MOS tube M 10 The source terminal is connected to the upper end of the resistor R7, and the lower end of the resistor R7 is grounded. This can ensure that the high voltage at the drain end does not affect the negative voltage at the source end, and also make the current flowing through the resistor R8 equal to the current flowing through the resistor R7, and finally output voltage at the output end. The current flowing through the operational amplifier OP4 and resistors R7 and R8 is determined by V CC Provided, that is, provided for all batteries together, without affecting battery balancing. The upper end of the operational amplifier OP4 is connected to V CC , the lower terminal resistor R 41 The upper end of the resistor R 41 The lower end is connected to the MOS tube M 41 The drain end of MOS tube M 41 The source terminal passes through the current source I 41 Ground, M 41 The gate terminal is connected to the EN4 signal, and the MOS tube M 41 and current source I 41 Provide tail current source and switch for operational amplifier OP4. Design operational amplifier OP4 as a five-tube operational amplifier with NMOS input pair tubes. Then MOS tube M 41 At the same time, the lower voltage of the operational amplifier is determined by the gate voltage of the tube input of the operational amplifier OP3, and the negative input of the operational amplifier OP4 is V 4- , the voltage between the upper end of the operational amplifier OP4 and the input pair tube is the voltage of one battery, and the voltage difference between the upper and lower ends of the operational amplifier OP4 is the voltage of one battery plus the gate-source voltage of the input pair tube of the operational amplifier OP4, which ensures that the voltage difference between the upper and lower ends of the operational amplifier OP4 is low, avoids the use of high-voltage MOS tubes in the operational amplifier OP4, and improves the accuracy of the voltage sampling circuit.

[0023] like Figure 3 It is a voltage sampling circuit for the rest of the batteries except the first and highest battery. Compared with the traditional structure, it adds a battery positive terminal voltage pre-processing circuit and a battery negative terminal pre-processing circuit. The output of the battery positive terminal pre-processing circuit converts the battery positive terminal voltage V + Raise a MOS tube M 32 The gate-source voltage V GS , connect the upper end of the sampling resistor, MOS tube M 32 and M33 It forms a negative feedback loop to improve the load capacity of the pre-processing circuit and make the highest battery voltage V CC3 Through the current source I 33 The operational amplifier OP and the sampling resistor R 32 , R 32 Provide current so that the sampling battery itself does not provide additional current compared to other batteries, ensuring the balance of each battery during the voltage sampling process. The battery negative terminal pre-processing circuit makes the battery negative terminal voltage V- raise one MOS tube M 31 The gate-source voltage V GS , by controlling the current source I 31 Equal to I 32 And M 31 , M 32 The two PMOS tubes are consistent, making the two V GS Equal, through the operational amplifier OP and MOS tube M 34 The negative feedback loop formed transmits the voltage to the sampling resistor R 32 The lower end of the sampling resistor R 32 Raise V at both ends simultaneously GS voltage, so the current flowing through the sampling resistor is The output voltage In addition, the upper voltage of the operational amplifier OP is V + +V GS , the lower end is connected to the resistor R, MOS tube M and current source I in sequence, and the operational amplifier OP is designed to be a five-tube operational amplifier with N input pairs, so that the lower end voltage of the operational amplifier OP is determined by the input voltage, and the negative input voltage of the operational amplifier OP is V-+V GS , the voltage difference between the upper and lower ends of the operational amplifier is the voltage of a battery plus the gate-source voltage of the operational amplifier OP input pair tube. The voltage difference is low voltage, which avoids the use of a large number of high-voltage MOS tubes in the operational amplifier OP, improves the performance of the operational amplifier, and improves the accuracy of the voltage sampling circuit.

[0024] The present invention is applied to a voltage sampling circuit of a multi-cell battery management chip. Compared to a conventional battery voltage sampling circuit, a unit-gain-connected operational amplifier is added to the positive-end battery voltage in the first-cell battery sampling circuit. This ensures that, while the voltage sampling result remains unchanged, the current consumed by the sampling circuit is provided by a low-voltage voltage source in the chip, i.e., provided simultaneously by all batteries in the battery pack, not by the first-cell battery alone. The current consumed by the highest-cell battery sampling circuit is itself provided by the highest-cell battery voltage, requiring no improvement. Positive-end voltage preprocessing circuits and negative-end voltage preprocessing circuits are added to the remaining cells, ensuring that no additional current flows out of the sampling cell itself and that the current flowing through the cells in the battery pack is consistent. Furthermore, the connection design of the operational amplifier in each cell voltage sampling circuit ensures that the voltage difference between the upper and lower ends of the operational amplifier is low, avoiding the use of a large number of high-voltage MOS transistors in the operational amplifier, improving the performance of the operational amplifier, and thereby improving the accuracy of voltage sampling.

[0025] like Figure 3 The figure shows the simulation diagram of the positive terminal current of the battery when the middle battery voltage is sampled. The results show that the current flowing out of the positive terminal of the battery is 13fA. Figure 4 The figure shows the simulation diagram of the negative terminal current of the battery when the voltage of the middle battery cell is sampled. The result shows that the current flowing out of the negative terminal of the battery is 15fA. It is assumed that there is no current flowing out of the positive and negative terminals of the battery. After the voltage sampling of the entire battery pack is completed, there will be no imbalance between the batteries. Figure 5 The following is a simulation diagram of the sampling voltage of the middle battery voltage sampling. When the battery voltage is 4V and the proportional coefficient is 1 / 2, the sampling voltage is 2.00008V, and the sampling voltage accuracy is

Claims

1. A voltage sampling circuit for a multi-cell battery management chip, characterized by: It includes a first battery sampling circuit, a plurality of middle battery sampling circuits and a highest battery sampling circuit connected in parallel; the first battery sampling circuit is provided with an operational amplifier OP1 at the positive terminal battery voltage; The middle battery sampling circuit includes an operational amplifier OP, the upper end of the operational amplifier OP is connected to the positive terminal voltage preprocessing circuit, the lower end of the operational amplifier is connected to the upper end of the resistor R, the lower end of the resistor R is connected to the drain end of the MOS tube M, the source end of the MOS tube M is connected to the upper end of the current source I, the lower end of the current source I is grounded, and the positive end of the operational amplifier OP is connected to the resistor R 32 The output of the operational amplifier OP is connected to the MOS tube M 34 The gate of the operational amplifier OP is connected to the negative terminal voltage pre-processing circuit, and the MOS tube M 34 The drain termination resistor R 32 The lower end of the MOS tube M 34 The source termination resistor R 31 The upper end of the output V OUT .

2. The voltage sampling circuit for a multi-cell battery management chip according to claim 1, wherein: The negative terminal voltage preprocessing circuit includes a current source I 31 , current source I 31 The lower end is connected to the MOS tube M 31 The source end of MOS tube M 31 The gate terminal is connected to the negative terminal of the battery, and the MOS tube M 31 The drain terminal is grounded, M 31 The source end of the current source is input to the negative terminal of the operational amplifier OP, and the current source I 31 The upper end is connected to the highest battery voltage V CC3 .

3. The voltage sampling circuit for a multi-cell battery management chip according to claim 1, wherein: The positive terminal voltage preprocessing circuit includes a current source I 33 , I 33 The lower end is connected to the PMOS tube M 32 , PMOS tube M 32 The gate terminal is connected to the positive terminal of the battery, and the PMOS tube M 32 The drain terminal is connected to the NMOS tube M 33 The gate terminal is connected to the current source I 32 The upper end of the PMOS tube M 32 The source terminal is connected to the NMOS tube M 33 The drain end of NMOS tube M 33 The source end of the current source I 33 The upper end is connected to V CC3 .

4. The voltage sampling circuit for a multi-cell battery management chip according to claim 1, wherein: The battery sampling process includes the following steps: the positive terminal of the first battery is connected to the positive input of the operational amplifier OP1, and the output voltage is equal to the positive terminal voltage of the battery; The positive terminal of the middle battery is connected to the positive terminal voltage pre-processing circuit, and the output voltage of the positive terminal voltage pre-processing circuit is V + +V GS , the negative terminal voltage of the battery is connected to the negative terminal voltage preprocessing circuit, and the output of the negative terminal voltage preprocessing circuit is V-+V GS , where V GS MOS tube M 31 and M 32 The absolute value of the gate-source voltage.

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