Method and apparatus for controlling display backlighting

Abstract

The present disclosure relates to methods and apparatus for controlling a display backlight. A display is disclosed herein that can have a display layer forming a pixel array. The pixel array can be illuminated using a backlight unit. The backlight unit can include a plurality of light emitting diode strings (LEDs). The plurality of LED strings can be controlled by one or more backlight driver integrated circuits (ICs). In a multi-driver IC architecture, an enable signal can be used to set a desired phase delay between the plurality of ICs. One or more of the LED strings can exhibit a short fault. Depending on the number of faulty LED strings, the backlight unit can selectively throttle the maximum brightness of the display. The LED strings can receive an output voltage from a DC / DC converter and can be driven using a current driver. The DC / DC converter can be controlled by a headroom feedforward control circuit to ensure that the current driver has sufficient headroom while suppressing acoustic noise.

Description

[0001] This application is a divisional application of the patent application with application number 201910839605.2 and titled "Method and apparatus for controlling display backlight" and filed on September 6, 2019. TECHNICAL FIELD

[0002] The present disclosure relates generally to electronic devices, and more particularly to electronic devices having displays. BACKGROUND

[0003] Electronic devices often include displays. Backlit displays, such as backlit liquid crystal displays, include a backlight unit. The backlight unit generates light that travels outward through an array of pixels in the display. The pixels modulate the intensity of the light from the backlight unit to form an image on the display.

[0004] The backlight unit helps ensure that the display can display images under a variety of ambient light illuminance conditions. However, if not careful, the backlight unit can generate light that does not effectively illuminate the display pixels or does not allow the display pixels to exhibit a desired level of color performance. SUMMARY

[0005] A display can have a display layer including a liquid crystal layer, a color filter layer, and a thin film transistor layer, and can also include a backlight unit configured to illuminate the display layer. In one suitable arrangement, the backlight unit can include a plurality of light emitting diode (LED) strings, a first backlight driver integrated circuit configured to drive a first subset of the LED strings of the plurality of LED strings, and a second backlight driver integrated circuit configured to drive a second subset of the LED strings of the plurality of LED strings. The first backlight driver integrated circuit and the second backlight driver integrated circuit are configured to receive a common synchronization signal for ensuring that a first pulse width modulation signal and a second pulse width modulation signal generated by the first backlight driver integrated circuit and the second backlight driver integrated circuit exhibit a same frequency. The first backlight driver integrated circuit and the second backlight driver integrated circuit can also receive an enable signal that sets a predetermined phase delay between the first pulse width modulation signal and the second pulse width modulation signal generated by the first backlight driver integrated circuit and the second backlight driver integrated circuit.

[0006] According to another suitable arrangement, the display can further include a current driver circuit coupled to the plurality of LED strings, where the current driver circuit is configured to throttle a maximum brightness of the backlight unit when at least one of the plurality of LED strings fails. The backlight unit can include a failure detection circuit configured to detect a number of failed LED strings in the plurality of LED strings. An amount by which the current driver circuit throttles the maximum brightness of the backlight unit is a function of the number of failed LED strings determined by the failure detection circuit (e.g., the amount by which the current driver circuit throttles the maximum brightness of the backlight unit is a function of a product of the number of failed LED strings and a throttle factor). The throttle factor can be a programmable value in a range of 5% to 20%.

[0007] According to another suitable arrangement, the backlight unit can further include a DC-to-DC converter configured to provide an output voltage to the plurality of LED strings and a headroom feedforward control circuit configured to receive a brightness command. In particular, the headroom feedforward control circuit directs the DC-to-DC converter to adjust the output voltage by a predicted amount in response to detecting a change in the brightness command. The predicted amount can be calculated using a linear or non-linear formula as a function of the brightness command.

[0008] According to yet another suitable arrangement, the DC-to-DC converter can be a boost converter including: an input port to receive an input voltage; an output port on which an output voltage is generated; a first inductor coupled between the input port and the output port; a first switch and a first current sense resistor coupled in series between the first inductor and a ground; a controller configured to receive a first sense signal from the first current sense resistor and selectively turn off the first switch in response to detecting that an amount of current flowing through the first switch exceeds a predetermined peak current level.

[0009] The boost converter can further include: a second inductor coupled between the input port and the output port; a second switch and a second current sense resistor coupled in series between the second inductor and the ground. In particular, the boost converter can operate in a single-phase mode during which only the first switch is on, and in a dual-phase mode during which both the first switch and the second switch are on. When transitioning down from the dual-phase mode to the single-phase mode, the controller can ramp up the output voltage to compensate for a voltage dip during the transition down. When transitioning up from the single-phase mode to the dual-phase mode, the controller can ramp up an amount of current flowing through the second switch to reduce a voltage overshoot during the transition up.

[0010] According to another suitable arrangement, a controller in the boost converter is configured to balance an average amount of current flowing through the first switch and the second switch during the two-phase mode to reduce power loss in the converter. The controller can include a peak current adjustment circuit to adjust an amount of current flowing through at least one of the first switch and the second switch. The peak current adjustment circuit can include a first current detection circuit configured to receive a first sense signal from a first current sense resistor and output a first detected current amount, a second current detection circuit configured to receive a second sense signal from a second current sense resistor and output a second detected current amount, and a peak current adjustment circuit configured to receive the first detected current amount and the second detected current amount and output a first adjustment signal to adjust an amount of current flowing through the first switch and a second adjustment signal to adjust an amount of current flowing through the second switch.

[0011] According to yet another suitable arrangement, the boost converter can be provided with a surge current controller interposed between the input port and the inductor. The surge current controller can include a transistor having a drain terminal connected to the inductor, a gate terminal, and a source terminal connected to the input port. The surge current controller can also include a detection resistor coupled between the gate terminal and the source terminal of the transistor, and a comparison circuit configured to receive a sense signal from the detection resistor to determine whether a short circuit fault is present in the converter circuit. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a diagram of an illustrative electronic device having a display in accordance with an embodiment.

[0013] Figure 2 is a diagram of an illustrative electronic device having a display in accordance with an embodiment.

[0014] Figure 3 is a cross-sectional side view of an illustrative display in accordance with an embodiment.

[0015] Figure 4A is a top layout diagram of an illustrative backlight unit controlled using two separate driver integrated circuit chips configured to drive interleaved light emitting diode (LED) strings in accordance with an embodiment.

[0016] Figure 4B is a diagram showing how two backlight driver integrated circuit chips shown in Figure 4A may be used to drive respective LED strings in accordance with an embodiment.

[0017] Figure 4CThis is a timing diagram illustrating how a backlight enable signal according to an embodiment can be used as a synchronization signal for phase-locked loop, wherein the channel associated with the second backlight driver is phase-delayed relative to the channel associated with the first backlight driver.

[0018] Figure 4D This is an illustration of another exemplary light strip arrangement according to an embodiment, wherein the first half of the light strip is controlled by a first backlight driver, and the second half of the light strip is controlled by a second backlight driver.

[0019] Figure 4E This is a timing diagram illustrating how a backlight enable signal according to an embodiment can be used as a synchronization signal for phase-locked loop, wherein the channels associated with the first backlight driver and the second backlight driver both begin at the rising edge of the backlight enable signal.

[0020] Figure 5A This is a diagram of an exemplary backlight driver circuit including a fault detection circuit, according to the implementation scheme.

[0021] Figure 5B This is a diagram illustrating how an exemplary LED current driver, according to an embodiment, can include a maximum brightness control circuit.

[0022] Figure 5C It is a graph illustrating how the LED current is limited based on the number of detected faults according to the implementation plan.

[0023] Figure 6A This is a diagram of an exemplary backlight driver circuit that includes a headroom jump control circuit.

[0024] Figure 6B It is a graph illustrating how the forward voltage on the LED changes with the current according to the implementation scheme.

[0025] Figure 6C This is a diagram of an exemplary backlight driver circuit that includes a headroom feedforward control circuit according to the implementation scheme.

[0026] Figure 6D This is a timing diagram illustrating the operation of the headroom feedforward control circuit according to the implementation plan.

[0027] Figure 6E It is a timing diagram that compares the result waveforms between the jump command and the feedforward control according to the implementation plan.

[0028] Figure 7A This is a circuit diagram of an exemplary boost converter with a single-phase, single-switch configuration according to the implementation scheme.

[0029] Figure 7B This explains how to shut down the system when the peak current level is reached, according to the implementation plan. Figure 7Aa timing diagram of a single switch in a boost converter according to an embodiment.

[0030] Figure 7C is a circuit diagram of an exemplary boost converter having a single-phase multi-switch configuration according to an embodiment.

[0031] Figure 7D is a timing diagram illustrating how multiple switches in a boost converter can be continuously turned on when reaching a peak current level according to an embodiment. Figure 7C

[0032] Figure 7E is a circuit diagram of an exemplary boost converter having a multi-phase multi-switch configuration according to an embodiment.

[0033] Figure 7F is a timing diagram illustrating how multiple switches in a boost converter can be turned off when reaching a peak current level according to an embodiment. Figure 7E

[0034] Figure 8A is a circuit diagram of an exemplary dual-phase boost converter according to an embodiment.

[0035] Figure 8B shows a timing diagram illustrating possible voltage overshoot at the output of a dual-phase boost converter when switching from one phase to two phases.

[0036] Figure 8C shows a timing diagram illustrating possible voltage undershoot at the output of a dual-phase boost converter when dropping from two phases to one phase.

[0037] Figure 8D is a diagram illustrating how a dual-phase boost converter transitions between single-phase and dual-phase operation while minimizing voltage overshoot / undershoot according to an embodiment.

[0038] Figure 8E is a timing diagram illustrating how to reduce voltage overshoot at the output of a dual-phase boost converter when switching from one phase to two phases according to an embodiment.

[0039] Figure 8F shows a timing diagram illustrating how to eliminate voltage undershoot at the output of a dual-phase boost converter when dropping from two phases to one phase.

[0040] Figure 8G is a diagram illustrating how a multi-phase boost converter transitions between any number of phase modes while minimizing voltage overshoot / undershoot according to an embodiment.

[0041] Figure 9A is a plot illustrating substantial power loss mismatch when there is inductance bias between two phases of a boost converter.

[0042] ​​Figure 9B is a timing diagram illustrating relevant current waveforms when a boost converter is operated using a pulse width modulation (PWM) scheme, according to an embodiment.

[0043] Figure 9C is a diagram of an exemplary current detection circuit, according to an embodiment.

[0044] Figure 9D is a diagram of an exemplary peak current adjustment circuit, according to an embodiment.

[0045] Figure 9E is a diagram of an exemplary peak current adjustment sub-circuit, according to an embodiment.

[0046] Figure 9F is a graph showing how average inductor current is balanced between two phases of a boost converter, according to an embodiment.

[0047] Figure 10A is a diagram of an exemplary valley current detection circuit, according to an embodiment.

[0048] Figure 10B is a diagram of an exemplary peak current adjustment circuit, according to an embodiment.

[0049] Figure 10C is a diagram of an exemplary peak current adjustment circuit, according to an embodiment.

[0050] Figure 11A is a diagram illustrating how a surge current controller can be provided for a DC-to-DC converter, according to an embodiment.

[0051] Figure 11B is a diagram of an exemplary surge current controller, according to an embodiment. DETAILED DESCRIPTION

[0052] Figure 1 An exemplary electronic device of the type that can be provided with a display is shown in FIG. 1. The electronic device 10 can be a computing device such as a laptop computer, a computer monitor containing an embedded computer, a tablet computer, a cellular telephone, a media player, or other hand-held or portable electronic device, a smaller device such as a wrist-watch device, a pendant device, a headphone or earpiece device, a device embedded in eyeglasses, other appliance with a display, or other wearable or miniature device, a computer display that does not contain an embedded computer, a computer display that includes an embedded computer, a gaming device, a navigation device, an embedded system such as a system in which an electronic device is mounted to a kiosk or to an automobile, a device that implements the functionality of two or more of these devices, or other electronic device.

[0053] In Figure 1In the example of FIG. 1, device 10 includes a display, such as display 14 mounted in housing 12. Housing 12 (which can sometimes be referred to as a case or casing) can be formed of plastic, glass, ceramic, fiber composite, metal (e.g., stainless steel, aluminum, etc.), other suitable materials, or a combination of any two or more of these materials. Housing 12 can be formed using an integral configuration in which a portion or all of housing 12 is machined or molded as a single structure, or can be formed using multiple structures (e.g., an internal frame structure, one or more structures forming an exterior housing surface, etc.).

[0054] Display 14 can be a touch screen display that incorporates electrically conductive capacitive touch sensor electrode layers or other touch sensor components (e.g., resistive touch sensor components, acoustic touch sensor components, force-based touch sensor components, light-based touch sensor components, etc.), or can be a non-touch sensitive display. Capacitive touch screen electrodes can be formed from an array of indium tin oxide pads or other transparent conductive structures. The electrodes or other structures can be used to form a touch sensor on a display layer containing an array of pixels or on a separate touch panel layer that is attached (e.g., using an adhesive) to the array of pixels.

[0055] Display 14 can include an array of pixels 22. The array of pixels 22 in display 14 can form a rectangular region or other suitably shaped region for displaying images to a user. Pixels 22 can be formed from liquid crystal display (LCD) components, electrophoretic pixel arrays, electrowetting pixel arrays, or pixels based on other display technologies. Configurations in which display 14 is a liquid crystal display that is illuminated by light sources are sometimes described herein as examples. Liquid crystal display pixels for display 14 can have any suitable switching configuration (e.g., fringe field switching, vertical alignment, twisted nematic, in-plane switching, etc.). Fringe field switching displays can exhibit reduced touch sensitivity. Twisted nematic designs can facilitate an arrangement in which blue light is modulated because the retardance of the liquid crystal material tends to be greater at short wavelengths. This use of liquid crystal display technology to form display 14 is merely illustrative. In general, display 14 can be formed using any suitable type of pixels.

[0056] Display 14 can be protected using a display cover layer such as a transparent glass layer or a light-transmissive plastic layer. Openings can be formed in the display cover layer. For example, openings can be formed in the display cover layer to accommodate buttons, speaker ports, or other components. Openings can be formed in housing 12 to form communication ports (e.g., audio jack ports, digital data ports, etc.), to form openings for buttons, etc. In some arrangements, the display cover layer for display 14 does not contain openings, and / or housing 12 does not contain openings for buttons, etc.

[0057] Figure 2This is a schematic diagram of device 10. (For example...) Figure 2 As shown, electronic device 10 may have control circuitry 16. Control circuitry 16 may include storage and processing circuitry for supporting the operation of device 10. Storage and processing circuitry may include storage devices such as hard disk drive storage devices, non-volatile memory (e.g., flash memory configured to form a solid-state drive or other electrically programmable read-only memory), volatile memory (e.g., static or dynamic random access memory), and so on. The processing circuitry in control circuitry 16 can be used to control the operation of device 10. This processing circuitry may be based on one or more microprocessors, microcontrollers, digital signal processors, baseband processors, power management units, audio chips, application-specific integrated circuits, etc.

[0058] The input-output circuitry in device 10, such as input-output device 18, can be used to allow data to be supplied to device 10 and to allow data to be provided from device 10 to external devices. Input-output device 18 may include buttons, joysticks, scroll wheels, touchpads, keypads, keyboards, microphones, speakers, audio generators, vibrators, cameras, sensors (e.g., ambient light sensors, proximity sensors, orientation sensors, magnetic sensors, force sensors, touch sensors, pressure sensors, fingerprint sensors, etc.), LEDs and other status indicators, data ports, etc. Users can control the operation of device 10 by providing commands via input-output device 18 and can use the output resources of input-output device 18 to receive status information and other outputs from device 10. Input-output device 18 may include one or more displays, such as display 14.

[0059] Software, such as operating system code and applications, can be run on device 10 using control circuitry 16. During operation of device 10, the software running on control circuitry 16 can display images on display 14 using the pixel array in display 14. When displaying images, control circuitry 16 can control the transmission of each pixel in the array and can adjust the amount of illumination of the pixel array generated by the light source structure in display 14.

[0060] The display 14 may have a rectangular shape (i.e., the display 14 may have a rectangular area and a rectangular perimeter extending around the rectangular area) or may have other suitable shapes. The display 14 may be planar or may have a curved profile.

[0061] Figure 3 A cross-sectional side view of display 14 is shown in the figure. Figure 3 As shown, the display 14 may include a light source, such as a light source 42. The light source 42 (sometimes referred to as a backlight unit) is configured to output light 44, which is used as backlight illumination for the display 14.

[0062] like Figure 3 As shown, light 44 moves outward from the backlight unit 42 (in...) Figure 3 The light 44 travels vertically upwards in dimension Z and is received by pixels 22 in display layer 46. Light 44 passes through transparent structures and / or suitable color filter elements in pixels 22. In this way, light 44 helps illuminate the image on the pixel array formed by pixels 22 in display layer 46, so that observer 48 can observe these images in direction 50.

[0063] The display layer 46 may be mounted in a base structure such as a plastic base structure and / or a metal base structure to form a display module for mounting in the housing 12, or the display layer 46 may be directly mounted in the housing 12 (e.g., by stacking the display layer 46 into a recess in the housing 12). The display layer 46 may form a liquid crystal display, or may be used to form other types of displays.

[0064] In a liquid crystal display, display layer 46 may include a liquid crystal layer, such as liquid crystal layer 52. Liquid crystal layer 52 may be sandwiched between display layers such as display layers 58 and 56. Display 14 may also include a polarizer. The polarizer may be formed by an external polarizing layer (e.g., a polarizing layer on the surface of layers 56 and 58 facing away from liquid crystal layer 52) and / or by an intra-cell polarizer (a polarizer facing liquid crystal layer 52).

[0065] Layers 58 and 56 may be formed from transparent substrate layers such as light-transmitting glass or plastic layers. Layers 58 and 56 may be layers such as thin-film transistor layers and / or color filter layers. Conductive traces, color filter elements, transistors, and other circuitry and structures may be formed on the substrates of layers 58 and 56 (e.g., to form thin-film transistor layers and / or color filter layers). Touch sensor electrodes may also be incorporated into layers such as layers 58 and 56, and / or touch sensor electrodes may be formed on other substrates.

[0066] In one exemplary configuration, the lower layer 58 may be a thin-film transistor layer comprising an array of pixel circuits based on thin-film transistors and associated electrodes (pixel electrodes) for applying an electric field to the liquid crystal layer 52 and thereby displaying an image on the display 14. The upper layer 56 may be a layer comprising an array of colored pixel elements (e.g., color filter elements and / or colored quantum dot elements) for providing the display 14 with the ability to display color images. If desired, the lower layer of the display 14 may be a layer comprising an array of colored elements (e.g., color filter elements and / or colored quantum dot elements), and the upper layer of the display 14 may be a thin-film transistor layer. A configuration in which the array of colored elements (e.g., color filter elements and / or colored quantum dot elements) is combined with the thin-film transistor structure on a common substrate layer in the upper or lower portion of the display 14 may also be used.

[0067] During operation of the display 14 in the device 10, control circuitry (e.g., one or more integrated circuits on a printed circuit) can be used to generate information (e.g., display data) to be displayed on the display 14. Display driver circuitry (e.g., one or more display driver integrated circuits and / or thin-film transistor circuitry) can be used to deliver the information to be displayed to the pixels 22, while the light source 42 provides light 44 to the pixels 22.

[0068] It can be desirable to limit the angular spread of light from the pixels 22 to improve display efficiency. Configurations in which the light source 42 produces polarized light can also help improve display efficiency (e.g., by reducing polarizer losses).

[0069] Figure 4A is a top layout diagram of an illustrative backlight unit 42 controlled using two separate driver integrated circuit chips. The backlight unit 42 (which can sometimes be referred to as a backlight, a backlight layer, a backlight structure, a backlight module, a backlight system, etc.) can be used to generate backlight illumination 44 that passes through a display layer 46 Figure 3 The backlight unit 42 can have optical films, a light diffuser layer, and associated light-emitting diode (LED) elements 62. The light-emitting diode elements 62 can include a one- or two-dimensional array of light sources, such as light-emitting diodes that generate the backlight illumination 44. Light generated by the LED structure 62 can travel up the dimension Z through a light diffuser and optical films (collectively referred to as layer 60) before passing through the display pixels 22. The light diffuser 60 can include light-scattering structures that diffusely scatter light from the light-emitting diode elements 62 and thus help provide uniform backlight illumination 44. The optical films 60 can include films such as dichroic filters, phosphor layers, microlens array layers, and additional films (e.g., brightness enhancement films that help collimate the light 44, thereby enhancing the brightness of the display 14 for the user 20 and / or other optical compensation films).

[0070] It is common to use a single backlight driver integrated circuit chip to control the light-emitting diode elements 62 within the backlight unit 42. This conventional approach of integrating all of the LED current drivers onto a single chip can provide the advantages of current matching, current tilt control, low cost, and miniaturization. However, when supporting larger size displays (such as 20+ inch displays or 30+ inch displays, etc.), the integrated single-chip solution can encounter thermal management issues (i.e., a single backlight driver chip driving a large LED structure can consume too much power and generate too much heat).

[0071] According to the implementation scheme, more than one backlight driver integrated circuit can be used to drive the backlight LEDs. From a scalability perspective, using multiple parallel backlight drivers may be technically advantageous to provide extended LED driving capabilities for larger displays without developing new integrated circuit designs. In other words, using multiple backlight drivers can also help shorten development time and reduce development risks.

[0072] like Figure 4A As shown, the backlight LED element 62 can be driven by a first backlight driver integrated circuit (IC) chip 64-1 and a second backlight driver integrated circuit (IC) chip 64-2. Figure 4A In the example, LED element 62 comprises sixteen individual LED groups, each of which may be referred to herein as an LED string. Corresponding to Figure 4A Each individual LED 63 corresponding to index "1" belongs to the first LED string (i.e., "string 1"); each LED element 63 corresponding to index "2" belongs to the second LED string (i.e., "string 2"); each LED element 63 corresponding to index "3" belongs to the third LED string (i.e., "string 3"); and so on up to the last LED string (i.e., "string 16"). Each LED string may include ten individual LEDs, fewer than ten LEDs, 10 to 20 LEDs, more than 20 LEDs, or any suitable number of light-emitting diodes connected in series or in a chain. This example of backlight unit 42 including 16 LED strings is merely illustrative. If desired, backlight unit 42 may be configured with fewer than 16 LED strings or more than 16 LED strings.

[0073] Figure 4B This is a schematic diagram illustrating how two backlight driver integrated circuit chips 64-1 and 64-2 can be used to drive corresponding LED strings. Each driver in 64-1 and 64-2 can receive an input voltage Vin, which is fed to an electrical power conversion circuit such as a DC-DC converter 70. The DC-DC converter 70 can be configured to convert a direct current (DC) supply from one voltage level to another. The converter 70 can be a boost converter (e.g., the DC-DC converter 70 can generate a corresponding Vout greater than Vin) or a buck converter (e.g., the DC-DC converter 70 can generate a corresponding Vout less than Vin). The output voltage Vout generated by the converter 70 can be used to power different LED strings coupled to the backlight driver circuit.

[0074] like Figure 4BAs shown, first backlight driver IC 64-1 can be used to drive all odd numbered LED strings (i.e., string 1, string 3, string 5, string 7, etc.), while second backlight driver IC 64-2 can be used to drive all even numbered LED strings (i.e., string 2, string 4, string 6, string 8, etc.). In other words, each of the two backlight driver ICs is configured to drive eight separate LED strings in an “interleaved” fashion. The term “LED channel” is used synonymously with “LED string” herein. Note that the first channel (Chl) of backlight driver 64-1 is coupled to string 1, while Chl of backlight driver 64-2 is coupled to string 2. The second channel (Ch2) of backlight driver 64-1 corresponds to string 3, while Ch2 of backlight driver 64-2 corresponds to string 4. The last channel (e.g., Ch8) of backlight driver 64-1 is connected to string 15, while Ch8 of backlight driver 64-2 is connected to string 16.

[0075] One challenge in implementing multiple backlight driver ICs is managing the LED channel phase shift from IC to IC. A reference to a phase shift between different LED channels can refer to an amount of phase delay between the control signals that modulate the various LED strings. Each LED string can receive a respective pulse width modulated (PWM) signal from the backlight driver circuit. A PWM signal is a clock signal with an adjustable pulse width. In other words, the duty cycle of a PWM signal can be modulated to control the time period during which each LED string is turned on.

[0076] The PWM signals output from backlight driver 64-1 can be generated using a first phase-locked loop (PLL) circuit 72-1 within driver 64-1, while the PWM signals output from backlight driver 64-2 can be generated using a second PLL circuit 72-2 within driver 64-2. Both PLL circuits 72-1 and 72-2 generate PWM signals from a common synchronization input signal LSYNC, so the frequency of the PWM signals generated by the two PLLs is the same, and their phase relationship can be fixed after power-up. However, the two backlight drivers 64-1 and 64-2 can exhibit different start-up behavior, such as varying PLL lock times. If the PLL lock times are different, then the LED strings driven by the two different backlight driver ICs will exhibit a fixed but unknown phase relationship after start-up. This unknown channel phase shift between multiple backlight driver chips can introduce undesirable on-screen artifacts on display 14.

[0077] To address the unknown phase relationship between the various LED channels driven by different backlight driver ICs, a backlight enable signal BL_EN can be used as a synchronization signal for phase locking purposes. As shown, backlight enable signal BL_EN can be provided to both backlight drivers 64-1 and 64-2. Figure 4B Figure 4C ​is a timing diagram showing how the backlight enable signal BL EN can be used as a synchronization signal for phase-locking.

[0078] As Figure 4C shown, when the signal BL EN is asserted (e.g., when BL EN goes from low to high), the PWM signal for channel 1 of the first backlight driver 64-1 will immediately start (e.g., the pulse-width modulated current will start flowing through string 1). Then, the second backlight driver 64-2 will use the PLL 72-2 to time the desired delay (see Tdelay in Figure 4C ), so that channel 1 of the second backlight driver 64-2 will start with the correct phase delay / offset. In this example, the backlight unit 42 includes a total of sixteen LED strings, and the channels associated with the first backlight driver 64-1 can exhibit the following phase relationships:

[0079] Channel 1 (string 1): 0 degrees

[0080] Channel 2 (string 3): 45 degrees

[0081] Channel 3 (string 5): 90 degrees

[0082] …

[0083] Channel 8 (string 15): 315 degrees

[0084] Similarly, the channels associated with the second backlight driver 64-2 can exhibit the following phase relationships:

[0085] Channel 1 (string 2): 22.5 degrees

[0086] Channel 2 (string 4): 67.5 degrees

[0087] Channel 3 (string 6): 112.5 degrees

[0088] …

[0089] Channel 8 (string 18): 337.5 degrees

[0090] Here, the 22.5° phase delay between channel 1 of the two backlight driver ICs is determined by dividing 360 by the number of total LED strings (e.g., 360 / 16 = 22.5), which can be created using a 160 kHz LSYNC clock, a 40 MHz PLL clock, a 20 kHz LED PWM frequency, and a 25 μβ Tdelay (as examples).

[0091] Driving a backlight LED using two backlight driver IC chips Figure 4A to Figure 4CThe examples provided are merely illustrative and are not intended to limit the scope of this embodiment. If desired, two or more parallel display backlight driver chips (e.g., three or more driver circuits, four or more driver circuits, 4 to 10 driver circuits, 10 or more driver circuits, etc.) can be used to drive any number of LED strings / channels in the backlight unit, wherein the phase delay between the various driver chips can be appropriately adjusted to achieve the desired timing relationship.

[0092] Figure 4A The configuration is merely exemplary, wherein the backlight LED elements are controlled in an interleaved manner by driver circuits 64-1 and 64-2 (e.g., wherein adjacent LED elements are driven in an interleaved manner by different backlight driver chips). Figure 4D Another example of an exemplary light strip arrangement is shown, in which the first half of the LED string is driven by a first backlight driver chip, while the second half of the LED string is driven by a second backlight driver chip. Here, both backlight driver ICs can also be controlled by a common enable signal BL_EN. Figure 4E This is a timing diagram showing how the backlight enable signal BL_EN can be used as a synchronization signal for the phase lock in this non-interleaved arrangement.

[0093] like Figure 4E As shown, when the signal BL_EN is asserted, the PWM signals of channel 1 of both driver ICs will start simultaneously. In other words, the rising edge of the enable signal BL_EN will trigger the PWM signals of both drivers, and no phase offset is required between the two driver ICs. Assuming that the backlight unit 42 includes a total of sixteen LED strings, the channels associated with the two driver IC chips can exhibit the following phase relationship:

[0094] Channel 1: 0 degrees

[0095] Channel 2: 45 degrees

[0096] Channel 3: 90 degrees

[0097] …

[0098] Channel 8: 315 degrees

[0099] Two backlight driver IC chips are used to drive the backlight LEDs. Figure 4D to Figure 4E The examples provided are merely illustrative and are not intended to limit the scope of this implementation. If desired, two or more parallel display backlight driver chips (e.g., three or more driver circuits, four or more driver circuits, 4 to 10 driver circuits, 10 or more driver circuits, etc.) can be used to drive any number of LED strings / channels in the backlight unit, wherein all driver circuits start simultaneously on the rising edge of the enable signal BL_EN.

[0100] The above-described method of setting the channel-to-channel phase relationship between multiple backlight driver IC chips using a backlight enable signal and an optional predetermined delay time can impose several technical requirements. For example, in conjunction with Figure 4A to Figure 4E The described method can require all LED strings to be fault-free. Thus, if there are any defective LED strings, the proposed synchronization scheme can not operate properly. As another example, proper synchronization of the two backlight driver ICs can also require receiving an externally supplied LSYNC signal (see Figure 4B ). If the signal LSYNC is lost, the PWM clock signals generated by the various PLL circuits (e.g., PLLs 72-1 and 72-2) can not lock to the same reference clock signal.

[0101] As noted above, one or more backlight driver ICs can be used to drive various LED strings in a backlight unit. Ideally, all LED strings are perfectly functional (i.e., have no defective backlight LED elements). However, in practice, even a single faulty LED in a given string will render the entire LED string defective. The amount of current required to be generated by the backlight driver can vary depending on the number of faulty LED strings. Thus, it can be desirable to provide a mechanism for detecting the number of faulty LED strings within a backlight unit.

[0102] Figure 5A is a diagram of an exemplary backlight driver circuit including a fault detection circuit in accordance with an embodiment. As Figure 5A shown, the backlight unit 42 can include a DC / DC converter 70 that receives an input voltage and generates corresponding output voltages Vout for a plurality of LED strings (e.g., a first LED string 65-1 associated with a first channel Chl, a second LED string 65-2 associated with a second channel Ch2, etc.), an LED current driver circuit 80 configured to provide a current (e.g., a pulse-width modulated current signal) to each LED channel connected to the driver 80, and a brightness register 90 for storing a brightness code and outputting to the LED current driver 80. The brightness code (sometimes referred to as a brightness command, an externally provided brightness setting, or a user-provided brightness setting) can control the duty cycle of the PWM current signal for the various LED channels, and thus can be used to adjust the overall brightness of the backlight unit 42.

[0103] The voltage at the node where each LED string is connected to the current driver 80 can be called the headroom voltage. In the example of Figure 5, the first LED string 65-1 generates a first headroom voltage Vhr1, while the second LED string 65-2 generates a second headroom voltage Vhr2. Each LED channel will have its own headroom voltage VhrX. Generally, the headroom voltages of all associated LED strings are sensed and adjusted to help maintain sufficient headroom margin so that the LED current driver 80 can deliver the desired target current. Generally, the headroom voltage should not be too high to avoid excessive headroom power loss.

[0104] In some configurations, headroom voltage can also be used for fault detection purposes. For example... Figure 5A As shown, the LED current driver 80 may also be equipped with an associated LED fault detector, such as a fault detection circuit 86. Consider a scenario with a nominal Vhr range of approximately 500mV. If a single LED in the first string 65-1 fails (i.e., if one LED in the first channel is short-circuited), the headroom voltage Vhr1 may increase the forward voltage Vf of that single LED, which could be 3V to 4V (for example). If two LEDs in the first string 65-1 fail (i.e., if any two LEDs in the first channel are short-circuited), the headroom voltage Vhr1 may increase by 2*Vf, i.e., 6V to 8V (for example).

[0105] The headroom voltage Vhr1 can be compared to one or more thresholds to determine whether there is a single LED short circuit or multiple LED short circuits in the string. Figure 5A In the example, a first comparator 82 can be used to compare the headroom voltage Vhr1 with a first threshold voltage Th1, and a second comparator 84 can be used to compare it with a second threshold voltage Th2. If the outputs of both comparators 82 and 84 are low, there is no fault in the LED string 65-1. If only the output of comparator 82 is high, a single LED fault is detected in the string. If the outputs of both comparators 82 and 84 are high, then at least two LED faults are detected in the channel. To calculate the headroom power loss for each LED string, the headroom voltage is multiplied by the string current (I0). LED Therefore, in the example above where a single LED in the string is short-circuited, the net loss will increase from (500mV)*I. LED Increase to (500mV+Vf)*I LED Assume the series current I LED With an input current of 100mA and an LED forward voltage of 4V, the net power loss increases dramatically from 50mW to 450mW. The net power loss will be even greater as the number of faulty LEDs in a given string increases (i.e., when two or more LEDs in a given channel are short-circuited).

[0106] If mishandled, the headroom power loss caused by LED short / faults can cause the LED driver to thermally runaway. One approach to handling LED short faults is to simply turn off the LED string if an LED short is detected. However, turning off a faulty LED string can result in noticeable brightness non-uniformity for the end user. Another approach to handling LED short faults is to over-design the backlight unit's thermal solution to accommodate the fault condition. However, over-designing the thermal solution can be overly conservative since the likelihood of an LED short is typically quite low.

[0107] According to embodiments, a global brightness throttling approach is provided to handle LED short faults without having to turn off faulty LED strings and without having to over-design the thermal solution. This approach can only allow a single LED short in any given string. In particular, the fault detection circuit 86 can be configured to output a fault signal on the feedback path 88. The fault signal can include information about the number of LED strings with a single LED short fault. Figure 5B is a diagram showing how the LED current driver 80 can include a maximum brightness limit control circuit 92. The maximum brightness limit control circuit 92 can receive the brightness command from the brightness register 90, can receive the fault information from the fault detection circuit 86 via path 88, and can output a corresponding adjusted maximum brightness setting to the current output driver 94, which controls the current sink switches 96 for the LED string.

[0108] The maximum brightness limit control circuit 92 can limit the maximum display brightness setting as follows:

[0109] Bmax_adj = Bmax_def * (1 - N*K_throttle) (1)

[0110] where Bmax_adj is the dynamically adjusted maximum brightness that can be output from the control circuit 92, where Bmax_def is the default maximum brightness level (e.g., 100%), where N is the total number of faulty LED strings determined by the fault detection circuit 86, and where K_throttle is the throttling factor. The throttling factor K_throttle can be a programmable parameter ranging from 5% to 20% or more.

[0111] Figure 5C is an illustration of how to limit the string current I LEDThe plot of FIG. 1 illustrates the maximum luminance level as a function of the number of shorted LED strings. Trace 100 represents a fault-free scenario (N = 0) in which the luminance code enables the maximum drive current level Imax. Trace 102 represents another scenario in which one LED string exhibits a shorted fault (N = 1) so that the maximum luminance is limited to only 90% of the default maximum. Trace 104 represents yet another scenario in which two LED strings exhibit shorted faults (N = 2) so that the maximum luminance will be limited to only 80% of the default maximum. Trace 106 represents yet another scenario in which three LED strings exhibit shorted faults (N = 3) so that the maximum luminance will be limited to only 70% of the default maximum.

[0112] Figure 5C The example of FIG. 1 illustrates a 10% K_throttle (since the maximum luminance level is adjusted in 10% increments for N increments), but this is merely illustrative. If desired, the throttle factor K_throttle can be set to 5%, 7.5%, 10%, 12.5%, 15%, or any suitable level between 1 and 20% to globally adjust the maximum luminance in the event of a detected fault condition. Configured and operated in this manner, the luminance uniformity across the display is maintained and there is no need for over-designing the heat dissipation solution. If the user sets the luminance to the maximum (i.e., when the user sets the luminance code / command to the maximum), then adjusting the maximum global luminance in the presence of a fault will dim the display (when N is not equal to zero). However, if the user does not set the luminance to the maximum, then there is little noticeable change in luminance.

[0113] As noted above, the headroom voltage Vhr needs to be adjusted to maintain sufficient headroom margin so that the LED current driver can deliver the accurate target current to each connected LED string, but Vhr should not be adjusted too high to avoid excessive headroom power loss. Figure 6A FIG. 5 is a diagram of an illustrative backlight driver circuit including an adaptive headroom control circuit 116 coupled with the DC-to-DC converter 70 in a closed loop configuration to dynamically adjust the headroom voltage Vhr. In the example of FIG. 5, the LED string 65 can be coupled in series with pull-down transistors 110 and 112 and a current sense resistor Rcs. Transistor 112 has a gate controlled by an operational amplifier 114 having a first input that receives a reference voltage from the current driver 80 and a second input that receives a sense voltage from the resistor Rcs. Arranged in this manner, the transistors 110 and 112 are driven to provide a target current I LED .

[0114] Generally, the adaptive headroom control loop controls the converter 70 to adjust the output voltage Vout based on the PWM frequency of the LED current driver 80. However, adjusting Vout over one or more cycles of the PWM signal can be too slow. In such scenarios, the headroom voltage Vhr may be too low when the LED current driver 80 starts driving the LED string. To increase response time and ensure sufficient Vhr is available before driving the LED string, the backlight driver circuit sometimes includes a headroom jump control circuit 118. The headroom jump control circuit 118 operates as follows: When the brightness code output from register 90 increases and the step size exceeds a predefined threshold, circuit 118 issues a jump command. The jump command instructs the DC / DC converter 70 to boost Vout to ensure sufficient headroom voltage Vhr.

[0115] However, issuing jump commands in this way is an discontinuous solution because a jump command is only issued if the step size is greater than a predetermined threshold. When adjusting the brightness code / command by an amount smaller than the predetermined threshold, headroom voltage adjustment will be managed by a slower adaptive control loop (i.e., via adaptive headroom control logic 116). In such scenarios, since no jump command is issued, Vhr may still be too low when the LED current driver 80 starts supplying current through series 65.

[0116] Figure 6B This explains how the forward voltage on an LED changes the current (I). LED The curve is shown in trace 120. The forward voltage Vf on a single LED can vary non-linearly. Figure 6B In the example, I is between 15mA and 60mA. LED Within the current range, the forward voltage Vf can increase from 5.7V to 6.3V by 0.6V. If there are 10 LED elements in each string, a brightness adjustment corresponding to a current step of 15mA to 60mA may cause the net voltage Vhr to decrease by 6V (e.g., 10 * 0.6) if no jump command is issued and if the adaptive control loop is too slow.

[0117] According to the implementation scheme, the backlight driver circuit may be provided with feedforward control logic, such as clearance feedforward control circuit 122 (see example). Figure 6C This is configured to adjust Vout based on changes seen directly at the luminance code. For example... Figure 6C As shown, the headroom feedforward control circuit 122 can directly receive the stored brightness code / command from the brightness register 90, and can generate the corresponding output voltage adjustment signal Vout_adj to the DC / DC converter 70 through the control path 124. For example, the feedforward control circuit 122 can calculate Vout_adj as follows:

[0118] Vout adj = G * (B next - B current) (2)

[0119] where B current represents the initial brightness code, where B next represents the new brightness code, and where G represents the output voltage gain as a function of the target LED current change. In other words, G can represent a linear or non-linear approximation of the slope of the trace 120, as shown in Figure 6B Formula (2) can be a linear or non-linear formula where both the current brightness setting (B current) and the target brightness setting (B next) are inputs. The value Vout adj calculated by formula (2) refers to the predicted amount by which the converter 70 should increase or decrease Vout. If desired, different gain values G can be applied from boost versus buck situations (e.g., a first gain value can be used for brightness increase, while a second gain value different from the first gain value can be used for brightness decrease). In other suitable embodiments, Vout adj can be encoded in the form of a lookup table rather than using a formula.

[0120] Figure 6D is a timing diagram illustrating the operation of the headroom feedforward control circuit 122. As shown in Figure 6D , the brightness code can be raised at time tl. In particular, a delay period (Tdelay) should be applied between the change in brightness code at time tl and the time t3 at which the LED drive current begins to increase. This delay will allow the headroom feedforward control circuit 122 to begin adjusting Vout to the desired level from time tl to t2 during phase 130. During the feedforward adjustment phase 130, the adaptive feedback closed control loop can optionally be disabled (e.g., the adaptive headroom control logic 116 can be turned off during phase 130) as the circuit 122 directs the DC-to-DC converter 70 to ramp up Vout. When the LED current begins to increase at time t3, the adaptive control loop can be enabled to further tune Vout to the target current level, as shown by the micro-adjustment 132.

[0121] Figure 6E is a timing diagram comparing the resulting waveforms between the jump command and the feedforward control scheme. Typically, the jump command provides only some threshold values, such as threshold values Jump Thl and Jump Th2. When the change in brightness setting or when the desired current change is greater than a specified threshold, the DC / DC converter 70 will adjust Vout to ensure that the LED current driver has sufficient headroom voltage. In Figure 6E the example, consider the jump control architecture of Figure 6A , where the first jump threshold is set to 8 mA and the second jump threshold is set to 16 mA.

[0122] When the current step size is 0mA to 7mA, no jump command is issued; Vout is simply adjusted upwards from the initial voltage level v1 via the adaptive loop (see solid line 134-1). When the current step size is 8mA, the first jump threshold is triggered, causing Vout to jump to (v1 + 1.5V), and then subsequently downwards back to (v1 + 0.8V), as shown in solid line 134-2. Therefore, the jump command introduces an additional 0.7V change before stabilizing at the correct voltage level. When the current step size is 9mA, the first jump threshold is triggered, causing Vout to jump to (v1 + 1.5V), and then subsequently downwards back to (v1 + 0.9V), as shown in solid line 134-3. Therefore, the jump command introduces an additional 0.6V change before stabilizing at the correct voltage level. When the current step size is 15mA, the first jump threshold is triggered, causing Vout to jump to (v1 + 1.5V) and requiring no further adjustment, as shown in solid line 134-4. Therefore, there is no excessive change. The additional voltage change introduced by the jump command may introduce acoustic noise, which is exacerbated when a ceramic capacitor is present at the output of the DC / DC converter 70.

[0123] In contrast to the aforementioned jump command mechanism, combined with Figure 6C and Figure 6D The described type of feedforward control scheme adjusts the converter output voltage Vout directly toward the target final value, such as... Figure 6E The dashed waveform is shown in the diagram. Any small deviations from the expected final value can be fine-tuned via an adaptive control loop (e.g., using adaptive headroom control circuit 116). Because the headroom feedforward control circuit 122 adjusts Vout directly toward the final target value, the additional voltage variation is much smaller than the additional voltage variation introduced by the jump command, which significantly reduces the risk of acoustic problems at the DC-to-DC converter 70. Therefore, this feedforward control mechanism can ensure that the LED current driver has sufficient headroom while minimizing DC / DC voltage variations and thus suppressing acoustic noise.

[0124] As described above, the DC-to-DC converter 70 can be either a boost converter or a buck converter. The following description uses a configuration where the DC / DC converter 70 is a boost converter as an example. For instance, consider a scenario where the boost converter receives a 12V input voltage and uses a switching transistor to generate a 60V output voltage with an output current of 1A. Assuming the switching transistor is modulated at a frequency of 250kHz, the power loss of this transistor could be as high as 2.8W. At this increased level of power loss, the switching transistor is at high risk of thermal overload, which could significantly shorten the converter's lifespan. Furthermore, DC / DC converters are typically part of systems with limited permissible heights, thus prohibiting the use of heat sinks for cooling.

[0125] To help improve product reliability, the converter 70 may be equipped with a peak current mode boost converter controller, which has multiple gate drivers for driving one or more switching transistors and multiple current sensing inputs for monitoring the current associated with one or more phases of the boost converter 70. Figure 7A This illustrates how to configure the boost converter 70 in a single-phase, single-switch arrangement. A single-phase, single-switch configuration may be particularly suitable for low-load applications.

[0126] like Figure 7A As shown, converter 70 has: an input port configured to receive an input voltage Vin; an input capacitor C1 coupled to the input port between node n1 and the ground power supply line; an inductor L1 coupled between nodes n1 and n2; a switching transistor 140-1 and a current sensing resistor Rcs1 connected in series between node n2 and ground; a diode 142 connected between nodes n2 and n3; an output capacitor C2 coupled between node n3 and ground; and output resistors R1 and R2 connected in series between node n3 and ground. Node n3 serves as the output port of boost converter 70, where the corresponding boosted output voltage Vout is provided to any load connected to output node n3.

[0127] According to the implementation, the switching transistor 140-1 (e.g., a metal-oxide-semiconductor field-effect transistor, a bipolar junction transistor, a microelectromechanical system switch, or other type of switching device) can be controlled by a control circuit such as a peak current mode boost converter controller 144. The controller 144 may have an input configured to receive a voltage signal from a voltage divider of R1 and R2 via a feedback path 146. The controller 144 may also include a first current sensing (CS1) input configured to receive a voltage signal from a current sensing resistor Rcs1 via a sensing path 148. By monitoring the voltage on the sensing path 148, the controller 144 can detect when a peak current level is reached. The peak current level can be any amount of current that, as determined by the designer, is placed on the switch 140-1 to create excessive stress.

[0128] In response to detecting a peak current level at input CS1, the peak current mode boost converter controller 144 can immediately disable transistor 140-1 (e.g., by de-asserting or driving the first gate driver output GDRV1 low) for the remainder of the switching cycle. For example, the controller 144 can include a comparator that compares the sense voltage received through path 148 to a predetermined threshold. If the sense voltage exceeds the predetermined threshold, the controller 144 can temporarily assert the gate driver output signal GDRV1. The gate driver output signal GDRV1 can be re-asserted at the beginning of the next switching cycle to re-activate the switching transistor 140-1. Figure 7B is a timing diagram illustrating how the boost converter is periodically turned off when a peak current level is reached. Figure 7A Figure 7B As shown, the first gate driver output signal GDRV1 is pulsed low whenever the controller 144 detects that the peak current level has been exceeded.

[0129] To further reduce the power loss on the switching transistor 140-1, an additional switching transistor can be coupled in parallel with transistor 140-1 to help distribute the thermal stress among a set of switching transistors. Figure 7C Another suitable arrangement of the boost converter 70 configured in a single-phase multi-switch arrangement is shown. The single-phase multi-switch configuration can be particularly suitable for medium load applications.

[0130] Figure 7C The general structure of the boost converter 70 is similar to the boost converter of Figure 7A . Accordingly, components drawn in the same locations and connected in the same manner need not be described again in detail to avoid obscuring the present embodiments. However, in contrast to the Figure 7A , the boost converter architecture of Figure 7C includes a plurality of switches 140 (e.g., switching transistors 140-1, 140-2,..., 140-n) coupled in parallel between node n2 and the current sense resistor Rcs1. Here, the source terminal of each transistor 140 is connected to the same common resistor Rcs1. A peak current mode boost converter controller 144 can be used to control these multiple parallel switches 140.

[0131] As described above, the controller 144 receives a current sense voltage signal from the resistor Rcs1 via the sense path 148. By monitoring the voltage on the sense path 148, the controller 144 is able to detect when a peak current level is reached. Similar to the single-switch embodiment of Figure 7A , the controller 144 can include a comparator that compares the sense voltage received through path 148 to a predetermined threshold. If the sense voltage exceeds the predetermined threshold, the controller 144 can temporarily assert the gate driver output signal GDRV1. The gate driver output signal GDRV1 can be re-asserted at the beginning of the next switching cycle to re-activate the switching transistor 140-1. Figure 7C ​The controller 144 may also include a single comparator that compares the sensed voltage received via path 148 with a predetermined threshold (e.g., all switches share the same current sensing resistor and the same peak current comparator). If the sensed voltage exceeds the predetermined threshold, the controller 144 may turn off the currently active switch 140.

[0132] In contrast to a single-switch scenario where switching transistor 140-1 is turned on at the beginning of each switching cycle, the gate-on cycles should be evenly distributed among the various switching transistors. Figure 7D This explains how to ensure continuous connection. Figure 7C Timing diagram of multiple parallel switches 140 in a boost converter. (See figure) Figure 7D As shown, the gate driver output signal GDRV1 can pulse to a high level at time t1 (i.e., at the start of the switching cycle) to turn on transistor 140-1; after GDRV1 drops to turn on transistor 140-2, the gate driver output signal GDRV2 can pulse to a high level at time t2; ...; and the gate driver output signal GDRVn can pulse to a high level at time tn to turn on transistor 140-n, where GDRVn will be driven back to a low level before the start of the next switching cycle at time tm, at which point the entire process repeats itself. Operating in this way balances and reduces the power loss of each switching transistor 140 in this group of parallel switches. Generally, the power loss of each switching transistor 140 can be reduced by approximately n times compared to a single-switch implementation.

[0133] Figure 7E This illustrates yet another suitable arrangement of the boost converter 70 in a multiphase, multi-switch configuration. The multiphase, multi-switch configuration may be particularly suitable for high-load applications. Figure 7E The general structure of the boost converter 70 is similar to Figure 7A The boost converter. Therefore, it is unnecessary to describe in detail the components drawn in the same location and connected in the same way again to avoid obscuring this embodiment.

[0134] However, with Figure 7A on the contrary, Figure 7E The boost converter topology includes multiple inductors L1, L2, ..., Ln coupled to corresponding switches 140, each connected to a different corresponding current-sensing resistor (i.e., the current-sensing resistor is not shared between the individual switching transistors). For example... Figure 7EAs shown, inductor LI is coupled to output node n3 via diode 142-1; inductor L2 is coupled to output node n3 via diode 142-2;...; and inductor Ln is coupled to output node n3 via diode 142-n. First switch transistor 140-1 and first current sense resistor Rcsi are coupled in series between node n2-1 (i.e., the node connecting LI to diode 142-1) and ground. Second switch transistor 140-2 and second current sense resistor Rcs2 are coupled in series between node n2-2 (i.e., the node connecting L2 to diode 142-2) and ground. Nth switch transistor 140-n and nth current sense resistor Rcsn are coupled in series between node n2-n (i.e., the node connecting Ln to diode 142-n) and ground. These multiphase switches 140 can be controlled using a peak current mode boost converter controller 144.

[0135] Configured in this way, each phase has its own dedicated switch transistor and its own dedicated current sense resistor. Unlike the previous embodiments, Figure 7E Controller 144 can include a dedicated comparator for each phase to individually turn off the corresponding switch transistor when the peak current is reached. For example, controller 144 can have: a first comparator that compares a first current sense voltage from Rcsi to a preselected threshold to determine whether to assert GDRVI; a second comparator that compares a second current sense voltage from Rcs2 to a preselected threshold to determine whether to assert GDRV2...; and an nth comparator that compares a last current sense voltage from Rcsn to a preselected threshold to determine whether to assert GDRVn. Operating in this way, controller 144 is able to detect when the peak current level has been reached for any of the switch transistors 140. If any of the sensed voltages exceeds the predetermined threshold, controller 144 can turn off the corresponding switch 140.

[0136] Figure 7F is a timing diagram illustrating how the switches 140 associated with different phases can be individually disabled when the peak current level is reached. As Figure 7FAs shown, the gate driver output signals GDRV1, GDRV2,... and GDRVn can be phase shifted 360 / n degrees from one another to help minimize voltage ripple. In an example where there are 12 phases (e.g., each of the 12 switching transistors is connected to a different respective current sense resistor), the gate driver output signals can be offset 30 degrees from one another. In another example where there are six phases, the gate driver output signals can be delayed 60 degrees from one another. In yet another example where there are only two phases, the gate driver output signals can be delayed 180 degrees from one another. Operating in this manner, power loss of each switching transistor 140 is reduced while reducing output voltage ripple at node n3 relative to a single phase implementation.

[0137] Figure 7A to Figure 7F An example of the boost converter 70 illustrates how it can be reconfigured to support a wide load range without over stressing the switching transistors.

[0138] According to another suitable implementation, the multi-phase boost converter can be configured in multiple modes depending on the size of the load. Figure 8A is a circuit diagram of an exemplary dual-phase boost converter 70 that can operate in a first (single-phase) mode to support light loads and in a second (dual-phase mode) to support larger loads. As shown, the boost converter 70 can include a first switching transistor 140-1 and a first current sense resistor Rcsi coupled in series between an inductor LI and ground, and a second switching transistor 140-2 and a second current sense resistor Rcs2 coupled in series between an inductor L2 and ground. During the single-phase mode, the controller 144 can activate only the first switch 140-1 (sometimes referred to as being associated with a “master” phase). During the dual-phase mode, the controller 144 can activate both the first switch 140-1 and the second switch 140-2 (sometimes referred to as being associated with a “slave” phase). Figure 8A

[0139] Transient issues can arise when transitioning between the two modes. Figure 8B shows a timing diagram illustrating a voltage overshoot at the output of the dual-phase boost converter 70 when switching from one phase to two phases. At time tl, the slave phase turns on, and the slave phase current Iph2 (i.e., the current flowing through transistor 140-2) rises to match the master phase current Iphl (e.g., both Iphl and Iph2 should settle at the current level II). During this transient period, the converter output voltage Vout can exhibit an overshoot of 800 mV.

[0140] Figure 8C ​A timing diagram illustrating a voltage undershoot at the output of a two-phase boost converter 700 when switching from two-phase to single-phase is shown (this process is sometimes referred to as "phase elimination"). At time ti, the from phase is turned off, which forces the from phase current Iph2 to decrease and the main phase current Iphl to rise back to the current level I2. During this transient period, the converter output voltage Vout can exhibit a 750 mV undershoot.

[0141] Figure 8B The excessive Vout overshoot shown in FIG. 1 1 1 can introduce additional power loss because the headroom voltage of the driven LED string increases. Figure 8C The excessive Vout undershoot shown in FIG. 1 1 1 can cause critical operation issues because the headroom voltage can drop below the driver saturation voltage.

[0142] To help reduce the overvoltage overshoot and undershoot at the output of the boost converter, an improved transition mechanism is provided. Figure 8D is a diagram illustrating how a two-phase boost converter 70 transitions between single-phase operation mode 160 and two-phase operation mode 164 while minimizing voltage overshoot / undershoot. Optionally, the boost converter 70 can operate in single-phase operation by default. When operating in single-phase mode 160, a boost soft start can be initiated such that the boost converter output ramps up (i.e., is not raised abruptly). When the boost soft start is complete and when the brightness setting (e.g., an externally provided brightness code or command) exceeds a first predetermined threshold, the boost converter can transition from single-phase mode 160 to two-phase mode 164 via an up transition state 162. In the up transition state 162, instead of driving the from phase current directly to the intended current level, the from phase current can be slowly ramped up to match the main phase current. After the from phase current ramp (sometimes referred to as a from phase "soft start") is complete, the boost converter will operate in two-phase mode 164.

[0143] When the brightness setting is below a second predetermined threshold (which can be equal to or different from the first predetermined threshold) and assuming phase elimination is enabled, the boost converter can transition from two-phase mode 164 to single-phase mode 160 via a down transition state 166. In the down transition state 166, the converter reference voltage is temporarily increased (e.g., Vout is adjusted to a raised level) and the from phase can be slowly ramped down to zero. After a boost timer expires, the boost converter will operate in single-phase mode 160. If the brightness is below the first predetermined threshold, the operation can optionally transition from the up transition state 162 to the down transition state 166, and if the brightness exceeds the second predetermined threshold, the operation can optionally transition from the down transition state 166 to the up transition state 162.

[0144] Figure 8EA timing diagram illustrating relevant waveforms during the up-transition state 162 when switching from one phase to two phases is shown. At time tl, the slave phase current Iph2 ramps up slowly to match the master phase current Iphl. By ramping up the slave phase current over a longer period of time, the converter output voltage overshoot can be reduced by half.

[0145] Figure 8F A timing diagram illustrating relevant waveforms during the down-transition phase kill state 166 is shown. At time to, the converter output voltage Vout can increase by 700 mV (for example) to compensate for the subsequent voltage dip when the switch actually occurs at time tl. When the slave phase is turned off at time tl, the resulting transient voltage dip will cause Vout to drop, but Vout will still remain at or below the minimum required nominal output level Vout nom. Operating in this manner, sufficient headroom voltage can be guaranteed to avoid converter operation problems.

[0146] Figure 8D The example of a dual phase boost converter in which the improved transition mechanism is applied is merely illustrative and is not intended to limit the scope of the present embodiments. If desired, the transition mechanism can be extended to N phase converters, where N is any integer greater than two. Figure 8G is a state diagram for an N phase boost converter in which each slave phase can be turned on and off individually while minimizing voltage overshoot / undershoot.

[0147] Another problem that can arise in a multi-phase boost converter is the issue of inductor mismatch. Consider, for example, a scenario in which a dual phase boost converter has mismatched inductances between the two phases. Figure 9A is a plot illustrating substantial power loss mismatch in a dual phase boost converter operating at a 2 MHz switching frequency when one phase has an inductance of 39.6 uH (i.e., 120% * 33 uH) and the other phase has an inductance of 26.4 uH (i.e., 80% * 33 uH). As shown in Figure 9A the peak-to-peak inductor current mismatch between the two phases results in a large power loss mismatch in the key electronic components within the converter.

[0148] Figure 9B is a timing diagram illustrating relevant current waveforms when operating a boost converter using a pulse width modulation (PWM) scheme. As shown in Figure 9BAs shown, the amount of current flowing through the inductor I_inductor can vary between a valley current level Ivalley and a peak current level Ipk. At time tO (at the rising edge of the PWM signal), the switch transistor can turn on, and the current through the switch transistor I_FET can increase from Ivalley toward Ipk for a time period Tl. At time t2 (at the falling edge of the PWM signal), the switch transistor can turn off, so I_FET drops to zero. As a result, the inductor current I_inductor can start to decrease during a time period T2. At time t3 (at the next rising edge of the PWM signal), the whole process can repeat. The time duration T3 between times tO and t3 can represent the whole period of the PWM signal. The time period Tl can be referred to as the PWM on-time, while the time period T2 can be referred to as the PWM off-time.

[0149] For a boost converter, the inductor current flows through an associated switch transistor and a current sense resistor. For example, in the example of FIG. 1, the current through the inductor LI can flow through the corresponding switch transistor 140-1 and the current sense resistor Rcs1. The voltage across the sense resistor can be used to at least partially represent the amount of current flowing through the source inductor. Figure 8A Figure 9C is a diagram of an illustrative current detection circuit 180 according to an embodiment. The input Ics_phx represents the current flowing through the x-phase sense resistor.

[0150] As shown, the current detection circuit 180 can include a comparator 184, a first multiplexing circuit 186, a second multiplexing circuit 188, a delay circuit 182, an adder circuit 190, a unit delay circuit 192, and a data converter (e.g., a digital-to-analog converter) 194. The comparator 184 can have a first (positive) input that receives the input Ics_phx, a second (negative) input, and an output that controls the multiplexer 186. The multiplexer 186 has a first (0) input configured to receive “-1,” a second (1) input configured to receive “1,” an output that outputs “-1” or “1” depending on the output of the comparator 184. If the comparator output is low, then the multiplexer 186 will pass “-1.” If the comparator output is high, then the multiplexer 186 will pass “1.” Figure 9C

[0151] ​​The multiplexer 188 has a first (0) input configured to receive "0", a second (1) input configured to receive "-1" or "1" from the output of the multiplexer 186, a control input that receives the signal from the delay circuit 182 and the output. The adder 190 has a first input connected to the output of the multiplexer 188, an output on which the detected current level Idet_phx is provided, and a second input that receives Idet_phx via a unit delay component 192. The adder 190 connected in this feedback loop can act as an integrator circuit. A digital-to-analog converter (DAC) 194 can receive the unit-delayed version of Idet_phx and can be configured to output an analog reference signal to the second (negative) input of the comparator 184 via a path 196.

[0152] Configured in this way, the current Ics_phx can be checked at specific times based on the rising and falling edges of the PWM signal. The signal PWM_rising_edge_phx will be asserted at the rising edge of the PWM signal, while the signal PWM_falling_edge_phx will be asserted at the falling edge of the PWM signal. For example, the current can be checked immediately after the PWM rising edge to obtain the inductor valley current level (Ivalley). The delay of the circuit 182 can be set to T1 ÷ 2 (see, e.g., Fig. 2B, where Tdelay is set to half of T1) so that the current can be checked for approximately 50% of the time of the PWM to obtain the average inductor current. The detected average current level is labeled Idet in Fig. 2B. Figure 9B The current Ics_phx can be compared to the reference signal provided by the DAC 194 at specific times. If the comparator output is high, the integrator will be incremented by one (because a "1" will pass through the multiplexer 186). Otherwise, the integrator will be decremented by one (because a "-1" will pass through the multiplexer 186). Figure 9B

[0153] Figure 9D is a diagram of an exemplary peak current regulation circuit 198 for a dual-phase boost converter. The peak current regulation circuit 198 can optionally be implemented as part of the controller 144. As shown in Fig. 2C, the peak current regulation circuit 198 can include a first current detection circuit 180-1 associated with a first phase (ph1), a second current detection circuit 180-2 associated with a second phase (ph2), a peak current regulation circuit 200, and adders 202-1 and 202-2 at the output. The peak current regulation circuit 200 can be configured to receive the detected current levels Idet_ph1 and Idet_ph2 from the first and second current detection circuits 180-1 and 180-2, respectively, and to output a peak current regulation signal (Ireg_ph1 and Ireg_ph2) to the first and second current detection circuits 180-1 and 180-2, respectively. Figure 9D Figure 9C ​​The current detection circuits 180-1 and 180-2 can be implemented in accordance with the structures described in the background. The peak current adjustment circuit 200 has a first input configured to receive the detected average current Idet_phl from circuit 180-1, and a second input configured to receive the detected average current Idet_ph2 from circuit 180-2.

[0154] Based on the received detected average current levels of the two phases, the peak adjustment circuit 200 can generate a first peak current adjustment amount Ipk_adj_phl for the first phase and a second peak current adjustment amount Ipk_adj_ph2 for the second phase. The peak current adjustment amounts Ipk_adj_phl and Ipk_adj_ph2 should be greater than or equal to each other. These current adjustment amounts can be added to the peak current reference signal Ipk_comp using adder circuits 202-1 and 202-2 to generate a final peak current (Ipk_phl) for the first phase and a final peak current (Ipk_ph2) for the second phase, respectively. The peak current Ipk_phl limits the amount of current flowing through the inductor LI, while the peak current Ipk_ph2 limits the amount of current flowing through the inductor L2.

[0155] Figure 9E is a diagram of an exemplary peak current adjustment sub-circuit that can be included within the peak current adjustment circuit 200. As shown in Figure 9E the peak current adjustment circuit 200 can include a first subtractor circuit 210-1, a first gain stage 212, a first low pass filter (LPF) 214, and a first digital-to-analog converter (DAC) 216 coupled together in a chain. The subtractor circuit 210-1 can have a first (+) input configured to receive Idet_ph2 and a second (-) input configured to receive Idet_phl. Configured in this way, the subtractor 210-1 will subtract Idet_phl from Idet_ph2, and the corresponding difference will be used to output Ipk_adj_phl.

[0156] Similarly, the peak current adjustment circuit 200 can also include a second subtractor circuit 210-2, a second gain stage 212, a second low pass filter (LPF) 214, and a second DAC 216 coupled together in a chain. The subtractor circuit 210-2 can have a first (+) input configured to receive Idet_phl and a second (-) input configured to receive Idet_ph2. Configured in this way, the subtractor 210-2 will subtract Idet_ph2 from Idet_phl, and the corresponding difference will be used to output Ipk_adj_ph2.

[0157] Figure 9F is a plot showing the results of using the peak current regulation circuit 198 to regulate the peak current of different converter phases. Even though there is a large inductance mismatch between the two phases (e.g., LI is 39.6 uH and L2 is 26.4 uH as noted above), and even though the peak-to-peak ripple of the lower inductance phase (see waveform 222) is 150% of the peak-to-peak ripple of the higher inductance phase (see waveform 220), the average inductor current is balanced between the two phases. By balancing the average inductor current level of the two phases, the power dissipation mismatch of critical components within the dual-phase boost converter is significantly reduced.

[0158] In conjunction with Figure 9B to Figure 9E The detection of average current levels in the described embodiments is merely illustrative. In another suitable arrangement, a valley current detection scheme can be provided. Figure 10A is a diagram of an illustrative current detection circuit 280 for sensing the inductor valley current of a dual-phase boost converter. Similar to above, input Ics_phx represents the current flowing through the x-phase sense resistor. As Figure 10A indicated, the current detection circuit 280 can include a comparator 284, a first multiplexing circuit 286, a second multiplexing circuit 288, a delay circuit 282, a summing circuit 290, a unit delay circuit 292, and a DAC 294. The comparator 284 can have a first (positive) input that receives input Ics_phx, a second (negative) input, and an output that controls multiplexer 286. The multiplexer 286 has a first (0) input configured to receive "-1", a second (1) input configured to receive "1", and an output that outputs either "-1" or "1" depending on the output of the comparator 284. If the comparator output is low, then the multiplexer 286 will pass "-1". If the comparator output is high, then the multiplexer 286 will pass "1".

[0159] The multiplexer 288 has a first (0) input configured to receive "0", a second (1) input configured to receive "-1" or "1" from the output of the multiplexer 286, a control input that receives the signal from the delay circuit 282 and the output. The adder 290 has a first input connected to the output of the multiplexer 288, an output on which the detected valley current level Ivalley_phx is provided, and a second input that receives Ivalley_phx via a unit delay component 292. The adder 290 connected in this feedback loop can act as an integrator circuit. The DAC 294 can receive a unit delayed version of Ivalley_phx and can be configured to output an analog reference signal to the second (negative) input of the comparator 284 via a path 296.

[0160] Configured in this way, the current Ics_phx can be checked at a certain time based on the rising edge of the PWM signal. The signal PWM_rising_edge_phx will be asserted at the rising edge of the PWM signal. The current can be checked immediately after the PWM rising edge, for example, to obtain the inductor valley current level (Ivalley). At the rising edge of the PWM signal, the integrator can combine the output of the multiplexer 288 and can convert the output of the integrator to an analog signal using the DAC 294 as a reference for the comparator 284. At a certain time, Ics_phx can be compared to the reference signal provided by the DAC 294. If the comparator output is high, the integrator will increase by one (because "1" will pass through the multiplexer 286). Otherwise, the integrator will decrease by one (because "-1" will pass through the multiplexer 286).

[0161] Figure 10B is a diagram of an exemplary peak current adjustment circuit 298 that includes Figure 10A a valley current detection circuit of FIG. 1. The peak current adjustment circuit 298 can optionally be implemented as part of the controller 144. As shown in Figure 10B the peak current adjustment circuit 298 can include a first current detection circuit 280-1 associated with a first phase (phl), a second current detection circuit 280-2 associated with a second phase (ph2), a peak current adjustment circuit 300, and an adder 301 at the output. The peak current adjustment circuit 300 can be implemented as a digital circuit, for example, as shown in Figure 10AThe structures described herein implement current detection circuits 280-1 and 280-2. Peak current adjustment circuit 300 has: a first input section configured to receive a detected valley current Ivalley_ph1 from circuit 280-1; and a second input section configured to receive a detected valley current Ivalley_ph2 from circuit 280-2.

[0162] Based on the received and detected valley current levels of the two phases, the peak adjustment circuit 300 can generate a peak current adjustment amount Ipk_adj_ph1 for the first phase. The adjustment value Ipk_adj_ph1 can be combined with a first peak current value determined by a compensator associated with the first phase (Ipk_con_ph1), which uses adder 301 to generate a first peak current reference Ipk_ref_ph1, which can be fed back as input to the peak current adjustment circuit 300. The circuit 300 can also receive a second peak current value determined by a compensator associated with the second phase (Ipk_con_ph2), which can be used as a second peak current reference Ipk_ref_ph2.

[0163] Figure 10C This is a diagram illustrating a suitable specific implementation of the peak current adjustment circuit 300. For example... Figure 10C As shown, the peak current adjustment circuit 300 may include a first adder circuit 310-1, a second adder circuit 310-2, a subtraction circuit 311, a gain stage 312, and an integrator 314 coupled together in a chain. Adder circuit 310-1 may be configured to combine Ipk_ref_ph2 and Ivalley_ph2. Adder circuit 310-2 may be configured to combine Ipk_ref_ph1 and Ivalley_ph1. Subtraction circuit 311 may have: a first (+) input configured to receive a sum from the output of adder 310-1; a second (-) input configured to receive a sum from the output of adder 310-2; and an output providing the corresponding difference, which is then fed to gain stage 312 for accumulation by integrator 314. The final integrated output is used as the peak current adjustment amount Ipk_adj_ph1 for the first phase.

[0164] With this configuration, Ipk_adj_ph1 can be expressed mathematically as follows:

[0165] Ipk_adj_ph1=∫Gain*(Ipk_ref_ph2+Ivalley_ph2–Ipk_ref_ph1–Ivalley_ph1)

[0166] dt(3)

[0167] The integration can be performed in the digital domain or the analog domain. By tracking the inductor valley current in this way, it can move up and down between cycles, the peak current is not affected too much because the peak current adjustment mechanism combines the error with a gain factor. The integrator 314 acts like a low pass filter that gradually adjusts the peak current over multiple switching cycles. Operating in this way, even when there is a large inductance mismatch, the average inductor current between the two phases will be balanced (see, e.g., the resulting waveforms in Figure 9F By balancing the average inductor current levels of the two phases, the power dissipation mismatch of critical components within the dual-phase boost converter is significantly reduced.

[0168] Another potential reliability issue associated with boost converters is if there is a fault or accidental short near the input of the boost converter. In such scenarios, a large current can flow into the input of the boost converter, which can damage critical electronic components within the boost converter. To help mitigate this potential current surge, a current control circuit can be provided for the boost converter, such as a surge current controller 320 coupled at the input of the boost converter 70 (see, e.g., Figure 11A ). As shown in Figure 11A The surge current controller 320 can be used in boost converters 70 having any number of phases (e.g., for single-phase boost converters, dual-phase boost converters, or general N-phase boost converters for N > 2)

[0169] Figure 11B is a circuit diagram showing one suitable implementation of the surge current controller 320. As shown in Figure 11B The surge current controller 320 can include a transistor 322. The transistor 322 (e.g., an n-channel MOSFET device) has a gate terminal connected to a current source Iz, has a gate-drain parasitic capacitance Cgd, and a gate-source parasitic capacitance Cgs. A potential fault short is represented as a short resistance Rshort. Without the surge current controller 320, a large input current lin (e.g., 1 A - 2 A or more) can inadvertently flow into the short path.

[0170] In particular, the surge controller 320 can be provided with a detection resistor Rdet coupled between the gate and source terminals of the transistor 322. When the gate-source voltage Vgs on the transistor 322 ramps up to turn on the transistor 322, a small amount of current can flow through the resistor Rdet, which will present a voltage difference to the first surge comparator 324 depending on whether a short fault is present or not. The voltage difference can be compared to a predetermined threshold (Thres) using the second surge comparator 326 to determine whether a short actually exists. For example, when no short is present, the comparator 324 can detect a difference of 0 mV to 40 mV, which is less than an exemplary predetermined threshold of 50 mV. However, if a short is present, the comparator 324 can detect a 100 mV difference, which can exceed the 50 mV predetermined threshold. Configured in this way, the surge controller 320 can be used to detect short faults within the boost converter 70 and can take any suitable action in response to detecting such a defect to help prevent irreversible damage.

[0171] In Figure 11A and Figure 11B In the example shown, the surge current controller 320 is connected at the input of the boost converter 70, but this is merely illustrative. If desired, a surge controller can also be formed at the output of the boost converter 70 or at any suitable intermediate location within the boost converter 70 to help reduce the risk of damage caused by inadvertent short faults.

[0172] According to an embodiment, a display is provided, the display comprising: a display layer comprising a liquid crystal layer, a color filter layer, and a thin film transistor layer; a backlight unit configured to illuminate the display layer, the backlight unit having a maximum brightness, and the backlight unit comprising: a plurality of light emitting diode (LED) strings; a current driver circuit coupled to the plurality of LED strings, the current driver circuit configured to throttle the maximum brightness of the backlight unit when at least one of the plurality of LED strings fails.

[0173] According to another embodiment, the backlight unit comprises a fault detection circuit configured to detect a number of failed LED strings in the plurality of LED strings.

[0174] According to another embodiment, the backlight unit comprises a comparator configured to compare a headroom voltage generated from one of the plurality of LED strings to a predetermined threshold.

[0175] According to another embodiment, an amount by which the current driver circuit throttles the maximum brightness of the backlight unit is a function of the number of failed LED strings determined by the fault detection circuit.

[0176] According to another implementation, the amount by which the current driver circuit throttles the maximum brightness of the backlight unit is a function of the product of the number of faulty LED strings and the throttling coefficient.

[0177] According to another implementation, the throttling coefficient is programmable.

[0178] According to another implementation, the throttling coefficient has a value in the range of 5% to 20%.

[0179] According to another embodiment, the backlight unit includes a maximum brightness limiting control circuit configured to receive an input brightness code, receive a control signal from a fault detection circuit, and generate a corresponding output signal for a control current driver circuit.

[0180] According to an embodiment, a display is provided, the display comprising: a display layer including a liquid crystal layer, a color filter layer, and a thin-film transistor layer; a backlight unit configured to illuminate the display layer, the backlight unit including: a plurality of light-emitting diode (LED) strings; a DC-DC converter configured to provide an output voltage to the plurality of LED strings; and a headroom feedforward control circuit configured to receive a brightness command and guide the DC-DC converter to adjust the output voltage by a predicted amount in response to detecting a change in the brightness command.

[0181] According to another embodiment, the headroom feedforward control circuit is also configured to calculate a predicted amount for adjusting the output voltage using a linear or nonlinear formula that is a function of the change in the brightness command.

[0182] According to another embodiment, the backlight unit includes an adaptive headroom control circuit configured to receive a headroom voltage from one of a plurality of LED strings, and the adaptive headroom control circuit is also configured to direct a DC-to-DC converter to increase the output voltage when the headroom voltage drops below a target value.

[0183] According to another embodiment, the DC-to-DC converter is configured to receive control signals from the headroom feedforward control circuit and the adaptive headroom control circuit.

[0184] According to another implementation, the adaptive headroom control circuit is temporarily disabled when the headroom feedforward control circuit is used to adjust the output voltage.

[0185] According to another embodiment, the backlight unit is also configured to wait for a predetermined delay time after the brightness command is changed, thereby allowing the current flowing through the multiple LED strings to change.

[0186] According to another implementation, the adaptive headroom control circuit is reactivated when a predetermined delay time expires.

[0187] According to another embodiment, the output voltage stabilizes prior to expiration of a predetermined delay time.

[0188] According to an embodiment, a display is provided, the display comprising: a display layer comprising a liquid crystal layer, a color filter layer, and a thin film transistor layer; a backlight unit configured to illuminate the display layer, the backlight unit comprising: a plurality of light emitting diode (LED) strings; a first backlight driver integrated circuit configured to drive a first subset of the LED strings of the plurality of LED strings; and a second backlight driver integrated circuit configured to drive a second subset of the LED strings of the plurality of LED strings, the second subset of the LED strings being different from the first subset of the LED strings.

[0189] According to another embodiment, the first subset of the LED strings is interleaved with the second subset of the LED strings.

[0190] According to another embodiment, the first backlight driver integrated circuit comprises a first phase-locked loop circuit configured to generate a first pulse width modulation signal for the first subset of the LED strings, the second backlight integrated circuit comprises a second phase-locked loop circuit configured to generate a second pulse width modulation signal for the second subset of the LED strings, the first backlight driver integrated circuit and the second backlight driver integrated circuit are configured to receive a common synchronization signal that ensures that the first pulse width modulation signal and the second pulse width modulation signal generated by the first backlight driver integrated circuit and the second backlight driver integrated circuit exhibit the same frequency, the first backlight driver integrated circuit and the second backlight driver integrated circuit are further configured to receive an enable signal, and the enable signal sets a predetermined phase delay between the first pulse width modulation signal and the second pulse width modulation signal generated by the first backlight driver integrated circuit and the second backlight driver integrated circuit.

[0191] According to another embodiment, the first subset of the LED strings is not interleaved with the second subset of the LED strings, the first backlight driver integrated circuit and the second backlight driver integrated circuit are further configured to receive an enable signal, and the enable signal directs the first backlight driver integrated circuit and the second backlight driver integrated circuit to begin generating the pulse width modulation signals at the same time.

[0192] The foregoing is merely illustrative and various modifications can be made to the described embodiments. The foregoing embodiments can be implemented independently or in any combination.

[0193] This patent application claims priority to U.S. Patent Application No. 16 / 418,857, filed May 21, 2019, and U.S. Provisional Patent Application No. 62 / 737,690, filed September 27, 2018, which are hereby incorporated by reference in their entirety.

Claims

1. A display, comprising: The display layer includes a liquid crystal layer, a color filter layer, and a thin-film transistor layer. and A backlight unit configured to illuminate the display layer, wherein the backlight unit has a maximum brightness, and wherein the backlight unit comprises: Multiple light-emitting diode (LED) strings; and A current driver circuit coupled to the plurality of LED strings, wherein the current driver circuit is configured to throttle the maximum brightness of the backlight unit when at least one of the plurality of LED strings fails.

2. The display according to claim 1, wherein the backlight unit further includes a fault detection circuit configured to detect the number of faulty LED strings among the plurality of LED strings.

3. The display of claim 2, wherein the backlight unit further comprises a comparator configured to compare a headroom voltage generated from one of the plurality of LED strings with a predetermined threshold.

4. The display according to claim 2, wherein the amount by which the current driver circuit throttles the maximum brightness of the backlight unit is a function of the number of faulty LED strings determined by the fault detection circuit.

5. The display according to claim 2, wherein the amount by which the current driver circuit throttles the maximum brightness of the backlight unit is a function of the product of the number of faulty LED strings and the throttling coefficient.

6. The display according to claim 5, wherein the throttling coefficient is programmable.

7. The display according to claim 5, wherein the throttling coefficient has a value in the range of 5% to 20%.

8. The display of claim 5, wherein the backlight unit further comprises a maximum brightness limiting control circuit configured to receive an input brightness code, receive a control signal from the fault detection circuit, and generate a corresponding output signal to control the current driver circuit.

9. A method of operating a display, the display having a display layer comprising a liquid crystal layer and a color filter layer, the method comprising: The display layer is illuminated by a backlight unit, the backlight unit comprising a plurality of light-emitting diode (LED) strings and a current driver circuit coupled to the plurality of LED strings; and Using the current driver circuit, in response to determining that at least one of the plurality of LED strings has failed, the maximum brightness of the backlight unit is limited.

10. The method of claim 9, further comprising: The number of faulty LED strings among the multiple LED strings is detected using a fault detection circuit.

11. The method of claim 10, further comprising: The net voltage generated by one of the multiple LED strings is compared with a threshold.

12. The method of claim 10, wherein the current driver circuit limits the maximum brightness of the backlight unit to a degree based on the number of faulty LED strings.

13. The method of claim 10, wherein the degree to which the current driver circuit limits the maximum brightness of the backlight unit is based on the product of the number of faulty LED strings and a throttling coefficient.

14. The method of claim 13, wherein the throttling coefficient has a value in the range of 5% to 20%.

15. The method of claim 10, further comprising: The maximum brightness limit control circuit receives the input brightness code and the control signal from the fault detection circuit. and The maximum brightness limit control circuit generates the output signal that controls the current driver circuit.

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