Display device and display driving method

Abstract

Embodiments of the present disclosure relate to a display apparatus and a display driving method, and more particularly, a display apparatus can be provided, including a display panel in which a plurality of sub-pixels and a plurality of reference voltage lines are disposed, the plurality of sub-pixels including a light emitting element that emits light by a high potential voltage supplied to a driving voltage line, the plurality of reference voltage lines connected to the plurality of sub-pixels to detect a characteristic value; a data driving circuit configured to supply a low potential voltage to the driving voltage line through the plurality of reference voltage lines; a base voltage switching circuit configured to control a base voltage node connected to a cathode electrode of the light emitting element; a current detecting circuit configured to detect a current flowing between the base voltage node and a ground; and a timing controller configured to control the base voltage switching circuit and to generate a defect detection signal for the driving voltage line according to the current detected by the current detecting circuit.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0108560, filed on August 18, 2021, which is incorporated herein by reference for all purposes, as fully set forth herein. Technical Field

[0003] Embodiments of this disclosure relate to display devices and display driving methods capable of effectively detecting defects in voltage lines or display panels. Background Technology

[0004] With the development of the information society, the demand for various types of image display devices is increasing. In this regard, a range of display devices, such as liquid crystal displays and organic light-emitting diode displays, have recently been widely used.

[0005] In such display devices, due to the use of self-emissive organic light-emitting diodes, organic light-emitting display devices have excellent characteristics such as fast response speed, high contrast, high luminous efficiency, high brightness and wide viewing angle.

[0006] Such an organic light-emitting display device may include light-emitting elements disposed in a plurality of sub-pixels arranged in a display panel, and the light-emitting elements may be controlled to emit light by controlling the current flowing through them, so as to display an image while controlling the brightness of the sub-pixels.

[0007] Such a display device includes a drive voltage supply source for supplying various drive voltages required to drive the display panel to the drive circuit and the display panel, as well as various components for transmitting the drive voltage.

[0008] Such a display device includes a display panel in which multiple sub-pixels are arranged in a matrix. The display panel receives scan signals from a gate driving circuit and data voltages from a data driving circuit to drive each sub-pixel. Furthermore, the display panel receives multiple driving voltages from a power management circuit.

[0009] At this time, when cracks appear due to an impact applied to the display panel from the outside, multiple drive voltage lines in the display panel may short-circuit or open-circuit with each other.

[0010] For example, a high-potential voltage line that receives a high-potential voltage from a power management circuit may be shorted to a low-potential voltage line that receives a low-potential voltage, or the voltage line may be shorted to the display panel.

[0011] When overcurrent flows in the driving voltage line or the display panel due to such a defect, the voltage line can be disconnected or a burning phenomenon in which the display panel can be burned can occur due to the overcurrent. SUMMARY

[0012] Therefore, the inventors of the disclosure invented a display apparatus and a display driving method capable of effectively detecting a defect in a voltage line or a display panel.

[0013] Embodiments of the disclosure can provide a display apparatus and a display driving method capable of reducing damage to a display panel due to a high potential voltage and effectively detecting a defect in the display panel by using a display driving reference voltage.

[0014] In addition, embodiments of the disclosure can provide a display apparatus and a display driving method capable of effectively reducing damage to a display panel due to a high potential voltage by detecting a defect in a driving voltage line or a display panel before a high potential voltage is supplied to a sub-pixel.

[0015] Embodiments of the disclosure can provide a display apparatus including a display panel in which a plurality of sub-pixels and a plurality of reference voltage lines are disposed, the plurality of sub-pixels including a light emitting element that emits light by a high potential voltage supplied to a driving voltage line, the plurality of reference voltage lines being connected to the plurality of sub-pixels to detect a characteristic value, a data driving circuit configured to supply a low potential voltage lower than the high potential voltage to the driving voltage line through the plurality of reference voltage lines, a base voltage switching circuit configured to control a base voltage node connected to a cathode electrode of the light emitting element, a current detection circuit configured to detect a current flowing between the base voltage node and a ground, and a timing controller configured to control the base voltage switching circuit and to generate a defect detection signal for the driving voltage line according to the current detected by the current detection circuit.

[0016] Embodiments of the disclosure can provide a display driving method for driving a display apparatus including a display panel in which a plurality of sub-pixels and a plurality of reference voltage lines are disposed, the plurality of sub-pixels having a light emitting element that emits light by a high potential voltage supplied to a driving voltage line, the plurality of reference voltage lines being connected to the plurality of sub-pixels to detect a characteristic value, the display driving method including maintaining a high potential voltage node at a level lower than a display driving reference voltage, floating a base voltage node, supplying a low potential voltage lower than the high potential voltage to the driving voltage line, detecting a current between the base voltage node and a ground, comparing the detected current with a reference value, and generating a defect detection signal according to a result of comparing the detected current with the reference value.

[0017] According to embodiments of the present disclosure, a display device and a display driving method capable of effectively detecting defects in a voltage line or a display panel can be provided.

[0018] According to embodiments of the present disclosure, a display device and a display driving method capable of reducing damage to a display panel due to a high potential voltage and effectively detecting defects in a display panel by using a display driving reference voltage can be provided.

[0019] According to embodiments of the present disclosure, a display device and a display driving method capable of effectively reducing damage to a display panel due to a high potential voltage by detecting defects in a driving voltage line or a display panel before a high potential voltage is supplied to a sub-pixel can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0020] In the drawings:

[0021] Figure 1 A schematic diagram of a display device according to an embodiment of the present disclosure is shown.

[0022] Figure 2 A system diagram of a display device according to an embodiment of the present disclosure is shown.

[0023] Figure 3 A circuit diagram of a sub-pixel in a display device according to an embodiment of the present disclosure is shown.

[0024] Figure 4 An exemplary circuit structure for sensing a characteristic value of a driving transistor in a display device according to an embodiment of the present disclosure is shown.

[0025] Figure 5 An exemplary circuit for detecting defects in a driving voltage line in a display device according to an embodiment of the present disclosure is shown.

[0026] Figure 6 An exemplary signal flow diagram when a driving voltage line is normal in a display device according to an embodiment of the present disclosure is shown.

[0027] Figure 7 An exemplary signal flow diagram of a signal flowing through a sub-pixel when a driving voltage line is normal in a display device according to an embodiment of the present disclosure is shown.

[0028] Figure 8 An exemplary signal flow diagram when a driving voltage line is defective in a display device according to an embodiment of the present disclosure is shown.

[0029] Figure 9An exemplary signal diagram flowing through a sub-pixel when a driving voltage line is defective in a display apparatus according to an embodiment of the present disclosure is illustrated.

[0030] Figure 10 A flowchart of a display driving method according to an embodiment of the present disclosure is illustrated. DETAILED DESCRIPTION

[0031] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the exemplary drawings. In the following description of examples or embodiments of the present disclosure, specific examples or embodiments that can be implemented are illustrated with the aid of drawings, and in the drawings, the same reference numerals can be used to designate the same or similar components even though they are illustrated in different drawings from each other. Also, in the following description of examples or embodiments of the present disclosure, a detailed description of well-known functions and components incorporated herein will be omitted when it is determined that the subject matter of some embodiments of the present disclosure will be rather unclear by incorporating the detailed description thereof. The terms such as "include," "have," "comprise," "comprise," "consist of," and "consist of" used herein are generally intended to allow addition of other components unless the terms "only" are used together. As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0032] Terms such as "first," "second," "A," "B," "(A)," or "(B)" can be used to describe elements of the present disclosure herein. Each of these terms is not used to limit the nature, order, sequence, or number of elements, etc., but is only used to distinguish the corresponding element from other elements.

[0033] When referring to a first element "connected or coupled to" a second element, "contacting or overlapping" a second element, etc., it should be interpreted that the first element can not only be "directly connected or coupled to" the second element or "directly contact or overlap" the second element, but also a third element can be "interposed" between the first element and the second element, or the first element and the second element can be "connected or coupled" to each other, "contacting or overlapping" via a fourth element, etc. Here, the second element can be included in at least one of two or more elements that are "connected or coupled" to each other, "contacting or overlapping" each other, etc.

[0034] When time-related terms such as "after," "subsequently," "next," "before," etc. are used to describe the process or operation of elements or configurations or the flow or steps in a process, manufacturing method, etc., these terms can be used to describe non-continuous or non-sequential processes or operations unless used together with the term "directly" or "immediately."

[0035] Also, when referring to any dimension, relative size, etc., it is to be understood that the numerical value or the corresponding information (e.g., horizontal, range, etc.) of the element or feature includes a tolerance or error range that can be caused by various factors (e.g., process factors, internal or external influences, noise, etc.) even when the relevant description is not specified. Also, the term "may" completely covers all the meanings of the term "can."

[0036] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0037] Figure 1 A schematic diagram of a display apparatus according to an embodiment of the present disclosure is illustrated.

[0038] Referring to Figure 1 The display apparatus 100 according to an embodiment of the present disclosure can include a display panel 110 connected to a plurality of gate lines GL and a plurality of data lines DL, in which a plurality of sub-pixels SP are arranged in rows and columns, a gate driving circuit 120 for supplying a scan signal to the plurality of gate lines GL and a data driving circuit 130 for supplying a data voltage to the plurality of data lines DL, a timing controller 140 for controlling the gate driving circuit 120 and the data driving circuit 130, and a power management circuit 150.

[0039] The display panel 110 displays an image based on a scan signal supplied from the gate driving circuit 120 through the plurality of gate lines GL and a data voltage supplied from the data driving circuit 130 through the plurality of data lines DL.

[0040] In the case of a liquid crystal display, the display panel 110 includes a liquid crystal layer formed between two substrates, and a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, an IPS (In-Plane Switching) mode, an FFS (Fringe Field Switching) mode can operate in any known mode. In the case of an organic light emitting display apparatus, the display panel 110 can be implemented in a top emission method, a bottom emission method, or a dual emission method.

[0041] In the display panel 110, a plurality of pixels can be provided in a matrix form. Each pixel can be composed of sub-pixels SP of different colors, for example, a white sub-pixel, a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Each sub-pixel SP can be defined by a plurality of data lines DL and a plurality of gate lines GL.

[0042] The sub-pixel SP can include a thin film transistor (TFT) arranged in an area where the data line DL and the gate line GL intersect, a light emitting element such as an organic light emitting diode that emits light according to a data voltage, and a storage capacitor that maintains the data voltage by being electrically connected to the light emitting element.

[0043] For example, when the display device 100 having a resolution of 2160x3840 includes four sub-pixels SP of white W, red R, green G, and blue B, 3840x4=15360 data lines DL can be provided by 2160 gate lines GL and 3840 data lines DL connected to the 4 sub-pixels WRGB, respectively. Each of the plurality of sub-pixels SP can be disposed in an area where the plurality of gate lines GL and the plurality of data lines DL cross.

[0044] The gate driving circuit 120 is controlled by the timing controller 140 and controls a driving timing of the plurality of sub-pixels SP by sequentially supplying a scan signal to the plurality of gate lines GL disposed in the display panel 110.

[0045] In the display device 100 having a resolution of 2160x3840, an operation of sequentially supplying a scan signal to 2160 gate lines GL from a first gate line GL1 to a 2160th gate line GL2160 can be referred to as a 2160-phase driving operation. In addition, an operation of sequentially supplying a scan signal to every four gate lines GL, such as a case where a scan signal is sequentially supplied from a first gate line GL1 to a fourth gate line GL4 and then from a fifth gate line GL5 to an eighth gate line GL8, can be referred to as a 4-phase driving operation. As described above, an operation of sequentially supplying a scan signal to every N number of gate lines can be referred to as an N-phase driving operation.

[0046] The gate driving circuit 120 can include one or more gate driving integrated circuits (GDICs), and the gate driving circuit 120 can be disposed at one side or both sides of the display panel 110 according to a driving method. Alternatively, the gate driving circuit 120 can be implemented in a gate-in-panel (GIP) structure embedded in a bezel area of the display panel 110.

[0047] The data driving circuit 130 receives image data DATA from the timing controller 140 and converts the received image data DATA into an analog data voltage. Then, upon supply of a scan signal through a gate line GL, the data driving circuit 130 supplies the analog data voltage to each of the data lines DL so that each of the sub-pixels SP connected to the data line DL emits light having a corresponding luminance in response to the analog data voltage.

[0048] Likewise, the data driving circuit 130 can include one or more source driving integrated circuits (SDICs). Each of the source driving integrated circuits SDICs can be connected to a bonding pad of the display panel 110 through tape automated bonding (TAB) or chip on glass (COG), or can be directly mounted on the display panel 110.

[0049] In some cases, each of the source driving integrated circuits (SDICs) can be integrated with the display panel 110. Also, each of the source driving integrated circuits (SDICs) can be implemented using a chip on film (COF) structure. In this case, the source driving integrated circuits SDICs can be mounted on a circuit film to be electrically connected to the data lines DL in the display panel 110 via the circuit film.

[0050] The timing controller 140 supplies various control signals to the gate driving circuit 120 and the data driving circuit 130 and controls the operations of the gate driving circuit 120 and the data driving circuit 130. That is, the timing controller 140 controls the gate driving circuit 120 to supply the scan signals in response to times implemented by respective frames, and on the other hand, the timing controller 140 transmits digital image data DATA from an external source to the data driving circuit 130.

[0051] Here, the timing controller 140 receives not only the image data DATA from the host system 200 but also various timing signals (including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a master clock MCLK) from the host system 200.

[0052] The host system 200 can be any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a wearable device.

[0053] Accordingly, the timing controller 140 generates control signals using the various timing signals received from the host system 200 and supplies the control signals to the gate driving circuit 120 and the data driving circuit 130.

[0054] For example, the timing controller 140 generates various gate control signals (including a gate start pulse GSP, a gate clock GCLK, and a gate output enable signal GOE) to control the gate driving circuit 120. Here, the gate start pulse GSP is used to control a start timing of one or more gate driving integrated circuits GDICs of the gate driving circuit 120. Also, the gate clock GCLK is a clock signal commonly supplied to the one or more gate driving integrated circuits GDICs for controlling a shift timing of the scan signals. The gate output enable signal GOE specifies timing information of the one or more gate driving integrated circuits GDICs.

[0055] Further, the timing controller 140 generates various data control signals (including a source start pulse SSP, a source sampling clock SSC, and a source output enable signal SOE) to control the data driving circuit 130. Here, the source start pulse SSP is used to control the start timing of data sampling of one or more source driving integrated circuits SDIC of the data driving circuit 130. The source sampling clock SSC is a clock signal used to control the timing of data sampling in each of the source driving integrated circuits SDIC. The source output enable signal SOE controls the output timing of the data driving circuit 130.

[0056] The display device 100 can include a power management circuit 150 for supplying or controlling various voltages or currents to the display panel 110, the gate driving circuit 120, and the data driving circuit 130.

[0057] The power management circuit 150 generates power to drive the display panel 110, the gate driving circuit 120, and the data driving circuit 130 by adjusting a DC input voltage Vin supplied from the host system 200.

[0058] Meanwhile, the sub-pixels SP can be positioned at points where the gate lines GL and the data lines DL intersect, and light emitting elements can be disposed in each of the sub-pixels SP. For example, the organic light emitting display device can include light emitting elements such as organic light emitting diodes in each of the sub-pixels SP, and can display an image by controlling a current flowing through the light emitting elements in response to a data voltage.

[0059] Such a display device 100 can be various types of devices such as a liquid crystal display, an organic light emitting display, and a plasma display panel.

[0060] Figure 2 A system diagram of a display device according to an embodiment of the disclosure is illustrated.

[0061] Referring to Figure 2 Each of the source driving integrated circuits SDIC of the data driving circuit 130 and the gate driving circuit 120 in the display device 100 according to an embodiment of the disclosure can be implemented using a COF type among various structures such as a TAB, a COG, and a COF.

[0062] At least one of the gate driving integrated circuits GDIC included in the gate driving circuit 120 can be mounted on each of the gate films GF, and one side of the gate film GF can be electrically connected to the display panel 110. Further, an electric wire for electrically connecting the gate driving integrated circuit GDIC and the display panel 110 can be disposed on the gate film GF.

[0063] Likewise, the data driving circuit 130 can include one or more source driving integrated circuits SDIC that can be mounted on the source film SF, respectively. A portion of the source film SF can be electrically connected to the display panel 110. Also, wires can be provided on the source film SF to electrically connect the source driving integrated circuits SDIC to the display panel 110.

[0064] The display device 100 can include at least one source printed circuit board SP CB to connect the plurality of source driving integrated circuits SDIC to other devices through an electrical circuit, and the display device 100 can include a control printed circuit board CPCB to mount various control components and electrical elements.

[0065] Other portions of the source film SF on which the source driving integrated circuits SDIC are mounted can be connected to the at least one source printed circuit board SP CB. That is, a portion of the source film SF on which the source driving integrated circuits SDIC are mounted can be electrically connected to the display panel 110, and another portion of the source film SF can be electrically connected to the source printed circuit board SP CB.

[0066] The timing controller 140 and the power management circuit 150 can be mounted on the control printed circuit board CPCB. The timing controller 140 can control the operations of the data driving circuit 130 and the gate driving circuit 120. The power management circuit 150 can supply driving voltages and driving currents, or control voltages and currents for the data driving circuit 130 and the gate driving circuit 120.

[0067] The at least one source printed circuit board SP CB and the control printed circuit board CPCB can have an electrical circuit system connection through at least one connection member. The connection member can be, for example, a flexible printed circuit FPC, a flexible flat cable FFC, or the like. In this case, the connection member for connecting the at least one source printed circuit board SP CB and the control printed circuit board CPCB can be variously changed according to the size and type of the display device 100. The at least one source printed circuit board SP CB and the control printed circuit board CPCB can be integrated into a single printed circuit board.

[0068] In the display device 100 having the above-described configuration, the power management circuit 150 supplies a driving voltage required for a display driving operation or a sensing operation of a characteristic value to the source printed circuit board SP CB through the flexible printed circuit FPC or the flexible flat cable FFC. The driving voltage supplied to the source printed circuit board SP CB is transmitted via the source driving integrated circuits SDIC to make a specific sub-pixel SP in the display panel 110 emit light or to sense the specific sub-pixel SP in the display panel 110.

[0069] Each of the sub-pixels SP arranged in the display panel 110 of the display device 100 can include an organic light emitting diode as a light emitting element and circuit elements such as a driving transistor to drive the organic light emitting diode.

[0070] The type and number of the circuit elements constituting each of the sub-pixels SP can be determined differently according to functions, designs, etc.

[0071] Figure 3 A circuit diagram of a sub-pixel in a display device according to an embodiment of the disclosure is illustrated.

[0072] Referring to Figure 3 Each of the sub-pixels SP arranged in the display device 100 according to an embodiment of the disclosure can include one or more transistors, a capacitor, and an organic light emitting diode as a light emitting element ED.

[0073] For example, the sub-pixel SP can include a driving transistor DRT, a switching transistor SWT, a sensing transistor SENT, a storage capacitor Cst, and a light emitting element ED.

[0074] The driving transistor DRT can have a first node N1, a second node N2, and a third node N3. The first node N1 of the driving transistor DRT can be a gate node to which a data voltage Vdata is supplied through a data line DL when the switching transistor SWT is turned on. The second node N2 of the driving transistor DRT can be electrically connected to an anode of the light emitting element ED, and can be a drain node or a source node. The third node N3 of the driving transistor DRT can be electrically connected to a driving voltage line DVL to be supplied with a driving voltage EVDD, and can be a source node or a drain node.

[0075] Here, a sub-pixel driving voltage EVDD for displaying an image can be supplied to the driving voltage line DVL in a display driving period. For example, the sub-pixel driving voltage EVDD for displaying an image can be a high potential voltage of 27 V.

[0076] The switching transistor SWT is electrically connected between the first node N1 of the driving transistor DRT and the data line DL, and operates in response to a scan signal SCAN supplied to the switching transistor SWT through a gate line GL connected to the gate node. Further, the switching transistor SWT controls the operation of the driving transistor DRT by transmitting the data voltage Vdata to the gate node of the driving transistor DRT through the data line DL when the switching transistor SWT is turned on.

[0077] The sensing transistor SENT is electrically connected between the second node N2 of the drive transistor DRT and the reference voltage line RVL, and operates in response to a sensing signal SENSE supplied through a gate line GL connected to the gate node. When the sensing transistor SENT is turned on, the reference voltage Vref supplied from the reference voltage line RVL is transmitted to the second node N2 of the drive transistor DRT.

[0078] That is, the voltage of the first node N1 and the voltage of the second node N2 of the drive transistor DRT can be controlled by controlling the switching transistor SWT and the sensing transistor SENT. Accordingly, a current for causing the light emitting element ED to emit light can be supplied.

[0079] Each of the gate nodes of the switching transistor SWT and the sensing transistor SENT can be connected to a single gate line GL or different gate lines GL. Here, an exemplary structure in which the switching transistor SWT and the sensing transistor SENT are connected to different gate lines GL is shown. In this case, the switching transistor SWT and the sensing transistor SENT are independently controlled by the scan signal SCAN and the sensing signal SENSE transmitted from the different gate lines GL.

[0080] On the other hand, when the switching transistor SWT and the sensing transistor SENT are connected to a single gate line GL, the switching transistor SWT and the sensing transistor SENT are simultaneously controlled by the scan signal SCAN or the sensing signal SENSE transmitted from the single gate line GL, and thus the aperture ratio of the sub-pixel SP can be improved.

[0081] Further, the transistors provided in the sub-pixel SP can not only be n-type transistors, but also p-type transistors. Here, an exemplary structure of n-type transistors is shown.

[0082] The storage capacitor Cst is electrically connected between the first node N1 and the second node N2 of the drive transistor DRT, and functions to maintain the data voltage Vdata during one frame.

[0083] Such a storage capacitor Cst can be connected between the first node N1 and the third node N3 of the drive transistor DRT according to the type of the drive transistor DRT. The anode electrode of the light emitting element ED can be electrically connected to the second node N2 of the drive transistor DRT, and a base voltage EVSS can be supplied to the cathode electrode of the light emitting diode EL.

[0084] Here, the base voltage EVSS can be a ground voltage or a voltage higher or lower than the ground voltage. Further, the base voltage EVSS can vary according to a driving condition. For example, the base voltage EVSS during a display driving period can be different from the base voltage EVSS during a sensing period.

[0085] The structure of the sub-pixel SP described as an example above is a 3T1C (3 transistors 1 capacitor) structure, which is only an example for explanation, and also includes one or more transistors, or in some cases, also includes one or more capacitors. Alternatively, each of the plurality of sub-pixels SP can have the same structure, or some of the plurality of sub-pixels SP can have different structures.

[0086] The display device 100 according to the embodiment of the disclosure can use a method for measuring a current flowing through a voltage charged in a storage capacitor Cst during a sensing period of a characteristic value of a driving transistor DRT in order to effectively sense the characteristic value of the driving transistor DRT, such as a threshold voltage or mobility. Such a method can be referred to as a current sensing operation.

[0087] That is, the characteristic value or the change in the characteristic value of the driving transistor DRT in the sub-pixel SP can be determined by measuring a current flowing through a voltage charged in the storage capacitor Cst during the sensing period of the characteristic value of the driving transistor DRT.

[0088] At this time, since the reference voltage line RVL is not only used to supply the reference voltage Vref, but also used as a sensing line for sensing the characteristic value of the driving transistor DRT in the sub-pixel SP, the reference voltage line RVL can be referred to as a sensing line.

[0089] Figure 4 An exemplary circuit structure for sensing a characteristic value of a driving transistor in a display device according to an embodiment of the disclosure is illustrated.

[0090] Referring to Figure 4 The display device 100 according to the embodiment of the disclosure can include a component for compensating for a deviation of a characteristic value of a driving transistor DRT.

[0091] For example, the characteristic value or the difference in the characteristic value of the driving transistor DRT can be reflected to a voltage in the second node N2 of the driving transistor DRT (e.g., Vdata-Vth).

[0092] When the sensing transistor SENT is turned on, the voltage in the second node N2 of the driving transistor DRT can correspond to the voltage in the reference voltage line RVL. Further, by the voltage in the second node N2 of the driving transistor DRT, a line capacitor Cline across the reference voltage line RVL can be charged, and the reference voltage line RVL can have a voltage corresponding to the voltage in the second node N2 of the driving transistor DRT by the sensing voltage Vsen charged in the line capacitor Cline.

[0093] The display device 100 can include an analog-to-digital converter ADC that measures a voltage in a reference voltage line RVL corresponding to a voltage in a second node N2 of the driving transistor DRT and then converts the measured voltage into digital data, and a switch SAM, SPRE for sensing one or more characteristic values of the driving transistor DRT.

[0094] The switch circuit SAM, SPRE for controlling the sensing operation of the characteristic values can include a sensing reference switch SPRE for controlling connection between the reference voltage line RVL and a sensing reference voltage node Npres to which a reference voltage Vref is supplied, and a sampling switch SAM for controlling connection between the reference voltage line RVL and the analog-to-digital converter ADC.

[0095] Here, the sensing reference switch SPRE is a switch for controlling the sensing operation of the characteristic values, and the reference voltage Vref supplied to the reference voltage line RVL through the sensing reference switch SPRE during the sensing operation corresponds to a sensing reference voltage VpreS.

[0096] Further, the switch circuit for sensing the characteristic values of the driving transistor DRT can include a display driving reference switch RPRE. The display driving reference switch RPRE controls connection between the reference voltage line RVL and a display driving reference voltage node Nprer to which a reference voltage Vref is supplied.

[0097] The display driving reference switch RPRE is a switch for controlling a display driving operation. The reference voltage Vref supplied to the reference voltage line RVL through the display driving reference switch RPRE during the display operation corresponds to a display driving reference voltage VpreR.

[0098] The display driving reference switch RPRE and the sensing reference switch SPRE can be provided separately from each other or can be integrated with each other, and thus implemented in a single body. The display driving reference voltage VpreR and the sensing reference voltage VpreS can have the same voltage value or different voltage values.

[0099] The timing controller 140 of the display device 100 can include a memory MEM that stores data supplied from the analog-to-digital converter ADC or one or more reference voltages pre-stored, and a compensation circuit COMP for compensating for a difference in one or more characteristic values by comparing the received data and the reference voltage stored in the memory MEM. In this case, a compensation value calculated by the compensation circuit COMP can be stored in the memory MEM.

[0100] The timing controller 140 can compensate the image data DATA to be supplied to the data driving circuit 130 using the compensation value calculated by the compensation circuit COMP, and then supply the compensated image data DATA_comp to the data driving circuit 130.

[0101] Accordingly, the data driving circuit 130 can convert the compensated image data DATA_comp into a compensated data voltage Vdata_comp in an analog signal form through a digital-to-analog converter DAC, and transmit the compensated data voltage Vdata_comp to a corresponding data line DL through an output buffer BUF. Accordingly, a deviation of one or more characteristic values (a deviation of a threshold voltage or a deviation of a mobility) of the driving transistor DRT in the corresponding sub-pixel SP can be compensated.

[0102] Meanwhile, the data driving circuit 130 can include a data voltage output circuit 136 including a latch circuit, a digital-to-analog converter DAC, an output buffer BUF, etc. In some cases, the data driving circuit 130 can further include an analog-to-digital converter ADC and several types of switches SAM, SPRE, RPRE. In another embodiment, the analog-to-digital converter ADC and several types of switches SAM, SPRE, RPRE can be located outside the data driving circuit 130.

[0103] Further, the compensation circuit COMP can be located outside the timing controller 140 or included inside the timing controller 140. The memory MEM can be located outside the timing controller 140 or implemented in the form of a register inside the timing controller 140.

[0104] The display apparatus 100 according to the embodiment of the disclosure can reduce a driving voltage line disconnection or a display panel burn-in by supplying a high potential voltage in a state in which a defect occurs in the driving voltage line. In particular, the display apparatus 100 according to the embodiment of the disclosure can detect a defect in the driving voltage line before a high potential voltage is supplied to the sub-pixel SP, thereby effectively reducing damage to the display panel due to the high potential voltage.

[0105] Figure 5 An exemplary circuit for detecting a defect in a driving voltage line in a display apparatus according to the embodiment of the disclosure is illustrated.

[0106] Reference Figure 5According to an embodiment of the present disclosure, the display device 100 can include a base voltage switching circuit SW for switching a base voltage EVSS to a ground GND or a floating state, a current detection circuit 310 for detecting a current flowing between the base voltage switching circuit SW and the ground GND, and a timing controller 140 for controlling the base voltage switching circuit SW and determining a defect of a driving voltage line DVL according to a detection result of the current detection circuit 310.

[0107] The base voltage switching circuit SW can be electrically connected to a cathode electrode of the light emitting element ED receiving the sub-pixel driving voltage EVDD through the driving transistor DRT, and can switch a base voltage node N(EVSS) receiving the base voltage EVSS to be electrically connected to the ground GND or the floating state through the timing controller 140. The base voltage switching circuit SW can be composed of a plurality of transistors, or composed of a transistor together with other circuit elements.

[0108] Accordingly, the current detection circuit 310 connected between the base voltage switching circuit SW and the ground GND can detect a current flowing to the ground GND through the base voltage node N(EVSS) in a state in which the base voltage node N(EVSS) is electrically connected to the ground GND or the base voltage node N(EVSS) is electrically floated.

[0109] Accordingly, the current detection circuit 310 detects a current flowing between the sub-pixel driving voltage EVDD and the ground GND through the base voltage node N(EVSS).

[0110] The timing controller 140 controls an operation of the display driving reference switching RPRE to determine when the display driving reference voltage VpreR is supplied through the reference voltage line RVL.

[0111] In addition, the timing controller 140 controls the reference voltage switching circuit SW so that the base voltage node N(EVSS) is electrically connected to the ground GND or is in the electrically floating state.

[0112] In addition, the timing controller 140 determines whether the driving voltage line DVL is defective according to a signal provided from the current detection circuit 310, and generates a defect detection signal BDP when it is determined that the driving voltage line DVL is defective.

[0113] The current detection circuit 310 can be composed of a resistor 312 for sensing a current, an operational amplifier 314, and a level detection circuit 318 for determining a level of the sensed current.

[0114] The resistor 312 can have a low resistance value for sensing a current, and can be connected between the base voltage node N(EVSS) and the ground GND.

[0115] The operational amplifier 314 has an inverting input terminal and a non-inverting input terminal connected to both ends of the resistor 312, such that it generates a voltage proportional to a current flowing from the base voltage node N(EVSS) to the ground (GND) through the resistor 312.

[0116] The level detection circuit 318 generates a high level signal in a case where a signal transmitted from the operational amplifier 314 is equal to or greater than a predetermined reference value, and otherwise generates a low level signal. That is, the level detection circuit 318 functions to transmit a signal to the timing controller 140 indicating a state in which an overcurrent equal to or greater than a predetermined reference value flows through the resistor 312.

[0117] Accordingly, when the timing controller 140 detects an overcurrent greater than or equal to a reference value through the current detection circuit 310 in a case where the base voltage node N(EVSS) is floating, that is, when the current detection circuit 310 transmits a high level signal to the timing controller 140, the timing controller 140 can determine that a defect such as a short occurs in the driving voltage line DVL, and generate a defect detection signal BDP having a high level.

[0118] Of course, transmitting a high level signal to the timing controller 140 when a current detected through the current detection circuit 310 is equal to or greater than a reference value is only one example. According to the configuration of the level detection circuit 318 or the timing controller 140, a low level signal can be transmitted to the timing controller 140 when a current greater than or equal to a reference value is detected through the current detection circuit 310, and a high level signal can be transmitted to the timing controller 140 when a current less than a reference value is detected through the current detection circuit 310.

[0119] Accordingly, before or after shipping the display device 100, a defective part can be replaced or repaired by checking a defect of a specific driving voltage line DVL.

[0120] A specific procedure for determining a defect state of a driving voltage line DVL will be described in more detail according to a connection state of a base voltage node N(EVSS) by using a display driving reference voltage VpreR supplied to the driving voltage line DVL.

[0121] Figure 6 A signal flow diagram in a display device according to an embodiment of the disclosure is shown when a driving voltage line is normal, and Figure 7 An exemplary signal flow diagram of a signal flowing through a sub-pixel in a display device according to an embodiment of the disclosure is shown when a driving voltage line is normal.

[0122] When overcurrent flows in the driving voltage line DVL or the display panel 110 by the sub-pixel driving voltage EVDD having a high potential voltage, the driving voltage line DVL can be disconnected or the display panel 110 can be burned due to the overcurrent.

[0123] Therefore, in order to prevent such a problem, the display device 100 according to the embodiment of the disclosure detects whether the driving voltage line DVL is defective by using the display driving reference voltage VpreR having a low potential voltage in a state in which the sub-pixel driving voltage EVDD is not supplied to the driving voltage line DVL.

[0124] The sub-pixel driving voltage EVDD generally corresponds to a high potential voltage level of 20 V or more, and the display driving reference voltage VpreR corresponds to a low potential voltage level of 3 V.

[0125] Referring to Figure 6 and Figure 7 , the display device 100 according to the embodiment of the disclosure turns on the switching transistor SWT and the sensing transistor SENT by supplying the scanning signal SCAN and the sensing signal SENSE having a high level, so that in a state in which the sub-pixel driving voltage EVDD is not supplied or a low level sub-pixel driving voltage EVDD(low) is supplied, the base voltage node N(EVSS) is electrically floated and the display driving reference voltage VpreR transmitted from the reference voltage line RVL is supplied through the driving voltage line DVL.

[0126] Here, the low level sub-pixel driving voltage EVDD(low) has a lower level than the display driving reference voltage VpreR.

[0127] Therefore, the current I(EVDD) flowing through the reference voltage line RVL by the display driving reference voltage VpreR is transmitted to the second node N2 of the driving transistor DRT through the turned-on sensing transistor SENT.

[0128] Meanwhile, since the switching transistor SWT is turned on by the high level scanning signal SCAN, a data voltage Vdata capable of turning on the driving transistor DRT through the data line DL can be supplied.

[0129] In this case, a period for detecting a defect of the driving voltage line DVL corresponds to a period in which the sub-pixel driving voltage EVDD is not supplied (for example, a blank period) or a period in which the low level sub-pixel driving voltage EVDD(low) is supplied. Therefore, it is preferable that the data voltage Vdata supplied to the driving transistor DRT is set to a level capable of turning on the driving transistor DRT, but is a black data voltage Vdata(black) indicating a black gray scale or a luminance close to a black gray scale.

[0130] At this time, since the low-level sub-pixel driving voltage EVDD(low) is maintained at a level lower than the display driving reference voltage VpreR, when the driving transistor DRT is turned on by the black data voltage Vdata(black), the current I(EVDD) flowing from the reference voltage line RVL flows from the second node N2 to the third node N3 of the driving transistor DRT. That is, in this state, the second node N2 of the driving transistor DRT operates as a drain node, and the third node N3 of the driving transistor DRT operates as a source node.

[0131] Meanwhile, since the base voltage switching circuit SW is in a floating state by the control of the timing controller 140, when the driving voltage line DVL is in the normal state, the current transmitted from the reference voltage line RVL to the driving voltage line DVL does not flow to the base voltage node N(EVSS).

[0132] Therefore, since no current flows into the current detection circuit 310 in the normal state, the current detection circuit 310 generates a low-level signal, and the timing controller 140 generates a low-level defect detection signal BDP(low) indicating that the driving voltage line DVL is in the normal state.

[0133] Therefore, in the case where the sub-pixel driving voltage EVDD having the high potential voltage is not supplied to the driving voltage line DVL, the display driving reference voltage VpreR having the low potential voltage can be used to detect the normal state of the driving voltage line DVL.

[0134] Figure 8 An exemplary signal flow diagram in a display apparatus according to an embodiment of the present disclosure is shown when a driving voltage line is defective, and Figure 9 An exemplary signal flow diagram flowing through a sub-pixel in a display apparatus according to an embodiment of the present disclosure is shown when a driving voltage line is defective.

[0135] Referring to Figure 8 and Figure 9 , the display apparatus 100 according to an embodiment of the present disclosure turns on the switching transistor SWT and the sensing transistor SENT by supplying a scanning signal SCAN and a sensing signal SENSE having a high level, so that the base voltage node N(EVSS) is electrically floated in a state where the sub-pixel driving voltage EVDD is not supplied or a low-level sub-pixel driving voltage EVDD(low) is supplied, and the display driving reference voltage VpreR transmitted from the reference voltage line RVL is supplied through the driving voltage line DVL.

[0136] Therefore, the current I(EVDD) flowing through the reference voltage line RVL due to the display driving reference voltage VpreR is transmitted to the second node N2 of the driving transistor DRT through the turned-on sensing transistor SENT.

[0137] Meanwhile, since the switching transistor SWT is turned on by the high-level scan signal SCAN, a high-level data voltage Vdata capable of turning on the driving transistor DRT through the data line DL can be supplied.

[0138] In this case, the period for detecting the defect of the driving voltage line DVL is a period in which the sub-pixel driving voltage EVDD is not supplied (e.g., a blank period) or a period in which a low-level sub-pixel driving voltage EVDD(low) is supplied. Therefore, it is preferable that the data voltage Vdata supplied to the driving transistor DRT is a level capable of turning on the driving transistor DRT, but is a black data voltage Vdata(black) representing or close to a black gray scale in luminance.

[0139] Since the sub-pixel driving voltage node is maintained at a low level, when the driving transistor DRT is turned on by the black data voltage Vdata(black), the current I(EVDD) transmitted from the reference voltage line RVL flows from the second node N2 to the third node N3 of the driving transistor DRT. That is, in this state, the second node N2 of the driving transistor DRT operates as a drain node, and the third node N3 of the driving transistor DRT operates as a source node.

[0140] Meanwhile, the base voltage switching circuit SWT is in a floating state by the control of the timing controller 140. However, when the driving voltage line DVL is in a short-circuit state due to moisture or foreign substances, the reference voltage line RVL can be electrically connected to the ground GND even though the base voltage switching circuit SWT is in a floating state.

[0141] Therefore, when the driving voltage line DVL is in a defective state, even though the base voltage switching circuit SWT is floating, a part of the current I(EVSS) flowing into the driving voltage line DVL flows to the ground GND through the base voltage node N(EVSS).

[0142] In this case, since the data voltage Vdata(black) of the black gray scale is supplied through the data line DL, even though the light emitting element ED emits light through the driving transistor DRT, the light emitting element ED displays the black gray scale. Therefore, a user cannot recognize the light emitting phenomenon due to the process for detecting the current flowing through the driving voltage line DVL.

[0143] Therefore, when the driving voltage line DVL is in the defective state, the current I(EVSS) flowing into the current detection circuit 310 exists even if the base voltage switching circuit SW is floated, and thus the current detection circuit 310 can detect the current I(EVSS) flowing through the base voltage node N(EVSS).

[0144] At this time, when the detected current is equal to or greater than the reference value, the current detection circuit 310 generates a high-level signal. Therefore, the timing controller 140 generates a defect detection signal BDP(high) having a high level indicating that the driving voltage line DVL is in the defective state.

[0145] Therefore, it is possible to detect the defective state of the driving voltage line DVL using the display driving reference voltage VpreR having a low potential voltage without supplying the sub-pixel driving voltage EVDD having a high potential voltage to the driving voltage line RVL.

[0146] Figure 10 A flowchart of a display driving method according to an embodiment of the disclosure is shown.

[0147] Referring to Figure 10 , the display driving method according to an embodiment of the disclosure can include: a step S100 of maintaining a high potential voltage node at a low level; a step S200 of floating a base voltage node N(EVSS); a step S300 of supplying a display driving reference voltage VpreR to a driving voltage line DVL; a step S400 of detecting a current between the base voltage node N(EVSS) and a ground GND; a step S500 of comparing the detected current with a reference value; a step S600 of generating a defect detection signal BDP(high) having a high level when the detected current is equal to or greater than the reference value; and a step S700 of generating a defect detection signal BDP(low) having a low level when the detected current is less than the reference value.

[0148] The step S100 of maintaining the high potential voltage node at the low level is a process in which the third node N3 of the driving transistor DRT does not receive the sub-pixel driving voltage EVDD having a high potential voltage and is maintained in a low level state.

[0149] The step S200 of floating the base voltage node N(EVSS) is a process of blocking and floating the base voltage node N(EVSS) from the ground GND by controlling the base voltage switching circuit SW.

[0150] At this time, the step S100 of maintaining the sub-pixel driving voltage EVDD at the low level can be different in time from the step S200 of floating the base voltage node N(EVSS), and the order can be changed.

[0151] The step S300 of supplying the display driving reference voltage VpreR to the driving voltage line DVL is a process of supplying the display driving reference voltage VpreR to the reference voltage line RVL by turning on the display driving reference switch RPRE and the sensing transistor SENT, and forming a current path to transmit the current I(EVDD) flowing through the driving voltage line DVL to the sub-pixel driving voltage node by turning on the driving transistor DRT.

[0152] At this time, the driving transistor DRT can be turned on by supplying the data voltage Vdata(black) of the black gray scale to the data line DL.

[0153] The step S400 of detecting the current between the base voltage node N(EVSS) and the ground GND is a process of detecting the current I(EVSS) flowing from the base voltage node N(EVSS) to the ground GND by the current detection circuit 310 connected between the base voltage node N(EVSS) and the ground GND.

[0154] The step S500 of comparing the detected current with the reference value is a process of comparing the detected current in the current detection circuit 310 with the reference value.

[0155] The step S600 of generating the defect detection signal BDP(high) having a high level when the detected current is equal to or greater than the reference value is a process of determining the driving voltage line DVL as a defective state such as a short circuit when the detected current in the current detection circuit 310 is equal to or greater than the reference value in the case where the base voltage node N(EVSS) is floating.

[0156] The step S700 of generating the defect detection signal BDP(low) having a low level when the detected current is less than the reference value is a process of determining the driving voltage line DVL as a normal state when the detected current in the current detection circuit 310 is less than the reference value in the case where the base voltage node N(EVSS) is floating.

[0157] Through the above-described processes, the display device 100 according to the embodiment of the disclosure can detect a defect of the driving voltage line DVL or the display panel 110 before supplying a high potential voltage such as the sub-pixel driving voltage EVDD, and can reduce damage to the display panel 110 due to the high potential voltage by using the display driving reference voltage VpreR.

[0158] The above-described brief explanation of the embodiment of the disclosure is as follows.

[0159] The display device 100 according to the embodiment of the present disclosure can include a display panel 110 in which a plurality of sub-pixels SP having an emission element ED that emits light by a high potential voltage supplied to a driving voltage line DVL and a plurality of reference voltage lines RVL connected to the plurality of sub-pixels SP to detect a characteristic value are disposed, a data driving circuit 130 configured to supply a low potential voltage to the driving voltage line DVL through the plurality of reference voltage lines RVL, a base voltage switching circuit SW configured to control a base voltage node N(EVSS) connected to a cathode electrode of the emission element ED, a current detection circuit 310 configured to detect a current flowing between the base voltage node N(EVSS) and a ground GND, and a timing controller 140 configured to control the base voltage switching circuit SW and to generate a defect detection signal BDP for the driving voltage line DVL according to the current detected by the current detection circuit 310.

[0160] The low potential voltage is supplied to the driving voltage line DVL in a period in which the high potential voltage is not supplied to the driving voltage line DVL.

[0161] The low potential voltage is supplied to the driving voltage line DVL in a period in which the base voltage node N(EVSS) is floated.

[0162] The low potential voltage is a display driving reference voltage VpreR supplied in a display driving period.

[0163] The sub-pixel SP includes a driving transistor DRT of which a third node N3 receives the high potential voltage and which provides a current to the emission element ED through the driving voltage line DVL, a switching transistor SWT electrically connected between a first node N1 of the driving transistor DRT and a data line DL, a sensing transistor SENT electrically connected between a second node N2 of the driving transistor DRT and a reference voltage line RVL, a storage capacitor Cst electrically connected between the first node N1 and the second node N2 of the driving transistor DRT, and the emission element ED electrically connected between the second node N2 of the driving transistor DRT and a base voltage node N(EVSS).

[0164] In the display device 100 according to the embodiment of the present disclosure, a first current path flowing to a third node N3 of a driving transistor DRT through a sensing transistor SENT and the driving transistor DRT is formed by a low potential voltage.

[0165] In the display device 100 according to the embodiment of the present disclosure, when the drive voltage line DVL is defective, a second current path flowing from the base voltage node N(EVSS) to the ground GND is formed.

[0166] The current detection circuit 310 includes a resistor 312 electrically connected between the base voltage node N(EVSS) and the ground GND, an operational amplifier 314 having an inverting input terminal and a non-inverting input terminal connected to both ends of the resistor 312 to generate a voltage proportional to a current flowing through the resistor 312, and a level detection circuit 318 configured to generate a result of comparing an output value from the operational amplifier 314 with a reference value.

[0167] The timing controller 140 is configured to generate a defect detection signal BDP for the drive voltage line DVL according to the output value of the level detection circuit 318.

[0168] A display driving method for driving a display device 100 according to the embodiment of the present disclosure, the display device 100 including a display panel 110 in which a plurality of sub-pixels SP having a light emitting element ED that emits light by a high potential voltage supplied to a drive voltage line DVL and a plurality of reference voltage lines RVL connected to the plurality of sub-pixels SP to detect a characteristic value are provided, the display driving method including: maintaining a high potential voltage node at a low level; floating a base voltage node N(EVSS); supplying a low potential voltage to the drive voltage line DVL; detecting a current between the base voltage node N(EVSS) and the ground GND; comparing the detected current with a reference value; and generating a defect detection signal BDP according to a result of comparing the detected current with the reference value.

[0169] The low potential voltage is supplied through the plurality of reference voltage lines RVL.

[0170] The low potential voltage is supplied in a period in which the high potential voltage is not supplied.

[0171] The low potential voltage is a display driving reference voltage VpreR supplied in a display driving period.

[0172] The sub-pixel SP includes a drive transistor DRT whose third node N3 receives a high potential voltage and which supplies a current to the light emitting element ED through a drive voltage line DVL, a switch transistor SWT electrically connected between a first node N1 of the drive transistor DRT and a data line DL, a sense transistor SENT electrically connected between a second node N2 of the drive transistor DRT and a reference voltage line RVL, a storage capacitor Cst electrically connected between the first node N1 and the second node N2 of the drive transistor DRT, and a light emitting element ED electrically connected between the second node N2 of the drive transistor DRT and a base voltage node N(EVSS).

[0173] In the display driving method according to the embodiment of the disclosure, a first current path flowing to a third node N3 of the drive transistor DRT through the sense transistor SENT and the drive transistor DRT is formed by a low potential voltage.

[0174] In the display driving method according to the embodiment of the disclosure, when the drive voltage line DVL is defective, a second current path flowing from the base voltage node N(EVSS) to the ground GND is formed.

[0175] Generating the defect detection signal BDP includes generating the defect detection signal BDP (high) having a high level when the detected current is equal to or greater than a reference value, and generating the defect detection signal BDP (low) having a low level when the detected current is less than the reference value.

[0176] The above description and drawings merely illustrate the technical idea of the present disclosure for explanatory purposes. Those of ordinary skill in the technical field to which the present disclosure belongs will understand that various modifications and changes, such as combinations, separations, replacements, and changes of configurations, can be made without departing from the essential characteristics of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are intended to illustrate the scope of the technical idea of the present disclosure, and the scope of the present disclosure is not limited by the embodiments. The scope of the present disclosure should be interpreted in such a manner that all technical ideas included in the scope equivalent to the claims belong to the present disclosure based on the appended claims.

Claims

1. A display apparatus comprising: a display panel in which a plurality of sub-pixels and a plurality of reference voltage lines are disposed, the plurality of sub-pixels including a light emitting element that emits light by a high potential voltage supplied to a driving voltage line as a sub-pixel driving voltage, the plurality of reference voltage lines connected to the plurality of sub-pixels to detect a characteristic value; a data driving circuit configured to supply a low potential voltage that is a display driving reference voltage and lower than the high potential voltage to the driving voltage line through the plurality of reference voltage lines; a base voltage switching circuit configured to control a base voltage node connected to a cathode electrode of the light emitting element; a current detection circuit configured to detect a current flowing between the base voltage node and a ground; and a timing controller configured to control the base voltage switching circuit and generate a defect detection signal for the driving voltage line from a current flowing between the base voltage node and the ground detected by the current detection circuit in a period in which the high potential voltage is not supplied to the driving voltage line and the low potential voltage is supplied to the driving voltage line through one of the plurality of reference voltage lines.

2. The display device according to claim 1, wherein The data driving circuit is configured to supply the low potential voltage to the driving voltage line in a period in which the base voltage node is floated.

3. The display device according to claim 1, wherein A sub-pixel of the plurality of sub-pixels includes: a driving transistor whose third node receives the high potential voltage and which provides a current to the light emitting element through the driving voltage line; a switching transistor electrically connected between a first node of the driving transistor and a data line; a sensing transistor electrically connected between a second node of the driving transistor and a corresponding reference voltage line of the plurality of reference voltage lines; and a storage capacitor electrically connected between the first node and the second node of the driving transistor; wherein the light emitting element is electrically connected between the second node of the driving transistor and the base voltage node.

4. The display device according to claim 3, wherein The sub-pixel is configured such that a first current path to the third node of the driving transistor through the sensing transistor and the driving transistor is formed by the low potential voltage.

5. The display device according to claim 1, wherein The sub-pixel is configured such that a second current path from the base voltage node to the ground is formed when the driving voltage line is defective.

6. The display device according to claim 1, wherein The current detection circuit includes: a resistor electrically connected between the base voltage node and the ground; an operational amplifier having an inverting input terminal and a non-inverting input terminal connected to both ends of the resistor to generate a voltage proportional to a current flowing through the resistor; and a level detection circuit configured to generate a result of comparing an output value from the operational amplifier with a reference value.

7. The display device of claim 6, wherein, The timing controller is configured to generate a defect detection signal for the drive voltage line according to an output value of the level detection circuit.

8. A display driving method for driving a display device, the display device including a display panel in which a plurality of sub-pixels and a plurality of reference voltage lines are provided, the plurality of sub-pixels having a light emitting element that emits light by a high potential voltage supplied to a drive voltage line as a sub-pixel drive voltage, the plurality of reference voltage lines being connected to the plurality of sub-pixels to detect a characteristic value, the display driving method comprising: maintaining a high potential voltage node at a level lower than a display driving reference voltage; floating a base voltage node connected to a cathode electrode of the light emitting element; supplying, through one of the plurality of reference voltage lines, a low potential voltage as the display driving reference voltage and lower than the high potential voltage to the drive voltage line without supplying the high potential voltage; detecting a current between the base voltage node and a ground; comparing the detected current with a reference value; and generating a defect detection signal according to a result of comparing the detected current with the reference value.

9. The display driving method according to claim 8, wherein A sub-pixel of the plurality of sub-pixels includes: a drive transistor whose third node receives the high potential voltage, and which supplies a current to the light emitting element through the drive voltage line; a switching transistor electrically connected between a first node of the drive transistor and a data line; a sensing transistor electrically connected between a second node of the drive transistor and a corresponding reference voltage line of the plurality of reference voltage lines; and a storage capacitor electrically connected between the first node and the second node of the drive transistor; wherein the light emitting element is electrically connected between the second node of the drive transistor and the base voltage node.

10. The display driving method according to claim 9, wherein The low potential voltage forms a first current path that flows to the third node of the drive transistor through the sensing transistor and the drive transistor.

11. The display driving method according to claim 8, wherein When the drive voltage line is defective, a second current path is formed that flows from the base voltage node to the ground.

12. The display driving method according to claim 8, wherein The generating a defect detection signal includes: when the detected current is equal to or greater than the reference value, generating a defect detection signal having a high level; and when the detected current is less than the reference value, generating a defect detection signal having a low level lower than the high level.

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