An FPGA prototyping method and device

Abstract

The embodiment of the application provides a FPGA prototype verification method and device, comprising: a system on chip of FPGA receives a target signal sent by an upper computer; the system on chip of FPGA determines the type of the target signal according to the time interval between the target signal and an adjacent signal; if the type of the target signal is a control instruction, the corresponding operation of the control instruction is executed; if the type of the target signal is configuration data, the configuration data is executed according to the previous control instruction of the configuration data; the configuration data is the software code of a chip module to be verified. The system on chip of FPGA can distinguish the control instruction and the configuration data more accurately according to the time interval between the target signal and the adjacent signal, which is convenient for finding problems and making corrections quickly subsequently, and the system on chip of FPGA has a certain expansibility, which is convenient for expanding more control instructions subsequently.

Description

Technical Field

[0001] This invention relates to the field of communication testing technology, and in particular to an FPGA prototype verification method and apparatus. Background Technology

[0002] Because the design process for advanced chips is extremely costly, chip quality largely depends on verification, and one method for chip verification is FPGA prototyping.

[0003] Currently, simulation testing typically involves writing pre-set data and instructions into code, burning it into the FPGA, and if the test result is a failure, the code needs to be readjusted and burned into the FPGA again until the test result is successful. This process is time-consuming and involves complex procedures.

[0004] In summary, how to achieve simple and rapid FPGA prototype verification is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This invention provides an FPGA prototype verification method to solve the problems of excessive time consumption and complex operation steps in the prior art for FPGA prototype verification.

[0006] In a first aspect, embodiments of the present invention provide an FPGA prototype verification method, comprising: an FPGA on-chip system receiving a target signal sent by a host computer; the FPGA on-chip system determining the type of the target signal based on the time interval between the target signal and adjacent signals; if the type of the target signal is a control instruction, then executing the operation corresponding to the control instruction; if the type of the target signal is configuration data, then executing the configuration data according to the preceding control instruction of the configuration data; the configuration data is the software code of the chip module to be verified.

[0007] In this embodiment of the invention, the FPGA's on-chip system can accurately distinguish between control commands and configuration data based on the time interval between the target signal and adjacent signals. This facilitates rapid problem identification and correction. Furthermore, separating control commands and configuration data enables the FPGA's on-chip system to have a certain degree of scalability, allowing for the addition of more control commands in the future.

[0008] Optionally, if the type of the target signal is configuration data, then executing the configuration data according to the preceding control instruction of the configuration data includes: if the preceding control instruction of the configuration data is a pin configuration instruction, then performing pin configuration according to the configuration data.

[0009] Optionally, if the type of the target signal is configuration data, then according to the previous control instruction of the configuration data, the configuration data is executed, including: if the previous control instruction of the configuration data is a burning instruction, then the configuration data is burned to the storage space corresponding to the burning instruction.

[0010] Optionally, the control instruction is an execution instruction; the operation corresponding to the execution of the control instruction includes: executing the configuration data burned into the RAM, and reporting the execution test results to the host computer;

[0011] If there is no configuration data in the RAM, the configuration data burned into the ROM will be executed, and the test results will be reported to the host computer.

[0012] Optionally, the on-chip system of the FPGA determines the type of the target signal based on the time interval between the target signal and adjacent signals, including: if the time interval between the target signal and any adjacent signal is greater than a set threshold, then the target signal is determined to be a control command; if the time interval between the target signal and both the preceding and following adjacent signals is less than a set threshold, then the target signal is determined to be configuration data.

[0013] Optionally, before the FPGA's on-chip system receives the target signal sent by the host computer, the method further includes: the FPGA's on-chip system performing regression testing according to a test script; the test script recording the test steps for each chip to be verified; and using the chips to be verified that fail in the regression test as chips to be verified in subsequent stand-alone tests.

[0014] Optionally, the FPGA's on-chip system performs regression testing according to a test script, including: for any chip to be verified, the FPGA's on-chip system reads the software code of the chip to be verified from a preset folder, programs it into the FPGA and executes the software code of the chip to be verified, and writes the test results of the chip to be verified into the preset folder; wherein, the software code of each chip to be verified is stored in the preset folder, and the test results of each chip to be verified are written into the preset folder.

[0015] Secondly, embodiments of the present invention also provide an FPGA prototype verification device, comprising: an acquisition unit for receiving a target signal sent by a host computer; and a processing unit for the FPGA's on-chip system to determine the type of the target signal based on the time interval between the target signal and adjacent signals; if the type of the target signal is a control instruction, then executing the operation corresponding to the control instruction; if the type of the target signal is configuration data, then executing the configuration data according to the preceding control instruction of the configuration data; wherein the configuration data is the software code of the chip module to be verified.

[0016] Optionally, the processing unit is specifically used to: if the preceding control instruction of the configuration data is a pin configuration instruction, then perform pin configuration according to the configuration data.

[0017] Optionally, the processing unit is specifically used to: if the preceding control instruction for the configuration data is a burning instruction, then burn the configuration data to the storage space corresponding to the burning instruction.

[0018] Optionally, the control instruction is an execution instruction; the processing unit is specifically used to: execute the configuration data burned in RAM and report the execution test results to the host computer; if there is no configuration data in RAM, execute the configuration data burned in ROM and report the execution test results to the host computer.

[0019] Optionally, the processing unit is specifically configured to: determine the target signal as a control command if the time interval between the target signal and any adjacent signal is greater than a set threshold; and determine the target signal as configuration data if the time interval between the target signal and both the preceding and following adjacent signals is less than a set threshold.

[0020] Optionally, the acquisition unit further includes: the FPGA's on-chip system performing regression testing according to a test script; the test script recording test steps for each chip to be verified; and the chip to be verified that fails in the regression test as the chip to be verified in subsequent stand-alone tests.

[0021] Optionally, the acquisition unit further includes: for any chip to be verified, the FPGA's on-chip system reads the software code of the chip to be verified from a preset folder, programs it into the FPGA and executes the software code of the chip to be verified, and writes the test results of the chip to be verified into the preset folder; wherein, the software code of each chip to be verified is stored in the preset folder, and the test results of each chip to be verified are written into the preset folder.

[0022] Thirdly, embodiments of the present invention also provide an electronic device, including at least one processor and at least one memory, wherein the memory stores a computer program, and when the program is executed by the processor, the processor performs the FPGA prototype verification method described in the first aspect above.

[0023] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing a program that, when run on a computer, causes the computer to execute the FPGA prototype verification method described in the first aspect above. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a flowchart of an FPGA prototype verification method provided in an embodiment of the present invention;

[0026] Figure 2 A schematic diagram for identifying the type of target signal;

[0027] Figure 3 A control command correspondence diagram provided for embodiments of the present invention;

[0028] Figure 4 This is a schematic diagram of the structure of an FPGA prototype verification device provided in an embodiment of the present invention;

[0029] Figure 5 This is a schematic diagram of an electronic device structure provided in an embodiment of the present invention. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0031] In one possible scenario, due to the high cost of chip design, verification methods are needed to identify defects and errors in the chip design before mass production. During chip verification, pre-written code is burned into an FPGA for prototype verification, thereby obtaining test results for each chip to be verified. Prototype verification includes regression testing and stand-alone testing. Regression testing is introduced first. Since there are multiple chips to be verified, simulation testing is required for each chip. Therefore, regression testing can be used to verify each chip, obtaining test results for each test module, including success and failure. Chips that fail the test are then identified for stand-alone testing. Stand-alone testing is used to determine which step of the chip fails and to debug the chip until the test result is successful. Therefore, stand-alone testing is necessary for the chips to be verified.

[0032] In one possible scenario, standalone testing of the chip to be verified can be performed. Specifically, this involves programming pre-configured data and instructions into the FPGA. However, since standalone testing inherently requires flexible adjustments to the subsequent steps based on the specific circumstances, the test results after programming into the FPGA must be considered. If the test fails, the data and instructions need to be reconfigured and programmed into the FPGA again until the test succeeds. This process is time-consuming and cumbersome.

[0033] In another possible scenario, one characteristic of simulation testing is that the chip to be verified is first subjected to regression testing, and then targeted single-machine testing is performed on the chip to be verified based on the results of the regression testing. However, since the systems for single-machine testing and regression testing are not unified, there is a possibility that errors may occur during the synchronization of data between regression testing and single-machine testing due to system differences, which in turn leads to a large error in simulation testing.

[0034] In summary, the embodiments of the present invention provide an FPGA prototype verification method to achieve simple, fast and accurate FPGA prototype verification.

[0035] like Figure 1 The diagram shown is a flowchart of an FPGA prototype verification method provided by an embodiment of the present invention. The method includes the following steps:

[0036] Step 101: The FPGA's on-chip system receives the target signal sent by the host computer.

[0037] In this embodiment of the invention, the host computer sends a target signal to the FPGA's on-chip system via a serial port, wherein the type of the target signal includes control instructions and configuration data.

[0038] Step 102: The FPGA's on-chip system determines the type of the target signal based on the time interval between the target signal and adjacent signals.

[0039] In this embodiment of the invention, since the target signals sent from the host computer to the FPGA on-chip system are all 8-bit valid UART communication data signals, the FPGA on-chip system can identify the type of the target signal based on the time interval between receiving adjacent target signals, which facilitates the subsequent execution of corresponding operations based on the type of the target signal.

[0040] Step 103: Determine whether the target signal is a control command. If yes, proceed to step 104; otherwise, proceed to step 105.

[0041] In this embodiment of the invention, for example, the target signal includes a first signal and a second signal. If the first signal and the second signal are adjacent signals, and the time interval between the first signal and the second signal is greater than a set threshold, then the first signal and the second signal are independent signals, and therefore, the first signal and the second signal are control commands. If the time interval between the first signal and the second signal is less than the set threshold, then the first signal and the second signal are continuous signals, and therefore, the first signal and the second signal can be identified as configuration data. See also... Figure 2 .

[0042] Step 104: Execute the operation corresponding to the control command.

[0043] In this embodiment of the invention, the control instructions include execution instructions. If there is configuration data in RAM, the configuration data burned into RAM is executed, and the execution test results are reported to the host computer. If there is no configuration data in RAM, the configuration data burned into ROM is executed, and the execution test results are reported to the host computer.

[0044] Step 105: Execute the configuration data according to the previous control instruction of the configuration data.

[0045] In this embodiment of the invention, the control instructions include pin configuration instructions, programming instructions, etc., which are not limited here. If the preceding control instruction for the configuration data is a pin configuration instruction, then the pins are configured according to the configuration data. If the preceding control instruction for the configuration data is a programming instruction, then the configuration data is programmed into the storage space corresponding to the programming instruction. The configuration data is the software code of the chip module to be verified.

[0046] As can be seen from steps 101 to 105 above, the FPGA's on-chip system can accurately distinguish between control commands and configuration data based on the time interval between the target signal and adjacent signals. This facilitates quick problem identification and correction. Furthermore, separating control commands and configuration data gives the FPGA on-chip system a certain degree of scalability, allowing for the addition of more control commands in the future.

[0047] In this embodiment of the invention, before step 101, the host computer needs to generate a target signal. Specifically, it first needs to associate individual characters with control commands, such as... Figure 3The diagram shown illustrates the control instruction correspondence provided in this embodiment of the invention. The control instructions are used to switch the current operating mode. Specifically, a single character 'a' corresponds to an execution instruction, which has a priority. Specifically, if there is configuration data in RAM, the configuration data burned into RAM is executed, and the test results are reported to the host computer. If there is no configuration data in RAM, the configuration data burned into ROM is executed, and the test results are reported to the host computer. The burning instructions are divided into ROM burning instructions and RAM burning instructions. The single character 's' corresponds to a ROM burning instruction, which can be understood as switching the current operating mode to ROM burning mode. The single character 'f' corresponds to a RAM burning instruction, which can be understood as switching the current operating mode to RAM burning mode. The single character 'd' corresponds to a pin configuration instruction, which can be understood as switching the current operating mode to pin configuration mode. After entering this mode, if the configuration data received next is a string, the pin connections will be configured according to the string's identifier. For example, if the string is 0X01, 0X02…0X0a, then the string identifier is used to configure pin 1 to port 1, pin 2 to port 2, and pin a to port n. A single character 'r' corresponds to switching the current operating mode to reset mode. By inputting a single character on the host computer's keyboard, the corresponding control command can be determined, and then the control command is used to generate the target signal, which is then sent to the FPGA's on-chip system.

[0048] In this embodiment of the invention, for example, if the target signal received by the FPGA's on-chip system at the first moment is a control instruction, then the FPGA's on-chip system executes the operation corresponding to the control instruction. If the target signal received by the FPGA's on-chip system at the second moment is configuration data, then the FPGA's on-chip system identifies the preceding control instruction of the configuration data, and then executes the configuration data. If the target signal received by the FPGA's on-chip system at the third moment is an execution instruction signal, the FPGA's on-chip system determines whether there is configuration data in the RAM according to the execution instruction. If there is, it executes the configuration data burned into the RAM and reports the execution test result to the host computer; if not, it executes the configuration data burned into the ROM and reports the execution test result to the host computer.

[0049] The test results display the outcome of each step described above, including both successful and unsuccessful results. It should be noted that the first time step precedes the second, and the second time step precedes the third.

[0050] In this embodiment of the invention, the FPGA's on-chip system sends the test results to the host computer. In one possible scenario, the test result may be a test failure. Since the test itself involves flexibly changing the subsequent steps based on the current situation to achieve a test success result, the host computer, based on the FPGA's on-chip system's test failure result, switches the control command by inputting a single character on the host computer's keyboard. It then generates an adjusted control command from the switched control command and sends it to the FPGA's on-chip system. The FPGA's on-chip system adjusts the control command according to the adjusted control command. The entire FPGA on-chip system subsequently needs to execute corresponding operations according to control instructions. The FPGA on-chip system receives adjusted configuration data sent from the host computer. The host computer then obtains the execution instruction by inputting a single character, generates an execution instruction signal, and sends it to the FPGA on-chip system. Based on the execution instruction, the FPGA on-chip system checks if configuration data exists in RAM. If it does, it executes the configuration data programmed into RAM and reports the execution result to the host computer. If not, it executes the configuration data programmed into ROM and reports the execution result to the host computer. This process repeats until the test result is successful.

[0051] In this embodiment of the invention, steps 101 to 105 are specific steps of single-machine testing. The chip to be verified mentioned in steps 101 to 105 is the chip to be verified in the single-machine test. Before step 101, it is necessary to find the chip to be verified in the single-machine test from among multiple chips to be verified. The following describes how to determine the chip to be verified in the single-machine test.

[0052] In this embodiment of the invention, since there are multiple chips to be verified requiring prototype verification, regression testing is required before stand-alone testing. Specifically, for any chip to be verified, the FPGA's system-on-a-chip reads the software code of the chip to be verified from a preset folder, programs it onto the FPGA, executes the software code, and writes the test results of the chip to be verified into the preset folder; wherein, the software code of each chip to be verified is stored in a preset folder, and the test results of each chip to be verified are written into a preset folder. The test script records the test steps for each chip to be verified; chips to be verified that fail in regression testing are designated as chips to be verified in subsequent stand-alone testing. In one possible implementation, chips to be verified that fail in testing can be found from the preset folder by searching for keywords, where the keyword is "failure," and then these chips are designated as chips to be verified in stand-alone testing, thereby allowing for faster identification and correction of problems based on stand-alone testing.

[0053] Based on the same technical concept described above, embodiments of the present invention also provide an FPGA prototype verification device, such as... Figure 4 As shown, the device 400 includes: an acquisition unit 401 for receiving a target signal sent by a host computer; and a processing unit 402 for the FPGA's on-chip system to determine the type of the target signal based on the time interval between the target signal and adjacent signals; if the type of the target signal is a control instruction, then the operation corresponding to the control instruction is executed; if the type of the target signal is configuration data, then the configuration data is executed according to the preceding control instruction of the configuration data; the configuration data is the software code of the chip module to be verified.

[0054] Optionally, the processing unit 402 is specifically used to: if the preceding control instruction of the configuration data is a pin configuration instruction, then perform pin configuration according to the configuration data.

[0055] Optionally, the processing unit 402 is specifically used to: if the preceding control instruction for the configuration data is a burning instruction, then burn the configuration data to the storage space corresponding to the burning instruction.

[0056] Optionally, the control instruction is an execution instruction; the processing unit 402 is specifically used to: execute the configuration data burned in RAM and report the execution test results to the host computer; if there is no configuration data in RAM, execute the configuration data burned in ROM and report the execution test results to the host computer.

[0057] Optionally, the processing unit 402 is specifically used to: determine the target signal as a control command if the time interval between the target signal and any adjacent signal is greater than a set threshold; and determine the target signal as configuration data if the time interval between the target signal and both the preceding and following adjacent signals is less than the set threshold.

[0058] Optionally, the acquisition unit 401 further includes: the FPGA on-chip system performing regression testing according to a test script; the test script recording test steps for each chip to be verified; and the chip to be verified that fails in the regression test as the chip to be verified in subsequent stand-alone tests.

[0059] Optionally, the acquisition unit 401 further includes: for any chip to be verified, the on-chip system of the FPGA reads the software code of the chip to be verified from a preset folder, programs it into the FPGA and executes the software code of the chip to be verified, and writes the test results of the chip to be verified into the preset folder; wherein, the software code of each chip to be verified is stored in the preset folder, and the test results of each chip to be verified are written into the preset folder.

[0060] Based on the same technical concept, embodiments of this application also provide an electronic device, such as... Figure 5 As shown, the electronic device 500 includes at least one processor 501 and a memory 502 connected to the at least one processor. In this embodiment, the specific connection medium between the processor 501 and the memory 502 is not limited. Figure 5 Taking the connection between processor 501 and memory 502 via a bus as an example, the bus can be divided into address bus, data bus, control bus, etc.

[0061] In this embodiment of the application, the memory 502 stores instructions that can be executed by at least one processor 501. By executing the instructions stored in the memory 502, at least one processor 501 can perform the steps included in the aforementioned FPGA prototype verification method.

[0062] The processor 501 is the control center of the computing device. It can connect to various parts of the computing device using various interfaces and lines, and performs data processing by running or executing instructions stored in the memory 502 and calling data stored in the memory 502. Optionally, the processor 501 may include one or more processing units. The processor 501 may integrate an application processor and a modem processor. The application processor mainly handles the operating system, user interface, and applications, while the modem processor mainly handles issuing instructions. It is understood that the modem processor may not be integrated into the processor 501. In some embodiments, the processor 501 and the memory 502 may be implemented on the same chip; in some embodiments, they may be implemented on separate chips.

[0063] Processor 501 can be a general-purpose processor, such as a central processing unit (CPU), digital signal processor, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the FPGA prototype verification method embodiments can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0064] Memory 502, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory 502 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic memory, magnetic disk, optical disk, etc. Memory 502 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited thereto. In the embodiments of this application, memory 502 can also be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.

[0065] Based on the same technical concept, embodiments of this application also provide a computer-readable storage medium storing a computer program executable by a computing device, which, when run on the computing device, causes the computing device to perform the steps of the above-described FPGA prototype verification method.

[0066] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0067] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0068] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0069] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0070] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0071] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An FPGA prototype verification method, characterized in that, include: The FPGA's on-chip system receives the target signal sent by the host computer; The FPGA's on-chip system determines the type of the target signal based on the time interval between the target signal and adjacent signals; The FPGA's on-chip system determines the type of the target signal based on the time interval between the target signal and adjacent signals, including: if the time interval between the target signal and any of the adjacent signals is greater than a set threshold, then the target signal is determined to be a control command; If the time interval between the target signal and the adjacent signals before and after it is less than a set threshold, then the target signal is determined to be configuration data. If the target signal is of the type of the control command, then the operation corresponding to the control command is executed; If the type of the target signal is the configuration data, then the configuration data is executed according to the previous control instruction of the configuration data; the configuration data is the software code of the chip module to be verified.

2. The method as described in claim 1, characterized in that, If the type of the target signal is configuration data, then according to the previous control instruction of the configuration data, the configuration data is executed, including: If the preceding control instruction for the configuration data is a pin configuration instruction, then the pin configuration is performed according to the configuration data.

3. The method as described in claim 1, characterized in that, If the type of the target signal is configuration data, then according to the previous control instruction of the configuration data, the configuration data is executed, including: If the preceding control instruction for the configuration data is a burning instruction, then the configuration data will be burned to the storage space corresponding to the burning instruction.

4. The method as described in claim 1, characterized in that, The control command is an execution command; The operation corresponding to executing the control command includes: The system executes the configuration data burned into RAM and reports the test results to the host computer. If there is no configuration data in the RAM, the configuration data burned into the ROM will be executed, and the test results will be reported to the host computer.

5. The method according to any one of claims 1-4, characterized in that, Before the FPGA's on-chip system receives the target signal sent by the host computer, it also includes: The FPGA's on-chip system performs regression testing according to the test script; the test script records the test steps for each chip to be verified. The chips that fail to be verified in the regression test will be used as the chips to be verified in the subsequent single-machine test.

6. The method as described in claim 5, characterized in that, The FPGA's on-chip system undergoes regression testing according to the test script, including: For any chip to be verified, the system-on-chip of the FPGA reads the software code of the chip to be verified from a preset folder, programs it into the FPGA and executes the software code of the chip to be verified, and writes the test results of the chip to be verified into the preset folder; wherein, the software code of each chip to be verified is stored in the preset folder, and the test results of each chip to be verified are written into the preset folder.

7. An FPGA prototype verification device, characterized in that, include: The acquisition unit is used to receive the target signal sent by the host computer; The processing unit is configured to: ...

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method according to any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, It stores a computer program executable by a computer device, which, when run on the computer device, causes the computer device to perform the steps of the method according to any one of claims 1-6.

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