Content addressable memory unit

Abstract

The present invention provides a content addressable memory cell, which includes a plurality of storage circuits and a comparison circuit. A first storage circuit of the plurality of storage circuits is configured to store a data, and a second storage circuit of the plurality of storage circuits is configured to store a status bit. The comparison circuit is configured to determine whether to adjust a level of a match line to a level of one of the data and the status bit in response to levels of a plurality of search bit lines and the other of the data and the status bit.

Description

TECHNICAL FIELD

[0001] The present invention relates to memory devices, and more particularly, to content addressable memory cells having tri-states. BACKGROUND

[0002] Content addressable memories can quickly compare stored data with data to be searched and output a comparison result. In conventional content addressable memories, in order to achieve a don't care state, additional programming is required to be performed on the originally stored data, which will change the originally stored data in the content addressable memory. As a result, the originally stored data cannot be obtained by the digital system, and thus the content addressable memory cannot be applied to applications requiring the use of a don't care state and the access of the originally stored data. SUMMARY

[0003] In some embodiments, a content addressable memory cell includes a plurality of storage circuits and a comparison circuit. A first storage circuit of the storage circuits is configured to store a data, and a second storage circuit of the storage circuits is configured to store a state bit. The comparison circuit is configured to determine whether to adjust a level of a match line to a level of one of the data and the state bit in response to levels of a plurality of search bit lines.

[0004] In some embodiments, a content addressable memory cell includes a plurality of storage circuits, a first switch, a second switch, a third switch, and a fourth switch. A first storage circuit of the storage circuits is configured to store a data, and a second storage circuit of the storage circuits is configured to store a state bit. A first terminal of the first switch is coupled to a match line. A first terminal of the second switch is coupled to the match line. A first terminal of the third switch is coupled to a second terminal of the first switch, and a control terminal of the third switch is coupled to a first search bit line. A first terminal of the fourth switch is coupled to the second terminal of the first switch, and a control terminal of the fourth switch is coupled to a second search bit line. If a first data value of the data is received at a control terminal of the first switch and a second data value of the data is received at a control terminal of the second switch, then a second terminal of the third switch and a second terminal of the fourth switch receive the state bit, or if the control terminal of the first switch and the control terminal of the second switch both receive the state bit, then the second terminal of the third switch receives the second data value and the second terminal of the fourth switch receives the first data value.

[0005] The features, implementations, and effects of the present invention will be described in detail below with reference to the preferred embodiments and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 A schematic diagram of a content addressable memory cell according to some embodiments of the present invention.

[0007] Figure 2 A circuit schematic diagram of a content addressable memory unit according to some embodiments of the present application. Figure 1 A circuit schematic diagram of a content addressable memory unit according to some embodiments of the present application.

[0008] Figure 3 A circuit schematic diagram of a content addressable memory unit according to some embodiments of the present application. Figure 1 A circuit schematic diagram of a content addressable memory unit according to some embodiments of the present application.

[0009] BRIEF DESCRIPTION OF DRAWINGS

[0010] DETAILED DESCRIPTION

[0011] All words used herein are to be interpreted according to their normal meaning. The definitions of the above words in a commonly used dictionary, and the usage examples of any of the words discussed herein included in the summary of the present application, are only examples and should not be used to limit the scope and meaning of the present application. Likewise, the present application is not limited only to the various embodiments shown in this specification.

[0012] As used herein, "coupled" or "connected" can mean either a direct connection between two or more elements, or an indirect connection through one or more intervening elements. As used herein, the term "circuit" can be a device that has at least one transistor and / or at least one passive element connected in a certain manner to process a signal.

[0013] As used herein, the term "and / or" includes any combination of one or more of the associated listed items. In this document, the use of first, second, third, etc., words to describe various elements is only used to distinguish one element from another. Thus, a first element as discussed herein could also be described as a second element without departing from the spirit of the present application. For ease of understanding, like elements in the various drawings will be designated by the same reference numerals.

[0014] Figure 1 A schematic diagram of a content addressable memory (CAM) cell 100 according to some embodiments of the present application.

[0015] The CAM cell 100 includes a storage circuit 110, a storage circuit 120, and a comparison circuit 130. The storage circuit 110 and the storage circuit 120 are coupled to a bit line BLN and a bit line BLP. The storage circuit 110 is used to store a data SD. The data SD can be represented by a data value Dl and a data value D2. For example, if the data value Dl has a logic value of 1 and the data value D2 has a logic value of 0, the data SD represents a bit having a first steady state (e.g., a bit of 1). Alternatively, if the data value Dl has a logic value of 0 and the data value D2 has a logic value of 1, the data SD represents a bit having a second steady state (e.g., a bit of 0), but the present application is not limited thereto.

[0016] The storage circuit 120 is used to store a status bit SC. The status bit SC can be used to indicate an operating state of the CAM cell 100. For example, when the status bit SC has a preset logic value (e.g., a logic value of 1), the CAM cell 100 operates in a don't care state. In this case, the comparison circuit 130 does not adjust the level of the match line ML (i.e., keeps the level of the match line ML unchanged). Alternatively, when the status bit SC has another logic value (e.g., a logic value of 0) different from the preset logic value, the CAM cell 100 operates in a care state. In this case, the comparison circuit 130 can decide whether to adjust the level of the match line ML according to a comparison result between a search data and the data SD to indicate whether the search data is identical to the data SD. In other words, the CAM cell 100 is a ternary CAM cell that can exhibit the first steady state, the second steady state, and the don't care state.

[0017] The comparison circuit 130 is used to decide whether to adjust the level of the match line ML to the level of one of the data SD and the status bit SC and the levels of a plurality of search bit lines SBLP and SBLN in response to the levels of the data SD and the status bit SC and the plurality of search bit lines SBLP and SBLN. In the example described below Figure 2 , the comparison circuit 130 decides whether to adjust the level of the match line ML to the level of the status bit SC in response to the levels of the data SD and the plurality of search bit lines SBLP and SBLN. Alternatively, in the example described below Figure 3 , the comparison circuit 130 decides whether to adjust the level of the match line ML to the level of the data value Dl or the level of the data value D2 in response to the levels of the status bit SC and the plurality of search bit lines SBLP and SBLN.

[0018] The levels of multiple search bit lines SBLP and SBLN can be used to indicate the data to be searched. For example, if search bit line SBLP is at a logic high level and search bit line SBLN is at a logic low level, it means that the data to be searched is bit 1. Alternatively, if search bit line SBLP is at a logic low level and search bit line SBLN is at a logic high level, it means that the data to be searched is bit 0, but this invention is not limited thereto.

[0019] In some embodiments, the comparator circuit 130 may operate as an XOR gate circuit to confirm whether the data SD is the same as the data to be searched. Before starting the data search, the matching line ML is pre-charged to a high level. If the CAM unit 100 operates in the relevant state and the data SD is the same as the data to be searched, the comparator circuit 130 may not adjust the level of the matching line ML (i.e., maintain the level of the matching line ML at a high level) to indicate that the comparison result is a match. Alternatively, if the CAM unit 100 operates in the relevant state and the data SD is different from the data to be searched, the comparator circuit 130 adjusts the level of the matching line ML to a low level to indicate that the comparison result is a mismatch. Detailed operation and setting methods will be referred to later. Figure 2 and Figure 3 illustrate.

[0020] Figure 2 Drawing according to some embodiments of the present invention Figure 1 A circuit diagram of CAM unit 100 is shown below. In this example, each of storage circuits 110 and 120 may be a bit cell implemented by six transistors. Specifically, storage circuit 110 includes multiple transistors T1 to T6. The first terminal (e.g., source / drain) of transistor T1 receives voltage VDD, the second terminal (e.g., drain / source) of transistor T1 is coupled to the first terminal of transistor T2, and the second terminal of transistor T2 is grounded. The first terminal of transistor T3 receives voltage VDD, the second terminal of transistor T3 is coupled to the first terminal of transistor T4, and the second terminal of transistor T4 is grounded. The control terminal (e.g., gate) of transistor T1, the control terminal of transistor T2, the second terminal of transistor T3, and the first terminal of transistor T4 are coupled to node n0d and used to generate data value D1. The control terminal of transistor T3, the control terminal of transistor T4, the second terminal of transistor T1, and the first terminal of transistor T2 are coupled to node n1d and used to generate data value D2.

[0021] By the above arrangement, the transistor T1 and the transistor T2 can form a first inverter circuit, the transistor T3 and the transistor T4 can form a second inverter circuit, and the first inverter circuit and the second inverter circuit can be cross-coupled to form a latch circuit. For example, an output terminal (i.e., the node n1d) of the first inverter circuit is coupled to an input terminal (e.g., the gate of the transistor T3 and the transistor T4) of the second inverter circuit, and an output terminal (i.e., the node n0d) of the second inverter circuit is coupled to an input terminal (e.g., the gate of the transistor T1 and the transistor T2) of the first inverter circuit. In other words, the data value D1 and the data value D2 are outputs of the latch circuit in the storage circuit 110, and the data value D1 and the data value D2 have opposite logic values. For example, if the data value D1 is a logic value 0, then the data value D2 is a logic value 1. Alternatively, if the data value D1 is a logic value 1, then the data value D2 is a logic value 0.

[0022] The first end of the transistor T5 is coupled to the node n1d, the second end of the transistor T5 is coupled to the bit line BLN, and the control end of the transistor T5 is coupled to the word line WLD. The first end of the transistor T6 is coupled to the bit line BLP, the second end of the transistor T6 is coupled to the node n0d, and the control end of the transistor T6 is coupled to the word line WLD. In response to the level of the word line WLD, the transistor T5 and the transistor T6 can be selectively turned on to adjust the level of the bit line BLN according to the level of the node n1d (e.g., the level of the data value D2) and to adjust the level of the bit line BLP according to the level of the node n0d (e.g., the level of the data value D1).

[0023] The storage circuit 120 includes transistors T1’-T6’. The node n0c and the node n1c in the storage circuit 120 correspond to the node n0d and the node n1d in the storage circuit 110, respectively. The arrangement between the transistors T1’-T6’, the word line WLC, the bit line BLN, and the bit line BLP in the storage circuit 120 is similar to the arrangement between the transistors T1-T6, the word line WLD, the bit line BLN, and the bit line BLP in the storage circuit 110, and thus is not repeated here. Similar to the storage circuit 110, the state bit SC is an output (in this example, a signal output from the node n0c) of the latch circuit included in the storage circuit 120.

[0024] In this example, the comparison circuit 130 can determine whether to adjust the level of the match line ML to the level of the state bit SC in response to the data SD (i.e., the data value Dl and the data value D2) and the levels of the plurality of search bit lines SBLN and SBLP. In detail, the comparison circuit 130 includes a plurality of switches MN0-MN3. The first end of the switch MN0 is coupled to the match line ML, the second end of the switch MN0 is coupled to the first end of the switch MNl, and the control end of the switch MN0 receives the data value D2. The switch MN0 is configured to selectively conduct according to the data value D2. The second end of the switch MNl receives the state bit SC, and the control end of the switch MNl is coupled to the search bit line SBLP. The switch MNl is configured to selectively conduct in response to the level of the search bit line SBLP to transmit the state bit SC to the switch MN0. The first end of the switch MN2 is coupled to the match line ML, the second end of the switch MN2 is coupled to the first end of the switch MN3, and the control end of the switch MN2 receives the data value Dl. The switch MN2 is configured to selectively conduct according to the data value Dl. The second end of the switch MN3 receives the state bit SC, and the control end of the switch MN3 is coupled to the search bit line SBLN. The switch MN3 is configured to selectively conduct in response to the level of the search bit line SBLN to transmit the state bit SC to the switch MN2.

[0025] In this example, the truth table of the CAM cell 100 can be represented as follows:

[0026]

[0027] As previously described, when the state bit SC has a predetermined logic value (e.g., logic value 1), the CAM cell 100 operates in the irrelevant state. Since the state bit SC is logic value 1, the logic value 1 corresponds to the same level as the pre-charged level of the match line ML (denoted as 1 in the above table). In this condition, regardless of whether the data SD (or the data to be searched) is bit 1 or bit 0, the plurality of switches MN0-MN3 cannot discharge the match line ML, so the level of the match line ML will not be adjusted. Therefore, the level of the match line ML remains unchanged.

[0028] When the status bit SC has the other logic value opposite to the preset logic value (e.g. logic value 0), the CAM cell 100 operates in the relevant state. In this condition, if the data SD is bit 1 (i.e. data value D1 is logic value 1 and data value D2 is logic value 0) and the search data is bit 1 (i.e. the search bit line SBLP is high (denoted as 1) and the search bit line SBLN is low (denoted as 0)), the switches MN0 and MN3 are not conductive, so that the comparison circuit 130 cannot discharge the match line ML. In this way, the level of the match line ML is maintained to indicate that the comparison result is match (i.e. the data SD is the same as the search data). Alternatively, if the data SD is bit 1 and the search data is bit 0 (i.e. the search bit line SBLP is low and the search bit line SBLN is high), the switches MN0 and MN1 are not conductive and the switches MN2 and MN3 are conductive, so that the comparison circuit 130 can pull down the level of the match line ML to the corresponding level of the status bit SC. In other words, in this condition, the match line ML can be discharged via the switches MN2 and MN3. In this way, the level of the match line ML is adjusted to a low level corresponding to logic value 0 to indicate that the comparison result is mismatch (i.e. the data SD is different from the search data).

[0029] Similarly, if the data SD is bit 0 (i.e. data value D1 is logic value 0 and data value D2 is logic value 1) and the search data is bit 1 (i.e. the search bit line SBLP is high and the search bit line SBLN is low) in the condition that the CAM cell 100 operates in the relevant state, the switches MN2 and MN3 are not conductive and the switches MN0 and MN1 are conductive, so that the comparison circuit 130 can pull down the level of the match line ML to the corresponding level of the status bit SC. In other words, in this condition, the match line ML can be discharged via the switches MN0 and MN1. In this way, the level of the match line ML is adjusted to a low level corresponding to logic value 0 to indicate that the comparison result is mismatch (i.e. the data SD is different from the search data). Alternatively, if the data SD is bit 0 and the search data is bit 0 (i.e. the search bit line SBLP is low and the search bit line SBLN is high), the switches MN0 and MN3 are conductive and the switches MN1 and MN2 are not conductive, so that the comparison circuit 130 cannot discharge the match line ML. In this way, the level of the match line ML is maintained at a high level to indicate that the comparison result is match.

[0030] Figure 3 A circuit schematic diagram of the CAM cell 100 according to some embodiments of the present application is shown in FIG. 1. Compared to the conventional CAM cell 100 shown in FIG. 2, the CAM cell 100 according to some embodiments of the present application has the following advantages: Figure 1 The CAM cell 100 according to some embodiments of the present application has the following advantages: Figure 2In this example, the comparison circuit 130 adjusts the level of the match line ML to the level of the data SD (i.e., the data value Dl or the data value D2) in response to the state bit SC and the levels of the plurality of search bit lines SBLN and SBLP. Figure 3 The connection relationship between the plurality of switches MN0-MN3 and the plurality of storage circuits 110 and 120 in this example is different from Figure 2 the connection relationship in the prior art.

[0031] The connection relationship between the plurality of switches MN0-MN3 and the plurality of storage circuits 110 and 120 in this example is different from Figure 2 In this example, the state bit SC is another output of the latch circuit included in the storage circuit 120 (in this example, the signal outputted from the node nlc). It should be understood that the signal outputted from the node nlc has an opposite logic value from the signal outputted from the node n0c. Therefore, in this example, when the state bit SC has a logic value of 0 (corresponding to a preset logic value), the CAM unit 100 operates in the irrelevant state. Alternatively, when the state bit SC has a logic value of 1, the CAM unit 100 operates in the relevant state.

[0032] In detail, as shown in Figure 2 if the control terminal of the switch MN0 receives the data value D2 and the control terminal of the switch 1 receives the data value Dl, the second terminal of the switch MNl and the second terminal of the switch MN3 receive the state bit SC. Different from Figure 2 as shown in Figure 3 if the control terminal of the switch MN0 and the control terminal of the switch MN2 receive the state bit SC, the second terminal of the switch MNl receives the data value Dl instead, and the second terminal of the switch MN3 receives the data value D2 instead. In other words, in the example of Figure 3 the switches MN0 and MN2 can be selectively turned on according to the state bit SC, the switch MNl can selectively transmit the data value Dl to the switch MN0, and the switch MN3 can selectively transmit the data value D2 to the switch MN2.

[0033] In this example, the truth table of the CAM unit 100 can be represented as follows:

[0034]

[0035] When the state bit SC is a logic value of 0, the CAM unit 100 operates in the irrelevant state. In response to this state bit SC, the switches MN0 and MN2 are not turned on. Under this condition, regardless of whether the data SD (or the data to be searched) is a bit 1 or a bit 0, the comparison circuit 130 cannot discharge the match line ML, so the level of the match line ML will not be adjusted. Therefore, the level of the match line ML remains unchanged.

[0036] When the state bit SC has a logic value of 1, the CAM unit 100 operates in the relevant state. Under this condition, if the data SD is bit 1 (i.e., data value D1 is logic value 1 and data value D2 is logic value 0) and the data to be searched is bit 1 (i.e., search bit line SBLP is high and search bit line SBLN is low), then switches MN0, MN1, and MN2 are turned on, and switch MN3 is turned off. Since data value D1 has a high level corresponding to logic value 1, the matching line ML cannot be discharged through switches MN0 and MN1. In this way, the level of the matching line ML remains unchanged to indicate that the comparison result is a match. Alternatively, if the data SD is bit 1 and the data to be searched is bit 0 (i.e., search bit line SBLP is low and search bit line SBLN is high), then switches MN0, MN2, and MN3 are turned on, and switch MN1 is turned off. Since data value D2 has a low level corresponding to logic value 0, the matching line ML can be discharged through switches MN2 and MN3. In other words, switches MN2 and MN3 can pull the level of the matching line ML low to the level of the data value D2. This adjusts the level of the matching line ML to a low level corresponding to the logic value 0, indicating a mismatch.

[0037] Similarly, when the state bit SC has a logic value of 1, the CAM unit 100 operates in the relevant state. Under this condition, if the data SD is bit 0 (i.e., data value D1 is logic value 0 and data value D2 is logic value 1) and the data to be searched is bit 1 (i.e., search bit line SBLP is high and search bit line SBLN is low), then switches MN0, MN1, and MN2 are turned on, and switch MN3 is turned off. Since the data value D1 has a low level corresponding to logic value 0, the matching line ML can be discharged via switches MN0 and MN1. In other words, switches MN0 and MN1 can pull the level of the matching line ML low to the level of the data value D1. In this way, the level of the matching line ML will be adjusted to a low level corresponding to logic value 0, indicating that the comparison result is a mismatch. Alternatively, if the data SD is bit 0 and the data to be searched is bit 0 (i.e., search bit line SBLP is low and search bit line SBLN is high), then switches MN0, MN2, and MN3 are turned on, and switch MN1 is turned off. Since the data value D2 has a high level corresponding to the logic value 1, the matching line ML will not discharge through switches MN2 and MN3. Therefore, the level of the matching line ML will remain unchanged to indicate that the comparison result is a match.

[0038] based on Figure 2 and Figure 3It can be known that, in some embodiments, the CAM unit 100 can utilize the original operation of the circuit to realize the disassociated state. In other words, the CAM unit 100 can operate in the disassociated state without using an additional compiling mechanism. In this way, the data SC stored in the CAM unit 100 can be prevented from being changed. In addition, the number of transistors included in the CAM unit 100 is the same as that of a general CAM unit, so that the element area does not increase significantly.

[0039] In the above embodiments, the switches MN0-MN3 can be implemented by N-type transistors, but the present application is not limited thereto. In other embodiments, the switches MN0-MN3 can be implemented by P-type transistors, or a combination of P-type and N-type transistors, according to actual requirements.

[0040] In summary, the CAM unit provided in some embodiments of the present application can realize the setting of the disassociated state without using an additional compiling program. In this way, the original data stored in the CAM unit can be maintained.

[0041] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application, and those skilled in the art can make changes to the technical features of the present application according to the content explicitly or implicitly shown in the present application. These changes can all belong to the scope of the patent protection required by the present application, in other words, the scope of the patent protection of the present application should be defined according to the claims of the present application.

Claims

1. A content-addressable memory cell, comprising: A plurality of storage circuits, wherein a first storage circuit of the plurality of storage circuits is used to store a data, and a second storage circuit of the plurality of storage circuits is used to store a status bit; as well as A comparator circuit is used to determine whether to adjust the level of a matching line to the level of the other of the data and the status bits in response to the level of one of the data and the status bits.

2. The content-addressable memory unit according to claim 1, characterized in that, When the status bit is a preset logic value, the comparison circuit does not adjust the level of the matching line.

3. The content-addressable memory unit according to claim 1, characterized in that, When the state bit is a preset logic value, the content-addressable memory cell operates in an irrelevant state.

4. The content-addressable memory unit according to claim 1, characterized in that, The comparison circuit includes: A first switch is configured to be selectively turned on based on a first data value in the data; A second switch is used to selectively conduct according to a second data value in the data; A third switch, configured to selectively conduct in response to the level of a first search bit line among the plurality of search bit lines, to transmit the status bit to the first switch; and A fourth switch is configured to selectively conduct in response to the level of a second search bit line among the plurality of search bit lines, so as to transmit the status bit to the second switch.

5. The content-addressable memory unit according to claim 1, characterized in that, The comparison circuit includes: A first switch is used to selectively turn on according to the state bit; A second switch is used to selectively turn on according to the state bit; A third switch, configured to selectively conduct in response to the level of a first search bit line among the plurality of search bit lines, to transmit a first data value from the data to the first switch; and A fourth switch is configured to selectively conduct in response to the level of a second search bit line among the plurality of search bit lines, so as to transmit a second data value from the data to the second switch.

6. The content-addressable memory cell according to claim 4 or 5, characterized in that, The first storage circuit includes a latch circuit, and the first data value and the second data value are multiple outputs of the latch circuit.

7. The content-addressable memory cell according to claim 4 or 5, characterized in that, The first data value and the second data value have opposite logical values.

8. The content-addressable memory cell according to claim 4 or 5, characterized in that, The second storage circuit includes a latch circuit, and the status bit is an output of the latch circuit.

9. A content-addressable memory cell, comprising: A plurality of storage circuits, wherein a first storage circuit of the plurality of storage circuits is used to store a data, and a second storage circuit of the plurality of storage circuits is used to store a status bit; A first switch, wherein a first terminal of the first switch is coupled to a matching line; A second switch, wherein a first terminal of the second switch is coupled to the mating line; A third switch, wherein a first terminal of the third switch is coupled to a second terminal of the first switch, and a control terminal of the third switch is coupled to a first search bit line; as well as A fourth switch, wherein a first terminal of the fourth switch is coupled to a second terminal of the first switch, and a control terminal of the fourth switch is coupled to a second search bit line. If the control terminal of the first switch receives a first data value from the data and the control terminal of the second switch receives a second data value from the data, then the second terminal of the third switch and the second terminal of the fourth switch receive the status bit; or if the control terminals of the first switch and the second switch both receive the status bit, then the second terminal of the third switch receives the second data value and the second terminal of the fourth switch receives the first data value.

10. The content-addressable memory cell according to claim 9, characterized in that, When the status bit is a preset logic value, the level of the matching line remains unchanged.

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