Light emission control driving circuit and driving method thereof, and driving method of display panel

Abstract

The embodiment of the application discloses a light-emitting control driving circuit and a driving method thereof, and a driving method of a display panel. By controlling input signals of a first input signal group and input signals of a second input signal group, a first output control module is caused to output a first potential signal to a first node in an initial power-on stage, and a second output control module is caused to output a second potential signal to a second node in the initial power-on stage. In the initial power-on stage, the first output module outputs an invalid light-emitting control signal, and the second potential signal is transmitted to an output end of a shift register through the first output module, that is, the shift register outputs an invalid light-emitting control signal in the initial power-on stage. The shift register of the light-emitting control driving circuit can keep stable output, and the voltage amplitude of the output signal of the shift register in the initial power-on stage is not pulled down, thereby improving the flicker phenomenon of the display panel caused by unstable output of the shift register of the light-emitting control driving circuit.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a light-emitting control driving circuit and its driving method, and a driving method for a display panel. Background Technology

[0002] With the development of display technology, users have increasingly higher requirements for display quality.

[0003] The display panel includes a light-emitting control driving circuit and a pixel circuit. The light-emitting control driving circuit is used to generate a light-emitting control signal, which is used to control the conduction state of the light-emitting control transistor in the pixel circuit.

[0004] However, in the existing technology, when entering the display mode from the off screen, the output signal of the light-emitting control driving circuit is unstable, which causes the display panel to flicker. Summary of the Invention

[0005] This invention provides a light-emitting control driving circuit and its driving method, as well as a driving method for a display panel, to improve the screen flickering phenomenon of the display panel.

[0006] In a first aspect, embodiments of the present invention provide a driving method for a light-emitting control driving circuit, the light-emitting control driving circuit including a multi-stage cascaded shift register, the shift register including: a first output module, a second output module, a first output control module and a second output control module;

[0007] The first output control module is used to control the potential of the first node according to the input signal of the first input signal group; the first output module is used to control the output of the invalid light emission control signal according to the potential of the first node;

[0008] The second output control module is used to control the potential of the second node according to the input signal of the second input signal group, and the second output module is used to control the output of the effective light emission control signal according to the potential of the second node.

[0009] The first input signal group and the second input signal group each include at least one input signal;

[0010] The driving methods include:

[0011] By controlling the input signals of the first input signal group and the second input signal group, the first output control module outputs a first potential signal to the first node during the initial power-on phase, and the second output control module outputs a second potential signal to the second node during the initial power-on phase, so that the first output module outputs an invalid light-emitting control signal during the initial power-on phase, and the second output module is turned off during the initial power-on phase.

[0012] The initial power-on phase includes at least the following: the phase from receiving a display command to displaying the first frame of the image when the screen is off, or the phase from receiving a power-on command to displaying the first frame of the image.

[0013] Optionally, the initial power-on phase includes the period between receiving a display command in the screen-off state and entering AOD mode to display the first frame.

[0014] Optionally, the input signals of the first input signal group include a third potential signal, a first clock signal, and a second clock signal; the second clock signal includes the first potential signal.

[0015] The input signals of the second input signal group include a first clock signal and a start signal. The start signal includes a second potential signal. The start signal of the first-stage shift register of the light-emitting control driving circuit includes a start signal. The start signals of the second-stage shift register and its subsequent shift registers of the light-emitting control driving circuit also include the output signal of the previous-stage shift register.

[0016] The first output control module is specifically used to control the transmission of the second clock signal to the first node based on the first clock signal, the second clock signal, and the third potential signal;

[0017] The second output control module is specifically used to control the transmission of the start signal to the second node according to the first clock signal.

[0018] Optionally, by controlling the input signals of the first input signal group and the second input signal group, the first output control module outputs a first potential signal to the first node during the initial power-on phase, and the second output control module outputs a second potential signal to the second node during the initial power-on phase, so that the first output module outputs an invalid light-emitting control signal during the initial power-on phase, and the second output module is turned off during the initial power-on phase, including:

[0019] During the initial power-on phase, an invalid start signal is input to the first-stage shift register, and valid first clock signals and valid second clock signals are input to each stage of the shift register. This causes the first output control module to transmit the second clock signal to the first node based on the first clock signal, the second clock signal, and the third potential signal, thereby causing the first output module to output an invalid light-emitting control signal. Additionally, the second output control module of the first-stage shift register transmits the start signal to the second node based on the first clock signal, and the second output control modules of the second-stage shift register and its subsequent stage shift registers transmit the output signal of the previous stage shift register to the second node based on the first clock signal, thereby turning off the second output module.

[0020] Optionally, the driving method for the light-emitting control driving circuit also includes:

[0021] When the screen is off, the voltage amplitudes of the first clock signal, the second clock signal, and the start signal are all the same as the voltage amplitude of the ground signal.

[0022] Optionally, the driving method for the light-emitting control driving circuit also includes:

[0023] After the initial power-on phase, a first clock signal and a second clock signal, which alternate between high and low levels, are input to the shift register.

[0024] Optionally, the first output control module includes a first output control unit, which includes a first transistor, a second transistor, and a third transistor;

[0025] The gate of the first transistor is connected to the first clock signal, the first terminal of the first transistor is connected to the third potential signal, the third potential signal serves as an effective light emission control signal, the second terminal of the first transistor is connected to the gate of the second transistor, the first terminal of the second transistor is connected to the second clock signal, the second terminal of the second transistor is connected to the first terminal of the third transistor, the gate of the third transistor is connected to the second clock signal, and the second terminal of the third transistor is connected to the first node.

[0026] Optionally, the first output control unit may also include a fourth transistor, the gate of which is connected to a third potential signal.

[0027] Optionally, the second output control module includes a second output control unit, which includes a fifth transistor, wherein the gate of the fifth transistor is connected to a first clock signal, the first terminal of the fifth transistor is connected to a start signal, and the second terminal of the fifth transistor is connected to a second node;

[0028] Optionally, the second output control unit also includes a sixth transistor, the gate of which is connected to a third potential signal, and the fifth transistor is connected to the second node through the sixth transistor;

[0029] Optionally, the first output control unit further includes a seventh transistor, the gate of which is connected to the second terminal of the fifth transistor, the first terminal of the seventh transistor is connected to the first clock signal, and the second terminal of the seventh transistor is connected to the second terminal of the first transistor;

[0030] Optionally, the first output control module further includes a third output control unit, which includes an eighth transistor. The gate of the eighth transistor is connected to the second terminal of the fifth transistor, and the first terminal of the eighth transistor is connected to a fourth potential signal, which serves as an invalid light emission control signal. The second terminal of the eighth transistor is connected to the first node.

[0031] Optionally, the second output control module further includes a fourth output control unit, which includes a ninth transistor and a tenth transistor. The gate of the ninth transistor is connected to the gate of the second transistor, the first terminal of the ninth transistor is connected to a fourth potential signal, the second terminal of the ninth transistor is connected to the first terminal of the tenth transistor, the gate of the tenth transistor is connected to a second clock signal, and the second terminal of the tenth transistor is connected to the second terminal of the fifth transistor.

[0032] Optionally, the fourth output control unit also includes an eleventh transistor, the gate of the ninth transistor is connected to the gate of the second transistor through the eleventh transistor, and the gate of the eleventh transistor is connected to a third potential signal.

[0033] Secondly, embodiments of the present invention also provide a light-emitting control driving circuit, which is driven by the driving method of the light-emitting control driving circuit of the first aspect.

[0034] Thirdly, embodiments of the present invention also provide a driving method for a display panel, the display panel including a light-emitting control driving circuit of the first aspect; the display panel further includes a first clock signal line, a second clock signal line, and a start signal line, the first clock signal line being used to transmit a first clock signal to an odd-level shift register and a second clock signal to an even-level shift register; the second clock signal line being used to transmit a second clock signal to an even-level shift register and a first clock signal to an odd-level shift register; the start signal line being used to transmit a start signal to a first-level shift register; the display panel further includes a pixel circuit, the pixel circuit including an anode power supply signal receiving terminal and a cathode power supply signal receiving terminal; the driving method for the display panel includes:

[0035] During the initial power-on phase, a valid clock signal is provided to the first clock signal line and the second clock signal line, and an invalid start signal is provided to the start signal line. The valid clock signal is the first potential signal, and the invalid start signal is the second potential signal. This causes the first output control module of the shift register of the light-emitting control driving circuit to output the first potential signal to the first node during the initial power-on phase, and causes the second output control module to output the second potential signal to the second node during the initial power-on phase. This causes the first output module to output an invalid light-emitting control signal during the initial power-on phase, and the second output module to be turned off during the initial power-on phase.

[0036] During the initial power-on phase, a voltage less than a set voltage threshold is provided to the anode power signal receiver. Preferably, providing a voltage less than a set voltage threshold to the anode power signal receiver during the initial power-on phase includes:

[0037] During the initial power-on phase, a ground voltage is provided to the anode power signal receiver and the cathode power signal receiver.

[0038] The driving method for the display panel also includes:

[0039] After the initial power-on phase ends, and at the same time or before the first-stage shift register outputs the first potential signal, a first power supply voltage is provided to the anode power supply signal receiver and a second power supply voltage is provided to the cathode power supply signal receiver. The voltage difference between the first power supply voltage and the second power supply voltage is greater than a set voltage threshold.

[0040] Optionally, the voltage threshold can be set to be equal to the turn-on threshold voltage of the light-emitting devices in the display panel.

[0041] The light emission control driving circuit and its driving method, and the driving method for the display panel of this invention, control the input signals of the first input signal group and the second input signal group to cause the first output control module to output a first potential signal to the first node during the initial power-on phase, and cause the second output control module to output a second potential signal to the second node during the initial power-on phase. This causes the first output module to output an invalid light emission control signal during the initial power-on phase, and the second output module to be turned off during the initial power-on phase. This allows the second potential signal to be transmitted to the output terminal of the shift register through the first output module. Even if the shift register outputs an invalid light emission control signal during the initial power-on phase, the shift register of the light emission control driving circuit can maintain a stable output. This prevents the voltage amplitude of the output signal of the shift register from being pulled down during the initial power-on phase, thus improving the flickering phenomenon of the display panel caused by the unstable output of the shift register of the light emission control driving circuit. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of a pixel circuit in the prior art;

[0043] Figure 2 This is a schematic diagram of the structure of a light-emitting control driving circuit provided in an embodiment of the present invention;

[0044] Figure 3 This is a schematic diagram of the structure of a shift register provided in an embodiment of the present invention;

[0045] Figure 4 This is a flowchart of a driving method for a light-emitting control driving circuit provided in an embodiment of the present invention;

[0046] Figure 5 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0047] Figure 6 This is a flowchart of another driving method for a light-emitting control driving circuit according to an embodiment of the present invention;

[0048] Figure 7This is a timing diagram of a shift register provided in an embodiment of the present invention;

[0049] Figure 8 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0050] Figure 9 This is a flowchart of a display panel driving method provided in an embodiment of the present invention. Detailed Implementation

[0051] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0052] As described in the background section, in existing technologies, when entering display mode from a screen-off state, the output signal of the backlight control driving circuit is unstable, causing screen flickering on the display panel. The inventors have discovered that the cause of this problem lies in the fact that existing display panels include a backlight control driving circuit, a scan driving circuit, and pixel circuits. Taking P-type transistors as an example, in existing technologies, the backlight control driving circuit needs to be powered on when entering display mode from a screen-off state. During the initial power-on phase, the output of the shift register in the backlight control driving circuit is floating. The output of the shift register is connected to at least one row of pixel circuits through the backlight control signal line in the display panel, resulting in a large load on the output of the shift register and pulling down its voltage. Since the output of the shift register is typically connected to a high-level signal through an output transistor, the amplitude of the high-level signal connected to the backlight control driving circuit is also pulled down. Furthermore, the high-level signals of the scan driving circuit and the backlight control driving circuit in the display panel are shared; therefore, during the initial power-on phase, the amplitude of the high-level signal output by the scan driving circuit also changes. Figure 1 This is a schematic diagram of a pixel circuit in the prior art. The conduction state of the data writing transistor M1 in the pixel circuit is controlled by the scan signal output by the scan driving circuit. The high-level signal output by the scan driving circuit is pulled low, which reduces the gate-source voltage difference of the data writing transistor M1 during the initial power-on stage. This results in a larger leakage current in the data writing transistor M1. The corresponding black screen data voltage Vdata will reach the source of the driving transistor DT in the pixel circuit through the data writing transistor M1, which pulls up the voltage at the anode power signal receiving end in the pixel circuit. This causes the voltage difference between the anode and cathode of the light-emitting device to be higher than the conduction threshold of the light-emitting device, resulting in the light-emitting device lighting up and the display panel flickering.

[0053] To address the aforementioned problems, embodiments of the present invention provide a driving method for a light-emitting control driving circuit. Figure 2 This is a schematic diagram of a light-emitting control driving circuit provided in an embodiment of the present invention, for reference. Figure 2 The light-emitting control driving circuit includes a multi-stage cascaded shift register 100. Figure 3 This is a schematic diagram of a shift register provided in an embodiment of the present invention, for reference. Figure 3 The shift register includes: a first output module 110, a second output module 120, a first output control module 130, and a second output control module 140; the first output control module 130 is used to control the potential of the first node N1 according to the input signal of the first input signal group INT1; the first output module 110 is used to control the output of the invalid light emission control signal NV according to the potential of the first node N1; the second output control module 140 is used to control the potential of the second node N2 according to the input signal of the second input signal group INT2; and the second output module 120 is used to control the output of the valid light emission control signal EV according to the potential of the second node N2; wherein, the first input signal group INT1 and the second input signal group INT2 each include at least one input signal.

[0054] Specifically, the first output control module 130 may include multiple transistors, and the conduction state of at least some of the transistors is controlled by the input signals of the first input signal group INT1. The first output control module 130 may include multiple input terminals, which are used to connect to the input signals of the first input signal group INT1. The input signals of the first input signal group INT1 include a first potential signal PVGL0, or a periodic signal containing high-low potential transitions of the first potential signal PVGL0. In the periodic signal containing high-low potential transitions, either the high-potential signal or the low-potential signal serves as the first potential signal PVGL0. In this embodiment, the low-potential signal in the periodic signal serves as the first potential signal PVGL0. The first output control module 130 also includes an output terminal, which is connected to the first node N1. Therefore, by controlling the input signals of the first input signal group INT1, the conduction state of at least some of the transistors in the first output control module 130 can be controlled, thereby controlling the output voltage of the first output control module 130's output terminal and achieving control of the potential of the first node N1. Specifically, by controlling the input signal of the first input signal group INT1, the first potential signal PVGL0 can be transmitted to the first node N1 during a certain working phase.

[0055] The second output control module 140 includes multiple transistors, and the conduction state of at least some of these transistors is controlled by the input signals of the second input signal group INT2. The second output control module 140 may include multiple input terminals, which are connected to the input signals of the second input signal group INT2. The input signals of the second input signal group INT2 include a second potential signal PVGH0, or a periodic signal containing high-low potential transitions of the second potential signal PVGH0. In this embodiment, the high potential signal in the periodic signal is used as the second potential signal PVGH0. The second output control module 140 also includes an output terminal, which is connected to the second node N2. Therefore, by controlling the input signals of the second input signal group INT2, the conduction state of at least some of the transistors in the second output control module 140 can be controlled, thereby controlling the output voltage of the second output control module 140 and achieving control of the potential of the second node N2. Specifically, by controlling the input signal of the second input signal group INT2, the second potential signal PVGH0 can be transmitted to the second node N2 during a certain working phase.

[0056] The control terminal of the first output module 110 is connected to the first node N1. The input terminal of the first output module 110 is connected to the invalid light emission control signal NV. The output terminal of the first output module 110 is connected to the output terminal OUT of the shift register. The potential of the first node N1 controls the first output module 110 to output the invalid light emission control signal NV to the output terminal OUT of the shift register. The control terminal of the second output module 120 is connected to the second node N2. The input terminal of the second output module 120 is connected to the valid light emission control signal EV. The output terminal of the second output module 120 is connected to the output terminal OUT of the shift register. The potential of the second node N2 controls the second output module 120 to output the valid light emission control signal EV to the output terminal OUT of the shift register.

[0057] Specifically, the first output module 110 may include a first output transistor TO1. The gate of the first output transistor TO1 is connected to the first node N1, the first terminal of the first output transistor TO1 is connected to an invalid light emission control signal NV, and the second terminal of the first output transistor TO1 is connected to the output terminal of a shift register. The first output transistor TO1 can be turned on or off according to the potential of the first node N1, thereby controlling the output of the invalid light emission control signal NV to the output terminal of the shift register. When the first output transistor TO1 is on, the output terminal of the shift register outputs the invalid light emission control signal NV to the pixel circuit in the display panel, specifically to the light emission control transistor in the pixel circuit, causing the light emission control transistor to turn off. For example, when the light emission control transistor is a P-type transistor, the invalid light emission control signal NV is a high-level signal.

[0058] The second output module 120 may include a second output transistor TO2. The gate of the second output transistor TO2 is connected to the second node N2. The first terminal of the second output transistor TO2 is connected to an effective light-emitting control signal EV. The second terminal of the second output transistor TO2 is connected to the output terminal of a shift register. The second output transistor TO2 can be turned on or off according to the potential of the second node N2. When the second output transistor TO2 is turned on, the output terminal of the shift register outputs the effective light-emitting control signal EV to the pixel circuit in the display panel, specifically to the light-emitting control transistor in the pixel circuit, thus turning on the light-emitting control transistor. For example, when the light-emitting control transistor is a P-type transistor, the effective light-emitting control signal EV is a low-potential signal.

[0059] Figure 4 This is a flowchart of a driving method for a light-emitting control driving circuit provided in an embodiment of the present invention, see reference. Figure 4 The driving methods for the light-emitting control driving circuit include:

[0060] Step 210: By controlling the input signals of the first input signal group and the second input signal group, the first output control module outputs a first potential signal to the first node during the initial power-on phase, and the second output control module outputs a second potential signal to the second node during the initial power-on phase, so that the first output module outputs an invalid light-emitting control signal during the initial power-on phase, and the second output module is turned off during the initial power-on phase.

[0061] Specifically, in this embodiment, the driver chip controls the potentials of the first node N1 and the second node N2 by controlling the input signals of the first input signal group INT1 and the second input signal group INT2. Specifically, the input signals included in the first input signal group INT1 and the second input signal group INT2 are both output by the driver chip. In this embodiment, the driver chip outputs at least one signal to the first output control module 130 (i.e., the input signal included in the first input signal group INT1 of the first output control module 130) and at least one signal to the second output control module 140 (i.e., the input signal included in the second input signal group INT2 of the second output control module 140). In the initial power-on phase, by controlling the high and low potential states of the input signals to the first output control module 130 and the second output control module 140, that is, controlling the high and low potential states of the input signals included in the first input signal group INT1 of the first output control module 130 and the high and low potential states of the input signals included in the second input signal group INT2 of the second output control module 140, the first output control module 130 outputs a first potential signal PVGL0 to the first node N1 in the initial power-on phase, and the second output control module 140 outputs a second potential signal PVGH0 to the second node N2 in the initial power-on phase. Taking the first output transistor TO1 of the first output module 110 and the second output transistor TO2 of the second output module 120 as P-type transistors as an example, the first potential signal PVGL0 is a low potential signal, and the second potential signal PVGH0 is a high potential signal. The first output transistor TO1 of the first output module 110 is turned on according to the first potential signal PVGL0 of the first node N1, and the second output transistor TO2 of the second output module 120 is turned off according to the second potential signal PVGH0 of the second node N2. This allows the invalid potential signal NV to be transmitted to the output terminal OUT of the shift register through the first output transistor TO1. This ensures that the shift register outputs an invalid light-emitting control signal during the initial power-on stage, and the shift register of the light-emitting control driving circuit can maintain a stable output. Consequently, the voltage amplitude of the output signal of the shift register is not pulled down during the initial power-on stage, thus improving the flickering of the display panel caused by the unstable output of the shift register of the light-emitting control driving circuit during the initial power-on stage. In this embodiment, the initial power-on phase includes at least the phase between receiving a display command and displaying the first frame in the screen-off state, or the phase between receiving a power-on command and displaying the first frame. Through the driving method of the light-emitting control driving circuit in this embodiment, the flickering phenomenon of the display panel can be improved during the phase between receiving a display command and displaying the first frame in the screen-off state, or the phase between receiving a power-on command and displaying the first frame.

[0062] The driving method of the light emission control driving circuit in this embodiment of the invention controls the input signals of the first input signal group and the second input signal group to cause the first output control module to output a first potential signal to the first node during the initial power-on phase, and to cause the second output control module to output a second potential signal to the second node during the initial power-on phase. This causes the first output module to output an invalid light emission control signal during the initial power-on phase, and the second output module to be turned off during the initial power-on phase. This allows the second potential signal to be transmitted to the output terminal of the shift register through the first output module. Even if the shift register outputs an invalid light emission control signal during the initial power-on phase, the shift register of the light emission control driving circuit can maintain a stable output. This prevents the voltage amplitude of the output signal of the shift register from being pulled down during the initial power-on phase, thus improving the flickering of the display panel caused by the unstable output of the shift register of the light emission control driving circuit.

[0063] Based on the above technical solution, optionally, the initial power-on phase includes the phase between receiving the display command in the screen-off state and entering AOD (Always On Display) mode to display the first frame.

[0064] AOD (Always-On Display) mode is a feature that allows mobile phones to display useful thumbnail information, minimizing basic information such as clock, calendar, notifications, and call logs even when the phone screen is off. Specifically, the inventors' experiments revealed that screen flickering is common when transitioning from a screen-off to AOD mode. This embodiment addresses this flickering issue by including a phase between the initial power-on stage and the display of the first frame in AOD mode.

[0065] Figure 5 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, see reference. Figure 5The input signals of the first output control module 130 include a third potential signal PVGL1, a first clock signal ECK1, and a second clock signal ECK2. The second clock signal ECK2 includes the first potential signal, wherein the low potential signal in the second clock signal ECK2 serves as the first potential signal. The third potential signal PVGL1 serves as the effective light emission control signal EV. That is, the input signals of the first input signal group INT1 include the third potential signal PVGL1, the first clock signal ECK1, and the second clock signal ECK2. The input signals of the second output control module 140 include a first clock signal ECK1 and a start signal EIN. The start signal includes a second potential signal, that is, the input signals of the second input signal group INT2 include the first clock signal ECK1 and the start signal EIN. The start signal EIN of the first-stage shift register of the light-emitting control driving circuit includes a start signal, and the start signal EIN of the second-stage shift register and its subsequent shift registers of the light-emitting control driving circuit includes the output signal of the previous stage shift register. The first output control module 130 is specifically used to control the transmission of the second clock signal ECK2 to the first node N1 according to the first clock signal ECK1, the second clock signal ECK2, and the third potential signal PVGL1. The second output control module 140 is specifically used to control the transmission of the start signal EIN to the second node N2 according to the first clock signal ECK1. Among them, the third potential signal PVGL1 is an opposite potential signal to the second potential signal, for example, the third potential signal is a low potential signal and the second potential signal is a high potential signal. The third potential signal PVGL1 is the same potential signal as the first potential signal, for example, both are low potential signals. However, the voltage amplitude of the third potential signal and the first potential signal may be equal or unequal.

[0066] Specifically, when the magnitudes of the first clock signal ECK1 and the second clock signal ECK2 in the first input signal group INT1 are both valid potential signals (e.g., when the magnitudes of the first clock signal ECK1 and the second clock signal ECK2 are both equal to the magnitude of the first potential signal), the first output control module 130 transmits the second clock signal ECK2 to the first node N1 based on the first clock signal ECK1, the second clock signal ECK2, and the third potential signal PVGL1. The first potential signal of the first node N1 is a valid potential signal, causing the first output transistor TO1 in the first output module 110 to conduct, thereby transmitting the invalid light-emitting control signal NV to the output of the shift register. When the first clock signal ECK1 in the second input signal group INT2 is a valid potential signal (e.g., when the first clock signal ECK1 is equal to the magnitude of the first potential signal), the second output control module 140 transmits the start signal EIN to the second node N2 of the first-stage shift register based on the first clock signal ECK1. The start signal EIN connected to the first-stage shift register is the initial signal; therefore, when the first clock signal ECK1 is a valid potential signal, the first-stage shift register can transmit the initial signal to the second node N2. For the second-stage shift register and its successor shift register, the start signal EIN is the output signal of the previous stage shift register. Therefore, when the first clock signal ECK1 is an effective potential signal, the second-stage shift register and its successor shift register can transmit the output signal of the previous stage to their own second node N2, so that the second transistor T2 of the second output module 120 can be turned on or off according to the potential of the second node N2.

[0067] Figure 6 This is a flowchart of another driving method for a light-emitting control driving circuit according to an embodiment of the present invention, see reference. Figure 6 Optionally, the driving method for the light-emitting control driving circuit includes:

[0068] Step 310: During the initial power-on phase, an invalid start signal is input to the first-stage shift register, and valid first clock signals and valid second clock signals are input to each stage of the shift register. This causes the first output control module to transmit the second clock signal to the first node based on the first clock signal, the second clock signal, and the third potential signal, thereby causing the first output module to output an invalid light-emitting control signal. Additionally, the second output control module of the first-stage shift register transmits the start signal to the second node based on the first clock signal, and the second output control modules of the second-stage shift register and its successors transmit the output signal of the previous stage shift register to the second node based on the first clock signal, thereby turning off the second output module.

[0069] For details, please refer to Figure 5During the initial power-on phase, a valid first clock signal ECK1 and a valid second clock signal ECK2 are input to the first-stage shift register. This causes the first output control module 130 to transmit the second clock signal ECK2 to the first node N1 based on the first clock signal ECK1, the second clock signal ECK2, and the third potential signal PVGL1. This turns on the first output transistor TO1 in the first output module 110, enabling the transmission of the second potential signal PVGH to the output of the shift register. Conversely, during the initial power-on phase, an invalid start signal is input to the first-stage shift register. The second output control module 140 transmits the invalid start signal to the second node N2 of the first-stage shift register based on the valid first clock signal ECK1, causing the second output transistor TO2 of the second output module 120 to turn off. In other words, the first-stage shift register outputs an invalid light-emitting control signal NV based on the valid first clock signal ECK1, the valid second clock signal ECK2, and the invalid start signal.

[0070] During the initial power-on phase, a valid first clock signal ECK1 and a valid second clock signal ECK2 are input to the first-stage shift register. This causes the first output control module 130 to transmit the second clock signal ECK2 to the first node N1 based on the first clock signal ECK1, the second clock signal ECK2, and the third potential signal PVGL1. During the initial power-on phase, the second clock signal ECK2 is the first potential signal, i.e., the valid potential signal, which turns on the first output transistor TO1 in the first output module 110, thereby transmitting the invalid light-emitting control signal NV to the output of the shift register. Furthermore, since the first-stage shift register outputs the invalid light-emitting control signal NV during the initial power-on phase, the second output control module 140 of the second-stage shift register transmits the invalid light-emitting control signal to the second node N2 of the second-stage shift register based on the valid first clock signal ECK1, causing the second output transistor TO2 of the second output module 120 of the second-stage shift register to turn off. That is, the second-stage shift register outputs an invalid light-emitting control signal NV based on the valid first clock signal ECK1, the valid second clock signal ECK2, and the invalid light-emitting control signal NV output by the first-stage shift register. Similarly, during the initial power-on phase, the subsequent shift registers of the second-stage shift register all output invalid light-emitting control signals NV, so that during the initial power-on phase, the shift register of the light-emitting control driving circuit can maintain a stable output of the invalid light-emitting control signal NV. This prevents the voltage amplitude of the output signal of the shift register from being pulled down during the initial power-on phase, thus improving the flickering of the display panel caused by the unstable output of the shift register of the light-emitting control driving circuit during the initial power-on phase.

[0071] Continue to refer to Figure 5Optionally, the first output control module 130 includes a first output control unit 131, which includes a first transistor T1, a second transistor T2, and a third transistor T3.

[0072] The gate of the first transistor T1 is connected to the first clock signal ECK1, and the first terminal of the first transistor T1 is connected to the third potential signal PVGL1. The third potential signal PVGL1 serves as the effective light emission control signal EV. The second terminal of the first transistor T1 is connected to the gate of the second transistor T2, and the first terminal of the second transistor T2 is connected to the second clock signal ECK2. The second terminal of the second transistor T2 is connected to the first terminal of the third transistor T3, and the gate of the third transistor T3 is connected to the second clock signal ECK2. The second terminal of the third transistor T3 is connected to the first node N1.

[0073] Specifically, when the first clock signal ECK1 is a valid potential signal, the first transistor T1 is turned on, transmitting the third potential signal PVGL1 to the gate of the second transistor T2, causing the second transistor T2 to turn on and transmit the second clock signal ECK2 to the first terminal of the third transistor T3. When the second clock signal ECK2 is a valid potential signal, the third transistor T3 is turned on, transmitting the second clock signal ECK2 to the first node N1, thereby controlling the conduction state of the first output module 110.

[0074] Optionally, the first output control unit 131 further includes a fourth transistor T4, the gate of which is connected to a third potential signal PVGL1.

[0075] Optionally, the second output control module 140 includes a second output control unit 141, which includes a fifth transistor T5, wherein the gate of the fifth transistor T5 is connected to the first clock signal ECK1, the first terminal of the fifth transistor T5 is connected to the start signal EIN, and the second terminal of the fifth transistor T5 is connected to the second node N2.

[0076] Specifically, when the first clock signal ECK1 is a valid potential signal, the fifth transistor T5 is turned on, transmitting the start signal EIN to the second node N2, thereby controlling the conduction state of the second output module 120.

[0077] Optionally, the second output control unit 141 further includes a sixth transistor T6, the gate of which is connected to a third potential signal PVGL1, and the fifth transistor T5 is connected to the second node N2 through the sixth transistor T6.

[0078] Based on the above technical solution, optionally, the first output control unit 131 further includes a seventh transistor T7, the gate of the seventh transistor T7 is connected to the second terminal of the fifth transistor T5, the first terminal of the seventh transistor T7 is connected to the first clock signal ECK1, and the second terminal of the seventh transistor T7 is connected to the second terminal of the first transistor T1.

[0079] Specifically, the seventh transistor T7 can be turned on or off according to the potential signal transmitted to its gate by the fifth transistor T5. When it is turned on, it transmits the first clock signal ECK1 to the second terminal of the first transistor T1, thereby controlling the conduction state of the second transistor T2 and thus controlling the potential of the first node N1.

[0080] Optionally, the first output control module 130 further includes a third output control unit 132. The third output control unit 132 includes an eighth transistor T8. The gate of the eighth transistor T8 is connected to the second terminal of the fifth transistor T5. The first terminal of the eighth transistor T8 is connected to a fourth potential signal PVGH1. The fourth potential signal PVGH1 serves as an invalid light emission control signal NV. The second terminal of the eighth transistor T8 is connected to the first node N1.

[0081] Specifically, the eighth transistor T8 can be turned on or off according to the potential signal transmitted to the gate of the eighth transistor T8 by the fifth transistor T5, and when it is turned on, it transmits the fourth potential signal PVGH1 to the first node N1.

[0082] Optionally, the second output control module 140 further includes a fourth output control unit 142, which includes a ninth transistor T9 and a tenth transistor T10. The gate of the ninth transistor T9 is connected to the gate of the second transistor T2. The first terminal of the ninth transistor T9 is connected to a fourth potential signal PVGH1. The second terminal of the ninth transistor T9 is connected to the first terminal of the tenth transistor T10. The gate of the tenth transistor T10 is connected to a second clock signal ECK2. The second terminal of the tenth transistor T10 is connected to the second terminal of the fifth transistor T5.

[0083] Specifically, the gate of the ninth transistor T9 is connected to the gate of the second transistor T2, and its gate potential signal is equal to the potential signal transmitted by the first transistor T1. When the ninth transistor T9 is turned on according to its own gate potential signal, it transmits the fourth potential signal PVGH1 to the first terminal of the tenth transistor T10. The gate of the tenth transistor T10 is connected to the second clock signal ECK2. When the second clock signal ECK2 is a valid potential signal, the tenth transistor T10 is turned on and transmits the signal transmitted by the ninth transistor T9 to the second terminal of the fifth transistor T5, and then to the second node N2.

[0084] Optionally, the fourth output control unit 142 further includes an eleventh transistor T11, the gate of the ninth transistor T9 is connected to the gate of the second transistor T2 through the eleventh transistor T11, and the gate of the eleventh transistor T11 is connected to the third potential signal PVGL1.

[0085] Continue to refer to Figure 5 The shift register also includes a first capacitor C1, a second capacitor C2, and a third capacitor C3. One end of the first capacitor C1 is connected to the gate of the second transistor T2, and the other end is connected to the second terminal of the second transistor T2. One end of the second capacitor C2 is connected to the second clock signal ECK2, and the other end is connected to the second node N2. One end of the third capacitor C3 is connected between the gate and source of the first output transistor TO1.

[0086] Figure 7 This is a timing diagram of a shift register provided in an embodiment of the present invention. The timing diagram can be... Figure 5 The timing diagram of the shift register shown is for reference. Figure 5 and Figure 7 Taking a shift register where all transistors are P-type transistors as an example, and PVGL1 being a low-level signal for the first and third potential signals, and PVGH1 being a high-level signal for the second and fourth potential signals, as an example, the operation of the shift register includes the screen-off phase t1, the power-on initial phase t2, and the display driving phase t3.

[0087] In the initial power-on phase t2, the first clock signal ECK1 and the second clock signal ECK2 are low-level signals, and the start signal EIN is a high-level signal (the high-level start signal is the second-level signal). The first transistor T1 turns on in response to the low-level gate of the first clock signal ECK1, transmitting the third-level signal PVGL1 (low-level signal) to the gate of the second transistor T2 through the fourth transistor T4, thus turning on the second transistor T2. The third transistor T3 turns on in response to the low-level second clock signal ECK2, allowing the low-level second clock signal ECK2 (the low-level second clock signal is the first-level signal) to be transmitted to the first node N1 through the second transistor T2 and the third transistor T3. The first output transistor TO1 turns on in response to the low-level signal of the first node N1, transmitting the fourth-level signal PVGH1 (high-level signal) to the output of the shift register; this fourth-level signal PVGH1 serves as the invalid light-emitting control signal NV.

[0088] Meanwhile, during the initial power-on phase t2, the fifth transistor T5 turns on in response to the low-level first clock signal ECK1, and the high-level start signal EIN is transmitted to the second node N2 through the fifth transistor T5 and the normally open sixth transistor T6, causing the second output transistor TO2 to turn off.

[0089] During the initial power-on phase t2, the third potential signal PVGL1 is also transmitted to the gate of the ninth transistor T9 through the first transistor T1, the fourth transistor T4, and the eleventh transistor T11, causing the ninth transistor T9 to turn on. The tenth transistor T10 will also turn on in response to the low-potential second clock signal ECK2, causing the fourth potential signal PVGH1 to be transmitted to the second node N2 through the ninth transistor T9, the tenth transistor T10, and the normally open sixth transistor T6. The seventh transistor T7 and the eighth transistor T8 turn off in response to the high potential of the second terminal of the tenth transistor T10.

[0090] The above analysis shows that during the initial power-on phase t2, the shift register can output a stable high-level signal, i.e., an invalid light-emitting control signal, which can improve the flickering phenomenon of the display panel.

[0091] Combination Figure 7 Optionally, the driving method of the light emission control driving circuit further includes: step 301, when the screen is off, controlling the voltage amplitude of the first clock signal, the second clock signal, and the start signal to be the voltage amplitude of the ground signal; thereby saving the power consumption of the display panel while ensuring the screen is off.

[0092] Continue to refer to Figure 5 and Figure 7 During the screen-off phase t1, the voltage amplitudes of the first clock signal ECK1, the second clock signal ECK2, and the start signal STV are all the voltage amplitudes of the ground signal. The potentials of each internal node in the shift register, including the first node and the second node, are floating, and the output of the shift register is floating.

[0093] Optionally, the driving method for the light-emitting control driving circuit further includes: step 320, after the power-on initial stage ends, inputting a first clock signal and a second clock signal that alternate between high and low levels into the shift register. The first clock signal ECK1 and the second clock signal ECK2 have the same period, and the pulse durations of the effective potential signals of the first clock signal ECK1 and the second clock signal ECK2 are equal, as are the pulse durations of the ineffective potential signals, and the effective potentials of the first clock signal ECK1 and the second clock signal ECK2 do not overlap.

[0094] Continue to refer to Figure 7 In the display driving phase t3, following the initial power-on phase, a first clock signal ECK1 and a second clock signal ECK2, alternating between high and low levels, are input to the shift register to prepare for the normal display of the image on the display panel. Specifically, during the display driving phase, the shift register can output valid light-emitting control signals to drive the display panel to display the image.

[0095] Combination Figure 5and Figure 7 The third potential signal PVGL1 (i.e., the effective light emission control signal EV) needs to be output through the second output transistor TO2. The gate potential of the second output transistor TO2 is mainly controlled by the start signal EIN through the fifth transistor T5 and the sixth transistor T6. Therefore, in the display driving stage t3, by controlling the potential of the start signal EIN, specifically by controlling the potential of the start signal STV output to the first-stage shift register, the third potential signal PVGL1 output by the first-stage shift register can be controlled. Since the output signal of the first-stage shift register serves as the start signal EIN of the second-stage shift register, and in the two adjacent shift registers, the output signal of the previous stage serves as the start signal EIN of the next stage shift register, the output control of the third potential signal PVGL1 of each stage shift register can be realized, that is, the control of the output of the effective light emission control signal of each stage shift register can be realized, thereby driving the display panel to display.

[0096] refer to Figure 5 and Figure 7 After adjusting the start signal STV to a low potential, the shift register can output a low potential signal, that is, the shift register can realize an effective light emission control signal, which in turn enables the light emission control transistor in the pixel circuit to conduct according to the effective light emission control signal, driving the driving current generated by the transistor to flow through the light emission device, causing the light emission device to emit light, and the display panel to display the image.

[0097] This invention also provides a light-emitting control driving circuit, the structural schematic of which can be found in the following embodiment: Figure 2 The light emission control driving circuit can be driven by the driving method of the light emission control driving circuit in any of the above embodiments.

[0098] This invention also provides a method for driving a display panel. Figure 8 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, for reference. Figure 8 The display panel includes the light-emitting control driving circuit of the above embodiment; the display panel also includes a first clock signal line CK1, a second clock signal line CK2, and a start signal line ETV. The first clock signal line CK1 is used to transmit a first clock signal to the odd-level shift register and a second clock signal to the even-level shift register; the second clock signal line CK2 is used to transmit a second clock signal to the even-level shift register and a first clock signal to the odd-level shift register; the start signal line is used to transmit a start signal to the first-level shift register; the display panel also includes a pixel circuit (the pixel circuit can be any pixel circuit in the prior art), combined with... Figure 1The pixel circuit includes an anode power signal receiver VDD, a cathode power signal receiver VSS, and light-emitting control transistors (first light-emitting control transistor M2 and second light-emitting control transistor M3). The display panel also includes multiple light-emitting control signal lines Emit, wherein the output of the shift register of the light-emitting control driving circuit can be connected to the gate of the light-emitting control transistor in at least one row of pixel circuits through the light-emitting control signal lines Emit.

[0099] Figure 9 This is a flowchart of a display panel driving method provided in an embodiment of the present invention, see reference. Figure 9 The driving methods for the display panel include:

[0100] Step 410: In the initial power-on phase, provide a valid clock signal to the first clock signal line and the second clock signal line, and provide an invalid start signal to the start signal line. The valid clock signal is the first potential signal, and the invalid start signal is the second potential signal. This causes the first output control module of the shift register of the light-emitting control driving circuit to output the first potential signal to the first node in the initial power-on phase, and causes the second output control module to output the second potential signal to the second node in the initial power-on phase. This causes the first output module to output an invalid light-emitting control signal in the initial power-on phase, and the second output module to be turned off in the initial power-on phase.

[0101] In this shift register, the first potential signal is the valid potential signal, and the second potential signal is the invalid potential signal. When the gate of the transistor in the shift register is at the first potential signal, the transistor is turned on; when the gate of the shift register is at the second potential signal, the transistor is turned off. The first potential signal output by the shift register is a valid light-emitting control signal, and the second potential signal output by the shift register is an invalid light-emitting control signal. When a valid light-emitting control signal is output to the gate of the light-emitting control transistor in the pixel circuit, the light-emitting control transistor is turned on; when an invalid light-emitting control signal is output to the gate of the light-emitting control transistor in the pixel circuit, the light-emitting control transistor is turned off.

[0102] The display panel driving method of this embodiment provides a first potential signal to the first clock signal line and the second clock signal line, and a second potential signal to the start signal line during the initial power-on phase. This causes the first output control module of the shift register of the light-emitting control driving circuit to output the first potential signal to the first node during the initial power-on phase, and causes the second output control module to output the second potential signal to the second node during the initial power-on phase. This causes the first output module to output an invalid light-emitting control signal during the initial power-on phase, and the second output control module to turn off during the initial power-on phase. This allows the shift register of the light-emitting control driving circuit to maintain a stable output of the invalid light-emitting control signal during the initial power-on phase, thereby preventing the voltage amplitude of the output signal of the shift register from being pulled down during the initial power-on phase and improving the flickering of the display panel caused by the unstable output of the shift register of the light-emitting control driving circuit.

[0103] Continue to refer to Figure 9 Optionally, the driving method for the display panel also includes:

[0104] Step 420: In the initial power-on phase, provide a voltage to the anode power signal receiver that is less than the voltage of the cathode power signal receiver, which is lower than the set voltage threshold.

[0105] The voltage threshold can be set to be equal to the conduction threshold voltage of the light-emitting device, so that the light-emitting device will not emit light due to leakage current in the transistors in the pixel circuit when the screen is off, which helps to avoid the flickering problem of the display panel caused by leakage current in the transistors in the pixel circuit.

[0106] Optionally, during the initial power-on phase, a voltage lower than a set voltage threshold is provided to the anode power signal receiver compared to the cathode power signal receiver. This includes providing a ground voltage to both the anode and cathode power signal receivers during the initial power-on phase. This helps avoid display panel flickering caused by transistor leakage in the pixel circuit and also saves power consumption on the display panel.

[0107] Continue to refer to Figure 9 The driving method for the display panel also includes:

[0108] Step 430: After the power-on initial phase ends, and at the same time or before the first-stage shift register outputs the first potential signal, a first power supply voltage is provided to the anode power supply signal receiver, and a second power supply voltage is provided to the cathode power supply signal receiver. The voltage difference between the first power supply voltage and the second power supply voltage is greater than a set voltage threshold.

[0109] Specifically, after the initial power-on phase ends and the first-stage shift register outputs the first potential signal, the display panel can be driven to display the image. In this embodiment, after the initial power-on phase ends and the first-stage shift register outputs the first potential signal, or simultaneously or before, a first power supply voltage is provided to the anode power signal receiver and a second power supply voltage is provided to the cathode power signal receiver. This ensures that after the initial power-on phase ends, the light-emitting control driving circuit can normally drive the display panel to display the image normally.

[0110] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A driving method for a light-emitting control driving circuit, characterized in that, The light emission control driving circuit includes a multi-stage cascaded shift register, which includes: a first output module, a second output module, a first output control module, and a second output control module; The first output control module is used to control the potential of the first node according to the input signal of the first input signal group; the first output module is used to control the output of the invalid light emission control signal according to the potential of the first node; The second output control module is used to control the potential of the second node according to the input signal of the second input signal group, and the second output module is used to control the output of the effective light emission control signal according to the potential of the second node; Both the first input signal group and the second input signal group include at least one input signal; The driving method includes: By controlling the input signals of the first input signal group and the second input signal group, the first output control module outputs a first potential signal to the first node during the initial power-on phase, and the second output control module outputs a second potential signal to the second node during the initial power-on phase, so that the first output module outputs an invalid light-emitting control signal during the initial power-on phase, and the second output module is turned off during the initial power-on phase. The initial power-on phase includes at least the phase between receiving a display command in the screen-off state and displaying the first frame, or the phase between receiving a power-on command and displaying the first frame.

2. The driving method for the light-emitting control driving circuit according to claim 1, characterized in that, The initial power-on phase includes the period between receiving a display command in the screen-off state and entering AOD mode to display the first frame.

3. The driving method for the light-emitting control driving circuit according to claim 1 or 2, characterized in that, The input signals of the first input signal group include a third potential signal, a first clock signal, and a second clock signal; the second clock signal includes the first potential signal. The input signals of the second input signal group include the first clock signal and the start signal. The start signal includes the second potential signal. The start signal of the first-stage shift register of the light-emitting control driving circuit includes the start signal. The start signals of the second-stage shift register and its subsequent shift registers of the light-emitting control driving circuit include the output signal of the previous-stage shift register. The first output control module is specifically used to control the transmission of the second clock signal to the first node according to the first clock signal, the second clock signal and the third potential signal; The second output control module is specifically used to control the transmission of the start signal to the second node according to the first clock signal.

4. The driving method for the light-emitting control driving circuit according to claim 3, characterized in that, The method of controlling the input signals of the first input signal group and the second input signal group to cause the first output control module to output a first potential signal to the first node during the initial power-on phase, and to cause the second output control module to output a second potential signal to the second node during the initial power-on phase, so that the first output module outputs an invalid light-emitting control signal during the initial power-on phase, and the second output module is turned off during the initial power-on phase, includes: During the initial power-on phase, an invalid start signal is input to the first-stage shift register, and valid first clock signals and valid second clock signals are input to each stage of the shift register. This causes the first output control module to transmit the second clock signal to the first node based on the first clock signal, the second clock signal, and the third potential signal, thereby causing the first output module to output an invalid light-emitting control signal. Additionally, the second output control module of the first-stage shift register transmits the start signal to the second node based on the first clock signal, and the second output control modules of the second-stage shift register and its subsequent stages transmit the output signal of the previous-stage shift register to the second node based on the first clock signal, thereby turning off the second output module.

5. The driving method for the light-emitting control driving circuit according to claim 3, characterized in that, Also includes: When the screen is off, the voltage amplitudes of the first clock signal, the second clock signal, and the start signal are all controlled to be the voltage amplitude of the ground signal.

6. The driving method for the light-emitting control driving circuit according to claim 3, characterized in that, Also includes: After the power-on initial phase is completed, a first clock signal and a second clock signal with alternating high and low levels are input to the shift register.

7. The driving method for the light-emitting control driving circuit according to claim 3, characterized in that, The first output control module includes a first output control unit, which includes a first transistor, a second transistor, and a third transistor; The gate of the first transistor is connected to the first clock signal, the first terminal of the first transistor is connected to the third potential signal, the third potential signal serves as the effective light emission control signal, the second terminal of the first transistor is connected to the gate of the second transistor, the first terminal of the second transistor is connected to the second clock signal, the second terminal of the second transistor is connected to the first terminal of the third transistor, the gate of the third transistor is connected to the second clock signal, and the second terminal of the third transistor is connected to the first node.

8. The driving method for the light-emitting control driving circuit according to claim 7, characterized in that, The first output control unit further includes a fourth transistor, the gate of which is connected to the third potential signal.

9. The driving method for the light-emitting control driving circuit according to claim 7, characterized in that, The second output control module includes a second output control unit, which includes a fifth transistor, wherein the gate of the fifth transistor is connected to the first clock signal, the first terminal of the fifth transistor is connected to the start signal, and the second terminal of the fifth transistor is connected to the second node.

10. The driving method for the light-emitting control driving circuit according to claim 9, characterized in that, The second output control unit further includes a sixth transistor, the gate of which is connected to a third potential signal, and the fifth transistor is connected to the second node through the sixth transistor.

11. The driving method for the light-emitting control driving circuit according to claim 9, characterized in that, The first output control unit further includes a seventh transistor, the gate of which is connected to the second terminal of the fifth transistor, the first terminal of which is connected to the first clock signal, and the second terminal of which is connected to the second terminal of the first transistor.

12. The driving method for the light-emitting control driving circuit according to claim 9, characterized in that, The first output control module further includes a third output control unit, which includes an eighth transistor. The gate of the eighth transistor is connected to the second terminal of the fifth transistor, and the first terminal of the eighth transistor is connected to a fourth potential signal, which serves as the invalid light emission control signal. The second terminal of the eighth transistor is connected to the first node.

13. The driving method for the light-emitting control driving circuit according to claim 9, characterized in that, The second output control module further includes a fourth output control unit, which includes a ninth transistor and a tenth transistor. The gate of the ninth transistor is connected to the gate of the second transistor. The first terminal of the ninth transistor is connected to a fourth potential signal. The second terminal of the ninth transistor is connected to the first terminal of the tenth transistor. The gate of the tenth transistor is connected to the second clock signal. The second terminal of the tenth transistor is connected to the second terminal of the fifth transistor.

14. The driving method for the light-emitting control driving circuit according to claim 13, characterized in that, The fourth output control unit further includes an eleventh transistor, the gate of the ninth transistor is connected to the gate of the second transistor through the eleventh transistor, and the gate of the eleventh transistor is connected to a third potential signal.

15. A light-emitting control driving circuit, characterized in that, Driven by the driving method of the light-emitting control driving circuit according to any one of claims 1-14.

16. A driving method for a display panel, characterized in that, The display panel includes the light-emitting control driving circuit as described in claim 15; The display panel further includes a first clock signal line, a second clock signal line, and a start signal line. The first clock signal line is used to transmit a first clock signal to the odd-level shift register and a second clock signal to the even-level shift register. The second clock signal line is used to transmit a second clock signal to the even-level shift register and a first clock signal to the odd-level shift register. The start signal line is used to transmit a start signal to the first-level shift register. The display panel also includes a pixel circuit, which includes an anode power signal receiver and a cathode power signal receiver. The driving method for the display panel includes: During the initial power-on phase, a valid clock signal is provided to the first clock signal line and the second clock signal line, and an invalid start signal is provided to the start signal line. The valid clock signal is a first potential signal, and the invalid start signal is a second potential signal. This causes the first output control module of the shift register of the light-emitting control driving circuit to output a first potential signal to the first node during the initial power-on phase, and causes the second output control module to output a second potential signal to the second node during the initial power-on phase. This causes the first output module to output an invalid light-emitting control signal during the initial power-on phase, and the second output module to be turned off during the initial power-on phase. During the initial power-on phase, a voltage is provided to the anode power signal receiver that is less than a set voltage threshold compared to the voltage at the cathode power signal receiver.

17. The driving method for a display panel according to claim 16, characterized in that, The step of providing a voltage to the anode power signal receiver that is less than a set voltage threshold compared to the voltage at the cathode power signal receiver during the initial power-on phase includes: During the initial power-on phase, a ground voltage is provided to the anode power signal receiver and the cathode power signal receiver. The driving method for the display panel further includes: After the power-on initial phase ends, and simultaneously or before the first stage shift register outputs the first potential signal, a first power supply voltage is provided to the anode power supply signal receiver, and a second power supply voltage is provided to the cathode power supply signal receiver. The voltage difference between the first power supply voltage and the second power supply voltage is greater than the set voltage threshold.

18. The driving method for a display panel according to claim 16, characterized in that, The set voltage threshold is equal to the conduction threshold voltage of the light-emitting device in the display panel.

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