Compressed addressing for transaction layer packets

Abstract

The invention relates to compression addressing for transaction layer packets, comprising: for a first time period, determining one or more low-entropy address bits in a plurality of first transaction layer packets; removing the one or more low-entropy address bits from one or more memory addresses of one or more second transaction layer packets; and transmitting the one or more second transaction layer packets.

Description

BACKGROUND

[0001] Improvements to interconnect for transaction layer packets come at the expense of weaker signal integrity. While error correction codes or other data enhance signal integrity, they impose significant coding overhead, degrading system performance. BRIEF DESCRIPTION OF DRAWINGS

[0002] Figure 1 is a block diagram of an exemplary processor for compressed addressing of transaction layer packets according to some embodiments.

[0003] Figure 2 is a flow diagram of an exemplary method for compressed addressing of transaction layer packets according to some embodiments.

[0004] Figure 3 is a flow diagram of an exemplary method for compressed addressing of transaction layer packets according to some embodiments.

[0005] Figure 4 is a flow diagram of an exemplary method for compressed addressing of transaction layer packets according to some embodiments.

[0006] Figure 5 is a flow diagram of an exemplary method for compressed addressing of transaction layer packets according to some embodiments.

[0007] Figure 6 is a flow diagram of an exemplary method for compressed addressing of transaction layer packets according to some embodiments.

[0008] Figure 7 is a flow diagram of an exemplary method for compressed addressing of transaction layer packets according to some embodiments. DETAILED DESCRIPTION

[0009] In some embodiments, a method for compressed addressing of transaction layer packets includes determining, for a first time period, one or more low entropy address bits in a plurality of first transaction layer packets; removing the one or more low entropy address bits from one or more memory addresses of one or more second transaction layer packets; and transmitting the one or more second transaction layer packets.

[0010] In some embodiments, determining the one or more low-entropy address bits in the plurality of first transaction layer packets over the first time period includes maintaining, for each address bit in the plurality of first transaction layer packets, a corresponding at least one counter, modifying the corresponding at least one counter based on a bit value of each address bit in the plurality of first transaction layer packets, and determining one or more low-entropy address bits based on the corresponding at least one counter for each address bit in the plurality of first transaction layer packets. In some embodiments, the method further includes storing a bit mask indicating the one or more low-entropy address bits in a first bit mask register and storing one or more predicted values for one or more low-entropy bits in a first bit array register. In some embodiments, the method further includes synchronizing the first bit mask register and the first bit array register with a second bit mask register and a second bit array register of a recipient of the one or more second transaction layer packets. In some embodiments, the method further includes regenerating one or more memory addresses based on one or more compressed memory addresses in the one or more second transaction layer packets and one or more stored values indicating one or more removed low-entropy bits. In some embodiments, the one or more stored values include a second bit mask register storing a bit mask indicating one or more low-entropy bits and a second bit array register storing one or more values for one or more low-entropy bits. In some embodiments, the method further includes sending a signal to a recipient of the one or more second transaction layer packets indicating that the one or more second transaction layer packets include one or more compressed destination addresses.

[0011] In some embodiments, an apparatus for compressing addressing of transaction layer packets performs steps including determining, for a first time period, one or more low-entropy address bits in a plurality of first transaction layer packets, removing the one or more low-entropy address bits from one or more memory addresses of one or more second transaction layer packets, and sending the one or more second transaction layer packets.

[0012] In some embodiments, determining the one or more low-entropy address bits in the plurality of first transaction layer packets for the first time period comprises maintaining, for each address bit in the plurality of first transaction layer packets, a corresponding at least one counter, modifying the corresponding at least one counter based on a bit value of each address bit in the plurality of first transaction layer packets, and determining one or more low-entropy address bits based on the corresponding at least one counter for each address bit in the plurality of first transaction layer packets. In some embodiments, the step further comprises storing a bit mask indicating the one or more low-entropy address bits in a first bit mask register and storing one or more predicted values for one or more low-entropy bits in a first bit array register. In some embodiments, the step further comprises synchronizing the first bit mask register and the first bit array register with a second bit mask register and a second bit array register of a recipient of the one or more second transaction layer packets. In some embodiments, the step further comprises regenerating one or more memory addresses based on one or more compressed memory addresses in the one or more second transaction layer packets and one or more stored values indicating one or more removed low-entropy bits. In some embodiments, the one or more stored values comprise a second bit mask register storing a bit mask indicating one or more low-entropy bits and a second bit array register storing one or more values for one or more low-entropy bits. In some embodiments, the step further comprises sending a signal to a recipient of the one or more second transaction layer packets indicating that the one or more second transaction layer packets comprise one or more compressed destination addresses.

[0013] In some embodiments, a system for compressed addressing of transaction layer packets comprises a device that performs the steps of: determining, for a first time period, one or more low-entropy address bits in a plurality of first transaction layer packets; removing the one or more low-entropy address bits from one or more memory addresses of one or more second transaction layer packets; and sending the one or more second transaction layer packets.

[0014] In some embodiments, determining the one or more low-entropy address bits in the first time period includes maintaining, for each address bit in the plurality of first transaction layer packets, a corresponding at least one counter, modifying the corresponding at least one counter based on a bit value of each address bit in the plurality of first transaction layer packets, and determining one or more low-entropy address bits based on the corresponding at least one counter of each address bit in the plurality of first transaction layer packets. In some embodiments, the step further includes storing a bit mask indicating the one or more low-entropy address bits in a first bit mask register and storing one or more predicted values of one or more low-entropy bits in a first bit array register. In some embodiments, the step further includes synchronizing the first bit mask register and the first bit array register with a second bit mask register and a second bit array register of a recipient of the one or more second transaction layer packets. In some embodiments, the step further includes regenerating one or more memory addresses based on one or more compressed memory addresses in the one or more second transaction layer packets and one or more stored values indicating one or more removed low-entropy bits. In some embodiments, the one or more stored values include a second bit mask register storing a bit mask indicating one or more low-entropy bits and a second bit array register storing one or more values for one or more low-entropy bits. In some embodiments, the step further includes sending a signal to a recipient of the one or more second transaction layer packets indicating that the one or more second transaction layer packets include one or more compressed destination addresses.

[0015] Figure 1 is a block diagram of a non-limiting example system 100. The example system 100 can be implemented in various computing devices including mobile devices, personal computers, peripheral hardware components, gaming devices, set-top boxes, and the like. The example system 100 includes devices 102a and 102b. The devices 102a / 102b include hardware devices or components (e.g., hardware devices or components of a computing system) communicatively coupled via an interconnect 104. For example, in some embodiments, the devices 102a / 102b include a central processing unit (CPU), a graphics processing unit (GPU), a memory module, and the like. In some embodiments, the interconnect 104 includes a peripheral component interface (PCI) interconnect.

[0016] The devices 102a / 102b communicate via the interconnect 104 using transaction layer packets (TLPs). For example, the device 102a performs a memory access command on the device 102b by sending one or more transaction layer packets to the device 102b. Each transaction layer packet includes a memory address in a header. The memory address is a target address for the memory access command (e.g., a read command, a write command).

[0017] In some embodiments, the memory addresses indicated in the transaction layer packets will have one or more low-entropy bits. In other words, the bits at one or more indices of each transaction layer packet received and / or transmitted within a given time window or period will have a low degree of entropy (e.g., the bits at these indices have a low degree of variance across the transaction layer packets within the period). To reduce the number of bits needed to express the memory addresses in the transaction layer packets, the memory addresses can be “compressed” to remove the low-entropy bits prior to transmitting the transaction layer packets to their recipients. These removed or “recycled” bits can then be used for other purposes. For example, these recycled bits can be used to add error correction codes or other data for ensuring data integrity, thereby improving the integrity of communications via the interconnect without increasing the overall size of the transaction layer packets.

[0018] The compression unit 106 of the device 102a determines one or more low-entropy bits in a plurality of first transaction layer packets within a first period. The plurality of first transaction layer packets are transaction layer packets received by the device 102a or generated by the device 102a for transmission to the device 102b. The first period is a time window during which the first transaction layer packets are received, generated, or set to be transmitted to the device 102b. The first period and other periods described herein include a predefined or configurable duration or interval.

[0019] In some embodiments, determining one or more low-entropy bits in the plurality of first transaction layer packets within the first period includes maintaining, for each address bit in the plurality of first transaction layer packets, a corresponding at least one counter 108. In some embodiments, for an n-bit memory address, the compression unit 106 maintains n counters 108. For each address bit in the memory addresses of the first plurality of transaction layer packets, the compression unit 106 updates the counter 108 corresponding to the index of the address bit. For example, where the address bit at a given index is a “1,” the compression unit 106 increments the counter 108 corresponding to the given index. Where the address bit at the given index is a “0,” the compression unit 106 decrements the counter 108 corresponding to the given index. Thus, for each of the first transaction layer packets, each counter 108 is incremented or decremented based on the value of the corresponding address bit.

[0020] In some implementations, for an n-bit memory address, the compression unit 106 maintains two sets of counters, each with n counters 108. In other words, each address bit in a transaction layer group corresponds to two counters 108. For each address bit in the memory address of a first plurality of transaction layer groups, the compression unit 106 updates one of the counters 108 corresponding to the address bit index based on the value of the address bit. For example, if the address bit at a given index is "1", the compression unit 106 increments the first counter 108 corresponding to that index. If the address bit at a given index is "0", the compression unit 106 increments the second counter 108 corresponding to that index. Thus, for each of the first transaction layer groups, either the first counter or the second counter 108 increments based on the value of the corresponding address bit.

[0021] Compression unit 106 then determines one or more low-entropy address bits based on counter 108 (e.g., at the end of the first time period). For example, in some embodiments where each address bit corresponds to a single counter 108 that increments or decrements based on the value of the corresponding address bit, low-entropy bits are identified by having counter 108 with an absolute value higher than a threshold. That is, low-entropy bits will have counter 108 with higher absolute values ​​because counter 108 will increment or decrement more frequently. Conversely, high-entropy bits will have counter 108 incremented and decremented to a more similar degree.

[0022] For example, suppose we use a t-bit counter 108 and define a threshold “T”, where 0 ≤ T ≤ 1. The value C of counter 108... x Greater than T*(2) t In the case of -1), the corresponding address bit is determined to be a low-entropy bit and the predicted bit value is "1". In C x Less than (1-T)*(2 t In the case of -1), the corresponding address bit is determined to be a low-entropy bit and the predicted bit value is "0". In C x >=(1-T)*(2 t -1) and C x <= T*(2 t In the case of -1), the corresponding address bit is determined and no value is predicted.

[0023] For example, in some embodiments where each address bit corresponds to two counters 108 that increment alternately based on the value of the corresponding address bit, low-entropy bits are identified by making the value of one counter 108 significantly greater than the value of the other counter 108 (e.g., the difference between the value of the first counter 108 and the value of the second counter 108 exceeds a threshold). Conversely, high-entropy bits are identified by making the first and second counters 108 have similar values.

[0024] In some embodiments, to identify which address bits (e.g., address bit indices) are determined to be low-entropy bits, compression unit 106 stores a bitmask in bitmask register 110a. Those skilled in the art will appreciate that, in some embodiments, the bitmask is stored in a non-register portion of the allocated memory. For example, where an address bit at index i is determined to be a low-entropy bit, the value of the bitmask at index i is set to “1”. Conversely, where an address bit at index i is determined to be a high-entropy bit, the value of the bitmask at index i is set to “0” or left unmodified. For example, in some embodiments, compression unit 106 resets or zeroes bitmask register 110a. Thus, the bitmask indices of high-entropy bits do not require modification from their initialized “0” state.

[0025] In some embodiments, to identify the predicted values of address bits (e.g., address bit indices) determined to be low-entropy bits, compression unit 106 stores the corresponding values in bit array register 112a. Those skilled in the art will appreciate that, in some embodiments, the predicted values are stored in a non-register portion of the allocated memory. Furthermore, while bit array register 112a is discussed as storing values in an array, those skilled in the art will appreciate that other non-array data structures can be used. For example, where the value of a low-entropy address bit at index i is predicted to be “1”, the value at index i of the bit array (stored in bit array register 112a) is set to “1”. As another example, where the value of a low-entropy address bit at index i is predicted to be “0”, the value at index i of the bit array (stored in bit array register 112a) is set to “0”. For high-entropy address bits, no value needs to be set in bit array register 112a, as there is no predicted value. In some embodiments, bit array register 112a is reset (e.g., zeroed, set to all null or default values) at each time period.

[0026] Compression unit 106 then removes one or more low-entropy address bits from one or more memory addresses of one or more second transaction layer packets associated with a second time period following the first time period. For example, the bitmask stored in bitmask register 110a is used to determine which indices of the memory addresses are determined to be low-entropy bits. For each index identified as a low-entropy bit (e.g., having a bitmask value of “1”), the value of bit array register 112a at these indices is compared to the corresponding values of the memory addresses in the second transaction layer packet. For each index identified as a low-entropy bit, if the corresponding bit in the memory address of the second transaction layer packet matches the corresponding value in bit array register 112a (e.g., if an exclusive OR comparison of each bit at the low-entropy bit indices of the memory address and the bit array results in “0”), the low-entropy address bit is removed from the memory address of the second transaction layer packet.

[0027] In some embodiments, additional data is encoded in one or more second transaction layer packets, such as error correction codes or other data integrity data. Device 102a subsequently transmits the one or more second transaction layer packets to device 102b.

[0028] In some embodiments, the above-described method is repeated for each time period (e.g., at a predefined interval). For example, for a first time period, compression unit 106 determines low-entropy address bits for a plurality of first transaction layer packets. For example, during the first time period, counter 108 is maintained and updated based on memory addresses of the plurality of first transaction layer packets. At the end of the first time period, low-entropy address bits are identified and bit mask register 110a and bit array register 112a are updated accordingly. During a second time period, low-entropy address bits are removed from one or more second transaction layer packets based on values of bit mask register 110a and bit array register 112a determined from the plurality of first transaction layer packets. Additionally, counter 108 is reset and updated based on memory addresses of the one or more second transaction layer packets. At the end of the second time period, bit mask register 110a and bit array register 112 are updated based on low-entropy bits identified from the second transaction layer packets. Then for a third time period, low-entropy bits are removed from third transaction layer packets that match, and so on.

[0029] Decompression unit 114 of device 102b regenerates the original uncompressed memory addresses for the received transaction layer packets (e.g., the one or more second transaction layer packets from which one or more low-entropy bits were removed). To facilitate regeneration of the memory addresses, in some embodiments, decompression unit 114 includes bit mask register 110b and bit array register 112b that are synchronized with bit mask register 110a and bit array register 112a of compression unit 106. For example, in some embodiments, after storing values in bit mask register 110a and / or bit array register 112a, compression unit 106 of device 102a provides a signal to decompression unit 114 of device 102b indicating the stored values. Further, in response to removing one or more low-entropy address bits, compression unit 106 provides a signal to decompression unit 114 of device 102b indicating that the one or more second transaction layer packets include compressed memory addresses. Accordingly, decompression unit 114 determines, based on the received signal, to regenerate memory addresses of the one or more second transaction layer packets based on values stored in bit mask register 110b and bit array register 112b. Decompression unit 114 can also include one or more counters 116 to synchronize bit mask register 110a / 110b and bit array register 112a / 112b.

[0030] While the example system 100 depicts two devices 102a / 102b, it should be understood that the methods described herein can be implemented in a system having any number of interconnected devices. Moreover, while the example system 100 shows device 102a as having compression unit 106 and device 102b as having decompression unit 114, it should be understood that in some embodiments, a device can include both compression unit 106 and decompression unit 114 to facilitate bidirectional transmission of transaction layer packet having compressed memory addresses.

[0031] To further illustrate, Figure 2 A flowchart showing an example method for compressed addressing of transaction layer packets is presented, the method including determining 202, for a first time period (e.g., by compression unit 200), one or more low-entropy address bits in a plurality of first transaction layer packets. Each transaction layer packet in the plurality of first transaction layer packets includes a memory address in a header. The memory address is a target address for a memory access command (e.g., a read command, a write command). The one or more low-entropy address bits are indices of bits in the memory address that have a low degree of entropy across each of the plurality of first transaction layer packets.

[0032] The plurality of first transaction layer packets are transaction layer packets received by a device 102a associated with compression unit 200 or generated by a device 102a associated with compression unit 200 for transmission to device 102b. The first time period is a window of time during which the first transaction layer packets are received, generated, or set to send to device 102b. The first time period and other time periods described herein include a predefined or configurable duration or interval.

[0033] In some embodiments, determining 202 the one or more low-entropy address bits includes storing an indication of which bits (e.g., which bit indices) correspond to low address bits. For example, a bit mask is stored in bit mask register 110a or other allocated portion of memory. Each index of the bit mask corresponding to a low-entropy bit index is set to a predefined value (e.g., “1”). In some embodiments, determining 202 the one or more low-entropy address bits includes predicting a value of the one or more low-entropy address bits and storing an indication of the predicted value. For example, in some embodiments, a bit array or other data structure is stored in bit array register 112a or other allocated portion of memory. Each entry in the bit array corresponding to a low-entropy address bit is set to a predicted value (e.g., “0” or “1”) of that low-entropy address bit.

[0034] Figure 2The method also includes removing one or more low-entropy address bits from one or more memory addresses of one or more second transaction layer packets 208 associated with a second time period following the first time period. For example, a bitmask stored in bitmask register 110a is used to determine which indices of the memory addresses are identified as low-entropy bits. For each index identified as a low-entropy bit (e.g., having a bitmask value "1"), the value of bit array register 112a at those indices is compared with the corresponding value in the memory address of the second transaction layer packet 208. For each index identified as a low-entropy bit, if the corresponding bit in the memory address of the second transaction layer packet matches the corresponding value in bit array register 112a, the low-entropy address bit is removed from the memory address of the second transaction layer packet.

[0035] In some implementations, additional data is encoded in one or more second transaction layer packets 208, such as error correction codes or other data integrity data. Figure 2 The method also includes sending 206 or more second transaction layer packets 208. For example, one or more second transaction layer packets 208 are sent to device 102b via interface 104.

[0036] To further illustrate, Figure 3 A flowchart illustrating an exemplary method for compressed addressing of transaction layer packets is provided, the method comprising determining one or more low-entropy address bits in a plurality of first transaction layer packets for a first time period (e.g., by compression unit 200); removing one or more low-entropy address bits from one or more memory addresses of one or more second transaction layer packets 208 associated with a second time period following the first time period; and sending one or more second transaction layer packets 208 206.

[0037] Figure 3 Methods and Figure 2 The method differs in that, for a first time period (e.g., via compression unit 200), determining one or more low-entropy address bits in a plurality of first transaction layer packets (202) includes maintaining at least one counter 108 corresponding to each address bit in the plurality of first transaction layer packets (302). In some embodiments, for an n-bit memory address, compression unit 200 maintains n counters 108. In other embodiments, for an n-bit memory address, compression unit 200 maintains two sets of counters, each set containing n counters 108. In other words, each address bit in a transaction layer packet corresponds to two counters 108.

[0038] Figure 3The method of also includes modifying 304 the corresponding at least one counter based on the bit value of each address bit in the plurality of first transaction layer packets. In cases where the compression unit 200 maintains n counters 108 for n-bit memory addresses, for each address bit in the memory addresses of the first plurality of transaction layer packets, the compression unit 200 updates the counter 108 corresponding to the address bit index. For example, in cases where the address bit at a given index is “1”, the compression unit 200 increments the counter 108 corresponding to the given index. In cases where the address bit at a given index is “0”, the compression unit 200 decrements the counter 108 corresponding to the given index. Thus, for each of the first transaction layer packets, each counter 108 is incremented or decremented based on the value of the corresponding address bit.

[0039] In cases where the compression unit 200 maintains 2*n counters 108 for n-bit memory addresses, for each address bit in the memory addresses of the first plurality of transaction layer packets, the compression unit 200 updates one of the counters 108 corresponding to the address bit index according to the value of the address bit. For example, in cases where the address bit at a given index is “1”, the compression unit 200 increments the first counter 108 corresponding to the given index. In cases where the address bit at a given index is “0”, the compression unit 200 increments the second counter 108 corresponding to the given index. Thus, for each of the first transaction layer packets, the first or second counter 108 is incremented based on the value of the corresponding address bit.

[0040] Figure 3 The method of also includes determining 306 one or more low-entropy address bits based on the counters 108 (e.g., at the end of the first time period). For example, in some embodiments where each address bit corresponds to a single counter 108 that is incremented or decremented based on the value of the corresponding address bit, a low-entropy bit is identified by having a counter 108 with an absolute value above a threshold. That is, a low-entropy bit will have a counter 108 with a higher absolute value, as the counter 108 will be incremented frequently or decremented frequently. Conversely, a high-entropy bit will have a counter 108 that is incremented and decremented to a more similar degree.

[0041] For example, assume that t-bit counters 108 are used, and define a threshold “T”, where 0 < T < 1. In cases where the value of a counter 108, C, is greater than T*(2 x -1), determine that the corresponding address bit is a low-entropy bit and predict the bit value to be “1”. In cases where C t < (1-T)*(2 x -1), determine that the corresponding address bit is a low-entropy bit and predict the bit value to be “0”. In cases where C t >= (1-T)*(2 x -1) and C t < (1-T)*(2 x< = T * (2 t -1), the corresponding address bit is determined and no value is predicted.

[0042] As another example, in some embodiments in which each address bit corresponds to two counters 108 that are alternately incremented based on the value of the corresponding address bit, a low-entropy bit is identified by having the value of one counter 108 significantly greater than the value of the other counter 108 (e.g., the difference between the value of the first counter 108 and the second counter 108 exceeds a threshold). Conversely, a high-entropy bit is identified by having the first and second counters 108 have similar values.

[0043] To further illustrate, Figure 4 A flowchart showing an exemplary method for compressed addressing of transaction layer packets is presented, the method including determining 202 one or more low-entropy address bits in a plurality of first transaction layer packets for a first time period (e.g., by a compression unit 200); removing 204 the one or more low-entropy address bits from one or more memory addresses in one or more second transaction layer packets 208 associated with a second time period subsequent to the first time period; and transmitting 206 the one or more second transaction layer packets 208.

[0044] Figure 4 The method of Figure 2 The method of Figure 4 The method of further includes storing 402 a bitmask 404 in a first bitmask register 406 indicating the one or more low-entropy address bits. For example, in the case that the address bit at index i is determined to be a low-entropy bit, the value of the bitmask 404 at index i is set to “1”. Conversely, in the case that the address bit at index i is determined to be a high-entropy bit, the value of the bitmask 404 at index i is set to “0” or left unmodified. For example, in some embodiments, the compression unit 200 resets or zeroes the bitmask register 406 (e.g., for each time period). Thus, the bitmask 404 index of a high-entropy bit need not be modified from its initialized “0” state.

[0045] Figure 4Also included is storing 408 one or more predicted values 410 of one or more low-entropy bits in the first bit array register 412. For example, in the case where the value of the low-entropy address bit at index i is predicted to be “1,” the value at the bit array (stored in the first bit array register 412) at index i is set to “1.” For another example, in the case where the value of the low-entropy address bit at index i is predicted to be “0,” the value at the bit array (stored in the first bit array register 412) at index i is set to “0.” For high-entropy address bits, no value is set in the first bit array register 412 because there is no predicted value. In some embodiments, the first bit array register 412 is reset (e.g., zeroed, set to all nulls or default values) at each time period.

[0046] To further illustrate, Figure 5 A flow diagram illustrating an example method for compressed addressing of transaction layer packets is presented, the method including determining 202 one or more low-entropy address bits for a first time period (e.g., by the compression unit 200) in a plurality of first transaction layer packets; storing 402 a bit mask 404 indicating the one or more low-entropy address bits in a first bit mask register 406; storing 408 one or more predicted values 410 of the one or more low-entropy bits in a first bit array register 412; removing 204 the one or more low-entropy address bits from one or more memory addresses of one or more second transaction layer packets 208 associated with a second time period subsequent to the first time period; and transmitting 206 the one or more second transaction layer packets 208.

[0047] Figure 5 The method of Figure 4 differ from the method of Figure 5 The method of

[0048] To further illustrate, Figure 6A flow diagram illustrating an exemplary method for compressed addressing of transaction layer packets is presented, the method including determining 202 one or more low-entropy address bits in a plurality of first transaction layer packets for a first time period (e.g., by compression unit 200); removing 204 the one or more low-entropy address bits from one or more memory addresses in one or more second transaction layer packets 208 associated with a second time period subsequent to the first time period; and transmitting 206 the one or more second transaction layer packets 208.

[0049] Figure 6 The method of Figure 2 differ from the method of Figure 6 The method of

[0050] To further illustrate, Figure 7 A flow diagram illustrating an exemplary method for compressed addressing of transaction layer packets is presented, the method including determining 202 one or more low-entropy address bits in a plurality of first transaction layer packets for a first time period (e.g., by compression unit 200); removing 204 the one or more low-entropy address bits from one or more memory addresses in one or more second transaction layer packets 208 associated with a second time period subsequent to the first time period; and transmitting 206 the one or more second transaction layer packets 208.

[0051] Figure 7 The method of Figure 2 differ from the method of Figure 7The method of compressing addresses for transaction layer packets further includes regenerating 702 one or more memory addresses based on one or more compressed memory addresses in one or more second transaction layer packets 208 and one or more stored values (e.g., by a decompression unit 702) indicative of one or more removed low-entropy bits. In some embodiments, the one or more stored values include a bitmask stored in a bitmask register and a bit array stored in a bit array register. For example, the bitmask register and the bit array register of the decompression unit 700 are synchronized with another bitmask register and bit array register of the compression unit 200. In some embodiments, the regenerating 702 of one or more memory addresses is performed in response to a signal from the compression unit 200 indicating that the second transaction layer packet 208 includes compressed memory addresses.

[0052] In view of the explanations set forth above, the reader will recognize that the benefits of compressing addresses for transaction layer packets include:

[0053] • improved performance of the computing system by reducing the size required to express memory addresses in transaction layer packets.

[0054] • improved performance of the computing system by allowing memory address bits reclaimed through memory address compression to be used for other values, such as error correction codes, thereby improving the integrity of the signal without increasing the size of the packet or transmission overhead.

[0055] • improved performance of the computing system by reducing packet transmission resource requirements due to the reduced total size required to express memory addresses.

[0056] Advantages and features of the present disclosure can be further described by the following statements:

[0057] Statement 1. A method of compressing addresses for transaction layer packets, the method comprising: determining, for a first time period, one or more low-entropy address bits in a plurality of first transaction layer packets; removing the one or more low-entropy address bits from one or more memory addresses in one or more second transaction layer packets associated with a second time period subsequent to the first time period; and transmitting the one or more second transaction layer packets.

[0058] Statement 2. The method of statement 1, wherein determining, for the first time period, the one or more low-entropy address bits in the plurality of first transaction layer packets comprises: maintaining, for each address bit in the plurality of first transaction layer packets, a corresponding at least one counter; modifying the corresponding at least one counter based on a bit value of each address bit in the plurality of first transaction layer packets; and

[0059] determine the one or more low-entropy address bits based on the corresponding at least one counter for each address bit in the plurality of first transaction layer packets.

[0060] Statement 3. The method of any of statements 1-2, further comprising storing a bitmask indicating the one or more low-entropy address bits in a first bitmask register and storing one or more predicted values for the one or more low-entropy bits in a first bit array register.

[0061] Statement 4. The method of any of statements 1-3, further comprising synchronizing the first bitmask register and the first bit array register with a second bitmask register and a second bit array register of a recipient of the one or more second transaction layer packets.

[0062] Statement 5. The method of any of statements 1-4, further comprising regenerating the one or more memory addresses based on one or more compressed memory addresses in the one or more second transaction layer packets and one or more stored values indicating the one or more removed low-entropy bits.

[0063] Statement 6. The method of any of statements 1-5, wherein the one or more stored values comprise a second bitmask register storing a bitmask indicating the one or more low-entropy bits and a second bit array register storing one or more values for the one or more low-entropy bits.

[0064] Statement 7. The method of any of statements 1-6, further comprising sending a signal to a recipient of the one or more second transaction layer packets indicating that the one or more second transaction layer packets include one or more compressed memory addresses.

[0065] Statement 8. An apparatus for compressed addressing of transaction layer packets, the apparatus configured to perform steps comprising: determining one or more low-entropy address bits in a plurality of first transaction layer packets for a first time period; removing the one or more low-entropy address bits from one or more memory addresses of one or more second transaction layer packets associated with a second time period subsequent to the first time period; and sending the one or more second transaction layer packets.

[0066] Statement 9. The apparatus of statement 8, wherein determining, for the first time period, the one or more low-entropy address bits in the plurality of first transaction layer packets comprises: maintaining, for each address bit in the plurality of first transaction layer packets, a corresponding at least one counter; modifying the corresponding at least one counter based on a bit value of each address bit in the plurality of first transaction layer packets; and determining the one or more low-entropy address bits based on the corresponding at least one counter for each address bit in the plurality of first transaction layer packets.

[0067] Statement 10. The apparatus of any one of statements 8-9, wherein the steps further comprise: storing, in a first bitmask register, a bitmask indicating the one or more low-entropy address bits; and storing, in a first bitarray register, one or more predicted values for the one or more low-entropy bits.

[0068] Statement 11. The apparatus of any one of statements 8-10, wherein the steps further comprise synchronizing the first bitmask register and the first bitarray register with a second bitmask register and a second bitarray register of a recipient of the one or more second transaction layer packets.

[0069] Statement 12. The apparatus of any one of statements 8-11, wherein the steps further comprise regenerating the one or more memory addresses based on one or more compressed memory addresses in the one or more second transaction layer packets and one or more stored values indicating the one or more removed low-entropy bits.

[0070] Statement 13. The apparatus of any one of statements 8-12, wherein the one or more stored values comprise a second bitmask register storing a bitmask indicating the one or more low-entropy bits and a second bitarray register storing one or more values for the one or more low-entropy bits.

[0071] Statement 14. The apparatus of any one of statements 8-13, wherein the steps further comprise sending, to a recipient of the one or more second transaction layer packets, a signal indicating that the one or more second transaction layer packets comprise one or more compressed memory addresses.

[0072] Statement 15. A system for compressed addressing of transaction layer packets, comprising: an apparatus configured to perform steps comprising: determining, for a first time period, one or more low-entropy address bits in a plurality of first transaction layer packets; removing the one or more low-entropy address bits from one or more memory addresses of one or more second transaction layer packets associated with a second time period subsequent to the first time period; and sending the one or more second transaction layer packets.

[0073] Statement 16. The system of statement 15, wherein determining the one or more low entropy address bits for the first time period includes, for each address bit in the plurality of first transaction layer packets: maintaining a corresponding at least one counter; modifying the corresponding at least one counter based on a bit value of each address bit in the plurality of first transaction layer packets; and determining the one or more low entropy address bits based on the corresponding at least one counter for each address bit in the plurality of first transaction layer packets.

[0074] Statement 17. The system of any one of statements 15-16, wherein the steps further comprise: storing a bit mask indicating the one or more low entropy address bits in a first bit mask register; and storing one or more predicted values for the one or more low entropy bits in a first bit array register.

[0075] Statement 18. The system of any one of statements 15-17, wherein the steps further comprise synchronizing the first bit mask register and the first bit array register with a second bit mask register and a second bit array register of a recipient of the one or more second transaction layer packets.

[0076] Statement 19. The system of any one of statements 15-18, wherein the steps further comprise regenerating the one or more memory addresses based on one or more compressed memory addresses in the one or more second transaction layer packets and one or more stored values indicating the one or more removed low entropy bits.

[0077] Statement 20. The system of any one of statements 15-19, wherein the one or more stored values include a second bit mask register storing a bit mask indicating the one or more low entropy bits and a second bit array register storing one or more values for the one or more low entropy bits.

[0078] Exemplary embodiments of the present disclosure are primarily described in the context of a fully functional computer system for transaction layer packet compression addressing. Those skilled in the art will immediately appreciate that the disclosure can also be embodied in a computer program product disposed on a computer readable storage medium for use with any suitable data processing system. Such computer readable storage medium can be any storage medium for machine-readable information, including magnetic media, optical media, or other suitable medium. Examples of such media include magnetic disks in hard drives or floppy disks, compact disks for optical drives, magnetic tape, and others as will occur to those in the art. Those skilled in the art will immediately appreciate that any computer system having suitable programming means will be capable of executing the steps of the method of the present disclosure as embodied in a computer program product. Those skilled in the art will also realize that, although some exemplary embodiments described in this specification are directed at software installed and executed on computer hardware, alternative embodiments implemented as firmware or hardware are within the scope of the present disclosure.

[0079] The present disclosure can be a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure.

[0080] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0081] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions to a computer readable storage medium within the respective computing / processing device for storage and / or execution. Components of computer 100 can also include one or more storage devices and / or computer storage media. Computer storage media can be tangible and non-transitory. Storage media can include volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. The system memory 104, the removable storage device 109 and the non-removable storage device 110 are all computer storage media examples (i.e., memory storage.) Storage media 104, 109, 110 can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, solid state RAM, or any other medium that can be used to store information and that can be accessed by computer 100. Any of the foregoing storage media can be employed in computer 100. The computer 100 can also include input / output (I / O) interface(s) 112 that enables the computer 100 to communicate with one or more devices or peripherals. The I / O interface 112 can include any one or combination of various types of peripherals interface devices. For example, the I / O interface 112 can include devices allowing the computer 100 to communicate with other computers or devices such as the Internet or Intranet communication ports, wireless communication ports, USB ports, serial ports, parallel ports, and / or the like. The I / O interface 112 can also include output interfaces 113, such as display, speakers, and / or the like, and input interfaces 114, such as a keyboard, mouse, trackball, microphone, touch screen, touch pad, and / or the like.

[0082] Computer readable program instructions for carrying out operations of the present disclosure can be in assembly code, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0083] Aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0084] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function / act specified in the flowchart and / or block diagram block or blocks.

[0085] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0086] The flow and block diagrams in the figures illustrate the architecture, functionality, and operations of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flow and block diagrams can represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical functions (‘instructions’). In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession can in fact be executed substantially concurrently or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

[0087] From the foregoing, it will be appreciated that modifications and changes can be made by those skilled in the art to various embodiments of the present disclosure. The descriptions in this specification are only for the sake of illustration and are not to be taken in a limiting sense. The scope of the present disclosure is limited only by the language of the appended claims.

Claims

1. An apparatus for compressed addressing of transaction layer packets, the apparatus comprising a first device including a compression unit, the first device including logic configured to: For the first time period, multiple first transaction layer packets are received; for each address bit in the multiple first transaction layer packets, a corresponding counter is maintained, and the corresponding counter indicates whether the address bit is a low-entropy address bit; Remove one or more low-entropy address bits from one or more memory addresses of one or more second transaction layer packets associated with the second time period following the first time period; and Send the one or more second transaction layer packets.

2. The apparatus of claim 1, wherein the compression unit further comprises logic: The corresponding counter is modified based on the bit value of each address bit in the plurality of first transaction layer packets; and The one or more low-entropy address bits are determined based on the corresponding counter for each address bit in the plurality of first transaction layer packets.

3. The apparatus of claim 1, wherein the compression unit further comprises logic: The first mask register stores a bitmask indicating the one or more low-entropy address bits; and One or more predicted values ​​of the one or more low-entropy address bits are stored in the first array register.

4. The apparatus of claim 3, wherein the compression unit further comprises logic to synchronize the first bitmask register and the first bit array register with the second bitmask register and the second bit array register of the receiver of the one or more second transaction layer packets.

5. The apparatus of claim 1, further comprising a bitmask register storing a bitmask indicating the one or more low-entropy address bits and a bit array register storing one or more values ​​for the one or more low-entropy address bits.

6. The apparatus of claim 1, wherein the compression unit further comprises logic to send a signal to a recipient of the one or more second transaction layer packets indicating that the one or more second transaction layer packets include one or more compressed memory addresses.

7. A system for compressed addressing of transaction layer packets, the system comprising: A first device and a second device, the first device being coupled to the second device via an interconnect, wherein the first device includes a compression unit, and wherein the first device includes logic to: For the first time period, multiple first-transaction-layer packets are received; For each address bit in the plurality of first transaction layer groups, a corresponding counter is maintained, and the corresponding counter indicates whether the address bit is a low-entropy address bit; Remove one or more low-entropy address bits from one or more memory addresses of one or more second transaction layer groups associated with the second time period following the first time period; as well as The interconnect sends one or more second transaction layer packets to the second device.

8. The system of claim 7, wherein, for the first time period, the compression unit of the first device determines, using logic, the one or more low-entropy address bits in the plurality of first transaction layer packets to: The corresponding counter is modified based on the bit value of each address bit in the plurality of first transaction layer packets; and The one or more low-entropy address bits are determined based on the corresponding counter for each address bit in the plurality of first transaction layer packets.

9. The system of claim 7, wherein the compression unit of the first device further includes logic for storing a bitmask indicating the one or more low-entropy address bits in a first-bit mask register; and storing one or more predicted values ​​of the one or more low-entropy address bits in a first-bit array register.

10. The system of claim 9, wherein the compression unit of the first device further includes logic to synchronize the first bitmask register and the first bit array register with the second bitmask register and the second bit array register of the second device.

11. The system of claim 7, wherein the second device includes a decompression unit, the decompression unit including logic to regenerate the one or more memory addresses based on one or more compressed memory addresses in the one or more second transaction layer packets and one or more storage values ​​indicating the one or more removed low-entropy address bits.

12. The system of claim 11, wherein the one or more stored values ​​include a bitmask register storing a bitmask indicating the one or more low-entropy address bits and a bit array register storing one or more values ​​for the one or more low-entropy address bits.

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