Dual-time system communication method and system based on Feiteng Kirin platform and CPLD

Abstract

The application discloses a dual-time system communication method and system based on a Feiteng Kirin platform and a CPLD, and the dual-time system communication method comprises the following steps: acquiring a generation source of a time system source; judging the type of the time system source according to the acquired generation source of the time system source; and controlling the CPLD by the CPU in the corresponding time system source mode according to the judged type of the time system source, so as to realize the control of the time system source. The dual-time system communication method and system based on the Feiteng Kirin platform and the CPLD have the advantages that the CPU and the CPLD are adopted, the manufacturing cost is low, the occupied space is small, the degree of intelligence is high, and the user is convenient to use.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of computer time system technology, and discloses a dual-time system communication method and system based on a Feiteng Kirin platform and a CPLD. BACKGROUND

[0002] The dual-difference time system of the Feiteng Kirin platform and the CPLD is a way of controlling a time system source by software of the Feiteng Kirin. At present, the existing control system adopts a time system mode when the time response requirement is high. The devices in the system respond to the time system signal inside the system, and a special time system device is configured in the system to provide a unified time system source to the inside.

[0003] At present, the devices responding to the time system all adopt a powerful and special time system board. The time system board can modify the control program according to the needs of the customer, receive or generate time system signals of different frequencies, duty cycles, different channels and time lengths of delay, meet the needs of different systems for time system signals, and can serve as the active party of time system control and also has the functions of receiving time system pulses and counting pulse signal quantities. However, the existing time system devices have the defects of large size, high price and inconvenient use for users.

[0004] Therefore, the existing time system devices have the defects of large size, high price and inconvenient use for users, which is a technical problem to be solved at present. SUMMARY

[0005] The present application provides a dual-time system communication method and system based on a Feiteng Kirin platform and a CPLD, aiming at solving the technical problem of the existing time system devices of large size, high price and inconvenient use for users.

[0006] One aspect of the present application relates to a dual-time system communication method based on a Feiteng Kirin platform and a CPLD, applied to a dual-time system communication control device, the dual-time system communication control device comprising a CPU and a CPLD connected with the CPU, and the dual-time system communication method based on the Feiteng Kirin platform and the CPLD comprises the following steps:

[0007] Obtaining the generation source of the time system source;

[0008] According to the obtained generation source of the time system source, the type of the time system source is determined;

[0009] According to the determined type of the time system source, the CPLD is controlled by the CPU in the corresponding time system source mode to realize the control of the time system source.

[0010] Further, the type of the time system source includes an external time system source and an internal time system source, and the step of determining the type of the time system source according to the obtained generation source of the time system source comprises:

[0011] If the collected time source signal is generated by a signal generator, it is determined that the type of the collected time source is an external time source;

[0012] If the collected time source signal is generated by a CPLD, it is identified that the type of the time source is an internal time source.

[0013] Further, the time source mode includes an external time source mode and an internal time source mode. According to the type of the time source determined, the CPU controls the CPLD in the corresponding time source mode, and the step of controlling the time source includes:

[0014] If it is identified that the time source is an external time source, the double-following time control of the external time source is realized in the external time source mode;

[0015] If it is identified that the time source is an internal time source, the double CPLD time control of the internal time source is realized in the internal time source mode.

[0016] Further, if it is identified that the time source is an external time source, the step of realizing the double-following time control of the external time source in the external time source mode includes:

[0017] Receiving the external time sent by the signal generator;

[0018] Opening the CPLD time switch through I 2 C communication to control the generation of the time synchronization following source of the CPLD;

[0019] Through GPIO communication, the input level signal of the GPIO corresponding to the time of the CPLD is processed by level pull-up;

[0020] Through I 2 C communication writes different pulse width decimal values to the register of the CPLD corresponding time channel;

[0021] Through I 2 C communication writes different delay level values to the register of the CPLD corresponding time channel;

[0022] Through I 2 C communication writes the level signal to the register of the CPLD corresponding time channel;

[0023] Through GPIO communication, it is monitored in real time whether the output GPIO level flip-flop signal of the CPLD corresponding time channel changes;

[0024] Through I 2 C communication, the register of the corresponding time channel obtains the counting and empty counting operation.

[0025] Further, if the time source is identified as the internal time source, then in the internal time source mode, the step of implementing the double CPLD time control of the internal time source includes:

[0026] Receiving the internal time sent by the CPLD;

[0027] Through I 2 C communication reads the register of the CPLD to determine whether the time signal is turned on;

[0028] Through GPIO communication, the input level signal of the GPIO corresponding to the time of the CPLD is processed by level pulling up;

[0029] Through I 2 C communication writes different pulse width decimal values to the register of the CPLD corresponding to the time channel;

[0030] Through I 2 C communication writes different delay level values to the register of the CPLD corresponding to the time channel;

[0031] Through I 2 C communication writes the level signal to the register of the CPLD corresponding to the time channel;

[0032] Through GPIO communication, it is monitored in real time whether the output GPIO level flip-flop signal of the CPLD corresponding to the time channel changes;

[0033] Through I 2 C communication to the register of the corresponding time channel to obtain the counting and empty counting operation.

[0034] Another aspect of the application relates to a double time communication system based on the Fengting Kirin platform and the CPLD, applied to a double time communication control device, the double time communication control device includes a CPU and a CPLD connected with the CPU, and the double time communication system based on the Fengting Kirin platform and the CPLD includes:

[0035] The acquisition module is used for acquiring the generation source of the time source;

[0036] The judgment module is used for judging the type of the time source according to the acquired generation source of the time source;

[0037] The control module is used for controlling the CPLD by the CPU in the corresponding time source mode according to the type of the time source, so as to realize the control of the time source.

[0038] Further, the type of the time source includes an external time source and an internal time source, and the judgment module includes:

[0039] The first judging unit is configured to judge that the type of the collected time source is an external time source if the collected time source is generated by the signal generator.

[0040] The second judging unit is configured to identify that the type of the time source is an internal time source if the collected time source is generated by the CPLD.

[0041] Further, the time source mode includes an external time source mode and an internal time source mode, and the control module includes:

[0042] The first control unit is configured to realize double-following time control of the external time source in the external time source mode if it is identified that the time source is an external time source.

[0043] The second control unit is configured to realize double-CPLD time control of the internal time source in the internal time source mode if it is identified that the time source is an internal time source.

[0044] Further, the first control unit includes:

[0045] The first receiving subunit is configured to receive the external time source sent by the signal generator.

[0046] The first control subunit is configured to open the CPLD time switch through I 2 C communication and control generation of the time synchronization following source of the CPLD.

[0047] The first processing subunit is configured to perform level pull-up processing on the input level signal of the GPIO corresponding to the time of the CPLD through GPIO communication.

[0048] The first read-write subunit is configured to write different pulse width decimal values to the register of the time channel corresponding to the CPLD through I 2 C communication.

[0049] The second read-write subunit is configured to write different delay level values to the register of the time channel corresponding to the CPLD through I 2 C communication.

[0050] The third read-write subunit is configured to write a level signal to the register of the time channel corresponding to the CPLD through I 2 C communication.

[0051] The first monitoring subunit is configured to monitor whether the output GPIO level flip-flop signal of the time channel corresponding to the CPLD changes in real time through GPIO communication.

[0052] The first acquisition subunit is configured to acquire the count and clear count operations of the register of the time channel corresponding to the CPLD through I 2 C communication.

[0053] Further, the second control unit comprises:

[0054] A second receiving subunit is arranged to receive the internal time system sent by the CPLD.

[0055] A second control subunit is arranged to write the register of the CPLD through the I 2 C communication to judge whether the time system signal is opened or not.

[0056] A second processing subunit is arranged to perform level pull-up processing on the input level signal of the GPIO corresponding to the time system of the CPLD through the GPIO communication.

[0057] A fourth reading and writing subunit is arranged to write different pulse width decimal values to the register of the time system channel of the CPLD through the I 2 C communication.

[0058] A fifth reading and writing subunit is arranged to write different delay level values to the register of the time system channel of the CPLD through the I 2 C communication.

[0059] A sixth reading and writing subunit is arranged to write the level signal to the register of the time system channel of the CPLD through the I 2 C communication.

[0060] A second monitoring subunit is arranged to monitor whether the output GPIO level flip-flop signal of the time system channel of the CPLD changes in real time through the GPIO communication.

[0061] A second acquisition subunit is arranged to acquire the count and empty count operation of the register of the time system channel through the I 2 C communication.

[0062] The beneficial effects achieved by the present application are as follows:

[0063] The present application provides a dual time system communication method and system based on the Flying Feng Kirin platform and CPLD, which acquires the generation source of the time system source; judges the type of the time system source according to the acquired generation source of the time system source; and controls the CPLD by the CPU in the corresponding time system source mode according to the judged type of the time system source, so as to realize the control of the time system source. The dual time system communication method and system based on the Flying Feng Kirin platform and CPLD provided by the present application adopts the CPU and the CPLD, has low manufacturing cost, small occupied space, high intelligent degree and good user convenience. BRIEF DESCRIPTION OF DRAWINGS

[0064] Figure 1 The flowchart of an embodiment of the dual time system communication method based on the Flying Feng Kirin platform and CPLD provided by the present application is shown.

[0065] Figure 2 For Figure 1 The detailed flowchart of one embodiment of the step of judging the type of the time system source according to the generating source of the acquired time system source is shown in FIG. 2;

[0066] Figure 3 For Figure 1 The detailed flowchart of one embodiment of the step of controlling the CPLD by the CPU under the corresponding time system source mode according to the judged type of the time system source to realize the control of the time system source is shown in FIG. 3;

[0067] Figure 4 For Figure 3 The detailed flowchart of one embodiment of the step of realizing the double-following time system control of the external time system source under the external time system source mode if the time system source is identified as the external time system source is shown in FIG. 4;

[0068] Figure 5 For Figure 3 The detailed flowchart of one embodiment of the step of realizing the double-CPLD time system control of the internal time system source under the internal time system source mode if the time system source is identified as the internal time system source is shown in FIG. 5;

[0069] Figure 6 The functional block diagram of one embodiment of the dual-time system communication system based on the Feiteng Kirin platform and the CPLD provided by the present application is shown in FIG. 6;

[0070] Figure 7 For Figure 6 The functional module diagram of one embodiment of the judging module is shown in FIG. 7;

[0071] Figure 8 For Figure 6 The functional module diagram of one embodiment of the control module is shown in FIG. 8;

[0072] Figure 9 For Figure 8 The functional module diagram of one embodiment of the first control unit is shown in FIG. 9;

[0073] Figure 10 For Figure 8 The functional module diagram of one embodiment of the second control unit is shown in FIG. 10.

[0074] Explanation of the reference signs:

[0075] 10, acquisition module; 20, judgment module; 30, control module; 21, first judgment unit; 22, second judgment unit; 31, first control unit; 32, second control unit; 311, first receiving subunit; 312, first control subunit; 313, first processing subunit; 314, first read-write subunit; 315, second read-write subunit; 316, third read-write subunit; 317, first monitoring subunit; 318, first acquisition subunit; 321, second receiving subunit; 322, second control subunit; 323, second processing subunit; 324, fourth read-write subunit; 325, fifth read-write subunit; 326, sixth read-write subunit; 327, second monitoring subunit; 328, second acquisition subunit. DETAILED DESCRIPTION

[0076] In order to better understand the above technical solutions, the above technical solutions will be described in detail below in combination with the description of the drawings and specific embodiments.

[0077] As shown in Figure 1 and Figure 2 , the first embodiment of the present application proposes a dual-time system communication method based on the Fengting Kirin platform and CPLD, which is applied to a dual-time system communication control device. The dual-time system communication control device includes a CPU and a CPLD connected with the CPU. The dual-time system communication method based on the Fengting Kirin platform and CPLD includes the following steps:

[0078] Step S100, acquiring the generation source of the time system source.

[0079] The time system source is divided into an external time system source and an internal time system source according to the generation source. The external time system source is generated by a signal generator. The internal time system source is generated by an internal CPLD. The CPU opens the CPLD by operating the register of the CPLD and receives the signal of the time system source.

[0080] Step S200, judging the type of the time system source according to the acquired generation source of the time system source.

[0081] According to the acquired generation source of the time system source, the type of the received time system source is judged. If the received time system source is generated by a signal generator, it is judged that the type of the time system source is an external time system source. If the received time system source is generated by a CPLD, it is judged that the type of the time system source is an internal time system source.

[0082] Step S300, controlling the CPLD by the CPU in the corresponding time system source mode according to the judged type of the time system source, so as to realize the control of the time system source.

[0083] According to the type of the time system source, a corresponding time system source mode is used, and the CPLD is controlled in the corresponding time system source mode, so as to realize the control of the time system source. For example, the time system source mode includes an external time system source mode and an internal time system source mode. In the external time system source mode, the control of the double-following time system of the CPLD is realized. In the internal time system source mode, the control of the double-following time system of the CPLD is realized.

[0084] Compared with the prior art, the method provided in the embodiment includes the following steps: obtaining the generation source of the time system source; judging the type of the time system source according to the obtained generation source of the time system source; and controlling the CPLD by the CPU in the corresponding time system source mode according to the type of the time system source, so as to realize the control of the time system source. The method provided in the embodiment is based on the double-time system communication of the Fengting Kirin platform and the CPLD. The CPU and the CPLD are used, the manufacturing cost is low, the occupied space is small, the intelligent degree is high, and the user is convenient to use.

[0085] Further, see Figure 2 , Figure 2 for Figure 1 an embodiment of the step S200 shown in FIG. 2. In the embodiment, the step S200 includes the following steps.

[0086] In step S210, if the collected time system source is generated by the signal generator, it is judged that the type of the collected time system source is an external time system source.

[0087] If it is identified that the collected time system source is generated by the signal generator, it is judged that the type of the time system source is an external time system source.

[0088] In step S220, if the collected time system source is generated by the CPLD, it is identified that the type of the time system source is an internal time system source.

[0089] If it is identified that the collected time system source is generated by the internal CPLD, it is judged that the type of the time system source is an internal time system source.

[0090] Compared with the prior art, if the collected time system source is generated by the signal generator, it is judged that the type of the collected time system source is an external time system source. If the collected time system source is generated by the CPLD, it is identified that the type of the time system source is an internal time system source. The method provided in the embodiment is based on the double-time system communication of the Fengting Kirin platform and the CPLD. The CPU and the CPLD are used, the manufacturing cost is low, the occupied space is small, the intelligent degree is high, and the user is convenient to use.

[0091] Preferably, see Figure 3 , Figure 3 forFigure 1 A detailed flowchart of an embodiment of step S200 shown in FIG. 10 is shown in FIG. 11. In this embodiment, step S300 includes:

[0092] If it is identified that the time source is an external time source, then in the external time source mode, double-following time control of the external time source is implemented.

[0093] If it is identified that the time source is an external time source, then in the external time source mode, double-following time control of the external time source is implemented. In this embodiment, the double-following time includes a first following time and a second following time, and the CPU controls the first following time and the second following time respectively.

[0094] If it is identified that the time source is an internal time source, then in the internal time source mode, double-CPLD time control of the internal time source is implemented.

[0095] If it is identified that the time source is an internal time source, then in the internal time source mode, double-CPLD time control of the internal time source is implemented. In this embodiment, the double-CPLD time includes a first CPLD time and a second CPLD time, and the CPU controls the first CPLD time and the second CPLD time respectively.

[0096] Compared with the prior art, if it is identified that the time source is an external time source, then in the external time source mode, double-following time control of the external time source is implemented; if it is identified that the time source is an internal time source, then in the internal time source mode, double-CPLD time control of the internal time source is implemented. The double-time communication method based on the Feiteng Kirin platform and the CPLD has low manufacturing cost, small space occupation, high intelligence, and good user convenience.

[0097] Further, see Figure 4 , Figure 4 for Figure 3 A detailed flowchart of an embodiment of step S310 shown in FIG. 10 is shown in FIG. 12. In this embodiment, step S310 includes:

[0098] Step S311 receives the external time sent by the signal generator.

[0099] The external time sent by the signal generator is mainly to verify whether the internal Feiteng CPU can control the external time signal source.

[0100] Step S312 opens the CPLD time switch through I 2 C communication to control the generation of the time synchronization following source of the CPLD.

[0101] Through I 2 The controller of the C communication controls the CPLD to realize the generation of the information of the external time signal source and the follow-up source of the time source of the CPLD. The CPU end realizes the control of the CPLD follow-up source of the external time signal through the software programming. The detection of whether the double follow-up time signal is opened is realized through the I 2 The C communication reads the level value of the register of the CPLD to judge whether the follow-up response function of the CPLD is opened, and the Feng end needs to do the clear interrupt operation after the time source of the CPLD end is generated. Specifically, when the switch register of the first follow-up time becomes high, the time is opened, and when the switch register of the second follow-up time becomes high, the time is opened.

[0102] Step S313, the input level signal of the GPIO corresponding to the time of the CPLD is processed through the GPIO communication.

[0103] The input level of the CPLD of the double follow-up time is monitored in real time through the GPIO communication, if the level of the output end of the GPIO of the double follow-up time is detected to be high, the pull-up and timely processing of the level flip are realized through the GPIO communication, and a signal source signal is obtained from the level flip process this time and the signal amount is counted by the CPLD and the CPU. Specifically, whether the input GPIO level of the first follow-up time CPLD is high is detected, and whether the input GPIO level of the second follow-up time CPLD is high is detected.

[0104] Step S314, the I 2 The C communication writes different pulse width decimal values to the register of the time channel corresponding to the CPLD.

[0105] The pulse width of the time signal of the follow-up source is controlled, the I 2 The C communication writes the corresponding pulse width parameter to the specific register of the follow-up source, sets the pulse width duty cycle of the double follow-up time to be 10%, 50% or 80%, and the pulse width control result verification method is to read whether the duty cycle size set by the CPU through the oscilloscope to capture the waveform or to obtain the duty cycle value by reading the CPLD register. Specifically, the pulse width duty cycle of the first follow-up time is set to be 10%, 50% or 80%, and the pulse width duty cycle of the second follow-up time is set to be 10%, 50% or 80%.

[0106] Step S315, the I 2 The C communication writes different delay level values to the register of the time channel corresponding to the CPLD.

[0107] Through the I 2C communication writes the corresponding delay amount to the CPLD register, sets the delay duration to 0ms, 20ms, 30ms, or 50ms, and verifies the delay result through an oscilloscope to compare the delay duration with the standard time source generated externally. Alternatively, the delay size of the CPLD register is directly read and compared with the CPU. Specifically, the delay duration of the first follow-up time is set to 0ms, 20ms, 30ms, or 50ms, and the delay duration of the second follow-up time is set to 0ms, 20ms, 30ms, or 50ms.

[0108] Step S316, through I 2 C communication writes the level signal to the CPLD register corresponding to the time.

[0109] The pulse counting function of the double follow-up time is realized, and the CPU communicates with the CPLD through I 2 C writes the level signal to the CPLD register corresponding to the time to open the counting switch. Specifically, the first follow-up time counting switch is opened, and the second follow-up time counting switch is opened.

[0110] Step S317, through GPIO communication, real-time monitoring of the output GPIO level flip signal of the CPLD corresponding to the time channel.

[0111] The output of the CPLD is monitored in real time through GPIO communication, and the level flip time signal amount is counted. Specifically, after the first follow-up time is opened for counting, the number of level flips is judged to accumulate the time signal amount, and the counting is stopped through the software signal. After the second follow-up time is opened for counting, the number of level flips is judged to accumulate the time signal amount, and the counting is stopped through the software signal.

[0112] Step S318, through I 2 C communication to the register corresponding to the time channel to get the counting and empty counting operation.

[0113] The counting is emptied and the follow-up time signal source is turned off, and the CPU communicates with the CPLD through I 2 C communication reads and writes the level value of the CPLD register. The counting method is that the CPU sends a stop signal command through ctrl+c, and the number of time level flips detected by the CPU is printed through the terminal, and the time source of the CPLD follow-up time is stopped. Specifically, after the first follow-up time receives the stop, the original time signal amount of the CPU and the CPLD is counted and compared to determine whether they are consistent, and the value in the register is emptied and the follow-up time signal is turned off in time. After the second follow-up time receives the stop, the original time signal amount of the CPU and the CPLD is counted and compared to determine whether they are consistent, and the value in the register is emptied and the follow-up time signal is turned off in time.

[0114] The embodiment provides a dual time system communication method based on a Feiteng Kirin platform and a CPLD. 2 The C communication opens a CPLD time system switch, controls time system synchronization of the CPLD to follow a source, and performs level pull-up processing on an input level signal of a GPIO corresponding to a time system of the CPLD through GPIO communication. 2 The C communication writes different pulse width decimal values to a register of a CPLD corresponding time system channel. 2 The C communication writes different delay level values to a register of a CPLD corresponding time system channel. 2 The C communication writes a level signal to a register of a CPLD corresponding time system channel, and monitors whether a change occurs in an output GPIO level flip-flop signal of the CPLD corresponding time system channel through GPIO communication. 2 The C communication performs counting and empty counting operations on a register of a CPLD corresponding time system channel. The dual time system communication method based on the Feiteng Kirin platform and the CPLD has low manufacturing cost, small space occupation, high intelligence, and good user convenience.

[0115] Preferably, referring to Figure 5 , Figure 5 for Figure 3 an embodiment of the step S310 shown in the figure, in the embodiment, the step S320 includes:

[0116] The step S321 receives an internal time system sent by the CPLD.

[0117] The I 2 C reads and writes a level value of a register of a CPLD to open or close a time system signal source, to realize generation of the internal time system signal.

[0118] The step S322 reads a register of the CPLD through the I 2 C communication, to determine whether the time system signal is opened.

[0119] Whether the internal time system source is opened is determined, specifically, the switch register of the first CPLD time system becomes high to open the time system, and the switch register of the second CPLD time system becomes high to open the time system.

[0120] The step S323 performs level pull-up processing on an input level signal of a GPIO corresponding to a time system of the CPLD through GPIO communication.

[0121] GPIO communication is used to monitor in real time whether the CPLD input level of the dual-CPLD system is high. If the level of the GPIO output terminal of the dual-CPLD system is detected to be high, the GPIO communication is used to pull it up to promptly handle the level flip. From this level flip process, a signal source signal is obtained, and the CPLD and CPU perform signal quantity statistics. Specifically, the input GPIO level of the CPLD of the first CPLD system is detected to be high, and the input GPIO level of the CPLD of the second CPLD system is detected to be high.

[0122] Step S324, through I 2 C communication writes the decimal values ​​of different pulse widths to the register of the corresponding timing channel of the CPLD.

[0123] Control the pulse width of the timing signal of the follower source through I 2 The corresponding pulse width parameters are written to the specific register of the follower source through C communication, and the pulse width duty cycle of the dual CPLD time system is set to 10%, 50%, or 80%. The pulse width control result is verified by capturing the waveform with an oscilloscope to determine whether it is the duty cycle set by the CPU or by reading the CPLD register to obtain the duty cycle value. Specifically, the pulse width duty cycle of the first CPLD time system is set to 10%, 50%, or 80%, and the pulse width duty cycle of the second CPLD time system is set to 10%, 50%, or 80%.

[0124] Step S325, through I 2 C communication writes different delay level values ​​to the register of the corresponding timing channel of the CPLD.

[0125] By I 2 C communication writes the corresponding delay value to the CPLD register and sets the delay length to 0ms, 20ms, 30ms, or 50ms. The delay results of the dual CPLD timing system are verified by capturing the waveform with an oscilloscope and comparing it with the external standard timing source to see if the delay length is consistent with the value set by the CPU, or by directly reading the delay value from the CPLD register and comparing it with the CPU. Specifically, the delay length of the first CPLD timing system is set to 0ms, 20ms, 30ms, or 50ms, and the delay length of the second CPLD timing system is set to 0ms, 20ms, 30ms, or 50ms.

[0126] Step S326, through I 2 C communication writes the level signal to the register of the corresponding timing channel of the CPLD.

[0127] Realize the pulse counting function of dual CPLD time system, CPU through I 2C write level signal to CPLD corresponding to the register switch of the time unit to open the start counting. Specifically, the first CPLD time unit opens the counting switch, and the second CPLD time unit opens the counting switch.

[0128] Step S327, the output GPIO level flip signal of the CPLD corresponding time unit channel is monitored in real time through GPIO communication.

[0129] The output of the CPLD is monitored in real time, and the level flip time unit signal quantity is counted. Specifically, the first CPLD time unit opens the counting, and the number of level flips is accumulated by judging the number of level flips, and the counting is stopped by software signal. The second CPLD time unit opens the counting, and the number of level flips is accumulated by judging the number of level flips, and the counting is stopped by software signal.

[0130] Step S328, through I 2 C communication corresponding to the register of the time unit channel to obtain the counting and empty counting operation.

[0131] The empty counting and the closing of the following time unit signal source are realized through I 2 C communication reads and writes the level value of the register of the double CPLD time unit. The counting is counted in the form of CPU, and the number of time unit level flips detected by the CPU is printed in the form of terminal, and the time unit source of the following time unit of the CPLD is stopped. Specifically, after the first CPLD time unit receives the stop, the original time unit signal quantity of the CPU and the CPLD is compared to determine whether they are consistent, and the value in the register is emptied and the following time unit signal is closed in time. After the second CPLD time unit receives the stop, the original time unit signal quantity of the CPU and the CPLD is compared to determine whether they are consistent, and the value in the register is emptied and the following time unit signal is closed in time.

[0132] The double time unit communication method based on the Feiteng Kirin platform and the CPLD provided in the embodiment, compared with the prior art, receives the internal time unit sent by the CPLD; I 2 C communication reads the register of the CPLD to determine whether the time unit signal is opened; through GPIO communication, the input level signal of the GPIO corresponding to the time unit of the CPLD is pulled up; through I 2 C communication writes different pulse width decimal values to the register of the time unit channel corresponding to the CPLD; through I 2 C communication writes different delay level values to the register of the time unit channel corresponding to the CPLD; through I 2 C write level signal to CPLD corresponding to the register switch of the time unit to open the start counting. Specifically, the first CPLD time unit opens the counting switch, and the second CPLD time unit opens the counting switch. 2The C communication corresponds to the register obtaining count and emptying count operation of the time-honored channel. The embodiment provided by the application provides a dual-time-honored communication method based on the Feiteng Kirin platform and the CPLD, adopts the CPU and the CPLD, has low manufacturing cost, small space occupation, high intelligent degree and good user convenience.

[0133] As shown in Figure 6 , Figure 6 The functional block diagram of an embodiment of the dual-time-honored communication system based on the Feiteng Kirin platform and the CPLD provided by the application is shown in the figure, in the embodiment, the dual-time-honored communication system based on the Feiteng Kirin platform and the CPLD is applied to a dual-time-honored communication control device, the dual-time-honored communication control device includes the CPU and the CPLD connected with the CPU, the dual-time-honored communication system based on the Feiteng Kirin platform and the CPLD includes the obtaining module 10, the judging module 20 and the control module 30, wherein the obtaining module 10 is used for obtaining the generation source of the time-honored source; the judging module 20 is used for judging the type of the time-honored source according to the obtained generation source of the time-honored source; the control module 30 is used for controlling the CPLD by the CPU in the corresponding time-honored source mode according to the judged type of the time-honored source, so as to realize the control of the time-honored source.

[0134] The obtaining module 10 opens the CPLD by operating the register of the CPLD, and receives the signal of the time-honored source.

[0135] The judging module 20 judges the type of the received time-honored source according to the obtained generation source of the time-honored source, if the received time-honored source is generated by the signal generator, then judges that the type of the time-honored source is the external time-honored source; if the received time-honored source is generated by the CPLD, then judges that the type of the time-honored source is the internal time-honored source.

[0136] The control module 30 uses the corresponding time-honored source mode according to the judged type of the time-honored source, and controls the CPLD in the corresponding time-honored source mode, so as to realize the control of the time-honored source. For example, the time-honored source mode includes the external time-honored source mode and the internal time-honored source mode, in the external time-honored source mode, the control of the dual-following time-honored of the CPLD is realized. In the internal time-honored source mode, the control of the dual-following time-honored of the CPLD is realized.

[0137] The embodiment provides a dual time system communication system based on a Feiteng Kirin platform and a CPLD.

[0138] Further, see Figure 7 , Figure 7 for Figure 6 The function module schematic diagram of the judgment module embodiment is shown in the figure, in the embodiment, the type of the time system source includes an external time system source and an internal time system source, the judgment module 20 includes a first judgment unit 21 and a second judgment unit 22, wherein the first judgment unit 21 is used for judging that the type of the collected time system source is the external time system source if the collected time system source is generated by the signal generator; and the second judgment unit 22 is used for identifying that the type of the time system source is the internal time system source if the collected time system source is generated by the CPLD.

[0139] The first judgment unit 21 judges that the type of the time system source is the external time system source if it is identified that the collected time system source is generated by the signal generator.

[0140] The second judgment unit 22 judges that the type of the time system source is the internal time system source if it is identified that the collected time system source is generated by the internal CPLD.

[0141] Compared with the prior art, the judgment module 20 adopts the first judgment unit 21 and the second judgment unit 22, judges that the type of the collected time system source is the external time system source if the collected time system source is generated by the signal generator, and identifies that the type of the time system source is the internal time system source if the collected time system source is generated by the CPLD. The dual time system communication system based on the Feiteng Kirin platform and the CPLD adopts the CPU and the CPLD, has low manufacturing cost, small occupied space, high intelligent degree and good user convenience.

[0142] Further, see Figure 8 , Figure 8 for Figure 6The function module schematic view of the control module embodiment shown in the figure is provided. In the embodiment, the time source mode includes an external time source mode and an internal time source mode. The control module 30 includes a first control unit 31 and a second control unit 32. The first control unit 31 is configured to implement double-following time control of the external time source in the external time source mode if it is identified that the time source is an external time source. The second control unit 32 is configured to implement double-CPLD time control of the internal time source in the internal time source mode if it is identified that the time source is an internal time source.

[0143] The first control unit 31 is configured to implement double-following time control of the external time source in the external time source mode if it is identified that the time source is an external time source. In the embodiment, the double-following time includes a first following time and a second following time. The CPU controls the first following time and the second following time respectively.

[0144] The second control unit 32 is configured to implement double-CPLD time control of the internal time source in the internal time source mode if it is identified that the time source is an internal time source. In the embodiment, the double-CPLD time includes a first CPLD time and a second CPLD time. The CPU controls the first CPLD time and the second CPLD time respectively.

[0145] Compared with the prior art, the control module 30 adopts the first control unit 31 and the second control unit 32. The first control unit 31 is configured to implement double-following time control of the external time source in the external time source mode if it is identified that the time source is an external time source. The second control unit 32 is configured to implement double-CPLD time control of the internal time source in the internal time source mode if it is identified that the time source is an internal time source. The double-time communication system based on the Feiteng Kirin platform and the CPLD has the advantages of low manufacturing cost, small space occupation, high intelligent degree, and good user convenience.

[0146] Preferably, see Figure 9 , Figure 9 For Figure 8 The function module schematic view of the first control unit embodiment shown in the figure is provided. In the embodiment, the first control unit 31 includes a first receiving subunit 311, a first control subunit 312, a first processing subunit 313, a first read-write subunit 314, a second read-write subunit 315, a third read-write subunit 316, a first monitoring subunit 317, and a first acquisition subunit 318. The first receiving subunit 311 is configured to receive the external time source sent by the signal generator. The first control subunit 312 is configured to send the external time source to the first processing subunit 313 through an I2C bus. The first processing subunit 313 is configured to send the external time source to the first read-write subunit 314. The first read-write subunit 314 is configured to send the external time source to the first monitoring subunit 317. The first monitoring subunit 317 is configured to send the external time source to the first acquisition subunit 318. The first acquisition subunit 318 is configured to send the external time source to the second control unit 32. 2C communication opens the CPLD timing switch, controls the CPLD timing synchronization to follow the source generation; the first processing subunit 313 is used for carrying out level pull-up processing to the input level signal of the GPIO of the corresponding timing of the CPLD through the GPIO communication; the first read-write subunit 314 is used for writing different pulse width decimal values to the register of the corresponding timing channel of the CPLD through the I 2 C communication writes different delay level values to the register of the corresponding timing channel of the CPLD; the third read-write subunit 316 is used for writing level signals to the register of the corresponding timing channel of the CPLD through the I 2 C communication writes different delay level values to the register of the corresponding timing channel of the CPLD; the third read-write subunit 316 is used for writing level signals to the register of the corresponding timing channel of the CPLD through the I 2 C communication writes different delay level values to the register of the corresponding timing channel of the CPLD; the third read-write subunit 316 is used for writing level signals to the register of the corresponding timing channel of the CPLD through the I 2 C communication writes different delay level values to the register of the corresponding timing channel of the CPLD; the third read-write subunit 316 is used for writing level signals to the register of the corresponding timing channel of the CPLD through the I

[0147] The first receiving subunit 311 receives the external timing sent by the signal generator, and the external timing is mainly used for verifying whether the internal Feiteng CPU can control the external timing signal source.

[0148] The first control subunit 312 controls the CPLD controller to realize the reception of the external timing signal source information and the generation of the following source of the timing source of the CPLD. 2 C communication controls the controller of the CPLD to realize the reception of the external timing signal source information and the generation of the following source of the timing source of the CPLD. 2 C communication reads the level value of the register of the CPLD to judge whether the following response function of the CPLD is opened, and the Feiteng end needs to do the interrupt clearing operation after the CPLD end generates the timing source. Specifically, the first following timing switch register becomes high to open the timing, and the second following timing switch register becomes high to open the timing.

[0149] The first processing subunit 313 monitors whether the input level of the CPLD of the double-following timing is high through the GPIO communication, and if the level of the output end of the GPIO of the double-following timing is detected to be high, the level flip is processed through the GPIO communication. Specifically, it is detected whether the input GPIO level of the first following timing CPLD is high, and whether the input GPIO level of the second following timing CPLD is high.

[0150] The first read-write subunit 314 controls the pulse width of the timing signal of the following source through the I 2C communication writes the corresponding pulse width parameters to the specific registers of the following source, sets the pulse width duty cycle of the double following time system to 10%, 50%, or 80%, and the pulse width control result verification mode is to read whether it is the duty cycle size set by the CPU through the oscilloscope waveform capture or to obtain the duty cycle value by reading the CPLD register. Specifically, the pulse width duty cycle of the first following time system is set to 10%, 50%, or 80%, and the pulse width duty cycle of the second following time system is set to 10%, 50%, or 80%.

[0151] The second read-write subunit 315 writes the corresponding delay amount to the CPLD register through I 2 C communication writes the corresponding delay amount to the CPLD register, sets the delay time to 0ms, 20ms, 30ms, or 50ms, and the double following time system delay result verification is to compare whether the delay time is consistent with the size set by the CPU through the oscilloscope waveform capture and the standard time system source generated externally, or directly compare the delay size of the CPLD register with the CPU. Specifically, the delay time of the first following time system is set to 0ms, 20ms, 30ms, or 50ms, and the delay time of the second following time system is set to 0ms, 20ms, 30ms, or 50ms.

[0152] The third read-write subunit 316 realizes the pulse counting function of the double following time system, and the CPU writes the level signal to the corresponding register switch of the CPLD to start counting. Specifically, the first following time counting switch is opened, and the second following time counting switch is opened. 2 C writes the level signal to the corresponding register switch of the CPLD to start counting. Specifically, the first following time counting switch is opened, and the second following time counting switch is opened.

[0153] The first monitoring subunit 317 communicates through GPIO to monitor the output of the CPLD in real time, and counts the level flip time signal amount. Specifically, after the first following time system is opened for counting, the number of level flips is judged to accumulate the time signal amount, and the counting is stopped through the software signal. After the second following time system is opened for counting, the number of level flips is judged to accumulate the time signal amount, and the counting is stopped through the software signal.

[0154] The first acquisition subunit 318 clears the count and closes the following time system signal source, and communicates through I 2 C communication reads and writes the level value of the CPLD register. The counting method is that the CPU issues a stop signal command through ctrl+c, and the number of time level flips detected by the CPU is printed through the terminal, and the CPLD following time system time source is stopped. Specifically, after the first following time system receives the stop, the CPU and the original time signal amount of the CPLD are counted and compared for consistency, and the values in the registers are cleared and the following time system signal is closed in time. After the second following time system receives the stop, the CPU and the original time signal amount of the CPLD are counted and compared for consistency, and the values in the registers are cleared and the following time system signal is closed in time.

[0155] Compared with the prior art, the dual-time system communication system based on the Feiteng Kylin platform and CPLD provided in this embodiment comprises a first receiving subunit 311, a first controlling subunit 312, a first processing subunit 313, a first reading and writing subunit 314, a second reading and writing subunit 315, a third reading and writing subunit 316, a first monitoring subunit 317 and a first acquiring subunit 318, which receives the external time system sent by the signal generator; and ... 2 C communication turns on the CPLD timing switch, controls the generation of the CPLD timing synchronization follower source; through GPIO communication, the input level signal of the GPIO corresponding to the CPLD timing is pulled high; through I 2 C communication writes the decimal value of different pulse widths to the register of the corresponding time channel of CPLD; through I 2 C communication writes different delay level values ​​to the register of the corresponding time channel of CPLD; through I 2 C communication writes the level signal to the register of the corresponding time channel of CPLD; through GPIO communication, it is monitored in real time whether the output GPIO level flip signal of the corresponding time channel of CPLD changes; through I 2 The dual-time communication system based on the Feiteng Kylin platform and CPLD provided in this embodiment uses CPU and CPLD, has low production cost and small space occupation, high intelligence and good user convenience.

[0156] Further, see Figure 10 , Figure 10 for Figure 8 , in this embodiment, the second control unit 32 includes a second receiving subunit 321, a second control subunit 322, a second processing subunit 323, a fourth read-write subunit 324, a fifth read-write subunit 325, a sixth read-write subunit 326, a second monitoring subunit 327 and a second acquisition subunit 328, wherein the second receiving subunit 321 is used to receive the internal time system sent by the CPLD; the second control subunit 322 is used to obtain the time system through I 2 C communication reads the register of CPLD to determine whether the time system signal is turned on; the second processing sub-unit 323 is used to pull the input level signal of GPIO of CPLD corresponding to the time system through GPIO communication; the fourth reading and writing sub-unit 324 is used to 2 C communication writes the decimal value of different pulse widths to the register of the corresponding time channel of CPLD; the fifth read-write subunit 325 is used to write the decimal value of different pulse widths to the register of the corresponding time channel of CPLD through I 2C communication writes different delay level values to the registers of the corresponding time channel of the CPLD; the sixth read-write subunit 326 is configured to write level signals to the registers of the corresponding time channel of the CPLD through I 2 C communication writes different delay level values to the registers of the corresponding time channel of the CPLD; the sixth read-write subunit 326 is configured to write level signals to the registers of the corresponding time channel of the CPLD through I 2 C communication writes different delay level values to the registers of the corresponding time channel of the CPLD; the sixth read-write subunit 326 is configured to write level signals to the registers of the corresponding time channel of the CPLD through I

[0157] The second receiving subunit 321 is configured to acquire the level values of the registers of the corresponding time channel of the CPLD through I 2 C reads and writes the level values of the registers of the time signal source of the CPLD to realize the generation of the internal time signal.

[0158] The second control subunit 322 is configured to determine whether to open the internal time source, specifically, the switch register of the first CPLD time is opened when the switch register of the second CPLD time becomes high.

[0159] The second processing subunit 323 is configured to monitor whether the CPLD input level of the double-CPLD time is high through GPIO communication in real time, and if the level of the output end of the GPIO of the double-CPLD time is detected to be high, the level flip is pulled high and processed in time through GPIO communication. A signal source signal is obtained from this level flip process, and the signal amount is counted by the CPLD and the CPU. Specifically, it is detected whether the input GPIO level of the first CPLD time CPLD is high, and whether the input GPIO level of the second CPLD time CPLD is high.

[0160] The fourth read-write subunit 324 is configured to control the pulse width of the time signal of the following source through I 2 C communication writes different delay level values to the registers of the corresponding time channel of the CPLD; the sixth read-write subunit 326 is configured to write level signals to the registers of the corresponding time channel of the CPLD through I

[0161] The fifth read-write subunit 325 is configured to write different delay level values to the registers of the corresponding time channel of the CPLD through I 2C communicates the corresponding delay amount to the register of the CPLD, sets the delay time length as 0 ms, 20 ms, 30 ms or 50 ms, and verifies the delay time length through the oscilloscope waveform and the standard time source generated externally. Specifically, the delay time length of the first CPLD time is set as 0 ms, 20 ms, 30 ms or 50 ms, and the delay time length of the second CPLD time is set as 0 ms, 20 ms, 30 ms or 50 ms.

[0162] The sixth read-write subunit 326 realizes the pulse counting function of the double CPLD time, and the CPU communicates with the CPLD through the I 2 C writes the level signal to the register of the corresponding CPLD time to open the switch to start counting. Specifically, the first CPLD time counting switch is opened, and the second CPLD time counting switch is opened.

[0163] The second monitoring subunit 327 communicates in real time to monitor the output of the CPLD, and counts the level flip time signal amount. Specifically, after the first CPLD time is opened for counting, the number of level flips is judged to accumulate the time signal amount, and the counting is stopped through the software signal. After the second CPLD time is opened for counting, the number of level flips is judged to accumulate the time signal amount, and the counting is stopped through the software signal.

[0164] The second acquisition subunit 328 clears the counting and closes the following time signal source, and communicates with the CPLD through the I 2 C communicates to read and write the level value of the register of the double CPLD time. The counting mode is that the CPU sends a stop signal command through ctrl+c, the number of time level flips detected by the CPU, and the terminal mode is used to print out, and the following time source of the CPLD is stopped. Specifically, after the first CPLD time receives the stop, the original time signal amount of the CPU and the CPLD is counted and compared to determine whether they are consistent, and the value in the register is cleared and the following time signal is closed in time. After the second CPLD time receives the stop, the original time signal amount of the CPU and the CPLD is counted and compared to determine whether they are consistent, and the value in the register is cleared and the following time signal is closed in time.

[0165] Compared with the prior art, the second control unit 32 adopts the second receiving subunit 321, the second control subunit 322, the second processing subunit 323, the fourth read-write subunit 324, the fifth read-write subunit 325, the sixth read-write subunit 326, the second monitoring subunit 327 and the second acquisition subunit 328, and communicates with the CPLD through the I 2C communication reads the register of the CPLD to determine whether the clock signal is open; the input level signal of the GPIO corresponding to the clock of the CPLD is pulled up through the GPIO communication; the I 2 C communication writes different pulse width decimal values to the register of the CPLD corresponding to the clock channel; the I 2 C communication writes different delay level values to the register of the CPLD corresponding to the clock channel; the I 2 C communication writes the level signal to the register of the CPLD corresponding to the clock channel; whether the output GPIO level flip signal of the CPLD corresponding to the clock channel changes is monitored in real time through the GPIO communication; the I 2 C communication registers of the corresponding clock channel get counting and empty counting operation. The dual-clock communication system based on the Feiteng Kirin platform and the CPLD provided in the embodiment adopts the CPU and the CPLD, and has low manufacturing cost, small space occupation, high intelligence, and good user convenience.

[0166] Although the preferred embodiments of the present application have been described, those skilled in the art who understand the basic inventive concept can make additional changes and modifications to the embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application. Obviously, those skilled in the art can make various modifications and changes to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and changes of the present application fall within the scope of the claims of the present application and their equivalents, the present application also intends to include these modifications and changes.

Claims

1. A dual-time system communication method based on the Feiteng Kylin platform and CPLD, applied to a dual-time system communication control device, the dual-time system communication control device including a CPU and a CPLD connected to the CPU, characterized in that: The dual time system communication method based on the Feiteng Kylin platform and CPLD includes the following steps: Obtain the source of the time source; Determining the type of the timing source according to the acquired source of the timing source, wherein if the acquired timing source is generated by a signal generator, then determining that the type of the acquired timing source is an external timing source; if the acquired timing source is generated by a CPLD, then determining that the type of the acquired timing source is an internal timing source; According to the determined type of the timing source, in the corresponding timing source mode, the CPU controls the CPLD to realize control of the timing source, wherein, if the timing source is identified as an external timing source, dual-following timing control is realized in the external timing source mode; if the timing source is identified as an internal timing source, dual-CPLD timing control is realized in the internal timing source mode; If the time synchronization source is identified as an external time synchronization source, then in the external time synchronization source mode, dual-following time synchronization control is implemented, including: Receive the external timing signal sent by the signal generator; By I 2 C communication turns on the CPLD timing switch to control the generation of the CPLD timing synchronization source; Through GPIO communication, the input level signal of the GPIO of the CPLD corresponding to the time system is pulled up; By I 2 C communication writes the decimal values ​​of different pulse widths to the register of the corresponding time channel of CPLD; By I 2 C communication writes different delay level values ​​to the register of the corresponding time channel of CPLD; By I 2 C communication writes the level signal to the register of the corresponding time channel of CPLD; Through GPIO communication, it is monitored in real time whether the output GPIO level flip signal of the corresponding timing channel of the CPLD changes; By I 2 C communication corresponds to the register acquisition count and clear count operations of the timing channel; If the timing source is identified as an internal timing source, then in the internal timing source mode, dual CPLD timing control is implemented, including: Receive the internal timing sent by CPLD; By I 2 C communication reads the CPLD register to determine whether the timing signal is turned on; Through GPIO communication, the input level signal of the GPIO of the CPLD corresponding to the time system is pulled up; By I 2 C communication writes the decimal values ​​of different pulse widths to the register of the corresponding time channel of CPLD; By I 2 C communication writes different delay level values ​​to the register of the corresponding time channel of CPLD; By I 2 C communication writes the level signal to the register of the corresponding time channel of CPLD; Through GPIO communication, it is monitored in real time whether the output GPIO level flip signal of the corresponding timing channel of the CPLD changes; By I 2 C communication corresponds to the register acquisition count and clear count operations of the timing channel.

2. A dual-time communication system based on the Feiteng Kylin platform and CPLD, applied to a dual-time communication control device, the dual-time communication control device including a CPU and a CPLD connected to the CPU, characterized in that: The dual-time communication system based on the Feiteng Kylin platform and CPLD includes: An acquisition module (10) is used to acquire the source of the time source; A judgment module (20) is used to judge the type of the timing source according to the source of the timing source obtained, wherein the judgment module (20) includes: a first judgment unit (21) for judging that the type of the timing source obtained is an external timing source if the timing source obtained is generated by a signal generator; a second judgment unit (22) for judging that the type of the timing source obtained is an internal timing source if the timing source obtained is generated by a CPLD; The control module (30) is used to control the CPLD by the CPU in the corresponding time source mode according to the type of the time source determined, thereby realizing control of the time source, wherein the control module (30) includes a first control unit (31) for realizing dual-following time control in the external time source mode if the time source is identified as an external time source; and a second control unit (32) for realizing dual-CPLD time control in the internal time source mode if the time source is identified as an internal time source. Wherein, the first control unit (31) comprises: A first receiving subunit (311) is used to receive an external timing signal sent by a signal generator; The first control subunit (312) is used to control the 2 C communication turns on the CPLD timing switch to control the generation of the CPLD timing synchronization source; The first processing sub-unit (313) is used for performing level-raising processing on the input level signal of the GPIO of the CPLD corresponding to the time system through GPIO communication; The first read-write subunit (314) is used to read 2 C communication writes the decimal values ​​of different pulse widths to the register of the corresponding time channel of CPLD; The second read-write subunit (315) is used to read 2 C communication writes different delay level values ​​to the register of the corresponding time channel of CPLD; The third read-write subunit (316) is used to read 2 C communication writes the level signal to the register of the corresponding time channel of CPLD; A first monitoring subunit (317) is used to monitor in real time through GPIO communication whether the output GPIO level flip signal of the corresponding time channel of the CPLD changes; The first acquisition subunit (318) is used to obtain 2 C communication corresponds to the register acquisition count and clear count operations of the timing channel; The second control unit (32) comprises: The second receiving subunit (321) is used for receiving the internal time system sent by the CPLD; The second control subunit (322) is used to control the 2 C communication reads the CPLD register to determine whether the timing signal is turned on; The second processing sub-unit (323) is used for performing level-raising processing on the input level signal of the GPIO of the CPLD corresponding to the time system through GPIO communication; The fourth read-write subunit (324) is used to read 2 C communication writes the decimal values ​​of different pulse widths to the register of the corresponding time channel of CPLD; The fifth read-write subunit (325) is used to read 2 C communication writes different delay level values ​​to the register of the corresponding time channel of CPLD; The sixth read-write subunit (326) is used to read 2 C communication writes the level signal to the register of the corresponding time channel of CPLD; The second monitoring subunit (327) is used to monitor in real time through GPIO communication whether the output GPIO level flip signal of the corresponding time channel of the CPLD changes; The second acquisition subunit (328) is used to obtain 2 C communication corresponds to the register acquisition count and clear count operations of the timing channel.

Images