A bandgap reference circuit generating low input offset voltage

Abstract

The present invention discloses a bandgap reference circuit that generates low input offset. The circuit comprises a bandgap reference circuit, an auxiliary operational amplifier circuit, and a chopper circuit. The bandgap reference circuit includes a startup circuit, a bandgap reference core circuit, and a voltage bias circuit. The auxiliary operational amplifier circuit includes a polarity-variable transconductance amplifier for reducing voltage input offset. The chopper circuit includes a discrete-time low-pass filter and a polarity conversion switch. The discrete-time low-pass filter is used to filter out high-frequency signals output by the reference, and the polarity conversion switch is used to complete the positive-negative polarity conversion of the operational amplifier. The present invention ensures that the equivalent input offset voltage is reduced by orders of magnitude through the chopper circuit and the auxiliary operational amplifier circuit. The auxiliary operational amplifier circuit also uses output and input storage technology to ensure the low input offset of the auxiliary operational amplifier, thereby ensuring the accuracy of the output voltage of the bandgap reference circuit and providing a good bandgap reference for subsequent analog circuits.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuits, and in particular relates to a bandgap reference circuit for generating low input offset voltage. Background Art

[0002] The importance of a bandgap reference in analog circuits, as it provides the reference voltage required by subsequent modules, is self-evident. The offset voltage caused by the mismatch between resistors and MOS transistor processes is similar to low-frequency noise and accumulates throughout the system through op amps, affecting system stability. Therefore, an offset cancellation circuit can reduce the offset voltage equivalent to the system input by an order of magnitude, thereby providing the system with a wider stable fluctuation range and effectively reducing the system's noise at low frequencies. Existing technologies typically use op amps with low input offset or layout matching techniques to achieve lower input offset voltage. This technology addresses the problem within the module itself, but after system amplification, even minor noise is amplified, which can affect system stability. Therefore, offset voltage reduction at the system level is necessary. Summary of the Invention

[0003] The purpose of the present invention is to provide a bandgap reference circuit with low input offset voltage, thereby ensuring low input offset of an auxiliary operational amplifier and eliminating the input offset voltage of the bandgap reference circuit in terms of magnitude.

[0004] The technical solution for achieving the purpose of the present invention is: a bandgap reference circuit for generating low input offset, comprising a bandgap reference circuit, an auxiliary operational amplifier circuit, and a chopper circuit:

[0005] The bandgap reference circuit includes a startup circuit, a bandgap reference core circuit, and a voltage bias circuit. The startup circuit is used to prevent a degeneracy point. The bandgap reference core circuit is used to generate a voltage with a zero temperature coefficient. The voltage bias circuit is used to provide a bias voltage for the main operational amplifier.

[0006] The auxiliary operational amplifier circuit includes a polarity variable transconductance amplifier, which is used to reduce the voltage input offset;

[0007] The chopping circuit includes a discrete time low-pass filter and a polarity conversion switch; the discrete time low-pass filter is used to filter out the high-frequency signal of the reference output, and the polarity conversion switch is used to complete the positive and negative polarity conversion of the operational amplifier.

[0008] Compared with existing technologies, this invention offers significant advantages: It uses chopper technology to periodically switch the op amp input and output polarity, thereby reducing the input offset voltage of the main op amp. This is further reduced by using a high-gain auxiliary op amp. The auxiliary op amp's own offset is reduced using auto-zero technology to ensure low input offset. This technology can significantly reduce the input offset voltage of the bandgap reference circuit, thereby achieving the required low input offset performance and improving system stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a low input offset bandgap reference circuit diagram of the present invention.

[0010] Figure 2 This is a circuit diagram of an auxiliary operational amplifier of the low input offset bandgap reference circuit of the present invention.

[0011] Figure 3 This is a main operational amplifier circuit and discrete-time low-pass filter circuit diagram of the low-input offset bandgap reference circuit of the present invention.

[0012] Figure 4 This is a chopper switch circuit diagram of the low input offset bandgap reference circuit of the present invention.

[0013] Figure 5 The figure is a topological diagram of an offset cancellation circuit using the low input offset bandgap reference circuit of the present invention. DETAILED DESCRIPTION

[0014] This embodiment provides a bandgap reference circuit that generates low input offset, including a bandgap reference circuit, an auxiliary operational amplifier circuit, and a chopper circuit.

[0015] The bandgap reference circuit includes a startup circuit, a bandgap reference core circuit, and a voltage bias circuit. The startup circuit is used to prevent a degeneracy point. The bandgap reference core circuit is used to generate a voltage with a zero temperature coefficient. The voltage bias circuit is used to provide a bias voltage for the main operational amplifier.

[0016] The auxiliary operational amplifier circuit includes a polarity variable transconductance amplifier, which is used to reduce the voltage input offset;

[0017] The chopper circuit includes a discrete time low-pass filter and a polarity conversion switch; the discrete time low-pass filter is used to filter out the high-frequency signal of the reference output, and the polarity conversion switch is used to complete the positive and negative polarity conversion of the transconductance amplifier.

[0018] Combine Figure 1 and Figure 3 The bandgap reference circuit may adopt a conventional reference circuit, including:

[0019] a first resistor R0, a second resistor R1, a third resistor R2, a fourth resistor R3, a fifth resistor R4, a third capacitor CL, a first PMOS transistor M0, a second PMOS transistor M1, a third PMOS transistor M2, a fourth PMOS transistor M7, a fifth PMOS transistor M8, a sixth PMOS transistor M9, a seventh PMOS transistor M10, an eighth PMOS transistor M11, a ninth PMOS transistor M14, a tenth PMOS transistor M15, an eleventh PMOS transistor M16, a twelfth PMOS transistor M17, a thirteenth PMOS transistor M18, a fourteenth PMOS transistor M19, a fifteenth PMOS transistor The transistor M20, the sixteenth PMOS transistor M21, the seventeenth PMOS transistor M24, the eighteenth PMOS transistor M25, the nineteenth PMOS transistor M28, the first NMOS transistor M3, the second NMOS transistor M4, the third NMOS transistor M5, the fourth NMOS transistor M6, the fifth NMOS transistor M12, the sixth NMOS transistor M13, the seventh NMOS transistor M22, the eighth NMOS transistor M23, the ninth NMOS transistor M26, the tenth NMOS transistor M27, the eleventh NMOS transistor M29, the twelfth NMOS transistor M30, the first PNP transistor Q1, and the second PNP transistor Q2.

[0020] The gate of the first PMOS transistor M0 is connected to the bias voltage VBIAS1, the source is connected to the power supply, and the drain is connected to the source of the second PMOS transistor M1 and the third PMOS transistor M2;

[0021] The gate of the second PMOS transistor M1 is connected to the control signal V+, and the drain and the gate of the first NMOS transistor M3 are connected to the control signal A. The gate of the third PMOS transistor M2 is connected to the control signal V-, and the drain and the gate of the second NMOS transistor M4 are connected to the control signal B.

[0022] The drain of the first NMOS transistor M3 and the drain of the second NMOS transistor M4 are connected to the ground;

[0023] The gate of the second PMOS transistor M7 is connected to the gate and drain of the third PMOS transistor M8, the source and the source of the third PMOS transistor are connected to the power supply, and the drain and the drain of the third NMOS transistor M5 are connected to the output VI;

[0024] The gates of the sixth PMOS transistor M9, the seventh PMOS transistor M10 and the eighth PMOS transistor M11 are grounded, the drain of the sixth PMOS transistor M9 is connected to the source of the seventh PMOS transistor M10, and the source is connected to the power supply;

[0025] The drain of the seventh PMOS transistor M10 is connected to the source of the eighth PMOS transistor M11;

[0026] The drain of the eighth PMOS transistor M11 and the drain of the fifth NMOS transistor M12 are connected to the gate of the sixth NMOS transistor M13, the source is grounded, and the gate is connected to the reference signal VREF;

[0027] The drain of the sixth NMOS transistor M13 is connected to the drain of the ninth PMOS transistor M14, and the source is grounded;

[0028] The gate of the ninth PMOS transistor M14 is connected to the gates of the tenth PMOS transistor M15 and the eleventh PMOS transistor M16; the source is connected to the source of the tenth PMOS transistor M15 and the eleventh PMOS transistor M16 and the power supply;

[0029] The drain of the tenth PMOS transistor M15 is connected to the voltage bias signal BIAS, and the drain of the eleventh PMOS transistor M16 is connected to the operational amplifier polarity signal VN;

[0030] The gate of the twelfth PMOS transistor M17 and the gates of the thirteenth PMOS transistor M18 and the fourteenth PMOS transistor M19 are connected to the low-pass filter signal VOUT, the source and the sources of the thirteenth PMOS transistor M18 and the fourteenth PMOS transistor M19 are connected to the power supply, and the drain is connected across the third capacitor CL and the fifth resistor R4 to the ground;

[0031] The drain of the thirteenth PMOS transistor M18, the third resistor R2 and the second resistor R1 are connected to the operational amplifier signal VP;

[0032] The drain of the fourteenth PMOS transistor M19, the second PNP transistor Q2 and the fourth resistor R3 are connected to the operational amplifier signal VN;

[0033] The second resistor R1 is connected to the emitter of the first PNP transistor Q1, and the base of the first PNP transistor Q1 and the base of the second PNP transistor Q2 are grounded;

[0034] The source of the fifteenth PMOS transistor M20 is connected to the source of the sixteenth PMOS transistor M21, the seventeenth PMOS transistor M24, and the eighteenth PMOS transistor M25, the gate is connected to the bias signal VBIAS1 along with the gates of the sixteenth PMOS transistor M21, the seventeenth PMOS transistor M24, and the eighteenth PMOS transistor M25, and the drain is connected to the gate of the seventh NMOS transistor M22 and the drain of the eighth NMOS transistor M23;

[0035] The drain of the sixteenth PMOS transistor M21 is connected to the drain of the seventh NMOS transistor M22;

[0036] The source of the seventh NMOS transistor M22 and the gate of the eighth NMOS transistor M23 are connected to the ground via the first resistor R0;

[0037] The drain of the seventeenth PMOS transistor M24 and the gates of the ninth NMOS transistor M26 and the tenth NMOS transistor M27 are connected to the bias signal VBISA2;

[0038] The source of the ninth NMOS transistor M26 and the source of the tenth NMOS transistor M27 are grounded;

[0039] The drain of the eighteenth PMOS transistor M25 and the gate and drain of the eleventh NMOS transistor M29 are connected to the bias signal VBIAS4;

[0040] The drain of the tenth NMOS transistor M27 is connected to the gate and drain of the nineteenth PMOS transistor M28 and the bias signal VBIAS3;

[0041] The source of the eleventh NMOS transistor M29 is connected to the source and drain of the twelfth NMOS transistor M30 , and the source of the twelfth NMOS transistor M30 is grounded.

[0042] Combine Figure 2 , the auxiliary operational amplifier circuit includes:

[0043] The first capacitor CB1, the second capacitor CC1, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixteenth switch S16, the seventeenth switch S17, the twentieth PMOS transistor M0A, the twenty-first PMOS transistor M1A, the twenty-second PMOS transistor M2A, the twenty-third PMOS transistor M3B, the twenty-fourth PMOS transistor M4B, the twenty-fifth PMOS transistor M0C, the twenty-sixth PMOS transistor M1C, the twenty-seventh PMOS transistor M2C, the the twenty-eighth PMOS transistor M3C, the twenty-ninth PMOS transistor M4C, the thirtieth PMOS transistor M5C, the thirty-first PMOS transistor M6C, the thirteenth NMOS transistor M3A, the fourteenth NMOS transistor M4A, the fifteenth NMOS transistor M0B, the sixteenth NMOS transistor M1B, the seventeenth NMOS transistor M2B, the eighteenth NMOS transistor M1B, the nineteenth NMOS transistor M7C, the twentieth NMOS transistor M8C, the twenty-first NMOS transistor M9C, and the twenty-second NMOS transistor M10C;

[0044] The gate of the 20th PMOS transistor M0A is connected to the bias voltage VBIAS1, the source is connected to the power supply, and the drain is connected to the source of the 21st PMOS transistor M1A and the 22nd PMOS transistor M2A;

[0045] The gate of the twenty-first PMOS transistor M1A and the left end of the first switch S1 are connected to the control signal VP, and the drain is connected to the gate and drain of the thirteenth NMOS transistor M3A;

[0046] The gate of the twenty-second PMOS transistor M2A is connected to the right end of the first switch S1 and the lower end of the second switch S2, and the drain is connected to the drains of the fourteenth NMOS transistor M4A, the fifteenth NMOS transistor M1B, and the twenty-third PMOS transistor M3B, and is also connected to the left ends of the third switch S3 and the fourth switch S4.

[0047] The drain of the thirteenth NMOS transistor M3A and the drain of the fourteenth NMOS transistor M4A are connected to the ground; the gate of the twenty-third PMOS transistor M3B and the gate and drain of the twenty-fourth PMOS transistor M4B are connected, and the source and the source of the twenty-fourth PMOS transistor M4B are connected to the power supply;

[0048] The gate of the sixteenth NMOS transistor M1B is grounded via the first capacitor CB1 and connected to the right end of the third switch S3, and the source and the source of the seventeenth NMOS transistor M2B are connected to the drain of the fifteenth NMOS transistor M0B;

[0049] The gate of the seventeenth NMOS transistor M2B and the source of the fifteenth NMOS transistor M0B are connected to the ground;

[0050] The gate of the fifteenth NMOS transistor M0B is connected to the bias voltage VBIAS2; the gate of the twenty-fifth PMOS transistor M0C is connected to the bias voltage VBIAS1, the source and the sources of the twenty-eighth PMOS transistor M3C and the twenty-ninth PMOS transistor M4C are connected to the power supply, and the drain is connected to the sources of the twenty-sixth PMOS transistor M1C and the twenty-seventh PMOS transistor M2C;

[0051] The gate of the twenty-sixth PMOS transistor M1C is connected to the right end of the fourth switch S4 and the left end of the fifth switch S5, and the drain is connected to the source of the nineteenth NMOS transistor M7C and the drain of the twenty-first NMOS transistor M9C;

[0052] The gate of the twenty-seventh PMOS transistor M2C is grounded via the second capacitor CC1 and connected to the left end of the sixteenth switch S16 , and the drain is connected to the source of the twentieth NMOS transistor M8C and the drain of the twenty-second NMOS transistor M10C;

[0053] The right end of the sixteenth switch is connected to the drains of the 31st PMOS transistor M6C and the 20th NMOS transistor M8C, and the right end is connected to the control signal VOUT; the right end of the fifth switch S5 is grounded;

[0054] The gate of the twenty-eighth PMOS transistor M3C and the gate of the twenty-ninth PMOS transistor M4C are connected to the drain of the thirtieth PMOS transistor M5C and the nineteenth NMOS transistor M7C, and the drain is connected to the source of the thirtieth PMOS transistor M5C.

[0055] The drain of the twenty-ninth PMOS transistor M4C is connected to the drain of the thirty-first PMOS transistor M6C; the gate of the thirty-first PMOS transistor M6C is connected to the gate of the twenty-ninth PMOS transistor M5C, and the drain is connected to the drain of the twentieth NMOS transistor M8C.

[0056] The gate of the nineteenth NMOS transistor M7C and the gate of the twentieth NMOS transistor M8C are connected to the bias voltage VBIAS4;

[0057] The gate of the twenty-first NMOS transistor M9C and the gate of the twenty-second NMOS transistor M10C are connected to the bias voltage VBIAS2 , and the source thereof and the source of the twenty-second NMOS transistor M10C are grounded.

[0058] Furthermore, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixteenth switch S16, and the seventeenth switch S17 are all connected to opposite signals F1 and F1-. The first switch S1, the third switch S3, and the fifth switch S5 are turned on when the gate control voltage F1- is a positive voltage, and otherwise the switches are turned off; the second switch S2 and the fourth switch S4 are turned on when the gate control voltage F1 is a positive voltage, and otherwise they are turned off.

[0059] Furthermore, the bias voltages VBIAS1 , VBIAS2 , VBIAS3 and VBIAS4 are generated by a voltage bias circuit.

[0060] Combine Figure 3 and Figure 4 , the chopper circuit comprises:

[0061] a third NMOS transistor M5, a fourth NMOS transistor M6, a sixth switch S6, a seventh switch S7, an eighth switch S8, a ninth switch S9, a tenth switch S10, an eleventh switch S11, a twelfth switch S12, a thirteenth switch S13, a fourteenth switch S14, a fifteenth switch S15, a fourth capacitor CS, and a fifth capacitor CH;

[0062] The left end of the fourteenth switch S14 is connected to the control signal VI, and the right end is connected to the left end of the fifteenth switch S15 and grounded through the fourth capacitor CS;

[0063] The fifteenth switch S15 is grounded via a fifth capacitor Ch;

[0064] The gate of the third NMOS transistor M5 is connected to the control signal C, and the source thereof and the source of the fourth NMOS transistor M6 are connected to the ground;

[0065] The gate of the fourth NMOS transistor M6 is connected to the control signal D;

[0066] The left end of the tenth switch S10 and the left end of the eleventh switch S11 are connected to the control signal A, and the right end of the tenth switch S10 and the right end of the twelfth switch S12 are connected to the control signal C;

[0067] The right end of the eleventh switch S11 and the right end of the thirteenth switch S13 are connected to the control signal d;

[0068] The left end of the thirteenth switch and the left end of the twelfth switch S12 are connected to the control signal B;

[0069] The left end of the sixth switch S6 is connected to the seventh switch S7 and the control signal V+, and the right end of the sixth switch S6 is connected to the eighth switch S8 and the control signal VP;

[0070] The right end of the seventh switch S7 and the right end of the ninth switch S9 are connected to the control signal VN;

[0071] The left end of the ninth switch S9 and the left end of the eighth switch S8 are connected to the control signal V−.

[0072] Furthermore, the sixth switch S6, the seventh switch S7, the eighth switch S8, the ninth switch S9, the tenth switch S10, the eleventh switch S11, the twelfth switch S12, and the thirteenth switch S13 are connected to opposite signals FC and FC-. The sixth switch S6 and the ninth switch S9, as well as the tenth switch S10 and the thirteenth switch S13, are turned on when the gate control voltage FC is high, and otherwise the switches are turned off. The seventh switch S7 and the eighth switch S8, as well as the eleventh switch S11 and the twelfth switch S12, are turned on when the gate control voltage FC- is high, and otherwise the switches are turned off.

[0073] Furthermore, the fourteenth switch S14 and the fifteenth switch S15 are connected to opposite signals FS and FS-. When the gate control signal FS of the fourteenth switch is high, the switch is turned on, otherwise the switch is turned off. When the gate control signal FS- of the fifteenth switch is high, the switch is turned on, otherwise the switch is turned off.

[0074] This circuit can ensure that its equivalent input offset voltage is reduced by an order of magnitude through chopper technology and auxiliary op amp offset cancellation circuit. The auxiliary op amp offset cancellation circuit also uses output and input storage technology to ensure the low input offset of the auxiliary op amp, thereby ensuring the accuracy of the output voltage of the bandgap reference circuit and providing a good bandgap reference for subsequent analog circuits.

[0075] Example

[0076] Figure 1 As shown in the figure, the startup circuit and voltage bias circuit ensure that the system is out of the degeneracy point after power-on and provide bias voltage for the auxiliary operational amplifier. The output voltage of the core operational amplifier circuit can be expressed as:

[0077]

[0078] like Figure 5 As shown, the first auxiliary transconductance amplifier G n1 With the second auxiliary transconductance amplifier G n2 The first auxiliary transconductance amplifier G is connected to the first main transconductance amplifier G1, and the third auxiliary operational amplifier A3 forms an auxiliary operational amplifier, and the first main operational amplifier A1 serves as the main operational amplifier. When F1 is low and F1- is high, the first switch S1 is turned on, the second switch S2 is turned off, the third switch S3 is turned on, the fourth switch S4 is turned off, the fifth switch S5 is turned on, the sixteenth switch S16 is turned on, and the seventeenth switch S17 is turned off. n1 With the second auxiliary transconductance amplifier G n2 Entering the storage phase, there is no signal path between the main op amp and the auxiliary op amp, and there are:

[0079] [V n1 G n1 +(V n2 -V c2 )G n2 ]R out1 =V out1

[0080] Since Vout1=Vc2 in the above formula, we have

[0081] V c2 =(V n1 G n1 R out1 +V n2 G n2 R out1 ) / (1+G n2 R out1 )

[0082] At this time, the third auxiliary operational amplifier A3 enters the storage stage, and at this time:

[0083] (V n3 -V c3 )A3=V out3

[0084] Since Vout3=Vc3 in the above formula, we have:

[0085]

[0086] When F1 is high and F1- is low, the first switch S1 is turned off, the second switch S2 is turned on, the third switch S3 is turned off, the fourth switch S4 is turned on, the fifth switch S5 is turned off, the sixteenth switch S16 is turned off, and the seventeenth switch S17 is turned on. n1 With the second auxiliary transconductance amplifier G n2Entering the signal operation stage, there is a signal path between the auxiliary op amp and the main op amp and there are:

[0087] [(V in +V n1 )G n1 +(V n2 -V c2 )G n2 ]R out1 =V out2

[0088] In the above formula, V c2 Bring in:

[0089]

[0090] Thus the first auxiliary transconductance amplifier G n1 With the second auxiliary transconductance amplifier G n2 The equivalent input offset voltage is effectively reduced. At this time, A3 enters the signal operation stage, and its input signal is the first auxiliary transconductance amplifier G n1 With the second auxiliary transconductance amplifier G n2 The output voltage Vout2 is:

[0091] V out3 =A3(V out2 +V n3 -V c3 )

[0092] Substituting Vc3 and Vout2 into the above formula, we can get:

[0093]

[0094] The overall gain of the auxiliary op amp is:

[0095] A v =G n1 R out1 A3

[0096] like Figure 2 As shown in FIG, the first auxiliary transconductance amplifier G n1 The gain of the first auxiliary transconductance amplifier A3 can be expressed as:

[0097]

[0098] like Figure 4In the example, when FC is high and FC- is low, the sixth switch S6 is turned on, the seventh switch S7 is turned off, the eighth switch S8 is turned off, the ninth switch S9 is turned on, the tenth switch S10 is turned on, the eleventh switch S11 is turned off, the twelfth switch S12 is turned off, and the thirteenth switch S13 is turned on. This means that control signal A is connected to control signal C, control signal B is connected to control signal D, control signal VN is connected to control signal V-, and control signal VP is connected to control signal V+. This enters the positive half-cycle of the chopper op amp. Conversely, when FC is low and FC- is high, the sixth switch S6 is turned off, the seventh switch S7 is turned on, the eighth switch S8 is turned on, the ninth switch S9 is turned off, the tenth switch S10 is turned off, the eleventh switch S11 is turned on, the twelfth switch S12 is turned on, and the thirteenth switch S13 is turned off. That is, control signal A is connected to control signal D, control signal B is connected to control signal C, control signal VN is connected to control signal V+, and control signal VP is connected to control signal V-, entering the negative half cycle of the chopper op amp. Thus, the offset of the main op amp A1 itself is eliminated by alternating cycles.

[0099] Through Figure 3 The first main operational amplifier A1 and the discrete-time low-pass filter shown can filter out the jitter after the chopper. The low-pass filter can provide a cutoff frequency of ω0 = (FSCS) / CH, and its cutoff frequency can be controlled by changing the off period of the fourteenth switch S14 and the fifteenth switch S15, effectively solving the problem of excessive resistance in the layout.

[0100] like Figure 5 The first auxiliary transconductance amplifier G n1 With the second auxiliary transconductance amplifier G n2 The third auxiliary operational amplifier A3 is used in parallel with the first main operational amplifier A1 to further reduce its equivalent input offset voltage in terms of magnitude. Due to the influence of the input offset voltage, the input offset voltage will be transmitted to the output end and multiplied by a coefficient of 1+C1 / C0, which will introduce a certain degree of accuracy. When the auxiliary operational amplifier is used, G n1 R out1 When A3>>A1, the input equivalent offset voltage is approximately:

[0101] (1+C1 / C0)(A1 / (G n1 R out1 A3))

[0102] It can be seen from the above formula that the offset voltage of the first main operational amplifier A1 can be reduced by an order of magnitude through the auxiliary operational amplifier and the chopper circuit described in this application.

Claims

1. A bandgap reference circuit for generating low input offset, characterized in that: Including bandgap reference circuit, auxiliary operational amplifier circuit and chopper circuit: The bandgap reference circuit includes a startup circuit, a bandgap reference core circuit, and a voltage bias circuit. The startup circuit is used to prevent a degeneracy point. The bandgap reference core circuit is used to generate a voltage with a zero temperature coefficient. The voltage bias circuit is used to provide a bias voltage for the main operational amplifier. The auxiliary operational amplifier circuit includes a polarity variable transconductance amplifier, which is used to reduce the voltage input offset; The chopping circuit includes a discrete time low-pass filter and a polarity conversion switch; The discrete-time low-pass filter is used to filter out the high-frequency signal of the reference output, and the polarity conversion switch is used to complete the positive and negative polarity conversion of the transconductance amplifier; The auxiliary operational amplifier circuit comprises: a first capacitor CB1, a second capacitor CC1, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixteenth switch S16, a seventeenth switch S17, a twentieth PMOS transistor M0A, a twenty-first PMOS transistor M1A, a twenty-second PMOS transistor M2A, a twenty-third PMOS transistor M3B, a twenty-fourth PMOS transistor M4B, a twenty-fifth PMOS transistor M0C, a twenty-sixth PMOS transistor M1C, a twenty-seventh PMOS transistor M2C, a twenty-eighth PMOS transistor M3C, a twenty-ninth PMOS transistor M4C, a thirtieth PMOS transistor M5C, a thirty-first PMOS transistor M6C, a thirteenth NMOS transistor M3A, a fourteenth NMOS transistor M4A, a fifteenth NMOS transistor M0B, a sixteenth NMOS transistor M1B, a seventeenth NMOS transistor M2B, a nineteenth NMOS transistor M7C, a twentieth NMOS transistor M8C, a twenty-first NMOS transistor M9C, and a twenty-second NMOS transistor M10C; The gate of the 20th PMOS transistor M0A is connected to the bias voltage VBIAS1, the source is connected to the power supply, and the drain is connected to the source of the 21st PMOS transistor M1A and the 22nd PMOS transistor M2A; The gate of the twenty-first PMOS transistor M1A and the left end of the first switch S1 are connected to the control signal VP, and the drain is connected to the gate and drain of the thirteenth NMOS transistor M3A; The gate of the twenty-second PMOS transistor M2A is connected to the right end of the first switch S1 and the lower end of the second switch S2, and the drain is connected to the drains of the fourteenth NMOS transistor M4A, the fifteenth NMOS transistor M1B, and the twenty-third PMOS transistor M3B, and is also connected to the left end of the third switch S3 and the left end of the fourth switch S4. The drain of the thirteenth NMOS transistor M3A and the drain of the fourteenth NMOS transistor M4A are connected to the ground; the gate of the twenty-third PMOS transistor M3B and the gate and drain of the twenty-fourth PMOS transistor M4B are connected, and the source and the source of the twenty-fourth PMOS transistor M4B are connected to the power supply; The gate of the sixteenth NMOS transistor M1B is grounded via the first capacitor CB1 and connected to the right end of the third switch S3, and the source and the source of the seventeenth NMOS transistor M2B are connected to the drain of the fifteenth NMOS transistor M0B; The gate of the seventeenth NMOS transistor M2B and the source of the fifteenth NMOS transistor M0B are connected to the ground; The gate of the fifteenth NMOS transistor M0B is connected to the bias voltage VBIAS2; the gate of the twenty-fifth PMOS transistor M0C is connected to the bias voltage VBIAS1, the source and the sources of the twenty-eighth PMOS transistor M3C and the twenty-ninth PMOS transistor M4C are connected to the power supply, and the drain is connected to the sources of the twenty-sixth PMOS transistor M1C and the twenty-seventh PMOS transistor M2C; The gate of the twenty-sixth PMOS transistor M1C is connected to the right end of the fourth switch S4 and the left end of the fifth switch S5, and the drain is connected to the source of the nineteenth NMOS transistor M7C and the drain of the twenty-first NMOS transistor M9C; The gate of the twenty-seventh PMOS transistor M2C is grounded via the second capacitor CC1 and connected to the left end of the sixteenth switch S16 , and the drain is connected to the source of the twentieth NMOS transistor M8C and the drain of the twenty-second NMOS transistor M10C; The right end of the sixteenth switch S16 is connected to the drain of the 31st PMOS transistor M6C, the drain of the 20th NMOS transistor M8C, and the left end of the seventeenth switch S17. The right end of the seventeenth switch S17 is connected to the control signal VOUT. The right end of the fifth switch S5 is grounded. The gate of the twenty-eighth PMOS transistor M3C and the gate of the twenty-ninth PMOS transistor M4C are connected to the drain of the thirtieth PMOS transistor M5C and the drain of the nineteenth NMOS transistor M7C, and the drain is connected to the source of the thirtieth PMOS transistor M5C. The drain of the twenty-ninth PMOS transistor M4C is connected to the drain of the thirty-first PMOS transistor M6C; the gate of the thirty-first PMOS transistor M6C and the gate of the twenty-ninth PMOS transistor M5C are connected to the bias voltage VBIAS3, and the drain is connected to the drain of the twentieth NMOS transistor M8C; The gate of the nineteenth NMOS transistor M7C and the gate of the twentieth NMOS transistor M8C are connected to the bias voltage VBIAS4; The gate of the twenty-first NMOS transistor M9C and the gate of the twenty-second NMOS transistor M10C are connected to the bias voltage VBIAS2 , and the source thereof and the source of the twenty-second NMOS transistor M10C are grounded.

2. The bandgap reference circuit for generating low input offset according to claim 1, wherein: The second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixteenth switch S16, and the seventeenth switch S17 are all connected to opposite signals F1 and F1-. The first switch S1, the third switch S3, and the fifth switch S5 are turned on when the gate control voltage F1- is a positive voltage, and are turned off otherwise. The second switch S2 and the fourth switch S4 are turned on when the gate control voltage F1 is a positive voltage, and are turned off otherwise.

3. The bandgap reference circuit for generating low input offset according to claim 1, wherein: The bias voltages VBIAS1 , VBIAS2 , VBIAS3 and VBIAS4 are generated by a voltage bias circuit.

4. The bandgap reference circuit for generating low input offset according to claim 1, wherein: The chopper circuit comprises: a third NMOS transistor M5, a fourth NMOS transistor M6, a sixth switch S6, a seventh switch S7, an eighth switch S8, a ninth switch S9, a tenth switch S10, an eleventh switch S11, a twelfth switch S12, a thirteenth switch S13, a fourteenth switch S14, a fifteenth switch S15, a fourth capacitor CS, and a fifth capacitor CH; The left end of the fourteenth switch S14 is connected to the control signal VI, and the right end is connected to the left end of the fifteenth switch S15 and grounded through the fourth capacitor CS; The fifteenth switch S15 is grounded via the fifth capacitor CH; The gate of the third NMOS transistor M5 is connected to the control signal C, and the source thereof and the source of the fourth NMOS transistor M6 are connected to the ground; The gate of the fourth NMOS transistor M6 is connected to the control signal D; The left end of the tenth switch S10 and the left end of the eleventh switch S11 are connected to the control signal A, and the right end of the tenth switch S10 and the right end of the twelfth switch S12 are connected to the control signal C; The right end of the eleventh switch S11 and the right end of the thirteenth switch S13 are connected to the control signal D; The left end of the thirteenth switch S13 and the left end of the twelfth switch S12 are connected to the control signal B; The left end of the sixth switch S6 and the left end of the seventh switch S7 are connected to the control signal V+, and the right end of the sixth switch S6 and the right end of the eighth switch S8 are connected to the control signal VP; The right end of the seventh switch S7 and the right end of the ninth switch S9 are connected to the control signal VN; The left end of the ninth switch S9 and the left end of the eighth switch S8 are connected to the control signal V-.

5. The bandgap reference circuit for generating low input offset according to claim 4, wherein: The sixth switch S6, the seventh switch S7, the eighth switch S8, the ninth switch S9, the tenth switch S10, the eleventh switch S11, the twelfth switch S12, and the thirteenth switch S13 are connected to opposite signals FC and FC-. The sixth switch S6 and the ninth switch S9, as well as the tenth switch S10 and the thirteenth switch S13, are turned on when the gate control voltage FC is high, and are turned off otherwise. The seventh switch S7 and the eighth switch S8, as well as the eleventh switch S11 and the twelfth switch S12 are turned on when the gate control voltage FC- is high, and are turned off otherwise.

6. The bandgap reference circuit for generating low input offset according to claim 4, wherein: The fourteenth switch S14 and the fifteenth switch S15 are connected to opposite signals FS and FS-. When the gate control signal FS of the fourteenth switch S14 is high, the switch is turned on, otherwise the switch is turned off. When the gate control signal FS- of the fifteenth switch S15 is high, the switch is turned on, otherwise the switch is turned off.

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