Switching modulator implementing power cycling

Abstract

A controller for a switched modulator receives an input voltage and generates a regulated output voltage. The controller activates a buck control circuit to generate a regulated output voltage having a first voltage value less than the input voltage. The controller activates a boost control circuit to return charge stored on an output capacitor at an output node to an input node to drive the regulated output voltage to a second voltage value lower than the first voltage value. In some embodiments, in response to a command indicating that the controller is to allow the output voltage to decay, the controller operates in a boost mode, using the boost control circuit to circulate the stored charge at the output node while reducing the output voltage.

Description

TECHNICAL FIELD

[0001] The present invention relates to a circuit and method for a switching modulator, and more particularly, to a switching modulator that implements power cycling. BACKGROUND

[0002] Electronic systems such as notebook computers typically include a power management integrated circuit for regulating the power usage of the electronic system. In addition, the electronic systems typically employ a voltage regulator to convert a main bus voltage of the system power supply to one or more voltages required to drive the integrated circuits therein. For example, a 5-volt power supply provided to an electronic system can need to be reduced to 1.8 volts to drive an integrated circuit in the electronic system. Portable computing devices, such as notebook computers or laptops, include a processor (or microcontroller) and local memory, which are coupled to components and execute embedded software to perform certain tasks. In effect, the processor power is provided by a voltage regulator that converts an input voltage of the power supply to a voltage value specified for the processor.

[0003] A switching power supply or switching regulator, also known as a DC-to-DC converter, is a type of voltage regulator that is typically used to convert an input power supply voltage to a desired output voltage at a selected voltage level for an integrated circuit. In one example, a 12V or 5V power supply voltage provided to power an embedded processor can be reduced to 1V or 0.9V. A switching regulator provides power supply functionality through low-loss elements (such as capacitors, inductors, and transformers) and power switches that are turned on and off to transfer energy from the input to the output in the form of discrete packets. A feedback control circuit is used to regulate the energy transfer to maintain a constant output voltage within the desired load limits of the circuit.

[0004] Some switching regulators employ pulse width modulation (PWM) to control the duty cycle of the power switches. That is, by adjusting the pulse width, the on-time of the power switches can be controlled at a given fixed or variable frequency. A switching regulator employing PWM control includes a PWM controller or modulator that drives a power block including the power switches, a drive circuit for the power switches, and an LC filter circuit. In some cases, the switching regulator is a single-phase converter and the PWM controller generates a single-phase PWM signal to drive a single-phase power block. In other cases, the switching regulator is a multi-phase converter and a multi-phase PWM controller generates switching signals having different phase shifts to drive a multi-phase power block, with each PWM signal driving a corresponding power block unit. A multi-phase PWM controller is required when the voltage regulator must provide high power levels in a thin form factor solution, or when high conversion efficiency needs to be maintained over a wide range of load conditions.

[0005] In some applications, the host system commands the switch regulator to output a specific voltage value (e.g., 1V) of the output voltage to drive an integrated circuit, such as a processor. When the processor is not in use, the host system can further command the switch regulator to reduce the output voltage. When the command is to ramp down, sometimes the switch regulator is instructed to stop switching the power switch and allow the output voltage to self-discharge or decay, typically to 0V. SUMMARY

[0006] A controller for a switch regulator configured to receive an input voltage and produce a regulated output voltage on an output node for driving a load, the controller comprising: a buck control circuit configured to receive a first error signal indicative of a difference between a feedback voltage indicative of the regulated output voltage and a reference voltage, the buck control circuit generating a first PWM signal to drive a power stage receiving the input voltage on an input node and delivering a first phase current through an inductor to the output node, the output node connected with an output capacitor and the load, the buck control circuit generating the first PWM signal to drive the regulated output voltage to a first voltage value lower than the input voltage; and a boost control circuit configured to receive a second error signal indicative of at least a sensed current of a current flowing through the power stage, the boost control circuit configured to generate a second pulse width modulation (PWM) signal to drive the power stage to cause a second phase current to flow from the output node to the input node to return charge stored on the output capacitor to the input node to drive the regulated output voltage to a second voltage value lower than the first voltage value, wherein in response to a first command, the buck control circuit is activated to produce the regulated output voltage having the first voltage value; and in response to a second command, the boost control circuit is activated to return charge at the output node stored on the output capacitor to the input node and drive the output voltage value to the second voltage value.

[0007] wherein a first error amplifier is configured to receive the feedback voltage indicative of the regulated output voltage and the reference voltage and generate the first error signal indicative of a difference between the feedback voltage and the reference voltage; and a second error amplifier is configured to receive the current sense signal indicative of the current flowing in the power stage and generate the second error signal indicative of the current sense signal.

[0008] wherein the controller comprises a multiphase controller, each of the buck control circuit and the boost control circuit generating a plurality of pulse width modulated (PWM) signals for driving a plurality of power stages in a plurality of phases, each power stage receiving an input voltage and delivering phase current through a respective inductor to an output node to which an output capacitor and a load are connected, the plurality of PWM signals being generated in response to respective error signals.

[0009] wherein each of the first and second PWM signals comprises a rising ramp portion and a falling ramp portion, and wherein: the buck control circuit is configured to generate the first PWM signal to adjust the rising ramp portion of the first PWM signal to cause the first phase current to flow from the input node to the output node to charge the inductor, the buck control circuit generating the falling ramp portion of the first PWM signal to deliver charge stored in the inductor to the output capacitor to output a first voltage value; and the boost control circuit is configured to generate the second PWM signal to adjust the falling ramp portion of the first PWM signal to cause the second phase current to flow from the output node to the input node, the boost control circuit returning charge stored in the output capacitor to the input node and driving the output node to a second voltage value.

[0010] wherein the power stage comprises an upper power switch and a lower power switch connected in series between the input node and a ground potential, the upper power switch and the lower power switch being controlled by the respective first or second PWM signal, the upper ramp portion of the PWM signal turning on the upper power switch, the lower ramp portion of the PWM signal turning on the lower power switch.

[0011] wherein the buck control circuit generates the first PWM signal to turn on the upper power switch to cause the first phase current to flow from the input voltage to the inductor and to turn on the lower power switch to deliver charge stored in the inductor to the output capacitor to generate a regulated output voltage having a first voltage value; and wherein the boost control circuit generates the second PWM signal to turn on the lower power switch to cause the second phase current to flow from the output voltage to the inductor and to turn on the upper power switch to deliver charge stored in the inductor to the input node to return charge stored in the output capacitor to the output node.

[0012] wherein the second command comprises a decay command instructing the controller to ramp down the regulated output voltage to the second voltage value, and in response to the second command, the controller activates the boost control circuit to return charge stored on the output capacitor to the input node while driving the regulated output voltage to the second voltage value.

[0013] wherein, during the charge cycle period in which the boost control circuit is activated to return stored charge from the output capacitor, the controller responds to an input command or request by providing a state indicator that the switch modulator is in the decay state even though the switch modulator is performing charge cycling.

[0014] wherein, in response to stored charge being returned to the input node and the output voltage being driven to a second voltage value, the boost control circuit is deactivated and the controller operates the switch modulator in a predetermined operating mode.

[0015] wherein, during the charge cycle period, the controller receives a first command indicative of an operating mode intended for use after the decay state, and the controller stores the first command in a memory; and after the charge cycle period is complete, the controller operates the switch modulator in the intended operating mode according to the first command stored in the memory.

[0016] wherein, during the charge cycle period in which the boost control circuit is activated to return stored charge from the output capacitor, the controller receives an input command and responds to the input command as if the switch modulator were in the decay state even though the switch modulator is performing charge cycling.

[0017] wherein, the controller stores in a memory an input command received during the charge cycle period; and after the charge cycle period is complete, the controller operates the switch modulator according to the command stored in the memory.

[0018] wherein, the second voltage value comprises 0V or a voltage value less than the first voltage value.

[0019] wherein, the boost control circuit generates a second PWM signal to control a rate of charge delivery from the output node to the input node.

[0020] The present invention also discloses a method in a controller for a switch modulator configured to receive an input voltage on an input node and generate a regulated output voltage on an output node for driving a load, the method comprising: receiving a first command to set the regulated output voltage to a first voltage value less than the input voltage; configuring the controller to operate in a buck mode to regulate an output voltage on the output node to the first voltage value; receiving a second command to ramp down the voltage at the output node to a second voltage value less than the first voltage value; and configuring the controller to operate in a boost mode to return stored charge on the output node to the input node.

[0021] wherein the controller is configured to operate in the buck mode to regulate the output voltage at the output node to the first voltage value includes receiving a first error signal indicative of a difference between a feedback voltage representative of the regulated output voltage and a reference voltage, and generating a first pulse width modulated (PWM) signal for driving a power stage to generate the regulated output voltage having the first voltage value, the power stage receiving the input voltage at the input node and delivering a first phase current through an inductor to an output capacitor and the output node to which a load is connected.

[0022] wherein the controller is configured to operate in the boost mode to return stored charge at the output node to the input node includes receiving a second error signal indicative of at least a current sense signal related to a current flowing in the power stage, and generating a second pulse width modulated (PWM) signal for driving the power stage to cause a second phase current to flow from the output node to the input node to return charge stored on the output capacitor to the input node to drive the voltage at the output node to the second voltage value.

[0023] wherein the controller includes a multiphase controller and generating the first or second PWM signal each includes generating a plurality of pulse width modulated (PWM) signals, each power stage receiving the input voltage and delivering a phase current through a corresponding inductor to an output capacitor and an output node to which a load is connected, the plurality of PWM signals being generated in response to corresponding error signals.

[0024] wherein each of the first PWM signal and the second PWM signal includes a rising ramp portion and a falling ramp portion, and wherein: generating the first PWM signal for driving the power stage includes adjusting the rising ramp portion of the first PWM signal to cause a first phase current to flow from the input node to the output node to store charge in the inductor, and generating the falling ramp portion of the first PWM signal to deliver the charge stored in the inductor to the output capacitor to regulate the output to the first voltage value; and generating the second PWM signal for driving the power stage includes adjusting the falling ramp portion of the first PWM signal to cause a second phase current to flow from the output node to the input node to return charge stored in the output capacitor to the input node and to drive the output node to the second voltage value.

[0025] wherein generating the second PWM signal includes generating the second PWM signal to control a rate of charge transfer from the output node to the input node.

[0026] wherein the second command includes a decay command to instruct the controller to ramp down the regulated output voltage to the third voltage value, the method further comprising: in response to receiving the second command and while the controller is configured to operate in the boost mode, during a charge cycle period to return stored charge to the input node.

[0027] wherein further comprising: in response to receiving the second command, storing in a state memory a state indicator indicating that the switching regulator is in the decay state; using the state indicator stored in the state memory to respond to input commands or requests during the charge cycle period.

[0028] wherein further comprising: in response to returning the stored charge between the input node and the output voltage being driven to the second voltage value, clearing the state indicator in the state memory and configuring the controller to operate in a predetermined operating mode.

[0029] wherein further comprising: in response to receiving a first command indicating an intended operating mode to use after the decay state, storing the first command in the state memory; and operating the switching regulator in the intended operating mode according to the first command stored in the memory after the charge cycle period is completed.

[0030] wherein further comprising: during the charge cycle, receiving input commands and responding to the input commands as if the switching regulator were in the decay state even though the switching regulator is in the middle of a charge cycle.

[0031] wherein further comprising: storing in a memory input commands received during the charge cycle period; and operating the switching regulator according to the commands stored in the memory after the charge cycle period is completed.

[0032] wherein the second voltage value includes 0V or a voltage value less than the first voltage value. BRIEF DESCRIPTION OF DRAWINGS

[0033] The following detailed description and accompanying drawings provide a further understanding of various embodiments of the application.

[0034] Figure 1 shows a schematic diagram of a switching regulator in some examples.

[0035] Figure 2 shows a schematic diagram of a multi-phase switching regulator in some examples.

[0036] Figure 3 shows waveforms for an output voltage and an input current for a switching regulator in some examples.

[0037] Figure 4FIG. 1 shows waveforms of output voltage and input current for a switching regulator in accordance with an embodiment of the present application.

[0038] Figure 5 FIG. 2 shows a flowchart of a power recycling method that can be implemented in a switching regulator in accordance with an embodiment of the present application.

[0039] Figure 6 FIG. 3 shows a schematic diagram of a switching regulator incorporating power recycling in accordance with an embodiment of the present application.

[0040] Figure 7A and 7B FIG. 4 shows signal waveforms of switching output voltage and inductor current for a buck mode and a boost mode in accordance with an embodiment of the present application.

[0041] Figure 8 FIG. 5 shows a schematic diagram of a switching regulator incorporating power recycling in accordance with an alternative embodiment of the present application. DETAILED DESCRIPTION

[0042] In accordance with an embodiment of the present application, a controller for a switching regulator that receives an input voltage and generates a modulated output voltage includes a buck control circuit and a boost control circuit. The controller activates the buck control circuit to generate the modulated output voltage having a first voltage value that is less than the input voltage. The controller activates the boost control circuit to return charge stored on an output capacitor at an output node to an input node, thereby driving the modulated output voltage to a second voltage value that is lower than the first voltage value. In some embodiments, the controller operates in a buck mode using the buck control circuit to generate the modulated output voltage in normal operation. In response to a command instructing the controller to allow the output voltage to decay, the controller operates in a boost mode using the boost control circuit to recycle the stored charge at the output node while allowing the output voltage to ramp down more quickly due to the active relocation of the stored charge.

[0043] A significant feature of the switching regulator described in the present application is that the controller can operate in a boost mode to recycle charge that would otherwise be lost due to load leakage current. In a conventional switching regulator, when instructed to allow the output voltage to self-discharge or decay, the controller simply stops switching the power switch, and the charge stored at the output node is eventually dissipated by the leakage path at the load. In contrast, the switching regulator of the present application actively controls the output voltage ramp-down process by recycling the charge stored at the output node back to the input node. The recycled charge can be used to extend battery life and generally improve the energy efficiency of an electronic system incorporating the switching regulator.

[0044] Figure 1 FIG. 1 shows waveforms of output voltage and input current for a switching regulator in accordance with an embodiment of the present application. Figure 1The switching modulator in the circuit uses pulse width modulation (PWM) to control the duty cycle of the power switch. That is, by adjusting the pulse width, the on-time of the power switch can be controlled at a given fixed or variable frequency. PWM-controlled switching modulators include PWM controllers or PWM modulators used to drive a power switch, a power switch drive circuit, and... LC Power supply block for the filter circuit. (Reference) Figure 1 The switching modulator 10 includes a coupled controller 22 for driving a power block, which includes a power stage 11 with an associated output inductor L1 and an output capacitor C. OUT More specifically, the switching modulator 10 receives the input voltage V at the input node 12. IN And generate a modulated output voltage V at output node 18. OUT Load 20 is provided. Controller 22 provides a PWM signal to drive power stage 11. Power stage 11 includes a pair of power switches M1 and M2 connected in series, which are alternately turned on and off by the PWM signal to reference a target voltage V. TARG (Also known as reference voltage) Modulated output voltage V OUT Specifically, power switches M1 and M2 in power stage 11 are alternately turned on and off to generate a switching output voltage V at switching output node 14. SW The output inductor L1 is coupled to the switching output node 14 of power stage 11 and the output capacitor C. OUT Between (node ​​18). Output inductor L1 and output capacitor C OUT An LC circuit is formed to supply current to output node 18 while maintaining a substantially constant output voltage V. OUT Then, the output voltage V OUT It can be used to drive a load of 20.

[0045] Switching modulator 10 executes a feedback control loop to modulate the output voltage V. OUT Therefore, the controller 22 receives an indication modulated output voltage V at output node 18 or load 20. OUT Feedback voltage V FB In some examples, the feedback voltage V FB It is the output voltage V OUT The step-down voltage. For example, the feedback voltage V. FB It can be generated by a voltage divider including resistors R1 and R2, with common node 16 providing the divided output voltage as feedback voltage V. FB The controller 22 also receives a reference voltage or a target voltage V. TARGindicating the voltage value required at the modulated output voltage or feedback point. In some examples, the target voltage can be represented by a voltage identification code that signals the required modulator output voltage. For example, in certain applications, the system implements voltage positioning where the target voltage varies with the load, i.e., target Vout = required Vout - R*load, where R is a fixed value. When voltage positioning is performed, the controller 22 can receive a voltage identification (VID) code that tells the modulator what output voltage it should provide. Each VID code is associated with a voltage value. A decoder (not shown in the figure) decodes the code to generate the target voltage, which is often further adjusted in real time according to the real-time load to provide an analog output impedance.

[0046] The controller 22 includes circuitry for implementing a feedback control loop for the switching modulator to generate a PWM signal to drive the power stage 11. In particular, the controller 22 includes an error amplifier 24 for comparing a feedback voltage V FB with a target voltage V TARG to generate a compensated control loop error signal V COMP . The error signal V COMP may be a voltage signal or a current signal. For example, the error amplifier 24 produces an output current that can be converted to a voltage signal by a loop filter 25 coupled to the output of the error amplifier 24. The error signal V COMP is provided to a PWM control circuit 26, which can include circuitry such as a modulator comparator and a latch circuit to generate a PWM signal. The PWM signal is coupled to drive circuits DRV1 and DRV2 to drive the respective power switches M1 and M2. In one example, the PWM signal is inverted at the drive circuit DRV2 to drive the lower power switch M2. In this way, the upper power switch M1 and the lower power switch M2 are alternately turned on and off by the PWM signal.

[0047] In the present example, the switching modulator 10 is configured as a buck modulator to reduce the input voltage V IN to generate an output voltage V OUT with a voltage value lower than the input voltage. The controller 22 generates a PWM signal with a rising slope portion and a falling slope portion. The rising slope portion of the PWM signal turns on the upper power switch M1 to allow a phase current to flow from the input voltage node 12 to the inductor L1. The inductor L2 stores the charge from the phase current. The falling slope portion of the PWM signal turns on the lower power switch M2 to transfer the stored charge in the inductor L1 to the output capacitor C OUT . The switching output voltage V SW switches between the input voltage V IN and ground potential and is determined by the inductor L1 and the output capacitor COUT formed LC The filter circuit generates a modulated output voltage with substantially constant amplitude.

[0048] Figure 1 The illustrated switch modulator 10 represents a single-phase voltage modulator. In other examples, the switch modulator can be implemented as a multi-phase voltage modulator. Figure 2 is a schematic diagram of a multi-phase switch modulator in some examples. Reference is made to Figure 2 , the multi-phase switch modulator 30 includes a multi-phase controller 42 that generates a set of PWM signals for driving the multi-phase power block 31. In the present example, the multi-phase power block 31 includes three power stages 1-3 having respective associated output inductors L1-L3 connected between respective switch output nodes (V SW1 -V SW3 ) and an output capacitor C OUT connected to an output node 38 to provide an output voltage V OUT The output voltage V OUT is available to drive a load 40.

[0049] The multi-phase controller 42 receives a feedback voltage V FB and a reference voltage V TARG and generates a set of PWM signals PWM1, PWM2, PWM3 having different phases to drive the respective power stages 1, 2, and 3. The multi-phase controller 41 enables the switch modulator 30 to provide a modulated output voltage with high accuracy over a wide range of load conditions.

[0050] The power recycling circuits and methods described herein can be applied to a single-phase switch modulator, such as the switch modulator 10 of Figure 1 , or a multi-phase switch modulator (such as the switch modulator 30 of Figure 2 ). A single-phase switch modulator includes a single-phase PWM modulator or controller that generates a single-phase PWM signal to drive a single-phase power block. A multi-phase switch modulator includes a multi-phase PWM modulator or controller that generates PWM signals having different phase shifts to drive a multi-phase power block, each PWM signal driving a respective power stage in the power block. The power recycling circuits and methods described herein can be incorporated in a single-phase modulator or a multi-phase modulator to recycle charge from an output node to an input node. The specific configuration of the switch modulator is not critical to the practice of the present invention. For ease of discussion, the following description refers to a single-phase switch modulator.

[0051] In certain applications, electronic systems can employ a switching regulator to generate a cycling output voltage. For example, switching regulators are commonly used in electronic systems to power a processor, microprocessor, CPU, or GPU. The switching regulator can receive an input voltage of 12V and can step down or buck the input voltage to a modulated output voltage of 0.9V. The system can command the switching regulator to generate a target output voltage while the processor is in use, and then allow the output voltage to self-discharge or decay while the processor is not in use. Figure 3 Output voltage and input current waveforms of a switching regulator are illustrated by way of example. Reference is made to Figure 3 During a time duration TD1, the output voltage V OUT rises to a target voltage. The input current (curve 46) is drawn from the input voltage. During a time duration TD2, the output voltage V OUT is modulated to the target voltage. The switching regulator modulates the output voltage V OUT by alternately turning on and off the upper and lower power switches. Thus, the upper power switch is periodically turned on and out of phase with the lower switch to provide an appropriate amount of current from the input voltage to power the load, which can vary, for example, during the time duration TD2. At some point in time, the output voltage is no longer needed and the switching regulator stops switching the power switches, and the output voltage V OUT， ramps down or decreases, for example, during a time duration TD3.

[0052] During operation of the electronic system, the output voltage V OUT may repeatedly cycle from a low voltage state (e.g., 0V) to a high voltage state (e.g., 0.9V) to drive the load, and then allow to decay when the load is not in use. In a conventional switching regulator, the self-discharge or decay of the output voltage is achieved by the controller stopping the switching of the power switches and allowing any stored charge at the output voltage to dissipate to ground (e.g., through leakage current in the load). The output voltage will then decay or decrease to the ground voltage. In practice, the output voltage of the switching regulator can repeatedly cycle - i.e., rise and then fall - multiple times during operation. Each time the output voltage falls, any remaining energy at the output node dissipates to ground and is wasted.

[0053] In embodiments of the present invention, a power cycling circuit and method is implemented in the switching regulator to cycle the portion of the charge that would otherwise dissipate to ground when the output voltage falls to the input voltage node. In this way, the unused energy is cycled and the output voltage falls faster compared to a self-discharge process based on leakage current alone. Figure 4 Output voltage and input current waveforms of a switching regulator are illustrated by way of example. Reference is made to Figure 4 During a time duration TD1, the output voltage V OUT(Plot 47) rises to the target voltage. The input current (Plot 48) is drawn from the input voltage. At the output voltage V OUT During the period when the output voltage is regulated to the target voltage, the switch modulator regulates the output voltage V OUT by alternately turning on and off the upper and lower power switches. For example, during a time duration TD2, the upper power switch is periodically turned on, out of phase with the lower switch, to provide an appropriate amount of current from the input voltage to power the load, which can vary. At some point in time, for example, during a time duration TD3, the output voltage is no longer needed. In this case, the switch modulator activates the power recycling by returning the charge at the output node to the input voltage node, where the output voltage is ramped down. In Figure 4 , the input current I IN is shown with a negative current pulse, which represents the charge return or recycling to the input voltage node.

[0054] When the switch modulator implements the power recycling circuit and method of the present invention, the switch modulator can achieve overall power savings by recycling the portion of energy that would otherwise be lost when the output voltage is ramped down. In a switch regulator with a large output capacitor, the amount of recycled energy can be a significant portion of the total input energy. The switch regulator incorporating the power recycling circuit and method of the present invention achieves a significant advantage over conventional switch regulators by improving energy utilization. In particular, when the input voltage is supplied by a battery, the switch regulator with the power recycling function can improve or extend the battery life.

[0055] Figure 5 A flowchart of the power recycling method that can be implemented in a switch modulator in an embodiment of the present invention is shown. In some examples, the power recycling method can be implemented in a single-phase switch regulator or a multi-phase switch regulator, such as the switch regulator shown in Figure 1 and Figure 2 . Referring to Figure 5 , when a command (52) is received from a host, the power recycling method 50 implemented in the switch regulator is initiated. In this specification, the host refers to an electronic system that contains the switch modulator. The command can be a normal operation command (54) instructing the switch modulator to set the output voltage to a target voltage. In this case, the power recycling method 50 configures the controller of the switch modulator to operate in a buck mode to step down the input voltage to generate the output voltage (56). The controller operates in the buck mode to regulate the output voltage to the target voltage. In practice, the buck mode is the main mode of operation of the switch regulator. The regulated output voltage is used to power a load, such as a processor. The power recycling method 50 continues to receive commands (52) from the host.

[0056] In another case, the command received from the host is a decay command (58) instructing the switch regulator to ramp down the output voltage. In this case, the power cycling method 50 configures the controller of the switch regulator to operate in a boost mode to cycle charge from the output voltage node to the input voltage node (60). At the same time, the power cycling method 50 continues to receive commands from the host (52).

[0057] More specifically, the decay command instructs the switch regulator to enter a decay mode whereby the switch regulator stops switching the power switch (i.e., stops turning the power switch on and off) and allows the output voltage on the output voltage node to decay or ramp down to a predetermined voltage value, such as 0 V. When the switch regulator stops switching, the output voltage is not supplied by the input voltage, and the output voltage will ramp down over time, typically through a leakage current at the load, as shown. The charge stored at the output voltage node (typically on an output capacitor) will dissipate through the leakage path in the load to ground. The ramp down of the output voltage can take a long time. Figure 3

[0058] In embodiments of the invention, the power cycling method 50 does not self-discharge or decay the output voltage in response to the decay command. Instead, the power cycling method 50 configures the controller to operate in a boost mode so that the switch regulator actively relocates the charge stored at the output voltage node. That is, the power cycling method 50 actively cycles the charge stored at the output voltage node (e.g., on an output capacitor). Rather than simply dissipating to ground, the stored charge is actively recirculated from the output voltage node to the input voltage node. In the case of a battery power source for the input voltage, the cycling of the charge has the effect of replenishing the battery power, thereby extending the battery power life.

[0059] In certain applications, when the host issues a decay command to the switch regulator, there can be various reporting requirements at the switch regulator during the decay mode to decay or self-discharge the output voltage (sometimes referred to as a “decay period”), or the switch regulator can need to respond differently to temporary commands based on whether it is in the decay period. A switch regulator implementing the power cycling method of the invention will need to provide appropriate responses to such reporting requirements or commands to avoid confusing the host system. That is, when the host system commands a decay operation, the switch regulator needs to report that it is in the decay state or behaves as if in the decay mode, even if it is actually performing charge cycling. For example, the host system can issue a command to change the switching mode of the switch regulator. If the switch regulator is in the decay mode, the switch regulator will ignore the command. In another example, the commands can also affect the mode of operation required by the switch regulator at the end of the ramp down period, and thus, the switch regulator needs to remember the command so as to know what mode to enter at the end of the output voltage ramp down.​

[0060] In embodiments of the application, the power cycling method 50 implements state reporting and command response to ensure that the switch modulator provides the correct state indicators that meet the reporting requirements and command response of the host system. Specifically, the charge cycling operation in the power cycling method 50 is performed covertly, that is, without the host's knowledge. Thus, the power cycling method 50 will provide state reporting as if the switch modulator were executing a decay command issued by the host, will respond to further commands received during the power cycle as if it were in a decay mode, and will exit from the hidden mode to the correct state. In other words, when the power cycling method 50 is implemented and a decay command is received, the switch modulator operates in a boost mode to perform the charge cycle, but the switch modulator will report to the host that it is decaying or self-discharging the output voltage. Similarly, if a command is received during a period when the switch modulator is supposed to be decaying the output voltage but is actually secretly cycling, the switch modulator will hold a memory of the received command to know what should happen at the end of the decay period, and then the switch modulator can exit the cycling mode into the correct state.

[0061] Still referring to Figure 5 In one embodiment, the power cycling method 50 stores a decay state indicator in a state memory (62). The state indicator stored in the state memory will be used for any reporting or response functions. The decay state indicator is stored when the charge cycle is in progress (64). When the charge cycle is complete, the power cycling method 50 places the switch modulator in the intended mode of operation to exit the decay command so that the switch modulator will be in a state consistent with having executed the decay command (66). The power cycling method 50 also clears the state memory (68). The switch modulator is essentially in an idle state, waiting for further commands to be received from the host (52). In this way, the power cycling method ensures that the switch modulator reports the decay state indicator when queried even while the switch modulator is cycling the charge, and the power cycling method further ensures that the switch modulator is in the intended mode of operation after the charge cycle.

[0062] Notably, the state indicator stored in the state memory can also be used to respond to incoming commands or requests during the power cycle. Referring to Figure 5 , the switch modulator can receive another command while performing the charge cycle (70). The power cycling method 50 stores the received command in the state memory (72). Thus, the switch modulator can respond to the incoming command by using the command stored in the state memory as if it were in a decay state. In this way, the switch modulator provides the expected response to the host to ensure seamless operation.

[0063] As described above, during the operation of the switching modulator, the host can command the switching modulator to ramp up the output voltage to the target voltage and repeatedly decay the output voltage over multiple cycles. By circulating charge each time the output voltage is commanded to self-discharge or decay, the system can circulate a large amount of energy that would otherwise be lost when the output voltage is only allowed to dissipate to ground. When the output capacitor C OUT With a large capacitance, the energy of the cycle can be significant.

[0064] Figure 6 This diagram illustrates a switching modulator including a power cycle in an embodiment of the present invention. (See reference) Figure 6 The switching modulator 100 includes a controller 120 coupled to drive a power block, the power block including an associated output inductor L1 and an output capacitor C. OUT The power stage 101. More specifically, the switching modulator 100 receives the input voltage V at the input node 102. IN And generate a regulated output voltage V at output node 108. OUT This is to supply power to the load (not shown in the figure). Controller 120 provides a PWM signal to drive power stage 101. Power stage 101 includes a pair of power switches M1 and M2 connected in series, which are alternately turned on and off by the PWM signal to reference the target voltage V. TARG The output voltage VOUT is regulated (also known as the reference voltage). Specifically, power switches M1 and M2 in power stage 101 are alternately switched on and off to generate a switching output voltage VSW at switching output node 104. Output inductor L1 is coupled to switching output node 104 of power stage 101 and output capacitor C. OUT (Output node 108). Output inductor L1 and output capacitor C OUT form LC The circuit is used to supply current to output node 108. Then, the output voltage V... OUT It can be used to drive loads.

[0065] In some embodiments, the PWM signal is coupled to driver circuits DRV1 and DRV2 to drive the corresponding power switches M1 and M2. In some examples, the PWM signal is inverted at one driver circuit (e.g., driver circuit DRV2 for driving the lower power switch M2). In this way, the upper power switch M1 and the lower power switch M2 are alternately turned on and off by the PWM signal. Figure 6 In the embodiment shown, the controller 120 generates a pair of PWM signals PWM1 and PWM2 respectively coupled to the drive circuits DRV1 and DRV2, for driving the upper power switch M1 and the lower power switch M2 respectively.

[0066] In embodiments of the application, the controller 120 in the switch modulator 100 implements power cycling. To this end, the controller 120 includes a buck control circuit 122 that operates in a main operating mode to reduce the input voltage V IN , generating a regulated output voltage V TARG having a voltage value indicated by a target voltage V OUT . To support power cycling, the controller 120 also includes a boost control circuit 124 that operates in response to a fade command to cycle charge from the output node 108. In the present embodiment, a selector 128 is used to select between the buck and boost control circuits. The selector 128 is controllable by a cycle select signal to select the PWM signal generated by either the buck control circuit 122 during the main operating mode or the boost control circuit 124 during the cycle operating mode. In one example, the cycle select signal is related to the fade command and is asserted to select the boost control circuit 124 in response to receiving a fade command from a host. The recirculated charge back to the input node 102 does not change the input voltage V IN , but rather adds to the stored energy (e.g., when the input voltage source is a battery power source).

[0067] The switch modulator 100 implements a feedback control loop to regulate the output voltage V OUT . In the present embodiment, the controller 120 receives a feedback voltage V OUT at the output node 108 or load indicative of the regulated output voltage V FB . In some examples, the feedback voltage V FB is a reduced voltage of the output voltage V OUT . For example, the feedback voltage V FB may be generated by a voltage divider (not shown). The controller 120 also receives a reference voltage or target voltage V TARG indicative of a voltage value required for the regulated output voltage. In the present embodiment, the controller 120 further receives a current sense signal CS as a feedback signal. The current sense signal CS represents a current flowing in the power stage, for example, the current flowing through the lower power switch M2. In one embodiment, the buck control circuit 122 operates in the feedback control loop using the feedback voltage V FB . Meanwhile, the boost control circuit 124 operates in the feedback control loop using the current sense signal CS to regulate the current level, controlling the charge cycling.

[0068] In embodiments of the application, the controller 120 further includes a state memory 126 for storing a state indicator and an intended state or mode of operation that the switch modulator should exit after discharging or decaying the output voltage. The state memory 126 supports the reporting and control functions of the switch modulator 100. When a decay command is received and the controller 120 is performing a charge cycle, the state memory 126 stores a decay state indicator. In this way, the switch modulator 100 can report a decay state to an external host system, rather than a decayed or ramped down output voltage, even though the controller 120 is actually performing a charge cycle. When the charge recovery operation is complete, the state memory 126 clears the decay state indicator and the controller 120 reports the intended mode of operation after the decay period, where the intended mode of operation is stored in the state memory 126.

[0069] With such a configuration, the controller 120 includes a buck control circuit 122 for reducing the input voltage in order to generate a primary mode of operation of the output voltage and a boost control circuit 124 for a power cycle mode of operation to cycle stored charge at the output voltage node back to the input voltage node. The switch modulator 100 described in the present application, including the buck control circuit and the boost control circuit, is different from a conventional buck-boost switching regulator. To be specific, a conventional buck-boost switching regulator regulates the output voltage by adjusting the PWM signal at the up-ramp and the down-ramp. That is, a conventional buck-boost switching regulator regulates the output voltage when current flows from the input voltage node to the output voltage node and when current flows from the output voltage node to the input voltage node.

[0070] In contrast, the switch modulator 100 includes a controller that regulates the output voltage for current flowing out of the output voltage node and current flowing into the output voltage node, respectively. More specifically, in some embodiments, the buck control circuit 122 of the controller 120 controls the up-ramp of the PWM signal that regulates the output voltage when current flows from the input voltage node to the output voltage node. At the same time, the boost control circuit 124 of the controller 120 controls the down-ramp of the PWM signal that regulates the output voltage when current flows from the output voltage node to the input voltage node. In this way, the controller 120 controls the transfer of stored charge from the output node 108, e.g., stored charge on the output capacitor COUT, to the input node 102. The boost control circuit 124 generates a PWM signal to control the rate of charge delivery from the output voltage node to the input voltage node such that the charge is recycled to the input voltage node in a controlled manner. In other words, the rate of charge cycling or return is controlled by the boost control circuit 124.

[0071] Reference is made to Figure 7A and 7Bto further explain the operation of the controller 120 in the buck mode and the boost mode. Figure 7A and 7B The signal waveforms of the switch output voltage and the inductor current in the buck mode and the boost mode are shown in the embodiments of the present application. Referring to Figure 6 and Figure 7A and 7B The PWM signal generated by the buck control circuit or the boost control circuit is a sawtooth signal waveform, including a rising slope portion and a falling slope portion. The rising slope portion turns on the upper power switch Ml and turns off the lower power switch M2. The falling slope portion turns on the lower power switch Ml and turns off the upper power switch M2. During the rising slope portion of the PWM signal, the upper power switch is on, and the switch output voltage VSW (node 104) is driven to the input voltage V IN During the falling slope portion of the PWM signal, the lower power switch is on, and the switch output voltage V SW is driven to the ground voltage.

[0072] Figure 7A The buck mode operation is illustrated. In the buck mode operation, the buck control circuit 122 regulates the rising slope portion of the PWM signal that connects the switch output voltage V SW (curve 130) to the input voltage V IN , and ramps up the inductor current IL (curve 132) from the input voltage node to the inductor. The inductor current IL stores charge in the inductor LI. During the falling slope portion of the PWM signal, the switch output voltage V SW switches to the ground voltage, and the inductor voltage IL falls, transferring charge to the output capacitor C OUT to maintain the regulated output voltage.

[0073] Figure 7B The boost mode operation is illustrated. In the boost mode operation, the boost control circuit 124 regulates the falling slope portion of the PWM signal that connects the switch output voltage V SW (curve 134) to the ground voltage, and ramps up the inductor current IL (curve 136) from the output voltage node to the inductor. The negative inductor current IL removes charge from the output capacitor C OUT and stores charge in the inductor LI. During the rising slope portion of the PWM signal, the switch output voltage V SW switches to the input voltage V IN , and the inductor voltage IL ramps down, transferring charge to the input node 102 to recycle the charge stored on the output node 108.

[0074] Figure 8 A schematic diagram of a switch modulator with power recycling in an alternative embodiment of the present application is shown. In particular, Figure 8The detailed structure of the controller in the switching regulator of Figure 6 is explained. Figure 6 Similar elements in Figure 8 are given the same reference numbers and will not be discussed further. As shown in Figure 8 , the switch modulator 200 includes a controller 220 that implements power recycling. The controller 220 includes a buck control circuit 228 to implement the main operating mode of bucking or reducing the input voltage V IN . The controller 220 also includes a boost control circuit 230 to implement the secondary operating mode of boosting the output voltage V OUT in the event that the output voltage V

[0075] In the present embodiment, the buck control circuit 228 operates under a voltage feedback control scheme. To this end, a feedback voltage V FB (e.g., generated by a voltage divider of resistors Rl and R2) is fed back to the controller 220. The controller 220 includes an error amplifier 222 to receive the feedback voltage V VB and a reference voltage V TARG . The error amplifier 222 compares the feedback voltage V FB to the reference voltage V TARG to generate a control loop error signal V COMPa . The error signal V COMPa may be a voltage signal or a current signal. For example, the error amplifier 222 generates an output current that can be converted to a voltage signal by a loop filter 223 coupled to the output of the error amplifier 221. The error signal V COMPa is provided to the buck control circuit 228, which generates a PWM signal. In the present embodiment, the buck control circuit 228 generates a PWM signal PWMhs-bk for the upper power switch Ml and a PWM voltage PWMls-bk for the lower power switch M2.

[0076] In the present embodiment, the boost control circuit 230 operates under a current feedback control scheme. To this end, a current sense signal CS (e.g., generated by sensing the current at the output node V SW 104 or the lower power switch M2) is fed back to the controller 220 to generate a control loop error signal V COMPb . The error signal V COMPb may be a voltage signal or a current signal. For example, the error amplifier 224 generates an output current that can be converted to a voltage signal by a loop filter 225 coupled to the output of the error amplifier 222. The error signal V COMPbThe boost control circuit 230 is provided with the current feedback signal, and generates PWM signals for the upper power switch Ml and the lower power switch M2. The boost control circuit 230 generates a PWM signal PWMhs-bt for the upper power switch Ml and a PWM signal PWMls-bt for the lower power switch M2.

[0077] In the present specification, the boost control circuit 230 operates under a current feedback control scheme. In other embodiments, the boost control circuit 230 can operate under a voltage feedback control scheme or a combination of current and voltage feedback control strategies. The particular feedback control scheme used by the boost control circuit 230 is not critical to the practice of the present application.

[0078] In the present embodiment, the controller 220 includes multiplexers 231 and 232 for selecting the PWM signals from either the buck control circuit 228 or the boost control circuit 230. The multiplexer 231 selects between the PWM signal PWMhs-bk and the PWM signal PWMhs-bt as the PWM signal PWMl for driving the upper power switch Ml. The multiplexer 232 selects between the PWM signal PWMls-bk and the PWM signal PWMls-bt as the PWM signal PWM2 for driving the lower power switch M2. A cycle selection signal (node 234) is used to select the respective PWM signals. For example, the cycle selection signal has a first logic state for selecting the PWM signal generated by the buck control circuit 228 and a second logic state for selecting the pulse width modulated signal generated by the boost control circuit 230. In one embodiment, the cycle selection signal is related to the fade command, and has the first logic state when no fade command is received.

[0079] With this configuration, the switch modulator 200 includes the controller 220 that implements charge recycling. In normal operation, the switch modulator 200 activates the buck control circuit to generate a regulated output voltage from the input voltage to supply the load. When the switch modulator 200 receives a fade command, the controller 220 activates the boost control circuit 230 to operate the power switches in a boost mode to recycle or return the charge stored in the output node 108 (e.g., output capacitor C OUT The output voltage V OUT is driven to a predetermined voltage level specified by the fade command (e.g., 0 V or a voltage value other than 0 V).

[0080] In alternative embodiments of the invention, the switching regulator uses a boost control circuit to operate in a boost mode to produce a regulated output voltage having a first voltage value greater than an input voltage. In this case, the controller activates a buck control circuit to return charge stored on an output capacitor at an output node to an input node to drive the regulated output voltage to a second voltage value lower than the first voltage value. More specifically, the controller uses the boost control circuit to operate in a boost mode to produce the regulated output voltage in normal operation. In response to a command indicating that the controller is to allow the output voltage to decay, the controller uses the buck control circuit to operate in a buck mode to circulate the stored charge at the output node while allowing the output voltage to ramp down more quickly due to the active relocation of the stored charge. At the same time, the switching regulator includes a state memory to enable the switching regulator to report a decay state while it is performing charge recovery and to exit to an expected mode of operation after the charge recovery operation is complete.

[0081] In other embodiments of the invention, the switching regulator operates in an operating mode that is different from a command operating mode of the input command. The switching regulator stores an expected command in a memory and uses the memory to track and respond to queries or requests based on the expected command.

[0082] The invention can be implemented in a number of ways, including as a method; an apparatus; a system; a composition of matter; a computer program product stored on a computer readable storage medium; as hardware such as a hardware processor or processor device configured to execute instructions stored on a processor and / or provided by a memory coupled to the processor. In this specification, these implementations, or any other form that the invention can take, can be referred to as techniques. Generally, the order of the steps disclosed in the methods of the invention can be changed.

[0083] A detailed description of one or more embodiments of the invention is provided above along with accompanying figures that illustrate the principles of the invention. The invention is described in connection with such embodiments, but the invention is not limited to any embodiment. The scope of the invention is limited only by the claims and the invention encompasses numerous alternatives, modifications and equivalents. Numerous specific details are set forth in the description in order to provide a thorough understanding of the invention. These details are provided for the purpose of example and the invention can be practiced according to the claims without some or all of these details. For the purpose of clarity, technical material that is known in the technical fields related to the invention has not been described in detail so that the invention is not unnecessarily obscured.

[0084] The detailed description provided above is for the purpose of illustrating the particular embodiments of the invention and not for the purpose of limiting the invention. Many modifications and variations of the present invention are possible in light of the above teachings. The scope of the invention is defined by the following claims.

Claims

1. A controller for a switching modulator configured to receive an input voltage and generate a regulated output voltage at an output node for driving a load, the controller comprising: A buck control circuit is configured to receive a first error signal indicating the difference between a feedback voltage and a reference voltage for the regulated output voltage. The buck control circuit generates a first PWM signal to drive a power stage that receives the input voltage at an input node and transmits a first phase current to an output node through an inductor. The output node is connected to an output capacitor and a load. The buck control circuit generates the first PWM signal to drive the regulated output voltage to a first voltage value lower than the input voltage. as well as A boost control circuit is configured to receive a second error signal indicating at least some relation to the current flowing through the power stage, the boost control circuit being configured to generate a second PWM signal to drive the power stage such that a second phase current flows from the output node to the input node, returning charge stored on the output capacitor to the input node, thereby reducing the regulated output voltage to a second voltage value below a first voltage value. In response to the first command, the buck control circuit is activated to generate the first PWM signal to drive the power stage to generate an regulated output voltage having the first voltage value. In response to the second command, the boost control circuit is activated to generate a second PWM signal to drive the power stage to return the charge stored on the output capacitor at the output node to the input node and reduce the regulated output voltage at the output node to the second voltage value. The second command includes a decay command, which instructs the controller to ramp down the regulated output voltage to the second voltage value, and in response to the second command, the controller activates the boost control circuit to return the charge stored on the output capacitor to the input node, while driving the regulated output voltage to the second voltage value; During the charge cycle when the boost control circuit is activated to return the stored charge from the output capacitor, the controller responds to input commands or requests by providing a status indicator that the switch modulator is in a decaying state, even though the switch modulator is performing a charge cycle.

2. The controller as claimed in claim 1, further comprising: A first error amplifier is configured to receive a feedback voltage and a reference voltage indicating the regulated output voltage and to generate a first error signal indicating the difference between the feedback voltage and the reference voltage. as well as A second error amplifier is configured to receive the induced current, which indicates the current flowing in the power stage, and to generate a second error signal indicating the induced current.

3. The controller of claim 1, wherein the controller comprises a multiphase controller, each of the buck control circuit and the boost control circuit generates a plurality of PWM signals for driving a plurality of power stages in a plurality of phases, each power stage receiving an input voltage and transmitting a phase current to an output node connected to an output capacitor and a load via a corresponding inductor, the plurality of PWM signals being generated in response to a corresponding error signal.

4. The controller of claim 1, wherein each of the first and second PWM signals includes a rising ramp portion and a falling ramp portion, and wherein: The buck control circuit is configured to generate the first PWM signal to adjust the rising ramp portion of the first PWM signal so that the first phase current flows from the input node to the output node to charge the inductor, and the buck control circuit generates the falling ramp portion of the first PWM signal to deliver the energy stored in the inductor to the output capacitor to adjust the output node to the first voltage value. as well as The boost control circuit is configured to generate the second PWM signal to adjust the falling slope portion of the second PWM signal so that the second phase current flows from the output node to the input node, thereby transferring the charge stored in the output capacitor to the inductor. The boost control circuit is configured to generate the rising ramp portion of the second PWM signal to deliver the energy stored in the inductor to the input node, thereby returning the charge stored in the output capacitor to the input node and driving the output node to the second voltage value.

5. The controller of claim 4, wherein the power stage includes an upper power switch and a lower power switch connected in series between the input node and ground potential, the upper power switch and the lower power switch being controlled by a corresponding first or second PWM signal to alternately turn on and off, thereby generating a switch output voltage at the switch output node, an inductor being connected between the switch output node and the output node, the upper ramp portion of the PWM signal turning on the upper power switch, and the lower ramp portion of the PWM signal turning on the lower power switch.

6. The controller of claim 5, wherein the buck control circuit generates a first PWM signal to turn on the upper power switch, causing the first phase current to flow from the input voltage to the inductor, and turns on the lower power switch to transfer the energy stored in the inductor to the output capacitor, thereby generating an regulated output voltage having a first voltage value; and wherein the boost control circuit generates a second PWM signal to turn on the lower power switch, causing the second phase current to flow from the output voltage to the inductor, and turns on the upper power switch to deliver the energy stored in the inductor to the input node, thereby returning the charge stored in the output capacitor to the input node.

7. The controller of claim 1, wherein in response to the stored charge being returned to the input node and the output voltage being driven to the second voltage value, the boost control circuit is deactivated and the controller operates the switching modulator in a predetermined operating mode.

8. The controller of claim 7, wherein during the charge cycle, the controller receives a first command indicating an operating mode to be used after the decay state, and the controller stores the first command in a memory; and after the charge cycle is completed, the controller operates the switching modulator in the expected operating mode according to the first command stored in the memory.

9. The controller of claim 1, wherein during a charge cycle in which the boost control circuit is activated to return stored charge from the output capacitor, the controller receives and responds to an input command as if the switch modulator were in a decay state, even though the switch modulator is performing a charge cycle.

10. The controller of claim 9, wherein the controller stores input commands received during the charge cycle in a memory; and after the charge cycle is completed, the controller operates the switching modulator according to the commands stored in the memory.

11. The controller of claim 1, wherein the second voltage value includes 0V or a voltage value less than the first voltage value.

12. The controller of claim 1, wherein the boost control circuit generates a second PWM signal to control the charge delivery rate from the output node to the input node.

13. A method in a controller for a switching modulator, the switching modulator being configured to receive an input voltage at an input node and generate a regulated output voltage at an output node for driving a load, the method comprising: Receive a first command to set the regulated output voltage to a first voltage value that is less than the input voltage; The controller is configured to operate in buck mode to generate a first PWM signal in response to a first error signal, thereby driving the power stage to adjust the output voltage at the output node to the first voltage value, wherein the first error signal indicates the difference between the feedback voltage of the adjusted output voltage and a reference voltage; The controller receives a second command to ramp down the voltage at the output node to a second voltage value less than the first voltage value, the second command including an attenuation command to instruct the controller to ramp down the regulated output voltage to the second voltage value; The controller is configured to operate in boost mode to generate a second PWM signal in response to a second error signal, thereby driving the power stage to return the charge stored on the output node to the input node while reducing the voltage at the output node to the second voltage value, wherein the second error signal indicates at least the induced current of the current flowing in the power stage; In response to receiving the second command, and during a charge cycle in which the controller is configured to return the stored charge to the input node in boost mode, the incoming command or request is responded to by providing a status indicator that the switching modulator is in a decay state.

14. The method of claim 13, wherein the controller is configured to operate in the buck mode to generate the first PWM signal in response to the first error signal, thereby driving the power stage to adjust the output voltage at the output node to the first voltage value, comprising: The first PWM signal is generated to drive the power stage to generate an regulated output voltage with the first voltage value. The power stage receives the input voltage at the input node and transmits the first phase current to the output capacitor and the output node to which the load is connected through an inductor.

15. The method of claim 14, wherein the controller is configured to operate in the boost mode to generate a second PWM signal in response to a second error signal, for driving the power stage to return the charge stored at the output node to the input node, while simultaneously reducing the voltage at the output node to the second voltage value, comprising: The second PWM signal is generated to drive the power stage so that the second phase current flows from the output node to the input node to return the charge stored on the output capacitor to the input node, thereby reducing the voltage at the output node to the second voltage value.

16. The method of claim 15, wherein the controller comprises a multiphase controller and generates the first or second PWM signal, each comprising generating a plurality of pulse width modulation (PWM) signals for driving a plurality of power stages in a plurality of phases, each power stage receiving an input voltage and transmitting a phase current through a corresponding inductor to an output node connected to an output capacitor and a load, the plurality of PWM signals being generated in response to a corresponding error signal.

17. The method of claim 15, wherein each of the first PWM signal and the second PWM signal includes a rising ramp portion and a falling ramp portion, and wherein: Generating a first PWM signal for driving a power stage includes adjusting a rising ramp portion of the first PWM signal to allow a first phase current to flow from an input node to an output node to store energy in an inductor, and generating a falling ramp portion of the first PWM signal to transfer the energy stored in the inductor to an output capacitor to adjust the output node to the first voltage value. as well as Generating the second PWM signal for driving the power stage includes adjusting the falling slope portion of the second PWM signal to cause the second phase current to flow from the output node to the input node, returning the charge stored in the output capacitor to the input node, and driving the output node to the second voltage value.

18. The method of claim 15, wherein generating the second PWM signal comprises: The second PWM signal is generated to control the charge transfer rate from the output node to the input node.

19. The method of claim 13, further comprising: In response to receiving the second command, a state indicator indicating that the switching modulator is in the attenuation state is stored in the state memory; Use state indicators stored in the state memory to respond to commands or requests that come in during the charge cycle.

20. The method of claim 19, further comprising: In response to the stored energy returning to the input node and the output voltage being driven to the second voltage value, the state indicator in the state memory is cleared, and the controller is configured to operate in a predetermined operating mode.

21. The method of claim 20, further comprising: In response to receiving a first command indicating the expected operating mode to be used after the decay state, the first command is stored in the state memory; as well as After the charge cycle is completed, the switch modulator operates in the expected operating mode according to the first command stored in the memory.

22. The method of claim 13, further comprising: During a charge cycle, the input command is received and responded to, as if the switching modulator were in a decaying state, even though the switching modulator is performing a charge cycle operation.

23. The method of claim 22, further comprising: The commands received during the charge cycle are stored in the memory; And after the charge cycle is completed, the switching modulator is operated according to the commands stored in the memory.

24. The method of claim 13, wherein the second voltage value includes 0V or a voltage value less than the first voltage value.

25. A controller for a switching modulator configured to receive an input voltage and generate a regulated output voltage at an output node for driving a load, the controller comprising: A buck control circuit is configured to receive a first error signal indicating the difference between a feedback voltage and a reference voltage for the regulated output voltage. The buck control circuit generates a first PWM signal to drive a power stage that receives the input voltage at an input node and transmits a first phase current to an output node through an inductor. The output node is connected to an output capacitor and a load. The buck control circuit generates the first PWM signal to drive the regulated output voltage to a first voltage value lower than the input voltage. as well as A boost control circuit is configured to receive a second error signal indicating at least some relation to the current flowing through the power stage, the boost control circuit being configured to generate a second PWM signal to drive the power stage such that a second phase current flows from the output node to the input node, returning charge stored on the output capacitor to the input node, thereby reducing the regulated output voltage to a second voltage value below a first voltage value. In response to the first command, the buck control circuit is activated to generate the first PWM signal to drive the power stage to generate an regulated output voltage having the first voltage value. In response to the second command, the boost control circuit is activated to generate a second PWM signal to drive the power stage to return the charge stored on the output capacitor at the output node to the input node and reduce the regulated output voltage at the output node to the second voltage value. The second command includes a decay command, which instructs the controller to ramp down the regulated output voltage to the second voltage value, and in response to the second command, the controller activates the boost control circuit to return the charge stored on the output capacitor to the input node, while driving the regulated output voltage to the second voltage value; During the charge cycle in which the boost control circuit is activated to return the stored charge from the output capacitor to the input node, the controller receives and responds to the input command as if the switch modulator were in a decay state, even though the switch modulator is performing a charge cycle.

26. The controller of claim 25, wherein the controller stores commands received during a charge cycle in a memory; and after the charge cycle is completed, the controller operates the switching modulator according to the commands stored in the memory.

27. The controller of claim 25, wherein during the charge cycle, wherein when the boost control circuit is activated to return the stored charge from the output capacitor, the controller provides a status indicator in response to an input command or request indicating that the switch controller is in a decay state, even if the switch controller is performing a charging cycle.

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