Wafer bonding structure and method of forming the same

Abstract

The application provides a wafer bonding structure and a forming method thereof. The structure comprises: a bottom wafer, a second dielectric layer is formed on the surface of the bottom wafer, a second metal layer and a second metal bonding mark are formed in the second dielectric layer; a third dielectric layer is located on the surface of the second dielectric layer, a first redistribution layer is formed in the third dielectric layer, the first redistribution layer extends to the second dielectric layer and is electrically connected to the second metal layer; a functional wafer, a first dielectric layer is formed on the second surface of the functional wafer, a second redistribution layer and a first metal bonding mark are formed in the first dielectric layer; the first dielectric layer of the functional wafer and the third dielectric layer of the bottom wafer are aligned and bonded through the first metal bonding mark and the second metal bonding mark. The application provides a wafer bonding structure and a forming method thereof, which can improve the wafer alignment accuracy without affecting the process complexity.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a wafer bonding structure and a method for forming the same. Background Technology

[0002] Currently, there are generally two wafer alignment schemes in wafer bonding processes. One scheme is notch alignment, which uses the wafer's built-in notch as an alignment reference. However, this scheme has lower alignment accuracy, especially after multilayer wafer bonding, which can affect the electrical connections between wafers. The other scheme uses specific bonding marks for wafer alignment, which has higher alignment accuracy, but the alignment accuracy is more dependent on the clarity of the alignment marks.

[0003] Current alignment markers include metallic bonding markers and non-metallic bonding markers. Metallic bonding markers are completely opaque, thus offering high contrast during bonding, easy identification, and high alignment accuracy. Non-metallic bonding markers, on the other hand, are formed by etching trenches in the dielectric layer, utilizing differences in dielectric layer thickness to create identifiable marks. Therefore, the clarity and alignment accuracy of non-metallic bonding markers are related to their etching depth and dielectric layer thickness.

[0004] However, current bonding requirements for functional wafers necessitate minimizing the total thickness variation (TTV) on the wafer surface to ensure successful wafer bonding. Reducing TTV necessitates multiple ceramic mechanical polishing (CMP) processes, which decreases the thickness of the dielectric layer and consequently affects the alignment accuracy of non-metallic bonding marks. Therefore, a more efficient and reliable technical solution is needed. Summary of the Invention

[0005] This application provides a wafer bonding structure and a method for forming the same, which can improve wafer alignment accuracy without affecting process complexity.

[0006] One aspect of this application provides a method for forming a wafer bonding structure, comprising: providing a carrier wafer and a functional wafer for bonding, wherein a first side of the functional wafer is bonded to the first side of the carrier wafer; forming a first dielectric layer on a second side of the functional wafer, and forming a second redistribution layer and a first metal bonding mark in the first dielectric layer, wherein the first metal bonding mark is formed during the fabrication of the first redistribution layer; providing a bottom wafer, wherein a second dielectric layer is formed on the surface of the bottom wafer, and a second metal layer and a second metal bonding mark are formed in the second dielectric layer; forming a third dielectric layer on the surface of the second dielectric layer; forming a first redistribution layer in the third dielectric layer that penetrates the third dielectric layer, extends to the second dielectric layer, and is electrically connected to the second metal layer; aligning the functional wafer and the bottom wafer through the first metal bonding mark and the second metal bonding mark, bonding the first dielectric layer of the functional wafer and the third dielectric layer of the bottom wafer, and electrically connecting the first redistribution layer and the second redistribution layer; and removing the carrier wafer.

[0007] In some embodiments of this application, a method for forming a first dielectric layer on the second side of the functional wafer and forming a second redistribution layer and a first metal bonding mark in the first dielectric layer includes: forming a first dielectric layer on the second side of the functional wafer; forming a first opening and a second opening in the first dielectric layer; depositing a metal material layer on the surface of the first dielectric layer and in the first and second openings; grinding the metal material layer to expose the first dielectric layer; and forming a second redistribution layer and a first metal bonding mark in the first opening and the second opening, respectively.

[0008] In some embodiments of this application, the second metal bonding mark is formed during the process of fabricating the second metal layer.

[0009] In some embodiments of this application, the first metal bonding mark is located on the cleaving track, and the second metal bonding mark is located on the cleaving track.

[0010] In some embodiments of this application, a buffer layer and an etch stop layer are sequentially formed between the second side of the functional wafer and the first dielectric layer.

[0011] In some embodiments of this application, a functional dielectric layer is further formed on the first side of the functional wafer, and a first metal layer is further formed in the functional dielectric layer.

[0012] In some embodiments of this application, the method further includes: forming a through-silicon via (TSV) structure that penetrates the functional dielectric layer and the functional wafer and extends into the first dielectric layer to electrically connect the second redistribution layer; forming a third redistribution layer in the functional dielectric layer to electrically connect the first metal layer; providing a stacked wafer, a first side of which has a stacked dielectric layer formed, a fourth redistribution layer and a third metal bonding mark formed in the stacked dielectric layer, wherein the third metal bonding mark is formed in the process of fabricating the fourth redistribution layer; aligning and bonding the stacked wafer and the functional wafer through the third metal bonding mark and the first metal bonding mark, wherein the fourth redistribution layer electrically connects the third redistribution layer and the TSV structure.

[0013] Another aspect of this application provides a wafer bonding structure, comprising: a bottom wafer, wherein a second dielectric layer is formed on the surface of the bottom wafer, and a second metal layer and a second metal bonding mark are formed in the second dielectric layer; a third dielectric layer, located on the surface of the second dielectric layer, wherein a first redistribution layer is formed in the third dielectric layer, penetrating the third dielectric layer and extending to the second dielectric layer and electrically connected to the second metal layer; and a functional wafer, wherein a first dielectric layer is formed on a second side of the functional wafer, and a second redistribution layer and a first metal bonding mark are formed in the first dielectric layer; the first dielectric layer of the functional wafer and the third dielectric layer of the bottom wafer are aligned and bonded through the first metal bonding mark and the second metal bonding mark, wherein the first redistribution layer and the second redistribution layer are electrically connected.

[0014] In some embodiments of this application, the first metal bonding mark is located on the cleaving track, and the second metal bonding mark is located on the cleaving track.

[0015] In some embodiments of this application, a buffer layer and an etch stop layer are sequentially formed between the second side of the functional wafer and the first dielectric layer.

[0016] In some embodiments of this application, a functional dielectric layer is further formed on the first side of the functional wafer, and a first metal layer is further formed in the functional dielectric layer.

[0017] In some embodiments of this application, the structure further includes: a through-silicon via (TSV) structure penetrating the functional dielectric layer and the functional wafer and extending into the first dielectric layer to electrically connect the second redistribution layer; a third redistribution layer located in the functional dielectric layer and electrically connected to the first metal layer; a stacked wafer having a stacked dielectric layer formed on a first side, a fourth redistribution layer and a third metal bonding mark formed in the stacked dielectric layer; the stacked wafer and the functional wafer being aligned and bonded through the third metal bonding mark and the first metal bonding mark, wherein the fourth redistribution layer is electrically connected to the third redistribution layer and the TSV structure.

[0018] This application provides a wafer bonding structure and a method for forming the same, in which a first redistribution layer originally located on the bottom wafer is formed on a functional wafer, and a first metal bonding mark is formed simultaneously when the first redistribution layer is formed, which can improve wafer alignment accuracy without affecting process complexity. Attached Figure Description

[0019] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein: Figure 1 This is a flowchart of the method for forming the wafer bonding structure described in the embodiments of this application; Figures 2 to 15 This is a schematic diagram of each step in the method for forming a wafer bonding structure according to the embodiments of this application. Detailed Implementation

[0020] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0021] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0022] Figure 1 This is a flowchart of the method for forming the wafer bonding structure described in the embodiments of this application.

[0023] Embodiments of this application provide a method for forming a wafer bonding structure, referencing Figure 1 As shown, it includes: Step S1: Provide a bonded carrier wafer and a functional wafer, wherein the first side of the functional wafer is bonded to the first side of the carrier wafer; Step S2: A first dielectric layer is formed on the second side of the functional wafer, and a second redistribution layer and a first metal bonding mark are formed in the first dielectric layer, wherein the first metal bonding mark is formed in the process of fabricating the first redistribution layer; Step S3: Provide a bottom wafer, on the surface of which a second dielectric layer is formed, and in the second dielectric layer a second metal layer and a second metal bonding mark are formed; Step S4: Form a third dielectric layer on the surface of the second dielectric layer; Step S5: Form a first redistribution layer in the third dielectric layer that penetrates the third dielectric layer, extends to the second dielectric layer, and is electrically connected to the second metal layer; Step S6: Align the functional wafer and the bottom wafer using the first metal bonding mark and the second metal bonding mark, bond the first dielectric layer of the functional wafer and the third dielectric layer of the bottom wafer, and electrically connect the first redistribution layer and the second redistribution layer; Step S7: Remove the carrier wafer.

[0024] Figures 2 to 15 This is a schematic diagram of each step in the method for forming a wafer bonding structure according to an embodiment of this application. The method for forming a wafer bonding structure according to an embodiment of this application will be described in detail below with reference to the accompanying drawings.

[0025] refer to Figure 1 and Figure 2 As shown, in step S1, a bonded carrier wafer 100 and a functional wafer 200 are provided, wherein the first side of the functional wafer 200 is bonded to the first side of the carrier wafer 100.

[0026] In some embodiments of this application, a functional dielectric layer 210 is further formed on the first side of the functional wafer 200, and a first metal layer 220 is further formed in the functional dielectric layer 210. The first metal layer 220 is used for electrically connecting active devices (not shown in the figure) in the functional wafer 200.

[0027] In some embodiments of this application, the carrier wafer 100 is a semiconductor wafer. The carrier wafer 100 is used to carry the functional wafer 200.

[0028] In some embodiments of this application, the functional wafer 200 is a semiconductor wafer. The functional wafer 200 is, for example, a wafer carrying a memory chip.

[0029] In some embodiments of this application, a carrier dielectric layer (not shown in the figures for simplicity) is further formed on the first side of the carrier wafer 100. Non-metallic bonding marks (not shown in the figures for simplicity) are formed in the carrier dielectric layer, and metallic bonding marks (not shown in the figures for simplicity) corresponding to the non-metallic bonding marks are further formed in the functional dielectric layer 210. The first side of the carrier wafer 100 and the first side of the functional wafer 200 are aligned and bonded through the non-metallic bonding marks and the metallic bonding marks. The metallic bonding marks are formed simultaneously with the first metal layer 220.

[0030] In some embodiments of this application, an edge trimming process is also required on the functional wafer 200 and the functional dielectric layer 220 to remove a portion of the edges of the functional wafer 200 and the functional dielectric layer 220. For simplicity, this edge trimming process is omitted in the embodiments of this application.

[0031] Continue to refer to Figure 1 and Figures 3 to 6 As shown, in step S2, a first dielectric layer 250 is formed on the second side of the functional wafer 200, and a second redistribution layer 260 and a first metal bonding mark 270 are formed in the first dielectric layer 250, wherein the first metal bonding mark 270 is formed in the process of fabricating the second redistribution layer 260.

[0032] In some embodiments of this application, a buffer layer 230 and an etch stop layer 240 are sequentially formed between the second surface of the functional wafer 200 and the first dielectric layer 250.

[0033] refer to Figure 3 As shown, a buffer layer 230, an etch stop layer 240, and a first dielectric layer 250 are sequentially formed on the second side of the functional wafer 200.

[0034] In some embodiments of this application, the buffer layer 240 is made of silicon oxide, and the method for forming the buffer layer 240 includes chemical vapor deposition or physical vapor deposition. Since the etch stop layer 240 cannot be directly formed on the second side of the functional wafer 200, the buffer layer 240 is used to grow the etch stop layer 240.

[0035] In some embodiments of this application, the etch stop layer 240 is made of silicon nitride, and the method for forming the etch stop layer 240 includes chemical vapor deposition or physical vapor deposition. The etch stop layer 240 is used as an etch stop layer in subsequent etching of the first dielectric layer 250, so that the depth of the first opening and the second opening formed by the etching is uniform.

[0036] In some embodiments of this application, the first dielectric layer 250 is made of silicon oxide, and the method for forming the first dielectric layer 250 includes chemical vapor deposition or physical vapor deposition. The first dielectric layer 250 is used to form the second redistribution layer 260 and the first metal bonding marker 270.

[0037] refer to Figure 4 As shown, a first opening 251 and a second opening 252 are formed in the first dielectric layer 250.

[0038] In some embodiments of this application, the method for forming a first opening 251 and a second opening 252 in the first dielectric layer 250 includes: forming a patterned photoresist layer on the surface of the first dielectric layer 250, the patterned photoresist layer defining the positions of the first opening 251 and the second opening 252; etching the first dielectric layer 250 to the etching stop layer 240 using the patterned photoresist layer as a mask to form the first opening 251 and the second opening 252; and removing the patterned photoresist layer.

[0039] refer to Figure 5 As shown, a metal material layer 253 is deposited on the surface of the first dielectric layer 250 and in the first opening 251 and the second opening 252.

[0040] In some embodiments of this application, the metal material layer 253 is made of copper or tungsten. Methods for forming the metal material layer 253 include chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0041] refer to Figure 6 As shown, the metal material layer 253 is ground until the first dielectric layer 250 is exposed, forming a second redistribution layer 260 and a first metal bonding mark 270 in the first opening 251 and the second opening 252, respectively. The first metal bonding mark 270 is formed simultaneously during the formation of the second redistribution layer 260, therefore, the first metal bonding mark 270 does not increase the complexity of the process, does not cause additional material loss, and does not increase costs.

[0042] In some embodiments of this application, the first metal bonding mark 270 is located on the dicing track, so the first metal bonding mark 270 does not affect the routing layout of the second redistribution layer 260.

[0043] In conventional processes, non-metallic bonding marks are formed in the first dielectric layer 250. However, due to the difficulty in controlling the thickness uniformity of the first dielectric layer 250, the alignment accuracy of the formed non-metallic bonding marks is poor. Directly fabricating metallic bonding marks in the first dielectric layer 250 would increase the process flow, making the process more complex, increasing material waste, and raising costs. In the technical solution of this application, the second redistribution layer, originally located on the bottom wafer, is moved to the functional wafer. The first metallic bonding mark is formed simultaneously with the formation of the second redistribution layer. This improves alignment accuracy by using the first metallic bonding mark without increasing process complexity or cost.

[0044] Continue to refer to Figure 1 and Figure 7 As shown, step S3: a bottom wafer 300 is provided, on the surface of the bottom wafer 300 a second dielectric layer 310 is formed, and a second metal layer 320 and a second metal bonding mark 330 are formed in the second dielectric layer 310.

[0045] In some embodiments of this application, the bottom wafer 300 is a semiconductor wafer. For example, a logic chip is formed in the bottom wafer 300.

[0046] In some embodiments of this application, the material of the second dielectric layer 310 is silicon oxide, and the method for forming the second dielectric layer 310 includes chemical vapor deposition or physical vapor deposition, etc.

[0047] In some embodiments of this application, the second metal layer 320 is used for electrically connecting active devices (not shown) in the bottom wafer 300.

[0048] In some embodiments of this application, the second metal bonding mark 330 is located on the dicing track, so the second metal bonding mark 330 does not affect the routing layout of the second metal layer 320.

[0049] In some embodiments of this application, the second metal bonding mark 330 is formed during the process of fabricating the second metal layer 320. That is, the second metal bonding mark 330 is formed simultaneously during the formation of the second metal layer 320. Therefore, the second metal bonding mark 330 does not increase the complexity of the process, does not cause additional material loss, and does not increase costs.

[0050] Continue to refer to Figure 1 and Figure 8 As shown, in step S4, a third dielectric layer 340 is formed on the surface of the second dielectric layer 310.

[0051] In some embodiments of this application, the material of the third dielectric layer 340 is silicon oxide, and the method for forming the third dielectric layer 340 includes chemical vapor deposition or physical vapor deposition. The third dielectric layer 340 is used to form the first redistribution layer.

[0052] Continue to refer to Figure 1 and Figure 9 As shown, in step S5, a first redistribution layer 350 is formed in the third dielectric layer 340, penetrating the third dielectric layer 340, extending to the second dielectric layer 310, and electrically connected to the second metal layer 320.

[0053] In some embodiments of this application, the material of the first redistribution layer 350 is copper or tungsten. The method for forming the first redistribution layer 350 includes an electroplating process.

[0054] In conventional processes, after forming the first redistribution layer 350, a second redistribution layer is fabricated on top of it. However, the fabrication of the second redistribution layer is performed at a high temperature, which heats the bottom wafer 300 and affects the device reliability of the bottom wafer 300. In the technical solution of this application, the second redistribution layer is fabricated on the functional wafer 200, reducing the heat treatment of the bottom wafer 300, making the devices on the bottom wafer 300 more stable, and improving the yield.

[0055] Continue to refer to Figure 1 and Figure 10 As shown, in step S6: Align the functional wafer 200 and the bottom wafer 300 with the first metal bonding mark 270 and the second metal bonding mark 330, bond the first dielectric layer 250 of the functional wafer 200 and the third dielectric layer 310 of the bottom wafer 300, and electrically connect the first redistribution layer 350 and the second redistribution layer 260.

[0056] In the technical solution of this application, the first redistribution layer 260, which was originally located on the bottom wafer, is formed on the functional wafer 200. Then, the first metal bonding mark 270 is formed simultaneously when the first redistribution layer 260 is formed. This can improve the alignment accuracy between the functional wafer 200 and the bottom wafer 300 without affecting the process complexity.

[0057] Continue to refer to Figure 1 and Figure 11 As shown, in step S7, the carrier wafer 100 is removed. The method for removing the carrier wafer 100 includes chemical mechanical polishing and etching processes.

[0058] Continue to refer to Figure 12As shown, the technical solution of this application further includes: forming a through-silicon via structure 400 that penetrates the functional dielectric layer 210 and the functional wafer 200 and extends into the first dielectric layer 250 to electrically connect the second redistribution layer 260.

[0059] Continue to refer to Figure 13 As shown, the technical solution of this application further includes: forming a third redistribution layer 410 electrically connected to the first metal layer 220 in the functional dielectric layer 210.

[0060] Continue to refer to Figure 14 As shown, the technical solution of this application further includes: providing a stacked wafer 500, wherein a stacked dielectric layer 510 is formed on a first side of the stacked wafer 500, and a fourth redistribution layer 520 and a third metal bonding mark 530 are formed in the stacked dielectric layer 510, wherein the third metal bonding mark 530 is formed in the process of fabricating the fourth redistribution layer 520.

[0061] Continue to refer to Figure 15 As shown, the technical solution of this application further includes: aligning and bonding the stacked wafer 500 and the functional wafer 200 through the third metal bonding mark 530 and the first metal bonding mark 270, wherein the fourth redistribution layer 520 is electrically connected to the third redistribution layer 220 and the through-silicon via structure 400.

[0062] In the technical solution of this application, the fourth redistribution layer 520, which was originally located on the functional wafer, is formed on the stacked wafer 500. Then, the third metal bonding mark 530 is formed simultaneously when the fourth redistribution layer 520 is formed. This can improve the alignment accuracy of the functional wafer 200 and the stacked wafer 500 without affecting the process complexity.

[0063] In the technical solution of this application, a multi-layer bonding structure of multi-layer wafer stacks can be formed by repeating the above steps, and the alignment accuracy of each wafer can be improved.

[0064] This application provides a method for forming a wafer bonding structure, in which a first redistribution layer originally located on the bottom wafer is formed on a functional wafer, and a first metal bonding mark is formed simultaneously when the first redistribution layer is formed, which can improve wafer alignment accuracy without affecting process complexity.

[0065] Embodiments of this application also provide a wafer bonding structure, see reference. Figure 15As shown, the wafer includes: a bottom wafer 300, on which a second dielectric layer 310 is formed, and a second metal layer 320 and a second metal bonding mark 330 are formed in the second dielectric layer 310; a third dielectric layer 340, located on the surface of the second dielectric layer 310, in which a first redistribution layer 350 is formed penetrating the third dielectric layer 340 and extending to the second dielectric layer 310 and electrically connected to the second metal layer 320; and a functional wafer 200, on which a first dielectric layer 250 is formed on the second side, and a second redistribution layer 260 and a first metal bonding mark 270 are formed in the first dielectric layer 250; the first dielectric layer 250 of the functional wafer 200 and the third dielectric layer 310 of the bottom wafer 300 are aligned and bonded through the first metal bonding mark 270 and the second metal bonding mark 330, wherein the first redistribution layer 350 and the second redistribution layer 260 are electrically connected.

[0066] In some embodiments of this application, a functional dielectric layer 210 is further formed on the first side of the functional wafer 200, and a first metal layer 220 is further formed in the functional dielectric layer 210. The first metal layer 220 is used for electrically connecting active devices (not shown in the figure) in the functional wafer 200.

[0067] In some embodiments of this application, the carrier wafer 100 is a semiconductor wafer. The carrier wafer 100 is used to carry the functional wafer 200.

[0068] In some embodiments of this application, the functional wafer 200 is a semiconductor wafer. The functional wafer 200 is, for example, a wafer carrying a memory chip.

[0069] In some embodiments of this application, a carrier dielectric layer (not shown in the figures for simplicity) is further formed on the first side of the carrier wafer 100. Non-metallic bonding marks (not shown in the figures for simplicity) are formed in the carrier dielectric layer, and metallic bonding marks (not shown in the figures for simplicity) corresponding to the non-metallic bonding marks are further formed in the functional dielectric layer 210. The first side of the carrier wafer 100 and the first side of the functional wafer 200 are aligned and bonded through the non-metallic bonding marks and the metallic bonding marks. The metallic bonding marks are formed simultaneously with the first metal layer 220.

[0070] In some embodiments of this application, a buffer layer 230 and an etch stop layer 240 are sequentially formed between the second surface of the functional wafer 200 and the first dielectric layer 250.

[0071] In some embodiments of this application, the buffer layer 240 is made of silicon oxide. Since the etch stop layer 240 cannot be formed directly on the second side of the functional wafer 200, the buffer layer 240 is used to grow the etch stop layer 240.

[0072] In some embodiments of this application, the etch stop layer 240 is made of silicon nitride. The etch stop layer 240 is used to ensure uniform depth of the subsequently formed second redistribution layer 260 and first metal bonding mark 270.

[0073] In some embodiments of this application, the first dielectric layer 250 is made of silicon oxide, and the first dielectric layer 250 is used to form the second redistribution layer 260 and the first metal bonding mark 270.

[0074] In some embodiments of this application, the first metal bonding mark 270 is formed simultaneously during the formation of the second redistribution layer 260. Therefore, the first metal bonding mark 270 does not increase the complexity of the process, nor does it result in additional material loss or increased cost.

[0075] In some embodiments of this application, the first metal bonding mark 270 is located on the dicing track, so the first metal bonding mark 270 does not affect the routing layout of the second redistribution layer 260.

[0076] In conventional processes, non-metallic bonding marks are formed in the first dielectric layer 250. However, due to the difficulty in controlling the thickness uniformity of the first dielectric layer 250, the alignment accuracy of the formed non-metallic bonding marks is poor. Directly fabricating metallic bonding marks in the first dielectric layer 250 would increase the process flow, making the process more complex, increasing material waste, and raising costs. In the technical solution of this application, the second redistribution layer, originally located on the bottom wafer, is moved to the functional wafer. The first metallic bonding mark is formed simultaneously with the formation of the second redistribution layer. This improves alignment accuracy by using the first metallic bonding mark without increasing process complexity or cost.

[0077] In some embodiments of this application, the bottom wafer 300 is a semiconductor wafer. For example, a logic chip is formed in the bottom wafer 300.

[0078] In some embodiments of this application, the material of the second dielectric layer 310 is silicon oxide.

[0079] In some embodiments of this application, the second metal layer 320 is used for electrically connecting active devices (not shown) in the bottom wafer 300.

[0080] In some embodiments of this application, the second metal bonding mark 330 is located on the dicing track, so the second metal bonding mark 330 does not affect the routing layout of the second metal layer 320.

[0081] In some embodiments of this application, the second metal bonding mark 330 is formed during the process of fabricating the second metal layer 320. That is, the second metal bonding mark 330 is formed simultaneously during the formation of the second metal layer 320. Therefore, the second metal bonding mark 330 does not increase the complexity of the process, does not cause additional material loss, and does not increase costs.

[0082] In some embodiments of this application, the material of the third dielectric layer 340 is silicon oxide, and the third dielectric layer 340 is used to form the first redistribution layer.

[0083] In some embodiments of this application, the material of the first redistribution layer 350 is copper or tungsten.

[0084] In conventional processes, after forming the first redistribution layer 350, a second redistribution layer is fabricated on top of it. However, the fabrication of the second redistribution layer is performed at a high temperature, which heats the bottom wafer 300 and affects the device reliability of the bottom wafer 300. In the technical solution of this application, the second redistribution layer is fabricated on the functional wafer 200, reducing the heat treatment of the bottom wafer 300, making the devices on the bottom wafer 300 more stable, and improving the yield.

[0085] The first dielectric layer 250 of the functional wafer 200 and the third dielectric layer 310 of the bottom wafer 300 are aligned and bonded through the first metal bonding mark 270 and the second metal bonding mark 330.

[0086] In the technical solution of this application, the first redistribution layer 260, which was originally located on the bottom wafer, is formed on the functional wafer 200. Then, the first metal bonding mark 270 is formed simultaneously when the first redistribution layer 260 is formed. This can improve the alignment accuracy between the functional wafer 200 and the bottom wafer 300 without affecting the process complexity.

[0087] The technical solution of this application further includes: a through-silicon via (TSV) structure 400 extending through the functional dielectric layer 210 and the functional wafer 200 and into the first dielectric layer 250, electrically connected to the second redistribution layer 260; a third redistribution layer 410 located in the functional dielectric layer 210, electrically connected to the first metal layer 220; a stacked wafer 500, wherein a stacked dielectric layer 510 is formed on the first side of the stacked wafer 500, and a fourth redistribution layer 520 and a third metal bonding mark 530 are formed in the stacked dielectric layer 510, wherein the third metal bonding mark 530 is formed in the process of fabricating the fourth redistribution layer 520; the stacked wafer 500 and the functional wafer 200 are aligned and bonded through the third metal bonding mark 530 and the first metal bonding mark 270, wherein the fourth redistribution layer 520 is electrically connected to the third redistribution layer 220 and the TSV structure 400.

[0088] In the technical solution of this application, the fourth redistribution layer 520, which was originally located on the functional wafer, is formed on the stacked wafer 500. Then, the third metal bonding mark 530 is formed simultaneously when the fourth redistribution layer 520 is formed. This can improve the alignment accuracy of the functional wafer 200 and the stacked wafer 500 without affecting the process complexity.

[0089] This application provides a wafer bonding structure and a method for forming the same, in which a first redistribution layer originally located on the bottom wafer is formed on a functional wafer, and a first metal bonding mark is formed simultaneously when the first redistribution layer is formed, which can improve wafer alignment accuracy without affecting process complexity.

[0090] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0091] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0092] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0093] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0094] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a wafer bonding structure, characterized in that, include: A carrier wafer and a functional wafer are provided for bonding, wherein a first side of the functional wafer is bonded to a first side of the carrier wafer, and a functional dielectric layer is further formed on the first side of the functional wafer, wherein a first metal layer is further formed in the functional dielectric layer; A first dielectric layer is formed on the second side of the functional wafer, and a second redistribution layer and a first metal bonding mark are formed in the first dielectric layer, wherein the first metal bonding mark is formed in the process of fabricating the second redistribution layer; A bottom wafer is provided, wherein a second dielectric layer is formed on the surface of the bottom wafer, and a second metal layer and a second metal bonding mark are formed in the second dielectric layer; A third dielectric layer is formed on the surface of the second dielectric layer; A first redistribution layer is formed in the third dielectric layer, penetrating the third dielectric layer, extending to the second dielectric layer, and electrically connected to the second metal layer; Align the functional wafer and the bottom wafer using the first metal bonding mark and the second metal bonding mark, bond the first dielectric layer of the functional wafer and the third dielectric layer of the bottom wafer, and electrically connect the first redistribution layer and the second redistribution layer. Remove the carrier wafer; A through-silicon via structure is formed that penetrates the functional dielectric layer and the functional wafer and extends into the first dielectric layer to electrically connect the second redistribution layer; A third redistribution layer electrically connected to the first metal layer is formed in the functional dielectric layer; A stacked wafer is provided, wherein a stacked dielectric layer is formed on a first side of the stacked wafer, a fourth redistribution layer and a third metal bonding mark are formed in the stacked dielectric layer, wherein the third metal bonding mark is formed in the process of fabricating the fourth redistribution layer; The stacked wafer and the functional wafer are aligned and bonded by the third metal bonding mark and the first metal bonding mark, wherein the fourth redistribution layer is electrically connected to the third redistribution layer and the through-silicon via structure.

2. The method for forming a wafer bonding structure as described in claim 1, characterized in that, A method for forming a first dielectric layer on a second surface of the functional wafer, and forming a second redistribution layer and a first metal bonding mark in the first dielectric layer, includes: A first dielectric layer is formed on the second surface of the functional wafer; A first opening and a second opening are formed in the first dielectric layer; A metallic material layer is deposited on the surface of the first dielectric layer and in the first and second openings; The metal material layer is ground until the first dielectric layer is exposed, and a second redistribution layer and a first metal bonding mark are formed in the first opening and the second opening, respectively.

3. The method for forming a wafer bonding structure as described in claim 1, characterized in that, The second metal bonding mark is formed during the process of fabricating the second metal layer.

4. The method for forming a wafer bonding structure as described in claim 1, characterized in that, The first metal bonding mark is located on the cleavage, and the second metal bonding mark is located on the cleavage.

5. The method for forming a wafer bonding structure as described in claim 1, characterized in that, A buffer layer and an etch stop layer are also formed sequentially between the second side of the functional wafer and the first dielectric layer.

6. A wafer bonding structure, characterized in that, include: A bottom wafer, wherein a second dielectric layer is formed on the surface of the bottom wafer, and a second metal layer and a second metal bonding mark are formed in the second dielectric layer; A third dielectric layer is located on the surface of the second dielectric layer, and a first redistribution layer is formed in the third dielectric layer, penetrating the third dielectric layer and extending to the second dielectric layer and electrically connected to the second metal layer. A functional wafer, wherein a first dielectric layer is formed on the second side of the functional wafer, a second redistribution layer and a first metal bonding mark are formed in the first dielectric layer, and a functional dielectric layer is also formed on the first side of the functional wafer, wherein a first metal layer is also formed in the functional dielectric layer. The first dielectric layer of the functional wafer and the third dielectric layer of the bottom wafer are aligned and bonded through the first metal bonding mark and the second metal bonding mark, wherein the first redistribution layer and the second redistribution layer are electrically connected. A through-silicon via structure penetrates the functional dielectric layer and the functional wafer and extends into the first dielectric layer to electrically connect to the second redistribution layer; The third redistribution layer is located in the functional dielectric layer and electrically connected to the first metal layer; A stacked wafer, wherein a stacked dielectric layer is formed on a first side of the stacked wafer, and a fourth redistribution layer and a third metal bonding mark are formed in the stacked dielectric layer; The stacked wafer and the functional wafer are aligned and bonded via the third metal bonding mark and the first metal bonding mark, wherein the fourth redistribution layer is electrically connected to the third redistribution layer and the through-silicon via structure.

7. The wafer bonding structure as described in claim 6, characterized in that, The first metal bonding mark is located on the cleavage, and the second metal bonding mark is located on the cleavage.

8. The wafer bonding structure as described in claim 6, characterized in that, A buffer layer and an etch stop layer are also formed sequentially between the second side of the functional wafer and the first dielectric layer.

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