Terahertz high-speed transceiver components and electronic equipment

Abstract

The present application provides a terahertz high-speed transceiver component and electronic equipment, which transmits and receives terahertz signals through an antenna, realizes modulation and demodulation of terahertz signals through a terahertz transceiver circuit, and improves the quality of the baseband signal through a continuous-time linear equalization circuit, a clock data recovery circuit, a driving circuit, and a limiting amplifier, so that the terahertz high-speed transceiver component can realize high-quality high-speed signal transmission at a low cost and meet the transmission distance requirements.

Description

Technical Field

[0001] The present application relates to the field of high-speed signal transmission technology, and in particular to a terahertz high-speed transceiver component and electronic equipment. Background Art

[0002] In facilities such as large-scale data centers that require high-speed signal interconnection, optical modules are often used to achieve high-speed interconnection between hosts. However, traditional optical modules used for high-speed optical interconnection not only have high power consumption but are also based on III-V chip technology, resulting in high material costs, complex manufacturing, and high processing costs. Summary of the Invention

[0003] The present application provides a terahertz high-speed transceiver component and an electronic device, which uses a terahertz circuit to transmit and receive high-speed signals, thereby reducing the cost of high-speed signal transmission and reception.

[0004] In a first aspect, the present application provides a terahertz high-speed transceiver component, comprising: a first antenna, a second antenna, a first terahertz circuit, a second terahertz circuit, a first continuous-time linear equalization circuit, a second continuous-time linear equalization circuit, a first clock data recovery circuit, a second clock data recovery circuit, a first drive circuit, a second drive circuit, and a limiting amplifier; the first antenna is connected to the input end of the first terahertz circuit, and the second antenna is connected to the output end of the second terahertz circuit; the input end of the first continuous-time linear equalization circuit is connected to the output end of the first terahertz circuit, the output end of the first continuous-time linear equalization circuit is connected to the input end of the limiting amplifier, the output end of the limiting amplifier is connected to the input end of the first clock data recovery circuit, and the output end of the first clock data recovery circuit is connected to the input end of the first drive circuit; the output end of the second continuous-time linear equalization circuit is connected to the input end of the second clock data recovery circuit, the output end of the second clock data recovery circuit is connected to the input end of the second drive circuit, and the output end of the second drive circuit is connected to the input end of the second terahertz circuit; the first antenna is used to Receive a first terahertz signal; the first terahertz circuit is used to demodulate a first baseband signal from the first terahertz signal; the first continuous-time linear equalization circuit is used to improve the gain flatness of the first baseband signal; the limiting amplifier is used to suppress the parasitic amplitude modulation of the first baseband signal; the first clock data recovery circuit is used to extract the clock information of the first baseband signal processed by the limiting amplifier and restore the first original baseband signal; the first driving circuit is used to amplify the first original baseband signal, wherein the first original baseband signal is the original baseband signal of the first baseband signal ; The second continuous-time linear equalization circuit is used to improve the gain flatness of the second baseband signal to be transmitted, the second clock data recovery circuit is used to extract the clock information of the second baseband signal passing through the second continuous-time linear equalization circuit, and restore the second original baseband signal, the second driving circuit is used to amplify the second original baseband signal, wherein the second original baseband signal is the original baseband signal of the second baseband signal; the second terahertz circuit is used to modulate the original baseband signal of the second baseband signal into a second terahertz signal; the second antenna is used to transmit the second terahertz signal.When the terahertz high-speed transceiver component provided in the present application receives a high-speed signal, the terahertz signal is received through the first antenna, the terahertz signal is demodulated into a baseband signal through the first terahertz circuit, and the baseband signal is processed through the first continuous-time linear equalization circuit, the first clock data recovery circuit and the first driving circuit, so that the high-speed baseband signal finally received meets the transmission requirements. In addition, the high-speed signal to be transmitted sent by the host is processed through the second continuous-time linear equalization circuit, the second clock data recovery circuit, the second driving circuit and the limiting amplifier, so that it meets the transmission requirements, and the high-speed signal that meets the transmission requirements is modulated into a terahertz signal through the second terahertz circuit and transmitted through the second antenna, thereby achieving the goal of low-cost terahertz circuit transceiver of high-speed signals and reducing the cost of transceiver of high-speed signals.

[0005] In a possible implementation, the first terahertz circuit and / or the second terahertz circuit is a chip, which is conducive to reducing the volume of the terahertz high-speed transceiver component.

[0006] In a possible implementation, the first terahertz circuit and / or the second terahertz circuit are integrated bare chips, which is conducive to further reducing the volume of the terahertz high-speed transceiver component.

[0007] In one possible implementation, the bare chip is mounted as a flip-chip, which is beneficial for further reducing the volume of the terahertz high-speed transceiver component to meet the requirements of a small package.

[0008] In a possible implementation, the first antenna and / or the second antenna may be an onboard antenna, which is beneficial for further reducing the volume of the terahertz high-speed transceiver component so as to meet the requirements of a small package.

[0009] In a possible implementation, the onboard antenna may be a printed circuit board onboard antenna, which is conducive to further reducing the volume of the terahertz high-speed transceiver component so that it meets the requirements of a small package.

[0010] In one possible implementation, the above-mentioned on-board antenna can be manufactured by controlled-depth milling, which is conducive to further reducing the volume of the terahertz high-speed transceiver component to meet the requirements of small packaging.

[0011] In a possible implementation, the terahertz high-speed transceiver assembly may further include: a first waveguide and / or a second waveguide, the first waveguide being spatially coupled to the first antenna, and the second waveguide being spatially coupled to the second antenna; the first waveguide being used to transmit the first baseband signal, and the second waveguide being used to transmit the second baseband signal, so that the terahertz high-speed transceiver assembly transmits and receives high-speed signals in a wired manner.

[0012] In a possible implementation, the first waveguide and / or the second waveguide is a plastic waveguide, which improves the transmission performance of the wired terahertz high-speed transceiver component.

[0013] In one possible implementation, the above-mentioned terahertz high-speed transceiver component may also include: a driving voltage circuit and / or a control circuit; the driving voltage circuit is used to power the above-mentioned first terahertz circuit and the above-mentioned second terahertz circuit; the control circuit is used to control the driving voltage circuit to power the above-mentioned first terahertz circuit and the above-mentioned second terahertz circuit, and is used to control the above-mentioned first continuous-time linear equalization circuit and the second continuous-time linear equalization circuit to improve the gain flatness of the above-mentioned first baseband signal and the above-mentioned second baseband signal, and control the above-mentioned first clock data recovery circuit and the second clock data recovery circuit to restore the original baseband signals of the above-mentioned first baseband signal and the second baseband signal, thereby realizing the controllability of the terahertz high-speed transceiver component.

[0014] In one possible implementation, the above-mentioned terahertz high-speed transceiver component may also include: a packaging shell, in which the above-mentioned first antenna, second antenna, first terahertz circuit, second terahertz circuit, first continuous-time linear equalization circuit, second continuous-time linear equalization circuit, first clock data recovery circuit, second clock data recovery circuit, first drive circuit, second drive circuit and limiting amplifier are arranged, thereby improving the safety protection performance of the terahertz high-speed transceiver component.

[0015] In one possible implementation, the above-mentioned packaging shell is a packaging shell of an optical module, so that a terahertz high-speed transceiver component that realizes high-speed signal transmission through terahertz signals can replace the existing optical module for high-speed interconnection, thereby reducing the hardware cost of high-speed interconnection.

[0016] In a second aspect, the present application provides an electronic device (such as a server, a switch, etc.) comprising any component of the first aspect. The electronic device can achieve high-speed interconnection with other electronic devices at a lower cost through the terahertz high-speed transceiver component. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic diagram of an application scenario of a terahertz high-speed transceiver component in an embodiment of the present application;

[0018] Figure 2 A schematic diagram of a terahertz high-speed transceiver assembly in an embodiment of the present application;

[0019] Figure 3 A schematic diagram of a terahertz receiving chip in an embodiment of the present application;

[0020] Figure 4 A schematic diagram of a terahertz emission chip in an embodiment of the present application;

[0021] Figure 5a A schematic diagram of a CDR chip in an embodiment of the present application;

[0022] Figure 5b A schematic diagram of a power supply chip of a CDR chip in an embodiment of the present application;

[0023] Figures 6a to 6e Schematic diagram of a driving voltage circuit in an embodiment of the present application;

[0024] Figure 7 A schematic diagram of the MCU in the embodiment of the present application;

[0025] Figure 8 Schematic diagram of the relationship between the MCU, CDR chip and driving voltage circuit in the embodiment of the present application;

[0026] Figure 9 This is another schematic diagram of the terahertz high-speed transceiver assembly in an embodiment of the present application;

[0027] Figure 10a and Figure 10b This is another schematic diagram of the terahertz high-speed transceiver assembly in an embodiment of the present application;

[0028] Figure 11a and Figure 11b Schematic diagram of the transmission performance of the terahertz high-speed transceiver component in an embodiment of the present application.

[0029] Figure 12 A schematic diagram of the structure of the server in the embodiment of the present application;

[0030] Figure 13 This is a schematic diagram of the structure of a switch in an embodiment of the present application. DETAILED DESCRIPTION

[0031] The terms used in the implementation section of this application are only used to explain the specific embodiments of this application and are not intended to limit this application.

[0032] The terahertz high-speed transceiver assembly provided in the embodiment of the present application can be used to transmit terahertz signals over short distances, such as for short-distance high-speed interconnection between various devices in a data center. Figure 1 As shown, a top-of-rack (TOR) switch 101 in a rack 100 and multiple servers 102 can be interconnected at high speed via a terahertz high-speed transceiver assembly. The terahertz high-speed transceiver assembly can also be used for high-speed interconnection between an end-of-rack (EOR) switch and servers.

[0033] In some embodiments, a terahertz high-speed transceiver assembly includes a terahertz receiving circuit, a terahertz transmitting circuit, a receiving antenna, and a transmitting antenna. The terahertz receiving circuit may be a circuit or chip with a terahertz demodulation function, such as a terahertz receiver or a terahertz signal demodulation circuit. The terahertz transmitting circuit may be a circuit or chip with a terahertz source and a modulator, such as a terahertz transmitter or a terahertz signal modulation circuit. Assuming the terahertz high-speed transceiver assembly is installed on a first host, such as a switch, the receiving antenna receives a terahertz signal transmitted by a second host, such as a server. The terahertz receiving circuit demodulates the terahertz signal to obtain a baseband signal, which is then output to the first host. When the first host transmits a signal to a second host or other hosts, the terahertz transmitting circuit modulates the baseband signal to be transmitted into a terahertz signal, which is then transmitted by the transmitting antenna. The terahertz high-speed transceiver assembly provided by these embodiments can achieve high-speed signal transmission and reception through the terahertz transceiver circuit, making it possible to replace high-cost optical modules with terahertz high-speed transceiver assemblies using low-cost terahertz transceiver circuits.

[0034] In other embodiments, the terahertz high-speed transceiver assembly adds one or more of a continuous time linear equalization (CTLE) circuit, a clock data recovery (CDR) circuit, a driver circuit, and a limiting amplifier (LA) on the basis of the above embodiments. For example, at least one of a CTLE, a CDR circuit, and a driver circuit is added to the terahertz signal transmission link, and at least one of a CTLE circuit, a CDR circuit, a driver circuit, and a LA is added to the terahertz signal reception link. The CTLE circuit is used to improve the gain flatness and link bandwidth of the high-speed link. The CDR circuit is used to recover the original baseband signal by extracting the clock information from the high-speed signal, the driver circuit is used to amplify the original baseband signal, and the LA is used to suppress parasitic amplitude modulation of the signal before the CDR circuit recovers the original baseband signal, remove excessively high or low voltage signals in the baseband signal, and output a baseband signal with a stable amplitude. Because baseband signal quality is a significant factor affecting the transmission performance of a high-speed transceiver assembly used to transmit terahertz signals, and terahertz signals, whether originating from the first or second host, may be subject to noise, energy loss, and other influences during transmission, causing signal distortion. For example, at the transmitter, the amplitude and quality of the baseband signal affect the terahertz modulated signal pulse waveform, thus impacting receiver decision making. At the receiver, the output baseband signal quality directly impacts the bit error rate. Therefore, as a variant embodiment, one or more of the aforementioned CTLE circuit, CDR circuit, driver circuit, and LA may be added to the terahertz high-speed transceiver assembly, depending on the signal rate and transmission distance requirements.

[0035] It should be understood that the terahertz high-speed transceiver assembly in the above-mentioned embodiment can only operate when powered. Furthermore, to better control the operation of the terahertz high-speed transceiver assembly, the terahertz high-speed transceiver assembly may further include a control circuit, such as a microcontroller processing unit (MCU), a CPU, a dedicated chip, or a programmable chip. The control circuit may execute a pre-set program to implement software control of the signal processing circuits, such as the terahertz transceiver circuit, in the terahertz high-speed transceiver assembly. For example, when the control circuit receives an interrupt signal sent by the first host, the control circuit may control the circuit in the terahertz high-speed transceiver assembly to transmit or stop transmitting signals by turning the power supply on and off.

[0036] Figure 2 A schematic diagram of a high-speed terahertz transceiver assembly is shown. In this embodiment, the assembly includes a housing 210 and, disposed within the housing 210, a control circuit 201, a CDR circuit 202, a terahertz receiving circuit 203, a terahertz transmitting circuit 204, a receiving antenna 205, and a transmitting antenna 206. For signals below 10 Gbps, the CDR circuit 202 can be omitted from the assembly to reduce costs while still meeting transmission requirements.

[0037] The receiving antenna 205 receives a terahertz signal from another host. The terahertz receiving circuit 203 demodulates the terahertz signal received by the receiving antenna 205 to obtain a baseband signal. The terahertz transmitting circuit 204 modulates the baseband signal from the host (HOST) 211 (such as a server or switch) to generate a terahertz signal, and the transmitting antenna 206 transmits the terahertz signal. Since the baseband signal quality is an important factor affecting the transmission performance of the terahertz transceiver component, for example, at the transmitting end, the amplitude and quality of the baseband signal affect the pulse waveform of the terahertz modulated signal and affect the receiver's decision. In addition, after the signal to be sent by the host (i.e., the original baseband signal) is sent to the high-speed transceiver component through an interface such as the gold finger 209, it will also be deformed due to interference and become a baseband signal to be processed. At the receiving end, the quality of the output baseband signal directly affects the bit error rate. Therefore, a CDR circuit 202 is added to the terahertz high-speed transceiver to retime the baseband signal, improving its sensitivity and thereby increasing its transmission distance by 50%. Retiming involves extracting a clock signal from the high-speed baseband signal, using it as a reference clock. After shaping the baseband signal, the original baseband signal is generated and outputted to the transmitting host, resulting in a higher-quality high-speed baseband signal.

[0038] The control circuit 201 has an interface management function and, using stored protocol information, manages the communication interface between the terahertz receiving circuit 203 and the terahertz transmitting circuit 204 and the host 211. Optionally, the control circuit 201 can further control the CDR circuit 202 to adjust the high-speed baseband signal. Optionally, the terahertz high-speed transceiver assembly may also include a drive voltage circuit, which, together with the control circuit 201, serves as the drive control center for the terahertz high-speed transceiver assembly.

[0039] In some embodiments, the terahertz receiving circuit 203 may be Figure 3 The terahertz receiving chip shown in FIG. After the terahertz signal RXSIN from the receiving antenna 205 is demodulated and processed by the terahertz receiving chip, a baseband signal RXOUT+− is output. Furthermore, the terahertz receiving chip may include a low-noise amplifier circuit to amplify the terahertz signal RXSIN and then demodulate the amplified terahertz signal RXSIN. Furthermore, the terahertz receiving chip may include a baseband amplifier circuit to amplify the baseband signal RXOUT+− before outputting it.

[0040] In some embodiments, the terahertz transmitting circuit 204 may be a terahertz transmitting chip. Figure 4 As shown, the terahertz transmitter chip has a built-in terahertz source. The terahertz carrier signal generated by the terahertz source passes through the terahertz carrier signal generated by the terahertz source through the modulator circuit within the terahertz transmitter chip, which modulates the baseband signal TXSIN to be transmitted onto the terahertz carrier signal generated by the terahertz source, outputting a terahertz signal TXSOUT carrying the baseband signal. The terahertz signal TXSOUT is transmitted by the transmitting antenna 206. In some embodiments, the terahertz transmitter chip may further include a power amplifier circuit, which amplifies the terahertz signal TXSOUT before outputting it to the transmitting antenna 206.

[0041] In some embodiments, the CDR circuit includes an optical digital signal processing (ODSP) chip for PAM4 applications in Pulse Amplitude Modulation (PAM) technology. In other embodiments, the CDR circuit 202 may include: Figure 5a The CDR chip shown and Figure 5b The chip shown here is the one that powers the CDR chip. In the receive chain of the terahertz high-speed transceiver assembly, the CDR chip's input signals, RXOUT+-, are the baseband signals output by the terahertz receiver chip. After retiming, the CDR chip outputs the original baseband signals, RD+-. In the transmit chain, the CDR chip's input signals are the baseband signals, TD+-, sent by host a11. After retiming, the CDR chip outputs the original baseband signals, TXSIN. Figure 5bThe chip output signal CDR1V6 is shown to power the CDR chip.

[0042] In some embodiments, the driving voltage circuit is as follows Figures 6a to 6e As shown, the total power signal INT_3.3V is Figures 6a to 6e The chip shown is powered, Figure 6a 、 Figure 6b 、 Figure 6c and Figure 6d Provide driving voltage signals VBUK_2, VBUK_3, VBUK_4, VBUK_6 and VBUK_7 for the terahertz receiving chip respectively. Figure 6e The chip shown provides DC bias voltage signals VDAC_1, VDAC_2, VDAC_3, and VDAC_4 for the terahertz receiving chip. Figure 6c The chip shown provides a driving voltage signal VBUK_5 for the terahertz emission chip.

[0043] In some embodiments, the control circuit 201 may be a microcontroller unit (MCU). Figure 7 As shown, the MCU implements interface management through interface signals TX-FAULT, TX-DIS and RX_LOS. Among them, the signal TX-FAULT is the interrupt signal that the MCU reports the transmission link error to the HOST. After that, the HOST turns off the transmission link signal through the signal TX-DIS. For example, the HOST sends the signal TX-DIS to the MCU. After receiving the signal, the MCU turns off the terahertz transmission chip and other circuits on the transmission link by driving the voltage circuit signal, so that it stops transmitting the terahertz signal. The signal RX_LOS is the interrupt signal reported by the terahertz receiving circuit to the MCU when the receiving link signal is lower than the required value. After analysis and judgment, the MCU reports it to the HOST. Based on the interrupt signal, the HOST can send a control signal to the MCU to turn off the receiving link. The signals CDR_SCL and CDR_SDA are I 2 C communication interface signal, MCU controls the CDR chip and drive voltage circuit chip through this signal.

[0044] Signals HOST_SCL and HOST_SDA are I 2 C communication interface. The host communicates with the MCU through this interface to obtain information about the terahertz high-speed transceiver component, such as voltage, temperature, and power monitoring information. It also controls its functions, such as output amplitude adjustment and software-based startup and shutdown. Signals VDAC_5, VDAC_6, VDAC_7, and VDAC_8 are the driving voltage signals provided by the MCU to the terahertz transmitter chip.

[0045] like Figure 8As shown, MCU 801 can 2 C bus controls the driving voltage circuit 803 to supply power to the terahertz receiving circuit 203 and the terahertz transmitting circuit 204. The MCU 801 can 2 C bus controls the CDR chip 802 to perform signal shaping on the high-speed signal. 2 C bus to communicate with the host 211. Optionally, the MCU may also store data of the terahertz receiving circuit 203 and the terahertz transmitting circuit 204, such as storing status information of the receiving and transmitting circuits, such as on or off status.

[0046] When the terahertz high-speed transceiver component is working, the MCU uniformly controls the voltage adjustment of the terahertz receiving chip and the terahertz transmitting chip, which can realize digital control and continuous adjustment of the voltage of multiple terahertz receiving chips and terahertz transmitting chips.

[0047] In some embodiments, the terahertz high-speed transceiver assembly may further include a waveguide, such as a plastic waveguide or a plastic fiber. Figure 2 As shown, the terahertz high-speed transceiver assembly includes a first waveguide 207 and a second waveguide 208. The first waveguide 207 is non-contact spatially coupled to the receiving antenna 205, and the second waveguide 208 is spatially coupled to the transmitting antenna 206. The terahertz signal transmitted by the first waveguide 207 is non-contact spatially coupled to the receiving antenna 205, and the terahertz signal emitted by the transmitting antenna 206 is coupled to the second waveguide 208 through non-contact spatial coupling for wired transmission.

[0048] Another example of terahertz high-speed transceiver components Figure 9As shown, in the signal transmission link of the terahertz high-speed transceiver component 900, the baseband signal is transmitted from the host end to the terahertz transmitter chip 904 through the connector and the signal line on the PCB. Due to the influence of transmission line signal integrity such as impedance mismatch and loss, the signal bandwidth and gain will be degraded, which is not conducive to the modulation of the terahertz signal. Therefore, a CTLE circuit 901, a CDR circuit 902 and a driver circuit 903 are added to the terahertz transmission link. In this way, the baseband signal from the host first passes through the CTLE circuit 901 to improve the gain flatness of the high-speed link transmitted through the interface and increase the link bandwidth; the signal processed by the CTLE circuit 901 is sent to the CDR circuit 902, and the clock information embedded in the data is extracted. The data is then retimed to restore the original baseband signal. Finally, it is output through the driver circuit 903 to improve the output swing of the baseband signal. The baseband signal is modulated into a terahertz carrier signal inside the terahertz transmitter chip 904 for transmission. In the signal reception link, terahertz signals transmitted via waveguides can degrade the entire baseband signal carried by the terahertz signal due to the effects of dispersion during waveguide transmission and differences in the signal's spectral response between the demodulation and transmission links, resulting in significant group delay. Therefore, after the terahertz receiver chip 905 demodulates the baseband signal from the terahertz signal, it processes the baseband signal to further meet the host's reception requirements. Similar to the signal processing in the transmission link, in the reception link, the baseband signal is processed by the CTLE circuit 906 to improve the high-speed link gain flatness and link bandwidth. The baseband signal then passes through a limiting amplifier (LA) to suppress parasitic amplitude modulation, remove excessively high or low voltage signals, and output a baseband signal with a stable amplitude. Finally, after recovery and amplification by the CDR circuit 907 and driver circuit 908, the baseband signal is output to the host, meeting the transmission bandwidth requirements. In this embodiment, the terahertz high-speed transceiver component effectively improves the link bandwidth and receiving sensitivity of terahertz waveguide transmission through the signal processing circuits in the transmitting link and the receiving link, thereby increasing the transmission distance and enabling the transmission of 25Gbps signals over a distance of 10 meters.

[0049] In some embodiments, the above-mentioned receiving antenna and transmitting antenna are PCB on-board antennas to reduce the loss of terahertz signals transmitted on the PCB, improve coupling efficiency, and reduce the space occupied by the terahertz high-speed transceiver component, thereby realizing miniaturized packaging of the terahertz high-speed transceiver component.

[0050] In some embodiments, the terahertz receiving chip and / or the terahertz transmitting chip are integrated bare chips (also called bare dies) to further reduce the space occupied by the terahertz high-speed transceiver component and achieve miniaturized packaging of the terahertz high-speed transceiver component.

[0051] In some embodiments, the terahertz high-speed transceiver assembly may further include a gold finger 209 , and its housing may be a housing in a packaging form such as SFP+, SFP28, DSFP, QSFP28, and QSFP-DD.

[0052] Figure 10a and Figure 10b A schematic diagram of another terahertz high-speed transceiver component is shown. In this embodiment, all functional circuits of the terahertz high-speed transceiver component, such as the terahertz transceiver chip 1003, the CDR circuit, the terahertz antenna 1004, etc., are encapsulated in a miniaturized housing 1001. The terahertz chip 1003, such as the terahertz transmitting chip or the terahertz receiving chip, is mounted on the PCB board 1002 in the form of a flip chip. The terahertz antenna 1004, such as the terahertz receiving antenna or the terahertz transmitting antenna, etches the antenna pattern on the PCB board 1001 in the form of PCB processing, and is placed at the tail end of the PCB board 1001 to facilitate the coupling and transmission of the terahertz signal. The terahertz signal emitted by the transmitting antenna is coupled to the waveguide 1005 (such as a plastic fiber) by using a spatial waveguide coupling method. Figure 10b As shown, the cross-sections of the terahertz antenna 1004 and the waveguide 1005 are opposite each other, so that the terahertz signal emitted by the terahertz antenna 1004 is coupled into the waveguide 1005 for transmission, or the terahertz signal transmitted by the waveguide 1005 is coupled into the terahertz antenna 1004 for reception. The bottom surface of the terahertz antenna 1004 on the PCB is processed using a controlled depth milling method. The thickness of the terahertz antenna 1004 on the PCB can be less than or equal to the thickness of a standard PCB board, meeting the plug-in and mechanical assembly requirements of the small package module gold finger. This allows the terahertz high-speed transceiver assembly to replace the traditional optical module and be inserted into the host to achieve terahertz signal transmission through the gold finger 209. In this embodiment, the terahertz high-speed transceiver assembly uses a bare die terahertz chip, which is mounted in a flip-chip manner. In addition, the PCB-mounted antenna ensures that the volume of the terahertz high-speed transceiver assembly meets the requirements of miniaturized packaging. For example, it can use the same miniaturized packaging housing as traditional optical modules, realizing a low-cost wired terahertz high-speed transceiver assembly. Furthermore, the terahertz high-speed transceiver component provided in this embodiment can meet the transmission requirements of high-speed signals. Figure 11a As shown in FIG, the transmission eye diagram of the 10Gbps signal transmitted by the terahertz high-speed transceiver assembly provided in this embodiment meets the data communication requirements. Figure 11bAs shown, the transmission eye diagram of the 25Gbps signal transmitted by the terahertz high-speed transceiver component provided by this embodiment still meets the requirements of the data communication for the transmission eye diagram. Moreover, in the terahertz high-speed transceiver component provided by this embodiment, the terahertz transmission and reception link system can achieve 25Gbps zero-error transmission. The terahertz high-speed transceiver component provided by this embodiment adopts terahertz wired waveguide communication, which can replace wireless point-to-point communication, and integrates the terahertz transceiver function into a small package pluggable module, which can replace the optical module at a lower cost to achieve high-speed signal transmission and reception, and is used for high-speed short-distance interconnection such as data centers. Moreover, in the above embodiment, the terahertz high-speed transceiver component is based on terahertz communication technology and adopts CMOS process technology to manufacture chips. It has low coupling accuracy requirements, mature preparation, and is easy to process. It has the advantages of low power consumption, low cost and high bandwidth.

[0053] The electronic device provided in the embodiment of the present application may include the terahertz high-speed transceiver component in any of the above embodiments to achieve high-speed interconnection with other electronic devices. Figure 1 Servers, switches, etc. shown.

[0054] like Figure 12 As shown, the server includes a housing 120 and a CPU 121, a memory 122, a disk system 123 and an interactive interface 124 arranged in the housing 120, and also includes a terahertz high-speed transceiver component 125 (see the description in the above embodiment) connected to the interactive interface 124 through an opening of the housing 120, such as the terahertz high-speed transceiver component 125 can be inserted into the interactive interface 124 to achieve connection. The server can be interconnected with the switch at high speed through the terahertz high-speed transceiver component 125. Among them, the interactive interface 124 receives a service request forwarded by the switch or sends a service response through the terahertz high-speed transceiver component 125. The CPU 121 responds to the service request, generates a service response by calling the data or program in the memory 122 or the disk system 123, and sends the service response at high speed through the terahertz high-speed transceiver component 125 connected to the interactive interface 124. The server can be a file server, a data server, an application server, etc.

[0055] like Figure 13As shown, the switch may include a housing 130, a processor 131, a memory 132, and an interactive interface 133 disposed within the housing 130, and a terahertz high-speed transceiver assembly 134 connected to the interactive interface 133. The switch can achieve high-speed interconnection with the aforementioned server via the terahertz high-speed transceiver assembly 134 and the aforementioned terahertz high-speed transceiver assembly 125. Upon receiving a service request, the switch uses the processor 131 to retrieve data from the memory 132 to dispatch the service request, sends the service request to the server via the high-speed interconnection, and receives a service response from the server via the high-speed interconnection. The processor 131 then retrieves data from the memory 132 to identify the destination address of the service response and forwards it accordingly.

[0056] The above-mentioned servers, switches and other electronic devices achieve high-speed interconnection by adopting terahertz high-speed transceiver components, thereby ensuring data processing efficiency while reducing hardware costs.

[0057] It is understood that some or all of the steps or operations in the above embodiments are merely examples, and the present application embodiments may also perform other operations or variations of various operations. In addition, the various steps may be performed in a different order than those presented in the above embodiments, and it is possible that not all of the operations in the above embodiments need to be performed.

[0058] In the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. Among them, A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can represent: a, b, c, a and b, a and c, b and c or a and b and c, where a, b, c can be single or multiple.

[0059] The above description is merely a specific embodiment of the present application. Any person skilled in the art may easily conceive of variations or substitutions within the technical scope disclosed in this application, and such variations or substitutions shall be within the scope of protection of this application. The scope of protection of this application shall be subject to the scope of protection of the claims.

Claims

1. A terahertz high-speed transceiver component, characterized in that: include: a first antenna, a second antenna, a first terahertz circuit, a second terahertz circuit, a first continuous-time linear equalization circuit, a second continuous-time linear equalization circuit, a first clock-data recovery circuit, a second clock-data recovery circuit, a first drive circuit, a second drive circuit, and a limiting amplifier; The first antenna is connected to the input end of the first terahertz circuit, and the second antenna is connected to the output end of the second terahertz circuit; An input end of the first continuous-time linear equalization circuit is connected to an output end of the first terahertz circuit, an output end of the first continuous-time linear equalization circuit is connected to an input end of the limiting amplifier, an output end of the limiting amplifier is connected to an input end of the first clock and data recovery circuit, and an output end of the first clock and data recovery circuit is connected to an input end of the first driving circuit; The output end of the second continuous-time linear equalization circuit is connected to the input end of the second clock data recovery circuit, the output end of the second clock data recovery circuit is connected to the input end of the second driving circuit, and the output end of the second driving circuit is connected to the input end of the second terahertz circuit; The first antenna is used to receive a first terahertz signal; The first terahertz circuit is used to demodulate a first baseband signal from the first terahertz signal; The first continuous-time linear equalization circuit is used to improve the gain flatness of the first baseband signal, the limiting amplifier is used to suppress parasitic amplitude modulation of the first baseband signal, the first clock data recovery circuit is used to extract clock information of the first baseband signal processed by the limiting amplifier and restore the first original baseband signal, and the first driving circuit is used to amplify the first original baseband signal, wherein the first original baseband signal is the original baseband signal of the first baseband signal; The second continuous-time linear equalization circuit is used to improve the gain flatness of the second baseband signal to be transmitted, the second clock data recovery circuit is used to extract clock information of the second baseband signal passing through the second continuous-time linear equalization circuit and restore the second original baseband signal, and the second driving circuit is used to amplify the second original baseband signal, wherein the second original baseband signal is the original baseband signal of the second baseband signal; The second terahertz circuit is used to modulate an original baseband signal of the second baseband signal into a second terahertz signal; The second antenna is used to transmit the second terahertz signal.

2. The assembly according to claim 1, characterized in that The first terahertz circuit and / or the second terahertz circuit is a chip.

3. The assembly according to claim 1 or 2, characterized in that The first terahertz circuit and / or the second terahertz circuit is an integrated bare chip.

4. The assembly according to claim 3, characterized in that The bare chip is mounted in a flip chip manner.

5. The assembly according to any one of claims 1 to 4, characterized in that The first antenna and / or the second antenna is an onboard antenna.

6. The assembly according to claim 5, characterized in that The onboard antenna is a printed circuit board onboard antenna.

7. Assembly according to claim 5 or 6, characterized in that The onboard antenna is manufactured by controlled deep milling.

8. Assembly according to any one of claims 1 to 7, characterized in that The invention further comprises: a first waveguide and / or a second waveguide, wherein the first waveguide is spatially coupled to the first antenna, and the second waveguide is spatially coupled to the second antenna; The first waveguide is used to transmit the first baseband signal, and the second waveguide is used to transmit the second baseband signal.

9. The assembly according to claim 8, characterized in that The first waveguide and / or the second waveguide is a plastic waveguide.

10. The assembly according to any one of claims 1 to 9, characterized in that Also includes: a driving voltage circuit and / or a control circuit; The driving voltage circuit is used to supply power to the first terahertz circuit and the second terahertz circuit; The control circuit is used to control the driving voltage circuit to power the first terahertz circuit and the second terahertz circuit, to control the first continuous-time linear equalization circuit and the second continuous-time linear equalization circuit to improve the gain flatness of the first baseband signal and the second baseband signal, and to control the first clock data recovery circuit and the second clock data recovery circuit to restore the original baseband signals of the first baseband signal and the second baseband signal.

11. The assembly according to any one of claims 1 to 10, characterized in that It also includes: a packaging shell, in which the first antenna, the second antenna, the first terahertz circuit, the second terahertz circuit, the first continuous time linear equalization circuit, the second continuous time linear equalization circuit, the first clock data recovery circuit, the second clock data recovery circuit, the first drive circuit, the second drive circuit and the limiting amplifier are arranged.

12. The assembly according to claim 11, characterized in that The packaging shell is a packaging shell of an optical module.

13. An electronic device, characterized in that: The device comprises the assembly according to any one of claims 1 to 12.

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