A data synchronization method based on phased array system

Abstract

The present invention discloses a data synchronization method based on a phased array system, which relates to the technical field of data synchronization. The data synchronization method based on a phased array system includes the following steps: system determination of a digital phased array system, system clock synchronization, system acquisition synchronization, DDC module synchronization, and system data transmission synchronization. The data synchronization method based on a phased array system facilitates problem troubleshooting. Whether in design or actual use, if a problem occurs, the problem can be quickly found by step-by-step troubleshooting according to the modularization. This can effectively improve the efficiency of system data synchronization and optimize the data processing efficiency of related systems. At the same time, the modularization setting can reduce equipment costs and improve the convenience of equipment maintenance. The corresponding modules can be deleted according to the complexity of the system. For a relatively simple system, removing a certain synchronization step in the middle will not affect the overall synchronization function.

Description

Technical Field

[0001] The present invention relates to the technical field of data synchronization, and in particular to a data synchronization method based on a phased array system. Background Art

[0002] As phased array systems gain increasing application in military and civilian electronic systems, phased array technology itself continues to advance. Digital phased array systems employ digital beamforming, offering advantages over analog phased arrays, such as wide dynamic range, high beam accuracy, and ease of simultaneous multi-beam formation. However, because beamforming occurs in the digital domain, the transceiver channel behind each antenna requires multiple frequency conversion channels and hybrid analog / digital components, such as AD and DA, in addition to the transceiver components found in analog phased arrays. This increases the complexity of the transceiver channel and significantly increases the number of components.

[0003] In the existing technology, with the development of the field of digital phased array, the number of channels contained in a digital phased array system ranges from dozens to tens of thousands. For such a large number of channels, modular design is generally adopted in consideration of cost and maintenance convenience when designing the solution. However, for complex systems, especially those with high signal sampling rates, large bandwidths, large data volumes, and communication between multiple modules, how to ensure the synchronization of data among modules is the core and difficulty of the phased array system. In view of this, we propose a data synchronization method based on the phased array system. Summary of the Invention

[0004] In response to the shortcomings of the existing technology, the present invention provides a data synchronization method based on a phased array system, which solves the problem of difficulty in synchronizing data among modules in complex systems, especially those with high signal sampling rates, large bandwidths, large data volumes, and communication between multiple modules.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solutions: A data synchronization method based on a phased array system, comprising the following steps:

[0006] Step S1: System determination of the digital phased array system. The digital phased array system includes clock synchronization, acquisition synchronization, DDC synchronization, and data transmission synchronization. All synchronizations require a synchronization master control system.

[0007] Step S2, system clock synchronization, the synchronization master control system first pulls up CLK_SYNC_FLAG, and then generates SYNC to generate a synchronous clock signal CLK_SYNC;

[0008] Step S3: System acquisition synchronization: the synchronization master control system first pulls up SAMPLE_SYNC_FLAG and then generates SYNC, generating a synchronous clock signal SAMPLE_SYNC;

[0009] Step S4, DDC module synchronization. During the DDC module synchronization process, the synchronization master control system first pulls up DDC_SYNC_FLAG and then generates SYNC to generate a synchronization clock signal DDC_SYNC.

[0010] Step S5, system data transmission synchronization, the data transmission module sends the data after the previous steps of synchronization processing to the back end for corresponding data processing. Only when each of the previous steps of processing is synchronized can the transmitted data be more reliable. During data transmission, a synchronous SYNC is required to trigger all transmission modules to send data at the same time.

[0011] Optionally, the step S2 further includes: the clock solution adopts a phase-locked loop chip with a SYNC function, and all clocks can be synchronized by pulling the SYNC of the chip.

[0012] Optionally, the step S3 further includes: the digital phased array system performs synchronous acquisition according to a synchronous clock signal SAMPLE_SYNC.

[0013] Optionally, the step S4 further includes: DDC synchronization can be processed inside the ADC chip or inside the FPGA.

[0014] Optionally, step S4 includes:

[0015] If processing is done inside the ADC chip, the synchronization function of the ADC chip needs to be configured according to this trigger signal;

[0016] If corresponding processing is performed inside the FPGA, the DDC module needs to be reset synchronously according to this synchronization signal.

[0017] Optionally, data is transmitted between different systems in the digital phased array system via optical fiber transmission.

[0018] Optionally, the synchronous main control system generates a synchronization flag according to different synchronization commands, by first pulling up the synchronization flag and then generating SYNC to generate a corresponding synchronization signal; even if the subsystem receives a SYNC signal but does not receive the corresponding synchronization flag, it will not be triggered by mistake.

[0019] The present invention provides a data synchronization method based on a phased array system. It has the following beneficial effects:

[0020] 1. This data synchronization method based on the phased array system facilitates problem troubleshooting. Whether in design or actual use, if a problem occurs, it can be quickly found by step-by-step troubleshooting according to the modularization. It can effectively improve the efficiency of system data synchronization and optimize the data processing efficiency of related systems. At the same time, the modular setting can reduce equipment costs and improve the convenience of equipment maintenance.

[0021] 2. This data synchronization method based on the phased array system can delete the corresponding modules according to the complexity of the system. For a relatively simple system, removing a certain step of synchronization function will not affect the overall synchronization function. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic diagram of the structure of the system of the present invention;

[0023] Figure 2 Schematic diagram of the timing structure of the signal of the system of the present invention. DETAILED DESCRIPTION

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0025] See also Figure 1-Figure 2 The present invention provides a technical solution: a data synchronization method based on a phased array system, comprising the following steps:

[0026] S1. Systematize the digital phased array system. The digital phased array system includes clock synchronization, acquisition synchronization, DDC synchronization, and data transmission synchronization. All synchronization requires a synchronization master control system. All synchronization instructions are sent through the synchronization master control system, and it is guaranteed that all control signals reach the subsystems at the same time.

[0027] S2. System clock synchronization. The synchronization master control system first pulls up CLK_SYNC_FLAG and then generates SYNC. This generates the synchronous clock signal CLK_SYNC. The clock solution uses a phase-locked loop chip with a SYNC function. By pulling the SYNC function of the chip, all clocks can be synchronized. The clock is the core of the phased array system. The clocks of all modules in the system come from the clock module. Only by ensuring that all system clocks are synchronized can the entire system work properly.

[0028] S3, system acquisition synchronization. For system acquisition synchronization, the synchronization master control system first pulls up SAMPLE_SYNC_FLAG and then generates SYNC, which generates the synchronization clock signal SAMPLE_SYNC. The system performs synchronous acquisition based on this signal. Phased array systems have many acquisition channels. Only by ensuring the phase consistency of each acquisition system can the synthesis gain in beamforming be maximized. Therefore, it is necessary to ensure that the data collected by all acquisition systems in the entire system are synchronized.

[0029] S4, DDC module synchronization. During the DDC module synchronization process, the synchronization master control system first pulls up DDC_SYNC_FLAG and then generates SYNC, which generates the synchronization clock signal DDC_SYNC. DDC synchronization can be processed inside the ADC chip or inside the FPGA. If it is processed inside the ADC chip, the synchronization function of the ADC chip needs to be configured according to this trigger signal. If it is processed inside the FPGA, the DDC module needs to be reset according to this synchronization signal. The data collected in the digital phased array generally needs to be down-converted, and DDC synchronization is also a very important step in the synchronization of the entire system.

[0030] S5. System data transmission synchronization. The data transmission module sends the data processed by the previous steps to the backend for corresponding data processing. Only when each step is synchronized can the transmitted data be reliable. Because phased array systems have many channels and large data volumes, fiber optic transmission is generally used. Therefore, a synchronization SYNC is required to trigger all transmission modules to send data simultaneously. Since different systems in a phased array system transmit data via fiber optic transmission at a high transmission rate, synchronous transmission is required to ensure data synchronization between subsystems.

[0031] In order to reduce the complexity of the design and improve the stability of the system, all system synchronization signals are triggered by a SYNC signal of the synchronous main control system. In addition, the synchronous main control system generates a synchronization flag according to different synchronization commands. By first pulling the synchronization flag high and then generating SYNC, the corresponding synchronization signal can be generated. In this way, even if the subsystem receives a SYNC signal but does not receive the corresponding synchronization flag, it will not be triggered incorrectly.

[0032] This data synchronization method based on the phased array system facilitates problem troubleshooting. Whether in design or actual use, if a problem occurs, it can be quickly found by step-by-step troubleshooting according to the modularization. It can effectively improve the efficiency of system data synchronization and optimize the data processing efficiency of related systems. At the same time, the modular setting can reduce equipment costs and improve the convenience of equipment maintenance.

[0033] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A data synchronization method based on a phased array system, characterized by: The following steps are involved: Step S1: System determination of the digital phased array system. The digital phased array system includes clock synchronization, acquisition synchronization, DDC synchronization, and data transmission synchronization. All synchronizations require a synchronization master control system. Step S2, system clock synchronization, the synchronization master control system first pulls up CLK_SYNC_FLAG, and then generates SYNC to generate a synchronous clock signal CLK_SYNC; Step S3: System acquisition synchronization: the synchronization master control system first pulls up SAMPLE_SYNC_FLAG and then generates SYNC, generating a synchronous clock signal SAMPLE_SYNC; Step S4, DDC module synchronization. During the DDC module synchronization process, the synchronization master control system first pulls up DDC_SYNC_FLAG and then generates SYNC to generate a synchronization clock signal DDC_SYNC. The step S4 further includes: the DDC synchronization can be processed inside the ADC chip or inside the FPGA; the step S4 includes: if the processing is performed inside the ADC chip, the synchronization function of the ADC chip needs to be synchronously configured according to the trigger signal; if the processing is performed inside the FPGA, the DDC module needs to be synchronously reset according to the synchronization signal; Step S5: System data transmission synchronization. The data transmission module sends the data processed by the previous steps to the backend for corresponding data processing. Only when each step is synchronized can the transmitted data be more reliable. During data transmission, a synchronization SYNC is required to trigger all transmission modules to send data simultaneously. The synchronous main control system generates a synchronization flag according to different synchronization commands, and generates a corresponding synchronization signal by first pulling up the synchronization flag and then generating SYNC; even if the subsystem receives the SYNC signal but not the corresponding synchronization flag, it will not be triggered by mistake.

2. The data synchronization method based on a phased array system according to claim 1, characterized in that: The step S2 further includes: the clock solution adopts a phase-locked loop chip with a SYNC function, and all clocks can be synchronized by pulling the SYNC of the chip.

3. The data synchronization method based on a phased array system according to claim 1, characterized in that: The step S3 further includes: the digital phased array system performs synchronous acquisition according to the synchronous clock signal SAMPLE_SYNC.

4. The data synchronization method based on a phased array system according to claim 1, characterized in that: Data transmission between different systems in the digital phased array system is performed via optical fiber transmission.

Images