A low voltage low power reference circuit with temperature compensation

Abstract

The application discloses a low-voltage and low-power reference voltage circuit with temperature compensation, comprising: a starting circuit connected with a power supply, used for making the reference voltage circuit deviate from the original zero bias point and enter a working state; a bias circuit, used for converting a bias current into a bias voltage of an operational amplifier circuit; the operational amplifier circuit, used for voltage clamping the voltage between two preset points in a voltage reference core circuit; the voltage reference core circuit, used for outputting a first-order temperature compensation reference voltage, and clamping the first-order temperature compensation reference voltage to another output point on the voltage reference core circuit through the operational amplifier circuit, so as to generate the bias current; and a temperature compensation circuit, used for generating a temperature compensation current, which is used for temperature compensation of the current flowing through the output end of the temperature compensation circuit. The application can meet the requirements of temperature performance, low power consumption and low power supply voltage, and can be widely applied in the field of circuit systems.

Description

Technical Field

[0001] The present invention relates to the field of circuit systems, and in particular to a low-voltage and low-power reference voltage circuit with temperature compensation. Background Art

[0002] With the rapid development of IoT technology, sensors used in various IoT nodes must operate under conditions where tiny batteries or natural energy sources are less than ideal, while also meeting long operating times and compact size. These long operating times and less-than-ideal natural energy supply requirements necessitate low-voltage, low-power designs for sensor circuits. To achieve this, a voltage reference circuit with good performance and meeting these requirements is necessary. Voltage reference circuits are fundamental building blocks in analog circuits and play a crucial role in various circuit systems. Their performance often impacts the overall performance of the entire circuit.

[0003] In 2012, Mingoo Seok and Gyouho Kim proposed a two-transistor structure to meet the requirements of low power consumption, small area, and a minimal VDD supply voltage. This structure avoids the need for amplifiers, saturated devices, and a resistor-based voltage reference. This significantly reduces power consumption while maintaining good TC temperature coefficient, linear sensitivity, and PSRR (power supply rejection ratio). They also analyzed several variations of the two-transistor structure and studied the technology's portability.

[0004] In 2019, Jie Lin proposed a new voltage and current reference (VCR) in a simple circuit. REF Generated by two NMOS transistors with different thresholds in series, the bias current is weakly dependent on temperature and is determined by V REF This is achieved by dividing by a temperature-insensitive resistor. Even when the temperature and supply voltage vary, the current consumption remains nearly constant, making it very useful for easier energy management in low-power IoT systems. However, there is room for further optimization of its temperature coefficient performance and power consumption.

[0005] In 2021, Lidan Wang proposed a CMOS sub-bandgap voltage reference using a single BJT and two resistors. The proposed negative temperature characteristic voltage generator circuit not only occupies a small area but is also less sensitive to the current mirror effect. Experimental results demonstrate the robustness and good performance of the circuit structure. However, due to the use of BJT transistors, the circuit's operating voltage is limited to above 0.7V, and power consumption is relatively high.

[0006] In 2021, Cheng-Ze Shao and Shih-Che Kuo proposed a startup setup time enhancement technology, using self-biasing and capacitive coupling to realize a voltage reference based on stacked diode-connected MOS transistors (SDMTs). The design achieved a 1% startup setup time of 0.2ms, which is 274 times higher than the design without increasing the startup setup time at the same power consumption of 1.8nW. The measured PSRR is -73.5dB at 100Hz, which is enough to suppress the primary interference coupling from the power supply, and the circuit does not use the trimming circuit, but its temperature coefficient performance does not have much advantage.

[0007] Therefore, the above problems need to be solved urgently. Summary of the Invention

[0008] In view of this, an embodiment of the present invention provides a low-voltage and low-power reference voltage circuit with temperature compensation, which is used to take into account the temperature performance requirements of the reference voltage circuit and the requirements of low power consumption and low power supply voltage.

[0009] One aspect of an embodiment of the present invention provides a low-voltage and low-power reference voltage circuit with temperature compensation, comprising: a startup circuit, a bias circuit, an operational amplifier circuit, a voltage reference core circuit, and a temperature compensation circuit;

[0010] The startup circuit is connected to a power supply and is used to make the reference voltage circuit deviate from the original zero bias point and enter a preset working state;

[0011] The bias circuit is configured to convert a bias current into a bias voltage of the operational amplifier circuit, wherein the bias current is a current flowing through the bias circuit when the reference voltage circuit is in the preset working state;

[0012] The operational amplifier circuit is used to clamp the voltage between two preset points in the voltage reference core circuit;

[0013] The voltage reference core circuit is configured to output a first-order temperature-compensated reference voltage, and clamp the first-order temperature-compensated reference voltage to another output point on the voltage reference core circuit through the operational amplifier circuit to generate the bias current;

[0014] The temperature compensation circuit is used to generate a temperature compensation current, and the temperature compensation current is used to perform temperature compensation on the current flowing through the output end of the temperature compensation circuit.

[0015] Optionally, the startup circuit includes a PMOS transistor: MS1, and NMOS transistors: MS2 and MS3;

[0016] Among them, the source and drain of MS1 are connected to the power supply, the gate of MS1 is connected to the gate of MS2 and the drain of MS3 respectively; the sources of MS2 and MS3 are connected to the ground; the drain of MS2 is connected to the temperature compensation circuit; and the gate of MS3 is connected to the output end of the temperature compensation circuit.

[0017] Optionally, the bias circuit includes a PMOS transistor: MP1, and NMOS transistors: MN1 and MN2;

[0018] The source of MP1 is connected to the power supply, the gate of MP1 is connected to the first input terminal of the temperature compensation circuit, the drain of MP1 is connected to the drain of MN1 and the gate of MN1 respectively; the source of MN1 is connected to the drain and gate of MN2 respectively; the source of MN2 is connected to the ground;

[0019] The gate of MN1 is also connected to the operational amplifier circuit; the gate of MN2 is also connected to the operational amplifier circuit.

[0020] Optionally, the operational amplifier circuit includes PMOS transistors: MP2, MP3 and MP4, NMOS transistors: MN3, MN4, MN5, MN6, P and M N ;

[0021] The sources of MP2, MP3 and MP4 are connected to the power supply, the gate of MP2 is connected to the first input terminal of the temperature compensation circuit, and the drain of MP2 is connected to the M P The drain and M N The drain of MN3 is connected to the gate of MP4; the drain of MN3 is connected to the gate and drain of MP3 respectively; the drain of MN4 is connected to the drain of MP4 and the first input terminal of the temperature compensation circuit respectively; the gate of MN3 is connected to the gate of MN4; the drain of MN5 is connected to the source of MN3 and M P The source of MN5 is connected to the gate of MN6, the source of MN5 is connected to the ground; the drain of MN6 is connected to the source of MN4 and the drain of MN6 respectively. N The source of MN6 is connected to the ground;

[0022] M P The gate of M is connected to the voltage reference core circuit; N The gate is connected to the voltage reference core circuit;

[0023] The gate of the MN1 is further connected to the operational amplifier circuit; the gate of the MN2 is further connected to the operational amplifier circuit, including:

[0024] The gate of MN1 is also connected to the gate of MN3 and the gate of MN4 respectively; the gate of MN2 is also connected to the gate of MN5 and the gate of MN6 respectively.

[0025] Optionally, the voltage reference core circuit includes PMOS transistors: MP5 and MP6, and NMOS transistors: MN7, MN8, and MN9;

[0026] The source of MP5 and the source of MP6 are connected to the power supply, the gate of MP5 and the gate of MP6 are respectively connected to the first input terminal of the temperature compensation circuit, the drain of MP5 is connected to the drain of MN7, the drain of MP6 is respectively connected to the drain and gate of MN9; the gate of MN7 is respectively connected to the drain of MP5 and the gate of MN8, the source of MN7 is connected to the drain of MN8; the source of MN8 is connected to the ground, and the source of MN9 is connected to the ground;

[0027] The M P The gate of M is connected to the voltage reference core circuit; N The gate is connected to the voltage reference core circuit, including:

[0028] M P The gate of M is connected to the drain of MP6; N The gate of is connected to the source of MN7.

[0029] Optionally, the voltage reference core circuit further includes a compensation capacitor;

[0030] One end of the compensation capacitor is connected to the power supply, and the other end is connected to the gate of MP5 and the gate of MP6 respectively.

[0031] Optionally, the temperature compensation circuit includes PMOS transistors: MP7 and MP8, and NMOS transistors: MN10, MN11, and MN12;

[0032] In which, the first input end of the temperature compensation circuit is respectively connected to the gate of MP7 and the gate of MP8, and the first input end of the temperature compensation circuit is also respectively connected to the startup circuit, the bias circuit, the operational amplifier circuit and the voltage reference core circuit; the second input end of the temperature compensation circuit is respectively connected to the source of MP7 and the source of MP8, and the second input end of the temperature compensation circuit is also connected to the power supply; the third input end of the temperature compensation circuit is respectively connected to the source of MN10, the source of MN11 and the source of MN12, and the third input end of the temperature compensation circuit is also connected to the ground; the output end of the temperature compensation circuit is respectively connected to the drain of MP8, the drain of MN12, the gate of MN12 and the drain of MN11; the drain of MP7 is respectively connected to the drain of MN10, the gate of MN10 and the gate of MN11.

[0033] Optionally, the temperature compensation circuit further includes an output capacitor;

[0034] One end of the output capacitor is connected to the output end of the temperature compensation circuit, and the other end is connected to the third input end of the temperature compensation circuit.

[0035] Optionally, the power supply is VDD.

[0036] Optionally, both the PMOS transistor and the NMOS transistor are configured to operate in a subthreshold region.

[0037] In order to solve the problem that the existing reference voltage circuit cannot achieve low voltage and low power consumption circuit design using BJT transistors, and the CMOS subthreshold voltage reference cannot achieve good temperature performance, the present invention uses an operational amplifier circuit to clamp the reference voltage and further performs subsequent high temperature compensation on the reference voltage, wherein the first-order temperature compensated voltage reference output is converted into the bias current of the circuit through the operational amplifier circuit, and the bias current is converted into the current of each branch of the entire circuit through the current mirror structure. The temperature compensation circuit generates a temperature compensation current under high temperature conditions and performs temperature compensation on the current flowing through the output end of the temperature compensation circuit. The reference voltage circuit of the present invention does not use BJT transistors and has the advantage of low temperature compensation cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1A circuit structure diagram of a low-voltage and low-power reference voltage circuit with temperature compensation provided by an embodiment of the present invention;

[0040] Figure 2 A temperature performance curve comparison diagram provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0042] It should be noted that although the functional modules are divided in the device schematic and the logical order is shown in the flow chart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flow chart. The terms "first", "second", etc. in the specification, claims and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0044] The existing CMOS low-power reference voltage circuit cannot well balance the temperature performance of the reference voltage circuit with the requirements of low power consumption and low power supply voltage, while the reference voltage structure using a BJT transistor cannot achieve low power consumption and low power supply voltage.

[0045] In view of this, the embodiment of the present invention provides a low voltage and low power reference voltage circuit with temperature compensation. For the specific structure of the circuit, please refer to Figure 1 , which specifically includes: a startup circuit, a bias circuit, an operational amplifier circuit, a voltage reference core circuit and a temperature compensation circuit.

[0046] First, yes Figure 1The current of each branch is explained, and the first-order temperature compensated voltage reference output is converted into the bias current I of the reference voltage circuit through the operational amplifier circuit. bias and uses a current mirror structure to bias the current I bias Converted into the current I of each branch of the entire circuit bias1 -I bias7 .in addition, Figure 1 V in REF Indicates the output voltage of the reference voltage circuit.

[0047] Then, each part of the reference voltage circuit is described. Among them, the startup circuit is connected to the power supply, and is used to make the reference voltage circuit deviate from the original zero bias point and enter a preset working state;

[0048] The bias circuit is configured to convert a bias current into a bias voltage of the operational amplifier circuit, wherein the bias current is a current flowing through the bias circuit when the reference voltage circuit is in the preset working state;

[0049] The operational amplifier circuit is used to clamp the voltage between two preset points in the voltage reference core circuit;

[0050] The voltage reference core circuit is configured to output a first-order temperature-compensated reference voltage, and clamp the first-order temperature-compensated reference voltage to another output point on the voltage reference core circuit through the operational amplifier circuit to generate the bias current;

[0051] The temperature compensation circuit is used to generate a temperature compensation current, and the temperature compensation current is used to perform temperature compensation on the current flowing through the output end of the temperature compensation circuit.

[0052] Next, each circuit in the reference voltage circuit according to the embodiment of the present invention will be further described.

[0053] Regarding the startup circuit, the startup circuit includes a PMOS transistor: MS1, NMOS transistors: MS2 and MS3;

[0054] Among them, the source and drain of MS1 are connected to the power supply, the gate of MS1 is connected to the gate of MS2 and the drain of MS3 respectively; the sources of MS2 and MS3 are connected to the ground; the drain of MS2 is connected to the temperature compensation circuit; and the gate of MS3 is connected to the output end of the temperature compensation circuit.

[0055] Specifically, the startup circuit may include a PMOS transistor: MS1, and NMOS transistors: MS2 and MS3. The startup circuit may cause the reference voltage circuit to deviate from the original zero bias point, thereby achieving a normal circuit working state.

[0056] Among them, MS1 acts as a capacitor. When the power supply is just turned on, the voltage output by the reference voltage circuit is zero. At this time, MS3 is closed. Through continuous charging, as the gate voltage of MS2 increases, MS2 turns on. Then, the gate voltages of MP5 and MP6 are pulled down. Current flows through the two branches of the voltage reference core circuit, I bias and I bias5 , copied to each branch of the circuit through the current mirror, the reference voltage circuit starts to work normally. When the output voltage reference of the reference voltage circuit is greater than the V TH (MS3 threshold voltage), MS3 turns on, the gate voltage of MS2 is pulled low, MS2 turns off, and the startup circuit is turned off.

[0057] Regarding the bias circuit, the bias circuit includes a PMOS transistor: MP1, and NMOS transistors: MN1 and MN2;

[0058] The source of MP1 is connected to the power supply, the gate of MP1 is connected to the first input terminal of the temperature compensation circuit, the drain of MP1 is connected to the drain of MN1 and the gate of MN1 respectively; the source of MN1 is connected to the drain and gate of MN2 respectively; the source of MN2 is connected to the ground;

[0059] The gate of MN1 is also connected to the operational amplifier circuit; the gate of MN2 is also connected to the operational amplifier circuit.

[0060] Specifically, the bias circuit includes a PMOS transistor: MP1, NMOS transistors: MN1 and MN2, and the bias circuit will be biased from the bias current I bias Copied I bias1 Converted to the bias voltage of the folded cascode amplifier, which is the bias voltage of the operational amplifier circuit.

[0061] Regarding the operational amplifier, the operational amplifier circuit includes PMOS tubes: MP2, MP3 and MP4, NMOS tubes: MN3, MN4, MN5, MN6, M P and M N ;

[0062] The sources of MP2, MP3 and MP4 are connected to the power supply, the gate of MP2 is connected to the first input terminal of the temperature compensation circuit, and the drain of MP2 is connected to the M P The drain and M N The drain of MN3 is connected to the gate of MP4; the drain of MN3 is connected to the gate and drain of MP3 respectively; the drain of MN4 is connected to the drain of MP4 and the first input terminal of the temperature compensation circuit respectively; the gate of MN3 is connected to the gate of MN4; the drain of MN5 is connected to the source of MN3 and M PThe source of MN5 is connected to the gate of MN6, the source of MN5 is connected to the ground; the drain of MN6 is connected to the source of MN4 and the drain of MN6 respectively. N The source of MN6 is connected to the ground;

[0063] M P The gate of M is connected to the voltage reference core circuit; N The gate is connected to the voltage reference core circuit;

[0064] The gate of the MN1 is further connected to the operational amplifier circuit; the gate of the MN2 is further connected to the operational amplifier circuit, including:

[0065] The gate of MN1 is also connected to the gate of MN3 and the gate of MN4 respectively; the gate of MN2 is also connected to the gate of MN5 and the gate of MN6 respectively.

[0066] Specifically, the operational amplifier circuit includes PMOS transistors: MP2, MP3 and MP4, NMOS transistors: MN3, MN4, MN5, MN6, M P and M N Taking into account power consumption, speed, gain, and swing, in an optional implementation, an embodiment of the present invention can use a folded cascode operational amplifier as an operational amplifier circuit to stabilize the voltage between points VN and VP and clamp the voltage.

[0067] Regarding the voltage reference core circuit, the voltage reference core circuit includes PMOS transistors: MP5 and MP6, and NMOS transistors: MN7, MN8, and MN9;

[0068] The source of MP5 and the source of MP6 are connected to the power supply, the gate of MP5 and the gate of MP6 are respectively connected to the first input terminal of the temperature compensation circuit, the drain of MP5 is connected to the drain of MN7, the drain of MP6 is respectively connected to the drain and gate of MN9; the gate of MN7 is respectively connected to the drain of MP5 and the gate of MN8, the source of MN7 is connected to the drain of MN8; the source of MN8 is connected to the ground, and the source of MN9 is connected to the ground;

[0069] The M P The gate of M is connected to the voltage reference core circuit; N The gate is connected to the voltage reference core circuit, including:

[0070] M P The gate of M is connected to the drain of MP6; N The gate of is connected to the source of MN7.

[0071] Specifically, the voltage reference core circuit includes PMOS transistors MP5 and MP6, and NMOS transistors MN7, MN8, and MN9. MN8 is a thick-gate NMOS transistor. The structure, formed by connecting two NMOS transistors, MN7 and MN8, with different threshold voltages, outputs a first-order temperature-compensated reference voltage at VN. This voltage is then clamped to VP by an operational amplifier circuit, generating bias currents for each branch of the reference voltage circuit. This current is then replicated to each branch of the reference voltage circuit by a current mirror structure.

[0072] Furthermore, the voltage reference core circuit of the embodiment of the present invention may further include a compensation capacitor, one end of which is connected to the power supply, and the other end of which is connected to the gate of MP5 and the gate of MP6 respectively.

[0073] Specifically, the compensation capacitor can be recorded as C C , used to compensate the feedback loop of the reference voltage circuit and stabilize it.

[0074] Regarding the temperature compensation circuit, the temperature compensation circuit includes PMOS transistors: MP7 and MP8, and NMOS transistors: MN10, MN11, and MN12;

[0075] In which, the first input end of the temperature compensation circuit is respectively connected to the gate of MP7 and the gate of MP8, and the first input end of the temperature compensation circuit is also respectively connected to the startup circuit, the bias circuit, the operational amplifier circuit and the voltage reference core circuit; the second input end of the temperature compensation circuit is respectively connected to the source of MP7 and the source of MP8, and the second input end of the temperature compensation circuit is also connected to the power supply; the third input end of the temperature compensation circuit is respectively connected to the source of MN10, the source of MN11 and the source of MN12, and the third input end of the temperature compensation circuit is also connected to the ground; the output end of the temperature compensation circuit is respectively connected to the drain of MP8, the drain of MN12, the gate of MN12 and the drain of MN11; the drain of MP7 is respectively connected to the drain of MN10, the gate of MN10 and the gate of MN11.

[0076] Specifically, the temperature compensation circuit includes PMOS transistors: MP7 and MP8, and NMOS transistors: MN10, MN11, and MN12. The temperature compensation structure composed of MP7, MN10, and MN11 utilizes the exponential characteristic of subthreshold current with respect to temperature to generate a temperature compensation current I under high temperature conditions. C The current flowing through the output end of the temperature compensation circuit is temperature compensated, thereby improving the temperature performance of the reference voltage circuit under high temperature conditions.

[0077] Further, the temperature compensation circuit can further include an output capacitor, one end of the output capacitor being connected with an output end of the temperature compensation circuit, and the other end being connected with a third input end of the temperature compensation circuit.

[0078] Specifically, the output capacitor can be denoted as C OUT , which is used to stabilize the reference voltage circuit output node level.

[0079] Optionally, the power supply in the embodiment of the present applicationapplicationemploy VDD, or a suitable type of power supply can be selected according to the actual application scenario of the circuit.

[0080] It should be noted that all the transistors in the embodiment of the present application, i.e., all the PMOS tubes and all the NMOS tubes, can be set to work in the sub-threshold region. All the transistors in the circuit are set to work in the sub-threshold region, and the purpose is to reduce the power supply operating voltage and power consumption, and to realize the application requirement of low voltage and low power consumption.

[0081] In summary, the present application has the following advantages and effects relative to the prior art:

[0082] 1. Since the sub-threshold CMOS structure is adopted, and no BJT transistor is used, the advantages of low power consumption and low power supply voltage are brought.

[0083] 2. Since the temperature compensation circuit is adopted, the advantages of wide temperature range and low temperature coefficient are brought.

[0084] 3. The low-power start-up circuit is adopted, so that the reference voltage circuit can quickly escape from the zero start-up point, and since the start-up circuit is closed under normal operation, no additional operating power consumption is brought.

[0085] Exemplarily, the embodiment of the present application provides a temperature performance curve comparison chart, details of which can be referred to Figure 2 .

[0086] Figure 2 is the simulation result of the reference voltage circuit when the output of the reference voltage circuit follows the temperature characteristic after the temperature compensation circuit is added. It can be seen that after the temperature compensation circuit of the embodiment of the present application is added, the temperature curve is effectively compensated in the high-temperature state, the sensitivity of the output voltage reference to temperature is reduced, and the circuit operating range of the entire reference voltage circuit is improved.

[0087] Specifically, Figure 2 The horizontal coordinate is temperature, and the vertical coordinate is the value of the output reference voltage. At room temperature, the two outputs are not much different, and are 308.34 mV and 308.21 mV, respectively. After the temperature compensation circuit is added, the temperature coefficient is improved to 6.42 ppm / ℃. The definition formula of the temperature coefficient TC is as follows:

[0088]

[0089] Where V REF,max Indicates the maximum value of the voltage reference output within the temperature range, V REF,min Indicates the minimum value of the voltage reference output within the temperature range, V REF,avg represents the average value of the voltage reference output over the entire temperature range, and TR represents the measured temperature range. Since the unit is one part per million, the unit of each variable in the definition needs to be multiplied by 1,000,000.

[0090] In order to describe the present invention more clearly, the application process of the present invention will be described below with specific examples.

[0091] The embodiment of the present invention proposes a CMOS subthreshold reference voltage circuit, and its specific circuit structure can still refer to Figure 1 The reference voltage circuit of the embodiment of the present invention includes a startup circuit, a bias circuit, an operational amplifier circuit, a voltage reference core circuit, and a temperature compensation circuit.

[0092] Specifically, the startup circuit includes MS1, MS2, and MS3, which can make the reference voltage circuit deviate from the original zero bias point, thereby achieving a normal circuit working state, in which MS2 acts as a capacitor. When the power supply is just turned on, the voltage reference output voltage value is zero. At this time, MS3 is closed. Through continuous charging, as the gate voltage of MS2 increases, MS2 turns on, and then all the gate voltages of MP5 and MP6 are pulled down. Current flows through the two branches of the voltage reference core circuit and is copied to each branch of the circuit through the current mirror, and the circuit starts to work normally. When the output voltage reference is greater than V TH When the voltage is 0, MS3 turns on, the gate voltage of MS2 is pulled down, MS2 turns off, and the startup circuit is turned off. The low temperature coefficient of the reference voltage circuit is mainly achieved by the temperature compensation circuit, which can adjust the voltage deviation of the output voltage of the voltage reference core circuit at high temperature.

[0093] All transistors in the reference voltage circuit are set to operate in the subthreshold region in order to reduce the power supply operating voltage and power consumption, and to achieve low voltage and low power consumption application requirements. MN8 and MN11 are typical V TH tube, the rest are 1.8V typical V TH The main part of the reference voltage circuit can generate positive temperature characteristic voltage and negative temperature characteristic voltage for linear temperature compensation.

[0094] The drain current I of the subthreshold transistor D As follows:

[0095]

[0096] where μ n is the NMOS carrier mobility, V TH is the threshold voltage of the transistor, V in the subsequent derivation TH It only represents the threshold voltage of NMOS transistor, V TH6 It represents the threshold voltage of MN6 transistor, K is the aspect ratio of the transistor, and different subscripts of K represent different aspect ratios of transistors, such as K P7 Represents the width-to-length ratio of the PMOS:MP7 transistor, K N6 represents the width-to-length ratio of the NMOS:MN6 transistor, C OX It is the gate oxide capacitor, with the same subscript type as K and V T =k B T / q is the thermal voltage, k B is the Boltzmann constant, T is the absolute temperature, q is the basic charge, and m is the subthreshold slope factor. In the derivation process, it can be approximated that the same type of NMOS transistor has C OX and V TH are equal, and the subthreshold slope factor m of any NMOS transistor is equal.

[0097] When the source-drain voltage of the transistor V DS ≥3V T , at this time the drain current of the subthreshold transistor can be approximated as:

[0098]

[0099] Since the drain current flowing through MN7 and MN8 is the same and there is a threshold voltage difference between MN7 and MN8, the voltage V N for:

[0100]

[0101] It can be seen that the voltage of node N is basically independent of the branch current, and due to the use of NMOS transistors with different gate oxide thicknesses, the difference in threshold voltage ΔV TH A negative temperature characteristic voltage is generated:

[0102] ΔV TH =ΔV TH0 +(α N8 -α N7 )(T-T0)

[0103] Among them, α N7 and α N8 are the first-order derivatives of the threshold voltages of NMOS transistors MN7 and MN8 with respect to temperature, ΔV TH0is the threshold voltage difference at room temperature, T0 is 300K. At the same time, due to the generation of α N8 -α N7 The negative temperature characteristic voltage coefficient difference, thermal voltage V T The coefficient generating the positive temperature characteristic voltage does not need to be too large to cancel the first-order temperature coefficient.

[0104] According to the characteristics of the operational amplifier, V P The voltage at the point is forced and V N The points are the same, so the bias current is:

[0105]

[0106] The final output voltage reference is determined by I OUT Generate, and I OUT =I bias6 -I C , where I bias6 For I bias The current mirror is used to copy the past current in a certain proportion according to the width-to-length ratio of the current mirror tube, I C The compensation current generated by the temperature compensation structure is used to compensate for the temperature characteristics under high temperature conditions. The gate bias voltage of the temperature compensation structure, that is, Figure 1 The voltage at the common connection point of the drain of MP7, the drain and gate of MN10, and the gate of MN11 is denoted as G. The voltage at point G is V G is the compensation current I C The control voltage is:

[0107]

[0108] And because I C To compensate only for the high temperature portion of the circuit, MN11 uses transistors with thicker gate oxides to reduce I C , compensation current I C as follows:

[0109]

[0110] And finally by I OUT The voltage reference output value generated by the active load MN12 is:

[0111]

[0112] It can be seen that when the temperature is not high, V T Smaller, can be approximated to zero, then the following relationship holds:

[0113]

[0114] At this time V REF Similar to the voltage of the node N, the negative temperature characteristic voltage generated by the threshold voltage difference and the positive temperature characteristic voltage with controllable coefficient can be superimposed to eliminate the first order coefficient of temperature by adjusting the width-length ratio. When the circuit is in a high temperature state, the voltage is no longer dominated by the first order temperature coefficient as the temperature rises, and compensation for the temperature is required.

[0115] As V T continuously rises, K C can no longer be ignored, and compensation is made for the continuously rising voltage reference output, reducing the temperature coefficient of the voltage reference output and increasing its operating temperature range. The positive temperature characteristic voltage used to compensate for the first order coefficient of the negative temperature characteristic depends on K N7 , K N8 , K N9 , K P6 , K P8 , and the compensation current I C used to compensate for the high temperature current of the circuit is determined by K N7 , K N8 , K N9 , K P6 , K P7 , K N10 , K N11 , K N12 At the same time, the power consumption of the entire circuit is also determined by the width-length ratio of each transistor, so the optimal size of each transistor is a balance between performance and power.

[0116] At the same time, the above theoretical analysis is verified by the simulation results of the reference voltage circuit, which is sufficient to prove that the reference voltage circuit of the embodiment of the present application has good reference circuit performance.

[0117] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0118] Although embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, replacements and variations can be made to these embodiments without departing from the principles and spirit of the present application, and the scope of the present application is defined by the claims and their equivalents.

[0119] The above is a specific description of the preferred embodiment of the present application, but the present application is not limited to the described embodiments, and those skilled in the art can make various equivalent modifications or replacements without departing from the spirit of the present application, and these equivalent modifications or replacements are all included in the scope defined by the claims of the present application.

Claims

1. A low-voltage and low-power reference voltage circuit with temperature compensation, characterized in that: Including startup circuit, bias circuit, operational amplifier circuit, voltage reference core circuit and temperature compensation circuit; The startup circuit is connected to a power supply and is used to make the reference voltage circuit deviate from the original zero bias point and enter a preset working state; The bias circuit is configured to convert a bias current into a bias voltage of the operational amplifier circuit, wherein the bias current is a current flowing through the bias circuit when the reference voltage circuit is in the preset working state; The operational amplifier circuit is used to clamp the voltage between two preset points in the voltage reference core circuit; The voltage reference core circuit is configured to output a first-order temperature-compensated reference voltage, and clamp the first-order temperature-compensated reference voltage to another output point on the voltage reference core circuit through the operational amplifier circuit to generate the bias current; The temperature compensation circuit is used to generate a temperature compensation current, and the temperature compensation current is used to perform temperature compensation on the current flowing through the output end of the temperature compensation circuit; The operational amplifier circuit includes PMOS tubes: MP2, MP3 and MP4, NMOS tubes: MN3, MN4, MN5, MN6, M P and M N ; The sources of MP2, MP3 and MP4 are connected to the power supply, the gate of MP2 is connected to the first input terminal of the temperature compensation circuit, and the drain of MP2 is connected to the M P The drain and M N The drain of MN3 is connected to the gate of MP4; the drain of MN3 is connected to the gate and drain of MP3 respectively; the drain of MN4 is connected to the drain of MP4 and the first input terminal of the temperature compensation circuit respectively; the gate of MN3 is connected to the gate of MN4; the drain of MN5 is connected to the source of MN3 and M P The source of MN5 is connected to the gate of MN6, the source of MN5 is connected to the ground; the drain of MN6 is connected to the source of MN4 and the drain of MN6 respectively. N The source of MN6 is connected to the ground; The voltage reference core circuit includes PMOS transistors: MP5 and MP6, and NMOS transistors: MN7, MN8 and MN9; Wherein, the source of MP5 and the source of MP6 are connected to the power supply, the gate of MP5 and the gate of MP6 are respectively connected to the first input terminal of the temperature compensation circuit, the drain of MP5 is connected to the drain of MN7, the drain of MP6 is respectively connected to the drain and gate of MN9; the gate of MN7 is respectively connected to the drain of MP5 and the gate of MN8, the source of MN7 is connected to the drain of MN8; the source of MN8 is connected to the ground, and the source of MN9 is connected to the ground; MP6 drain and M P The gate of MN7 is connected to the source of M N The gate connection; The temperature compensation circuit includes PMOS transistors: MP7 and MP8, and NMOS transistors: MN10, MN11 and MN12; In which, the first input end of the temperature compensation circuit is respectively connected to the gate of MP7 and the gate of MP8, and the first input end of the temperature compensation circuit is also respectively connected to the startup circuit, the bias circuit, the operational amplifier circuit and the voltage reference core circuit; the second input end of the temperature compensation circuit is respectively connected to the source of MP7 and the source of MP8, and the second input end of the temperature compensation circuit is also connected to the power supply; the third input end of the temperature compensation circuit is respectively connected to the source of MN10, the source of MN11 and the source of MN12, and the third input end of the temperature compensation circuit is also connected to the ground; the output end of the temperature compensation circuit is respectively connected to the drain of MP8, the drain of MN12, the gate of MN12 and the drain of MN11; the drain of MP7 is respectively connected to the drain of MN10, the gate of MN10 and the gate of MN11.

2. A low-voltage and low-power reference voltage circuit with temperature compensation according to claim 1, characterized in that: The startup circuit includes a PMOS transistor: MS1, and NMOS transistors: MS2 and MS3; Among them, the source and drain of MS1 are connected to the power supply, the gate of MS1 is connected to the gate of MS2 and the drain of MS3 respectively; the sources of MS2 and MS3 are connected to the ground; the drain of MS2 is connected to the temperature compensation circuit; and the gate of MS3 is connected to the output end of the temperature compensation circuit.

3. The low-voltage and low-power reference voltage circuit with temperature compensation according to claim 1, characterized in that: The bias circuit includes a PMOS transistor: MP1, and NMOS transistors: MN1 and MN2; The source of MP1 is connected to the power supply, the gate of MP1 is connected to the first input terminal of the temperature compensation circuit, the drain of MP1 is connected to the drain of MN1 and the gate of MN1 respectively; the source of MN1 is connected to the drain and gate of MN2 respectively; the source of MN2 is connected to the ground; The gate of MN1 is also connected to the gate of MN3 and the gate of MN4 respectively; the gate of MN2 is also connected to the gate of MN5 and the gate of MN6 respectively.

4. The low-voltage and low-power reference voltage circuit with temperature compensation according to claim 1, characterized in that: The voltage reference core circuit also includes a compensation capacitor; One end of the compensation capacitor is connected to the power supply, and the other end is connected to the gate of MP5 and the gate of MP6 respectively.

5. The low-voltage and low-power reference voltage circuit with temperature compensation according to claim 1, characterized in that: The temperature compensation circuit further includes an output capacitor; One end of the output capacitor is connected to the output end of the temperature compensation circuit, and the other end is connected to the third input end of the temperature compensation circuit.

6. A low-voltage and low-power reference voltage circuit with temperature compensation according to any one of claims 1 to 5, characterized in that: The power supply is VDD.

7. A low-voltage and low-power reference voltage circuit with temperature compensation according to any one of claims 2 to 5, characterized in that: The PMOS transistor and the NMOS transistor are both configured to operate in a subthreshold region.

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