In-memory logic computing system and method with one or non-logic formula

Abstract

The application relates to an in-memory logic computing system of one or non-logic type, which comprises a timing control unit D, at least one set of memory diodes A, B and C and at least one control unit U; the negative poles of the five memory diodes are connected to one end of a bit line, the positive poles of the five memory diodes are connected to different word lines, the other end of the bit line is connected to the control unit U, and the control unit U is used for controlling the bit line to be grounded or pulling the voltage on the bit line to -1 / 2VDD. The in-memory logic computing can be realized in a large-scale storage array, the in-memory computing of the non-Von Neumann architecture is popularized to the general computing field, the energy efficiency and speed of the in-memory computing chip are improved, and the in-memory computing chip is applied to the logic operation field.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of in-memory logic computing system, in particular to an in-memory logic computing system and a computing method of the in-memory logic computing system. BACKGROUND

[0002] In the past few decades, the shrinking of semiconductor device feature size has driven the continuous increase of logic and memory capacity of digital computers. However, with the advent of the post-Moore era, Moore's law has reached its limit. The physical limit of the feature size of standard CMOS elements is approaching. This means that the expansion of computing power will reach a limit in the next ten or twenty years. A feasible solution for future growth of computing power is to implement in-memory computing in a non-Von Neumann architecture. In the Von Neumann architecture, the storage unit and the operation unit are separated, which causes two serious problems of limiting the performance of the computing system, namely the "memory wall" and the "power wall". The "memory wall" refers to the speed mismatch between the CPU and the memory. The operation speed of the CPU is much faster than the read-write speed of the memory, and as the CPU develops, its speed improves faster, but the speed of the memory improves relatively slowly, resulting in a lot of wasted time for the CPU waiting for the memory to complete reading and writing, thereby limiting the performance of the entire operation system. The "power wall" refers to the data transmission involved in the process of CPU executing instructions. The CPU needs to read data from the memory and then write the calculation result back to the memory. The data transmission consumes a lot of energy, and when the CPU frequency becomes higher and higher, the data transmission volume also becomes larger and larger, resulting in higher and higher power consumption, thereby limiting the performance of the entire operation system. In-memory computing in a non-Von Neumann architecture can solve these two problems. In a non-Von Neumann architecture, data can be operated directly in the storage unit, which can greatly improve the energy efficiency and speed of the chip.

[0003] In the past decade, the field of analog numerical computing based on in-memory computing has made good progress. However, how to implement in-memory logic operation in a large-scale storage array is still a challenge so far. For a long time, researchers have been studying in-memory logic operation with memory diodes and have made a lot of achievements. However, their previous researches are limited to single logic operation and circuit unit demonstration, and cannot implement in-memory logic operation in a large-scale storage array. Therefore, how to implement a feasible in-memory logic computing system in a large-scale storage array is an urgent problem. SUMMARY

[0004] Disclosed is an in-memory logic computing system and method based on NOR logic. The in-memory logic computing system is based on a memory array with programmable diodes having non-volatility and rectification characteristics. The in-memory logic computing system is capable of directly performing logic operations in memory cells. Compared with conventional solutions, the in-memory logic computing system is easy to operate, has strong scalability, can be used in large-scale memory arrays, and can be used to implement any binary Boolean logic formula. The in-memory logic computing system has important significance for the development of in-memory logic computing.

[0005] The in-memory logic computing system based on NOR logic comprises a timing control unit D, at least one group of memory diodes A, B, C, and at least one control unit U. The negative electrodes of the memory diodes are connected to one end of a bit line, the positive electrodes of the five memory diodes are connected to different word lines, the other end of the bit line is connected to the control unit U, and the word lines are connected to the timing control unit D.

[0006] Further, the memory diodes are based on germanium-based MOS devices.

[0007] Further, the memory diodes are composed of three different layers, the top layer is composed of a metal electrode, the middle layer is composed of a resistance conversion layer, and the bottom layer is composed of a semiconductor electrode. The metal electrode of the top layer is made of Pt metal, the resistance conversion layer is sequentially stacked from bottom to top by germanium oxide, aluminum oxide, and hafnium oxide, and the semiconductor electrode of the bottom layer is made of germanium material.

[0008] Further, in the working state, the bottom electrode of the memory diode is grounded, and a corresponding voltage is applied to the top electrode, so as to realize the conversion of the memory diode between the off state and the on state.

[0009] Further, the resistance of the memory diode in the off state suddenly decreases after a negative voltage is applied. This process is called SET, and the memory diode is converted from the off state to the on state, which can be regarded as a diode device. The resistance of the memory diode in the on state suddenly increases after a positive voltage is applied. This process is called RESET, and the memory diode is converted from the on state to the off state, which can be regarded as a resistor with a high resistance.

[0010] The in-memory logic computing method of the in-memory logic computing system based on NOR logic is used to realize in-memory logic computing by decomposing any binary Boolean logic formula into a NOR logic formula.

[0011] Any binary Boolean logic formula is decomposed into a logic expression based on NOR logic according to the following formula:

[0012] (1) wherein,

[0013] C' is the output of the logic expression, corresponding to the conduction state of the memory diode C, C' is 1, then the corresponding memory diode C is turned on; C' is 0, then the corresponding memory diode C is not turned on;

[0014] A', B' are the inputs of any one binary Boolean logic, logic represents the logic operator, M1, M2, M3, M4 are one of A', B' in the logic expression, and each is different; A', B', corresponding to the conduction state of the memory diode A, B, if A', B', is 1, then the corresponding memory diode A, B, is turned on, if A', B', is 0, then the corresponding memory diode A, B, is not turned on; wherein is the or operation of M1 and M2 followed by negation; is the or operation of M3 and M4 followed by negation; is the negation operation on A'; is the negation operation on B';

[0015] (2) in the first time sequence control process TO-T1 generated by the time sequence control unit D, the memory diode corresponding to the operation M1 and M2, if the logic value corresponding to M1 is logic 1, then the SET voltage is applied to the memory diode corresponding to M1; if the logic value corresponding to M1 is logic 0, then 0 voltage is applied to the memory diode corresponding to M1; if the logic value corresponding to M2 is logic 1, then the SET voltage is applied to the memory diode corresponding to M2; if the logic value corresponding to M2 is logic 0, then 0 voltage is applied to the memory diode corresponding to M2;

[0016] (3) in the second time sequence control process T1-T2 generated by the time sequence control unit D, the memory diode C is operated, and the SET voltage is applied to the memory diode C;

[0017] ​(4) in the third timing control process T2~T3 generated by the timing control unit D, the memory diode corresponding to the operation M3 and M4, if the logic value corresponding to M3 is logic 1, the SET voltage is applied to the memory diode corresponding to M3; if the logic value corresponding to M3 is logic 0, 0 voltage is applied to the memory diode corresponding to M3; if the logic value corresponding to M4 is logic 1, the SET voltage is applied to the memory diode corresponding to M4; if the logic value corresponding to M4 is logic 0, 0 voltage is applied to the memory diode corresponding to M4;

[0018] (5) in the fourth timing control process T3~T4 generated by the timing control unit D, the memory diode C is operated, and the SET voltage is applied to the memory diode C.

[0019] The beneficial effects of the present application are:

[0020] In-memory logic calculation can be realized in a large-scale storage array, in-memory calculation of non-von Neumann architecture is popularized to the general computing field, the energy efficiency and speed of in-memory calculation chip are improved, and the in-memory calculation chip is applied to the logic operation field. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a circuit schematic diagram of the in-memory logic calculation system and calculation method of the present application one or non-logic type;

[0022] Figure 2 is a structural diagram of the memory diode of the in-memory logic calculation system and calculation method of the present application one or non-logic type;

[0023] Figure 3 is a circuit symbol diagram of the memory diode of the in-memory logic calculation system and calculation method of the present application one or non-logic type;

[0024] Figure 4 is an I-V characteristic diagram of the memory diode of the in-memory logic calculation system and calculation method of the present application one or non-logic type;

[0025] Figure 5 is a simulation waveform diagram for realizing binary exclusive or logic by using the in-memory logic calculation system and calculation method of the present application one or non-logic type;

[0026] Figure 6 is a simulation waveform diagram for realizing binary exclusive or logic by using the in-memory logic calculation system and calculation method of the present application one or non-logic type. DETAILED DESCRIPTION

[0027] In order to further illustrate the technical means and effects taken by the present application to achieve the predetermined invention purpose, the specific embodiments, structures, features and effects according to the present application are described in detail below in combination with the drawings and preferred embodiments.

[0028] An in-memory logic computing system of or non-logic formula, comprising a timing control unit D, at least one set of memory diode A, B, C and at least one control unit U; the negative pole of the memory diode is connected to one end of the same bit line, and the positive pole of the five memory diodes is connected to different word lines; the other end of the bit line is connected to the control unit U; the word line is connected to the timing control unit D.

[0029] The memory diode is a memory diode based on a germanium-based MOS device.

[0030] The memory diode is composed of three different structures, the top layer is composed of a metal electrode, the middle layer is composed of a resistance conversion layer, and the bottom layer is composed of a semiconductor electrode; the metal electrode of the top layer is made of Pt metal, the resistance conversion layer is stacked from bottom to top by germanium oxide, aluminum oxide and hafnium oxide, and the semiconductor electrode of the bottom layer is made of germanium material.

[0031] The memory diode is in working state, the bottom electrode is grounded, and the corresponding voltage is applied to the top electrode, so as to realize the conversion of the memory diode between off state and on state.

[0032] The resistance of the memory diode in off state suddenly decreases after applying a negative voltage, which is called SET, and the memory diode changes from off state to on state, which can be regarded as a diode device; the resistance of the memory diode in on state suddenly increases after applying a positive voltage, which is called RESET, and the memory diode changes from on state to off state, which can be regarded as a resistance with high resistance.

[0033] The in-memory logic computing method of the in-memory logic computing system of or non-logic formula is realized by the method of decomposing any binary Boolean logic formula into or non-logic formula, specifically:

[0034] The computing system generates four timing control processes T0-T1, T1-T2, T2-T3 and T3-T4 through the timing control unit D, and at least needs five memory diodes A, B, C and a control unit U, realizes in-memory logic computing by the method of decomposing any binary Boolean logic formula into or non-logic formula, specifically:

[0035] Any binary Boolean logic formula is decomposed into a logic expression with or non-logic as the basic element according to the following formula:

[0036] (1) Wherein, C' is the output in the logic expression, corresponding to the on state of the memory diode C, C' is 1, then the corresponding memory diode C is on; C' is 0, then the corresponding memory diode C is not on;

[0037] A' and B' are the input of any one binary Boolean logic, logic represents the logic operator, M1, M2, M3 and M4 are one of A', B' in the logic expression, and each is different; A', B' is in turn corresponding to the on state of the memory diode A, B, If A', B', is 1, then the corresponding memory diode A, B, is on, if A', B', is 0, then the corresponding memory diode A, B, is not on; wherein M1 and M2 are or operated and then inverted; M3 and M4 are or operated and then inverted; A' is inverted operation; B' is inverted operation; (2) in the first time sequence control process T0~T1 generated by the time sequence control unit D, the operation memory diode corresponding to M1, if the logic value corresponding to M1 is logic 1, then the SET voltage is applied to the memory diode corresponding to M1; if the logic value corresponding to M1 is logic 0, then the 0 voltage is applied to the memory diode corresponding to M1; if the logic value corresponding to M2 is logic 1, then the SET voltage is applied to the memory diode corresponding to M2; if the logic value corresponding to M2 is logic 0, then the 0 voltage is applied to the memory diode corresponding to M2;

[0038] (3) in the second time sequence control process T1~T2 generated by the time sequence control unit D, the operation memory diode C, the SET voltage is applied to the memory diode C;

[0039] (3) in the second time sequence control process T1~T2 generated by the time sequence control unit D, the operation memory diode C, the SET voltage is applied to the memory diode C;

[0040] ​(4) In the third timing control process T2-T3 generated by the timing control unit D, the memory diodes corresponding to M3 and M4 are operated. If the logic value corresponding to M3 is logic 1, a SET voltage is applied to the memory diode corresponding to M3; if the logic value corresponding to M3 is logic 0, a 0 voltage is applied to the memory diode corresponding to M3; if the logic value corresponding to M4 is logic 1, a SET voltage is applied to the memory diode corresponding to M4; if the logic value corresponding to M4 is logic 0, a 0 voltage is applied to the memory diode corresponding to M4;

[0041] (5) In the fourth timing control process T3-T4 generated by the timing control unit D, the memory diode C is operated and the SET voltage is applied to the memory diode C;

[0042] The specific implementation of the present invention takes the realization of XOR logic operation and XNOR logic operation as an example. First, Figure 1 It can be seen that 5 programmable diodes and a control unit are used to implement the XOR operation. Figure 2 As shown in the figure, it consists of three different layers of structure: the top layer is composed of metal electrodes, the middle layer is composed of resistance conversion layer, and the bottom layer is composed of semiconductor electrodes. Figure 3 As shown in the IV characteristic diagram Figure 4 As shown. The bit line of each row aggregates the current of all memory cells in this row in the memory array, which is equivalent to performing an OR operation on the current of all memory cells. The control unit is the key to realizing the OR logic. Each time an OR operation is performed, the control unit reads the current value on the bit line (BITLINE) and determines whether the current value is greater than a preset threshold. Here, the threshold current is the current value when any memory cell on the bit line (BITLINE) is turned on. This means that as long as any memory cell on the bit line (BITLINE) is turned on, the current read into the control unit will be greater than the threshold current. At this time, the voltage on the bit line (BITLINE) will be immediately pulled to -1 / 2VDD. On the contrary, if the current value read into the control unit is not greater than the threshold current, the bit line (BITLINE) will always be connected to the ground line.

[0043] Example 1

[0044] In the XOR operation, first decompose it into a form with OR and NOT logic as the basic logical operation: In this example, assuming input A=1, B=0, then Output C = 1. The operation method is divided into two steps. First, perform A and The first sequence of the NOR operation is 0 to 100 ns. Operation, due to A and The logical values ​​represented are all logical 1, so for A and Apply SET voltage, A and is turned on. Due to A and Both are turned on, so BL is pulled to -1 / 2VDD. Then in the second timing process, that is, 100ns to 200ns, the C unit is operated and a SET voltage is applied to the C unit. The C unit does not reach the turn-on voltage and remains in the cut-off state. A and In the third timing process of 200 to 300 ns, the operation of B and Operation, due to B and The logical values ​​represented are all logical 0, so B and Apply 0 voltage, B and Both are in cut-off state. In this process, BL is not turned on, so it is connected to the ground. Similarly, in the next fourth timing process of 300-400ns, the C unit is operated, and a SET voltage is still applied to the C unit. At this time, since BL is connected to the ground, the two ends of the C unit are turned on and a high current is output, representing a logic 1. At this point, B and The NOR operation is completed, and the XOR operation of A and B is also completed, and the C unit outputs logic 1.

[0045] Example 2

[0046] In the exclusive OR operation, first decompose it into a form with the OR NOT logic as the basic logical operation: In this example, assuming input A=1, B=0, then Output C = 0. The operation method is divided into two steps. First, and The first timing process is 0 to 100 ns. and Operate because The logical value represented by The logical value represented is logic 1, so Apply SET voltage, is turned on. It is turned on, so BL is pulled to -1 / 2VDD. Then in the second timing process, that is, 100ns to 200ns, the C unit is operated and a SET voltage is applied to the C unit. The C unit does not reach the turn-on voltage and remains in the cut-off state. and The NOR operation is complete. In the third timing process, 200-300ns, operations are performed on A and B. Since A represents a logic 1 and B represents a logic 0, a SET voltage is applied to A, turning it on. Since A is turned on, BL is pulled to -1 / 2VDD. Similarly, in the fourth timing process, 300-400ns, cell C is operated, still applying a SET voltage. At this point, since BL is pulled to -1 / 2VDD, cell C does not reach the turn-on voltage and remains in the off state. At this point, the NOR operation of A and B is completed, and the exclusive OR operation of A and B is also completed, with cell C outputting a logic 0.

[0047] Figure 5 shows the simulation results of the XOR logic operation. Figure 6 Table 1 shows the input and output truth table of the in-memory logic computing system for the proposed NOR logic. The simulation results demonstrate that the proposed computing system is feasible. The proposed in-memory logic computing system can be used to implement arbitrary binary Boolean logic expressions in a memory array.

[0048] Table 1 Input and output truth table

[0049]

[0050] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as above in terms of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can, without departing from the scope of the technical solution of the present invention, make some changes or modifications to equivalent embodiments using the technical contents disclosed above. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A method for in-memory logical calculation of an OR-non-logical type, characterized in that: The in-memory logic calculation system adopts the OR-NOT logic type, including a timing control unit D, at least one set of memory diodes A, , B, , C and at least one control unit U; the cathodes of the memory diodes are all connected to one end of the same bit line (Bitline), and the anodes of the five memory diodes are connected to different word lines; the other end of the bit line is connected to the control unit U; the word line is connected to the timing control unit D; The in-memory logic calculation is achieved by decomposing any binary Boolean logic expression into OR and NOT logic expressions. The specific steps are as follows: (1) C ' = logic = + ,in, C ' is the output in the logic expression, corresponding to the conduction state of the memory diode C. If C' is 1, the corresponding memory diode C is conductive; if C' is 0, the corresponding memory diode C is not conductive. 、B It is the input of any binary Boolean logic expression. Logic represents the logical operator. M1, M2, M3, and M4 are the A ’ 、 B ’ 、 、 One of them, and each one is different; A ’ 、 、B ’ 、 Corresponding to memory diode A, , B, The conduction state, if A ’ 、 、B ’ 、 is 1, then the corresponding memory diode A, , B, If A ’ 、 、B ’ 、 is 0, then the corresponding memory diode A, , B, No conduction; Perform an OR operation on M1 and M2 and then invert them; Perform an OR operation on M3 and M4 and then perform the inversion; For Perform the inversion operation; For Perform the inversion operation; (2) In the first timing control process T0~T1 generated by the timing control unit D, the memory diodes corresponding to M1 and M2 are operated. If the logic value corresponding to M1 is logic 1, a SET voltage is applied to the memory diode corresponding to M1; if the logic value corresponding to M1 is logic 0, a 0 voltage is applied to the memory diode corresponding to M1; if the logic value corresponding to M2 is logic 1, a SET voltage is applied to the memory diode corresponding to M2; if the logic value corresponding to M2 is logic 0, a 0 voltage is applied to the memory diode corresponding to M2; (3) In the second timing control process T1~T2 generated by the timing control unit D, the memory diode C is operated and the SET voltage is applied to the memory diode C; (4) In the third timing control process T2~T3 generated by the timing control unit D, the memory diodes corresponding to M3 and M4 are operated. If the logic value corresponding to M3 is logic 1, a SET voltage is applied to the memory diode corresponding to M3; if the logic value corresponding to M3 is logic 0, a 0 voltage is applied to the memory diode corresponding to M3; if the logic value corresponding to M4 is logic 1, a SET voltage is applied to the memory diode corresponding to M4; if the logic value corresponding to M4 is logic 0, a 0 voltage is applied to the memory diode corresponding to M4; (5) In the fourth timing control process T3~T4 generated by the timing control unit D, the memory diode C is operated and the SET voltage is applied to the memory diode C.

2. The one-or-no-logical in-memory logic computing system according to claim 1, characterized in that: The memory diode consists of three different layers: the top layer is composed of a metal electrode, the middle layer is composed of a resistance conversion layer, and the bottom layer is composed of a semiconductor electrode. The top metal electrode is made of Pt metal, the resistance conversion layer is composed of germanium oxide, aluminum oxide, and hafnium oxide stacked in sequence from bottom to top, and the bottom semiconductor electrode is made of germanium material.

3. The one-or-no-logical in-memory logic computing system according to claim 2, characterized in that: The bottom electrode of the memory diode is grounded in the working state, and a corresponding voltage is applied to the top electrode of the memory diode, thereby realizing the conversion between the off state and the on state.

4. The one-or-no-logical in-memory logic computing system according to claim 3, characterized in that: When a negative voltage is applied to a memory diode in the off state, its resistance suddenly decreases. This process is called SET, and the memory diode switches from the off state to the on state, and can be regarded as a diode device. When a forward voltage is applied to a memory diode in the on state, its resistance suddenly increases. This process is called RESET, and the memory diode switches from the on state to the off state, and can be regarded as a resistor with a high resistance value.

5. The method according to claim 1 , wherein when any memory diode on the bit line is turned on during the two timing control processes T0 to T1 and T2 to T3 , the control unit U pulls the bit line voltage to -1 / 2VDD; otherwise, the bit line is always grounded.

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