Inl detection and calibration for phase interpolators

Abstract

The present disclosure relates to INL detection and calibration for phase interpolators. An apparatus includes control logic coupled to a phase detector circuit and an adjustable delay circuit. The control logic is configured to obtain a state of a first phase of an output signal of a phase interpolator relative to a second phase of a reference signal, and adjust a delay of the reference signal until the second phase matches the first phase. The control logic is further configured to measure a total delay of the reference signal when the second phase matches the first phase, and determine an integral nonlinearity of the phase interpolator at a first code based on the total delay. The control logic can further calibrate the first code of the phase interpolator based at least in part on the integral nonlinearity.

Description

[0001] Copyright Notice

[0002] A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the U.S. Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. Technical Field

[0003] The present disclosure generally relates to methods, systems, and apparatus for addressing errors introduced by nonlinearities in phase interpolators. Background Art

[0004] Phase interpolators (PIs), often also called "phase rotators," are core components that implement basic transceiver functions such as clock and data recovery (CDR), loop timing modes, and spread spectrum clocking (SSC). Transceiver performance is affected by the integral nonlinearity (INL) in the PI, which introduces jitter into the recovered clock.

[0005] Jitter is important in systems that employ advanced modulation schemes such as pulse amplitude modulation 4 levels (PAM4) and quadrature amplitude modulation 16 levels (QAM16) / quadrature amplitude modulation 64 levels (QAM64), which are the primary modulation schemes for links with speeds of 100 Gigabit and above. The timing and noise limits of the modulated signals are significantly smaller than those of non-return-to-zero (NRZ) signals. For receivers based on analog-to-digital converters (ADCs) with advanced modulation, inaccurate sampling clock timing can degrade ADC performance. The degradation effect is even greater for high-speed input signals.

[0006] Therefore, methods, systems, and apparatus for INL detection and calibration are provided. Summary of the Invention

[0007] In one aspect, the present disclosure relates to a method comprising: determining a first phase of an output signal of a phase interpolator, wherein the output signal is generated by the phase interpolator based on a first code; adjusting a delay of a reference signal having a second phase via an adjustable delay circuit until the second phase matches the first phase, wherein the delay of the reference signal can be adjusted in increments of a step size; measuring the delay of the reference signal via control logic when the second phase matches the first phase, wherein the delay is measured in steps; determining an integral nonlinearity of the phase interpolator under the first code based at least in part on the delay; and calibrating the first code based at least in part on the integral nonlinearity via the control logic.

[0008] In another aspect, the present disclosure relates to a circuit comprising: a phase detector circuit configured to: determine a first phase of an output signal of a phase interpolator, wherein the output signal is generated by the phase interpolator based on a first code; determine a second phase of a reference signal; determine a state of the first phase relative to the second phase, wherein the state indicates whether the first phase leads or lags behind the second phase; an adjustable delay circuit coupled to the phase detector circuit, the adjustable delay circuit configured to adjust the delay of the reference signal until the second phase matches the first phase, wherein the delay of the reference signal can be adjusted in increments of step size; control logic coupled to the phase detector circuit and the adjustable delay circuit, the control logic configured to: measure a total delay of the reference signal when the second phase matches the first phase, wherein the total delay is measured in steps; determine an integral nonlinearity of the phase interpolator under the first code based on the total delay; and calibrate the first code at least in part based on the integral nonlinearity.

[0009] In another aspect, the present disclosure relates to a device comprising: control logic coupled to a phase detector circuit and an adjustable delay circuit, the control logic being configured to: obtain, via the phase detector circuit, a state of a first phase of an output signal of a phase interpolator relative to a second phase of a reference signal, wherein the state indicates whether the first phase leads or lags behind the second phase, wherein the output signal is generated by the phase interpolator based on a first code; adjust the delay of the reference signal via the adjustable delay circuit until the second phase matches the first phase, wherein the delay of the reference signal can be adjusted in increments of a step size; measure the total delay of the reference signal when the second phase matches the first phase, wherein the total delay is measured in steps; determine the integral nonlinearity of the phase interpolator under the first code based on the total delay; and calibrate the first code at least in part based on the integral nonlinearity. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A further understanding of the nature and advantages of certain embodiments may be achieved by referring to the remainder of the specification and the accompanying drawings, in which like reference numerals are used to refer to similar components. In some instances, a sub-label is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without identifying the existing sub-label, it is intended to refer to all such multiple similar components.

[0011] Figure 1 is a schematic block diagram of a receiver system according to various embodiments;

[0012] Figure 2is a schematic block diagram of a transmitter system according to various embodiments;

[0013] Figure 3 is a schematic block diagram of an INL detection circuit according to various embodiments;

[0014] Figure 4 is a schematic diagram illustrating a process for INL detection according to various embodiments;

[0015] Figure 5 is a schematic diagram illustrating a control logic implementation for INL calibration according to various embodiments; and

[0016] Figure 6 is a flowchart of a method for linear phase interpolation for variation tolerance according to various embodiments. DETAILED DESCRIPTION

[0017] Various embodiments provide tools and techniques for INL detection and calibration in a phase interpolator.

[0018] In some embodiments, a method for INL detection and calibration in a phase interpolator is provided. The method can include determining a first phase of an output signal of a phase interpolator, where the output signal is generated by the phase interpolator based on a first code, and adjusting a delay of a reference signal having a second phase via an adjustable delay circuit until the second phase matches the first phase, where the delay of the reference signal is adjusted in increments of a step size. The method further includes measuring the delay of the reference signal via control logic when the second phase matches the first phase, where the delay is measured in step sizes, determining an integral nonlinearity of the phase interpolator at the first code based at least in part on the delay, and calibrating the first code based at least in part on the integral nonlinearity via the control logic.

[0019] In some embodiments, a circuit for INL detection and calibration in a phase interpolator is provided. The circuit may include a phase detector circuit configured to: determine a first phase of an output signal of a phase interpolator, wherein the output signal is generated by the phase interpolator based on a first code; determine a second phase of a reference signal; and determine a state of the first phase relative to the second phase, wherein the state indicates whether the first phase leads or lags the second phase. The circuit may further include an adjustable delay circuit coupled to the phase detector circuit, the adjustable delay circuit configured to adjust the delay of the reference signal until the second phase matches the first phase, wherein the delay of the reference signal can be adjusted in increments of a step size. The circuit may further include control logic coupled to the phase detector circuit and the adjustable delay circuit. The control logic may be configured to: measure a total delay of the reference signal when the second phase matches the first phase, wherein the total delay is measured in steps; determine the integral nonlinearity of the phase interpolator for the first code based on the total delay; and calibrate the first code based at least in part on the integral nonlinearity.

[0020] In a further embodiment, an apparatus for INL detection and calibration in a phase interpolator is provided. The apparatus may include control logic coupled to a phase detector circuit and an adjustable delay circuit. The control logic may be configured to: obtain, via the phase detector circuit, a state of a first phase of an output signal of the phase interpolator relative to a second phase of a reference signal, wherein the state indicates whether the first phase leads or lags the second phase, wherein the output signal is generated by the phase interpolator based on a first code; adjust, via the adjustable delay circuit, a delay of the reference signal until the second phase matches the first phase, wherein the delay of the reference signal can be adjusted in increments of a step size; and measure a total delay of the reference signal when the second phase matches the first phase, wherein the total delay is measured in steps. The control logic may further be configured to: determine the integral nonlinearity of the phase interpolator at the first code based on the total delay; and calibrate the first code based at least in part on the integral nonlinearity.

[0021] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the described embodiments. It will be apparent, however, to one skilled in the art that embodiments can be practiced without some or all of these details. In other instances, well known structures and devices are shown in block diagram form. Several embodiments are described herein, and while various features are attributed

[0022] Similarly, when an element is referred to as being "connected" or "coupled" to another element, it should be understood that the element can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, it should be understood that no intervening elements are present in the "direct" connection. The use of "directly connected" or "directly coupled" does not, however, exclude the presence of other connections in which intervening elements can be present.

[0023] Furthermore, the described methods and processes can be described in specific orders, sequences, or flowcharts. However, it should be understood that the ordering, sequences, or flowcharts described are illustrative and can be changed, reordered, added to, or omitted, unless otherwise specifically stated.

[0024] Unless otherwise indicated, all numbers expressing quantities, dimensions, and so forth used herein are to be understood as approximations as to the term "about." In this application, the use of the singular includes the plural, unless specifically stated otherwise, and the use of "and" means "and / or," unless otherwise indicated. Furthermore, the use of the term "including," as well as other forms such as "includes" and "included," should be considered nonexclusive. Also, terms such as "element" or "component" encompass both elements and components comprising one unit and elements and components that comprise more than one unit, unless specifically stated otherwise.

[0025] Conventional approaches typically focus on improving the PI itself and the preceding circuitry. For example, to mitigate INL, conventional approaches attempt to adjust transistor size and input amplitude combinations to linearize the phase-to-input control relationship. However, conventional approaches fail to achieve good linearity across varying process, voltage, and temperature (PVT) conditions. These approaches often result in excessive power consumption and / or area overhead, resulting in large transistor sizes or large input amplitudes. Another conventional approach attempts to balance the nonlinear phase-to-PI code relationship by shaping the PI current bias digital-to-analog converter (DAC) using nonuniform weighting. Similarly, this approach is not applicable across varying PVT conditions because the PI nonlinear shape (e.g., the shape of the PI nonlinear profile, which plots the INL across the PI code) varies with PVT. The PI nonlinear shape can also change with input signal amplitude variations and rise / fall times, which cannot be compensated for by nonuniform weighting of the PI current bias DAC. Furthermore, shaping the PI current bias DAC (e.g., the current DAC) can result in significant amplitude variations across the PI code (e.g., the amplitude of the PI output varies depending on the PI code).

[0026] The embodiments described below can enable a more robust and scalable approach to mitigating INL. Specifically, the embodiments below describe techniques for detecting the INL of a specific PI and calibrating to remove the detected INL of the PI. For example, non-idealities originating from the PI input clock (e.g., multi-phase skew errors, duty cycle distortion, signal amplitude, and shape) are eliminated. This can reduce the power consumption and size of the preceding circuitry that provides the clock to the PI input.

[0027] Figure 1 1 is a schematic block diagram of a receiver system 100 according to various embodiments. The system 100 includes an equalizer 105, a sampler 110, a phase interpolator 115, a receiver (Rx) phase locked loop (PLL) 120, a PI phase control 125, a phase detector and loop filter 130, and a deserializer 135. It should be noted that Figure 1 Various components of system 100 are schematically illustrated in , and modifications to the various components and other arrangements of system 100 are possible according to various embodiments.

[0028] In various embodiments, the system 100 may be configured to receive an input signal V in , the input signal V in Will be converted into a digital output signal D out In various examples, V in is an analog signal received by receiver system 100. In some examples, equalizer 105 may be configured to make the input signal V inEqualization. In some examples, the equalizer 105 includes a linear equalizer, such as a continuous time linear equalizer (CTLE), while in further embodiments, the equalizer 105 includes a nonlinear equalizer, such as a decision feedback equalizer (DFE), or a combination of a CTLE and / or a DFE. In some examples, the equalizer 105 includes one or more equalizers in a multi-stage arrangement. The equalizer 105 may include, but is not limited to, a digital equalizer and / or a hybrid equalizer. The equalizer 105 may further include an adjustable amplifier with automatic gain control (AGC). According to some examples, the equalizer 105 may be configured to make the input signal V in Equalization to account for channel characteristics (e.g., channel loss) and noise.

[0029] The equalized signal from the equalizer 105 may be provided to the sampler 110. In some examples, the sampler 110 may include an ADC and / or one or more clippers. According to various embodiments, the sampler 110 may be configured to perform a scalar operation on the equalized input signal V in In some examples, the input signal may be a demodulated signal, wherein the sampler 110 sequentially outputs the sampled signal to the deserializer 135. In various embodiments, the sampler 110 may be clocked by a clock signal generated by the PI 115. The sampler 110 may sample the serial data of the input signal, which is equalized by the equalizer 105 and synchronized with the clock signal output by the PI 115. Therefore, the deserializer 135 may convert the serial samples of the sampler 110 into a plurality of parallel samples as the output digital signal D. out The corresponding bits of are transmitted to the downstream digital block. In one example, the deserializer 135 can include a demultiplexer circuit.

[0030] In some examples, to generate the clock signals, PI 115 receives a set of quadrature clock signals (e.g., in-phase clock signals (I / IB) and quadrature clock signals (Q / QB)) from Rx PLL 120. In various examples, each of the clock signals may be phase-shifted from a reference clock signal, with the four clock signals I, IB, Q, and QB being evenly spaced. In some examples, I and Q may be separated in phase by 90 degrees, IB may be phase-shifted by 90 degrees from Q, and QB may be phase-shifted by 90 degrees from IB. Although the clock signals are described herein as four-phase quadrature clock signals with respect to various examples for purposes of explanation, it should be understood that the clock signals are not limited to four-phase quadrature clock signals, and that a different number of clock signals may be used in other embodiments. Thus, in various examples, the clock signals may include a multi-phase clock signal having m number of phases (e.g., four phases, eight phases), where m is an integer. In some examples, the multi-phase clock signal may be provided by a PLL (e.g., Rx PLL 120). A PLL, such as Rx PLL 120 (and Tx PLL 220 below), is a circuit configured to generate a clock signal with a feedback mechanism to accurately track the frequency of the input signal. In other examples, PI 115 can be configured to generate a multi-phase clock signal directly from a reference clock signal, as opposed to receiving the multi-phase clock signal from a PLL.

[0031] In some examples, the PI 115 can generate complementary recovered clock signals CK and CKb, which can be sampling clock signals for the sampler 110. In various examples, the PI 115 can adjust or interpolate the phase of the clock signal from the Rx PLL 120 based on the phase control signal generated by the PI phase control 125. Thus, the recovered clock signal can be a clock signal generated by the PI 115 based on the phase error extracted from the output digital signal. Therefore, in some examples, the PI phase control 125 can be further coupled to a phase detector (PD) and loop filter 130 circuit. The PD and loop filter 130 can be configured to detect the phase error extracted from the output digital signal D. out The extracted phase error information is filtered and tracks the phase of the input signal. Therefore, the PI phase control 125 can receive the phase error information extracted from the output digital signal from the PD and the loop filter 130.

[0032] Therefore, while the PI phase control 125 can mitigate some timing errors through, for example, a clock data recovery (CDR) loop, it cannot address the nonlinearity of the PI 115. Figure 3 PI 115 implementing the INL detection and calibration architecture is further presented and described in detail.

[0033] Figure 22 is a schematic block diagram of a transmitter system 200 according to various embodiments. The system 200 includes a serializer 205, a retimer 210, a PI 215, a Tx PLL 220, a PI phase control 225, and a driver 230. It should be noted that Figure 2 Various components of system 200 are schematically illustrated in , and modifications to the various components and other arrangements of system 200 are possible according to various embodiments.

[0034] In various embodiments, the system 200 may be configured to receive a digital input signal D in , the digital input signal will be converted into an analog output signal V out The serializer 205 may be configured to convert the digital input signal D in 2. Serializer 205 converts multiple parallel bits into a serial stream of corresponding bits. In one example, serializer 205 may include a multiplexer circuit. Retimer 210 may be configured to: recover data from serializer 205; extract the embedded clock from the digital input signal; and retransmit the data using the clock signal provided by PI 215. Thus, retimer 210 may be configured to synchronize the output of the serializer to the correct clock phase.

[0035] Driver 230 receives the output of retimer 210, converts the data stream into an analog signal, and drives the analog signal to the appropriate channel. In various examples, driver 230 can be implemented as voltage-mode driver circuitry, current-mode driver circuitry, or a DAC. In some examples, serializer 205 and retimer 210 can be combined into a single circuit element. Similarly, in some examples, retimer 210 and driver 230 can also be combined into a single circuit element. Tx PLL 220 includes circuitry for providing a low-noise clock signal to retimer 210.

[0036] In various examples, the transmitter system 200 may transmit data at a rate slightly different from the clock signal from the Tx PLL 220 frequency. Therefore, the transmitter system 200 may employ the PI 215 to introduce a frequency offset from the Tx PLL 220. In various examples, the PI code may be generated (or controlled) via the PI phase control circuit 225. Therefore, the PI phase control circuit 225 may be configured to generate a frequency offset according to a given frequency offset (F offset The phase of the PI output clock signal may be shifted and / or rotated by the PI phase control circuit 225 to introduce a desired frequency offset into the Tx PLL 220 clock signal.

[0037] In the transmitter system 200, PI nonlinearity may cause jitter, which may degrade the performance of the retimer 210 and distort the output of the driver 230.Figure 3 PI 215 implementing an INL detection and calibration architecture is presented and described in further detail.

[0038] Figure 3 3 is a schematic block diagram of an INL detection circuit 300 according to various embodiments. The INL detection circuit 300 includes a PI 305, a time scale circuit 310, a phase detector 315, and a control logic 320. It should be noted that Figure 3 Various components of circuit 300 are schematically illustrated in , and modifications to the various components and other arrangements of circuit 300 are possible according to various embodiments.

[0039] According to various embodiments, the PI 305 can be configured to rotate an input signal (e.g., a clock signal) based on a PI code. Specifically, the PI 305 can rotate the input signal from 0 degrees to 360 degrees (e.g., a phase shift of 0 to 360 degrees) based on the PI code. For purposes of explanation, in one example, the PI code can be a 2-bit value including PI codes 1 (00), 2 (01), 3 (10), and 4 (11). In an ideal situation, each "ideal" PI code should produce a corresponding phase shift of 1 least significant bit (LSB). It should be understood that in other embodiments, the PI code can have more possible values ​​(e.g., 4-bit PI codes, 8-bit PI codes, etc.), and is not limited to the examples used above and below. Using the examples above (e.g., 4 possible codes), 1 LSB can correspond to a 90-degree shift (e.g., PI code 1 results in a 90-degree shift, PI code 2 results in a 180-degree shift, PI code 3 results in a 270-degree shift, and PI code 4 results in a 360-degree shift). However, due to INL, PI 305 may not produce the ideal 1-LSB shift for each PI code. Therefore, in various embodiments, PI 305 may receive the PI code and generate a phase-shifted clock signal based on the PI code. The phase of the output signal of PI 305 may be referred to as "PI phase." Due to INL, each PI code causes a shift in PI phase that is different from the ideal phase corresponding to the PI code (e.g., the phase shift produced by an ideal PI without INL). In various examples, INL is expressed as the difference between the PI phase and the ideal PI phase, in LSBs. In conjunction with phase detector 315, time scale circuit 310 may be used in INL detection circuit 300 to measure INL.

[0040] Accordingly, in various embodiments, in conjunction with phase detector 315, time scale circuit 310 can be configured to measure the phase difference of PI 305 (e.g., the phase of the signal output by PI 305, or the "PI phase") under different PI codes. In various examples, time scale circuit 310 can include various types of tunable on-chip delay (TOD) circuits (also referred to as "adjustable delay circuits"). In some examples, time scale circuit 310 can include, without limitation, various types of circuits such as skew control blocks, digital-to-time converters (DTCs), time-to-digital converters (TDCs), or other suitable circuits configured to measure the phase of PI 305. In some embodiments, time scale circuit 310 can include a coarse delay line with fine delay control. For example, time scale circuit 310 can include an additional PI configured to generate a reference signal, such as a replica PI. In some examples, the replica PI can provide coarse control of the reference signal phase, while fine delay can be provided via a downstream adjustable delay circuit portion of time scale circuit 310.

[0041] In various examples, time scale circuit 310 can be configured to delay (e.g., cause a phase shift) the reference signal in "steps." Each step of time scale circuit 310 results in a delay of a given duration. In other words, each step results in an increase in delay of a "step size." For example, in some embodiments, time scale circuit 310 can be an inverter with an output controlled by a plurality of capacitors corresponding to the number of steps of time scale circuit 310. The capacitors can be selectively turned on or off to adjust the delay. Accordingly, time scale circuit 310 can be configured to delay a reference signal, such as a clock signal, having a reference phase. In this way, the phase of the reference signal can be scanned (e.g., shifted over time) by adjusting the delay via time scale circuit 310. The phase of the delayed clock signal is thus referred to as the delayed reference phase.

[0042] In some examples, the delayed reference phase can match the phase of PI 305. In some examples, the delayed reference phase can match the phase of PI 305 under the first code and / or a code corresponding to no phase shift. To determine when the delayed reference phase matches the phase of PI 305, the delay introduced to the reference signal by time scale circuit 310 can be scanned (e.g., the delay step is increased) until it is determined that a transition has occurred in the relative phase of the delayed reference signal and the phase of PI 305, as will be described below. In this way, the phase of PI 305 can be matched to the delayed reference phase.

[0043] Once the phase of PI 305 and the delayed reference phase have been matched, the phase of PI 305 for various PI codes can then be measured using a similar matching process using time scale circuit 310. For example, for each PI code of PI 305, the phase of PI 305 can be measured by comparing it with the phase of a delayed reference signal (e.g., the delayed reference phase). Thus, time scale circuit 310 can delay the reference signal by step increments until the phase of the reference signal for the corresponding PI code matches the phase of PI 305. In this way, the phase of PI 305 for each PI code can be measured (in the step size of time scale circuit 310), thereby utilizing the delayed reference phase for comparison with the phase of PI 305.

[0044] In various embodiments, the reference signal may be generated, for example, by a replica circuit. In some examples, the replica circuit includes a replica PI configured to generate an output having a PI phase to be used as a reference phase. In some examples, the replica PI may generate an output based on a clock signal shared with the PI 305. In some examples, the replica circuit may be located in close proximity to the PI 305 so as to experience similar environmental conditions (e.g., voltage, temperature, etc.). In other examples, the time scale circuit 310 may include the replica PI and the reference signal used as an input to the replica PI, which may provide coarse phase control of the reference signal. As previously described, the time scale circuit 310 may then use an adjustable delay circuit (e.g., a TOD) to exert fine control over the output phase of the replica signal.

[0045] In various embodiments, phase detector 315 is configured to detect a phase difference between the output of time scale circuit 310 and the output of PI 305. Phase detector 315 may include, but is not limited to, various types of phase detector circuits, such as a D-type flip-flop (DFF) phase detector or an ADC-based phase detector. In some examples, phase detector 315 is configured to indicate the phase of PI 305 relative to a delayed reference phase (e.g., whether the phase of the signal generated by PI 305 leads or lags the phase of the reference signal delayed by time scale circuit 310).

[0046] In some examples, the step at which the transition occurs (e.g., from phase lag to phase lead) can be used to determine the phase of the PI 305 (e.g., based on the delay / delayed reference phase of the reference signal). For example, in some embodiments, the phase detector 315 can output a value of "0" to indicate that the phase of the PI 305 lags the delayed reference phase (e.g., the output of the time scale circuit 310), and can output a value of "1" to indicate that the phase of the PI 305 leads the delayed reference phase. In yet further embodiments, the transition point can be determined in the opposite direction (e.g., when the phase detector 315 outputs a transition from 1 to 0), or both transitions (from 0 to 1 and from 1 to 0) can be utilized. Thus, in operation, the time scale circuit 310 can be used to measure the respective phase of the PI 305 at each respective PI code of the PI 305.

[0047] Thus, based on the output of the phase detector 315, it can be determined at which steps of the time scale circuit 310 the phase becomes matched. For example, at a first step of the time scale circuit 310, the phase detector 315 can indicate that the output of the time scale circuit 310 lags in phase from the output of the PI 305. At a subsequent step of the time scale circuit 310, the phase detector 315 can indicate that the output of the time scale circuit 310 leads in phase from the output of the PI 305. Thus, in some examples, the point between the delay steps can be determined as a measurement point between two steps of the time scale circuit 310 (e.g., to measure the phase of the PI 305). For example, in some embodiments, a fractional step (e.g., a value measured between two steps of the time scale circuit 310) can be determined based at least in part on a statistical noise distribution between the steps (e.g., before and after the output of the phase detector 315 transitions). In some examples, the noise distribution follows a Gaussian distribution, and the fractional step is determined based on the Gaussian distribution (e.g., as the mean value of the noise distribution).

[0048] In some examples, the delay of the time scale circuit 310 can be measured in steps, or alternatively, as a unit of time. For example, the time scale circuit 310 can produce a maximum delay that is divided into n number of steps. Thus, the delay can be expressed as a number of steps. Thus, in some examples, the control logic 320 can be configured to determine the delay of the time scale circuit 310 by converting from steps of the PI 305 to LSBs. For example, to convert the delay of the time scale in LSB units, the control logic 320 can perform a conversion as described in more detail below with respect to Figure 4

[0049] ​In various embodiments, the control logic 320 can include hardware, software, or a combination of hardware and software. In some instances, the control logic 320 can be incorporated at least in part in the PI phase control circuit 125, 225 of Figure 1 and 2 In further instances, the control logic 320 can be at least in part a portion of a control subsystem and / or circuit separate from the PI phase control circuit 125, 225.

[0050] In some embodiments, the control logic 320 can be configured to detect INL by measuring the phase of the PI 305 for each respective PI code, as described above. In some instances, the control logic 320 can further output a delay control signal configured to control the adjustable delay of the time scale circuit 310. In some instances, the adjustable delay can be controlled via a control signal (e.g., "delay control") configured to activate and / or deactivate a capacitor in the capacitor-controlled delay circuit.

[0051] In further embodiments, the control logic 320 can be configured to convert the delay of the time scale circuit 310 into LSB units. Based on the conversion to LSB units, the control logic 320 can be further configured to calibrate the PI 305 for INL suppression, as will be described in greater detail below with respect to Figure 5 In some embodiments, the INL can be determined based on the measured phase of the PI 305 and the ideal phase of the corresponding PI code. The INL can be determined in LSBs for each PI code of the PI 305. The control logic 320 can thus generate calibrated PI codes based on the determined INL for each PI code. In other embodiments, the INL can be measured for every m number of PI codes, where m is an integer. For example, the INL can be measured for every one PI code, every four PI codes, every eight PI codes, etc.

[0052] Accordingly, in some embodiments, the control logic 320 can remap each of a plurality of raw PI codes to a respective calibrated PI code based on the measured INL of the PI 305 for a given raw PI code. In some instances, the calibrated PI code is the raw PI code adjusted by the measured INL. In further instances, each of the m number of raw PI codes preceding the raw PI code for which the INL is measured (including the raw PI code for which the INL is measured) can be calibrated based on the measured raw PI code. In other instances, each of the m number of PI codes following the raw PI code for which the INL is measured (including the raw PI code for which the INL is measured) can be calibrated according to the measured raw PI code.

[0053] Thus, in one example, to produce a delay in the phase of PI 305 for a given original PI code, the original PI code can be adjusted by the measured INL (e.g., as measured in LSBs). The adjusted original PI code can be set as the calibrated PI code (in this example, a lower PI code). Thus, the calibrated PI code can produce a phase of PI 305 that is closest to the ideal phase of the original PI code. For original PI codes in which the phase of PI 305 lags in phase relative to the ideal phase of the original PI, the original PI code can be adjusted by an amount that advances the phase (as measured in LSBs). Similarly, for original PI codes in which the phase of PI 305 leads in phase relative to the ideal phase of the original PI, the original PI code can be adjusted by an amount that causes a delay in the phase (as measured in LSBs). In this example, the original PI code can be adjusted by the INL to produce a larger PI code. The adjusted PI code can be set as the calibrated PI code, and thus the original PI code can map to a larger calibrated PI code. For each original PI code, calibration can be performed in this manner, with each original PI code mapping to a respective calibrated PI code. Thus, PI codes produced at a receiver, such as receiver system 100, or a transmitter, such as transmitter system 200, can be remapped based on the INL calibration procedure above, and provide calibrated PI codes for respective PIs.

[0054] In some examples, adjustment of an original PI code by the measured INL can result in a value that is between PI codes. For example, a given PI code can need to be adjusted by a fractional LSB value. In such examples, the closest whole PI code to the adjusted PI code can be selected as the calibrated PI code. In some examples, this can result in a scenario in which multiple PI codes can map to the same calibrated PI code. Similarly, in some examples, the calibrated PI codes can not include every PI code. For example, original PI code 64 (e.g., 00111111) can map to calibrated PI code 63 (e.g., 00111110), and original PI code 65 (e.g., 01000000) can map to calibrated PI code 65. Thus, any calibrated PI code can not correspond to PI code 64.

[0055] In some further examples, the digital-to-analog converter calibration can be used to calibrate the PI 305 for INL. In some examples, the PI can include DAC cells segmented into groups with different code offsets. In one set of examples, each segment of DAC cells can include three DAC cells, each with a respective code. In various examples, each segment of DAC cells can be controlled by a respective PI code. In some examples, the output of each respective DAC cell can be weighted. For example, the DAC weights can be reprogrammed based on the detected INL. In particular, the weights can be adjusted to exhibit a non-linear calibration curve. In this way, in some examples, a particular DAC segment can be weighted according to the INL measurement for a given raw PI code (or every group m number of PI codes as previously described).

[0056] Figure 4 is a schematic diagram illustrating a process 400 of INL detection according to various embodiments. In particular, Figure 4 illustrates the ideal PI phase of a signal according to a raw PI code relative to the PI phase of a signal produced by the PI of a given raw PI code (e.g. Figure 3 the PI 305 of FIG. 1). In this example, a 2-bit PI code with 4 possible values is utilized (e.g., via a full PI rotation of the 4 PI codes). At a PI code of 1, a signal with a first PI phase 405 is produced by the PI. A time scale circuit can be used to measure the difference between the first PI phase 405 and a first ideal PI phase corresponding to the raw PI code of 1. As previously described, the time scale steps can be discrete increments of time by which a reference signal can be delayed. Thus, the phase difference between the ideal PI phase and the phase of the PI can be determined based on the measured step difference of the time scale. Similarly, at a PI code of 2, a second PI phase 410 can be produced. The phase difference between the second PI phase 410 and a second ideal PI phase corresponding to the raw PI code of 2 can be similarly measured. Similar phase differences can be determined for a third PI phase 415 and a fourth PI phase 420.

[0057] In particular, to determine the phase difference, a control logic, such as the control logic 320, can be configured to convert the measured steps of the time scale circuit into LSB units of the PI. In some embodiments, the conversion can be determined based on a scale factor (SF). In particular, in some examples, the SF is given by the ratio of the total number of LSBs of the PI code (e.g., a 2-bit PI code has 4 total LSBs, 4-bit has 16 total LSBs, and 8-bit has 256 total LSBs) to the total number of steps of the time scale circuit (e.g., the number of delay steps).

[0058]

[0059] The phase difference between the PI phase of the PI and the ideal PI phase can then be given in LSBs, as the number of steps by which the reference signal is delayed to match the corresponding PI phase of the PI multiplied by the scaling factor, minus the number of LSBs of the PI code (e.g., PI code 1 = 1 LSB, PI code 2 = 2 LSB, and so on).

[0060] INL LSB =(scaling factor x number of steps) -(original phase interpolator code) (Equation 2)

[0061] In some instances, such as Figure 4 As shown in , the reference signal may have a phase corresponding to PI code 0. Therefore, the number of steps from the phase of the unshifted PI signal to the corresponding phase of the PI for a given PI code can be effectively measured. In the example shown, the total number of steps in the time scale may be equal to: 20 + 12 + 8 + 8 = 48 steps. The total number of LSBs of the PI code is 4 (for a 2-bit PI code). Therefore, SF is given by: 4 / 48 = 1 / 12.

[0062] For the first PI phase 405, the number of steps is measured to be 20. Therefore, the INL of the PI at the first PI code (e.g., 1) (e.g., the measured phase difference from the reference "ideal" PI phase) may be given by (20×1 / 12)-1LSB=0.67LSB, as shown in the phase difference graph 425. For the second PI phase 410, the INL of the PI at the second PI code (e.g., 2) may be given by (32×1 / 12)-2LSB=0.67LSB. For the third PI phase 415, the INL of the PI at the third PI code (e.g., 3) may be given by (40×1 / 12)-3LSB=0.32LSB. The fourth PI phase 420 may correspond to no phase shift (or full rotation) of the PI, and therefore there is an INL=(48×1 / 12)-4LSB=0LSB, as expected. In this way, the INL can be detected and measured using a time ruler circuit and converted to LSBs via control logic.

[0063] Thus, in some examples, to produce a desired PI phase corresponding to original PI code 1, original PI code 0 produces a PI phase that is closer in phase to the desired PI phase than first PI phase 405. Thus, in some examples, original PI code 1 can be mapped to calibrated PI code 0. Similarly, to produce a desired PI phase corresponding to original PI code 2, original PI code 1 produces a PI phase that is closer in phase to the desired PI phase than second PI phase 410. In other words, first PI phase 405 is closer in phase to the desired PI phase for PI code 2 than second PI phase 410. Thus, in some examples, original PI code 2 can be mapped to calibrated PI code 1. For third PI phase 415, which corresponds to original PI code 3, third PI phase 415 is closest in phase to the corresponding desired PI phase. Thus, in some examples, original PI code 3 can be mapped to itself (e.g., calibrated PI code 3). For PI codes 0 / 4, similarly no adjustment is needed and thus the PI codes can be mapped to themselves. The following is described in more detail with respect to Figure 5 This mapping is described in more detail.

[0064] Figure 5 FIG. 5 is a schematic diagram illustrating a control logic implementation 500 for INL calibration, in accordance with various embodiments. Specifically, Figure 5The mapping scheme 505 between raw PI codes to calibrated PI codes based on measured INL as previously described is illustrated. As shown, an 8-bit PI code [7:0] is used here as an example for illustration purposes (although other sizes of PI codes can also be used). As previously described, the INL for a given raw PI code can be measured. For an 8-bit PI code, the range of values for the PI code can be from 0 to 255, for a total of 256 LSBs. On the left side of the mapping scheme, the raw PI code is provided as a first input to a digital adder / subtractor circuit. The PI code can then be adjusted by the corresponding measured INL (in LSBs) via the digital adder / subtractor circuit. In other examples, the INL can be rounded to the nearest whole LSB. In other embodiments, the sum (or difference, as the case can be) can be rounded to the nearest whole LSB. In this example, the PI code is represented by its corresponding decimal value (e.g., PI code “0” corresponds to binary “00000000”, whereas in the previous example, the 2-bit binary PI code “00” was referred to as the first PI code or PI code 1). Thus, in the example shown, the raw PI code 0 is adjusted by the measured INL (the difference between the PI’s phase and the ideal PI phase) to determine the calibrated PI code. Thus, the calibrated PI code is the same as the raw PI code. However, for PI code 100, the raw PI code is adjusted by 3 LSBs, and thus maps to calibrated PI code 97. Similarly, raw PI code 192 can map to calibrated PI code 193, and raw PI code 255 maps to calibrated PI code 255. In some examples, as previously described, the INL can be measured every m number of PI codes. In such examples, PI codes (100-m) to 100 map to calibrated PI codes (100-m-3) to 97, respectively.

[0065] It should be understood that in other examples, different algorithms (e.g., mapping schemes) for mapping raw PI codes to calibrated PI codes can be utilized, and the mapping is not intended for any single implementation. For example, in other embodiments, the mapping of raw PI codes to calibrated PI codes can be determined according to a curve fitting function. For example, a curve or other mathematical function can be generated based on the measured INL and the calibrated PI codes determined to fit the curve. In some examples, the calibrated PI codes can be determined applying an interpolation scheme. In yet further examples, a machine learning model can be applied to determine the calibrated PI codes.

[0066] In some embodiments, the mapping scheme 505 can be implemented as, for example, a mapping circuit. In some examples, the mapping circuit includes control logic (e.g., a microprocessor, microcontroller, or other programmable logic) that is programmed to perform the mapping scheme 505. In some examples, the mapping circuit includes a look-up table that is programmed to perform the mapping scheme 505. In some examples, the mapping circuit includes a combination of control logic and a look-up table. Figure 3The mapping scheme 505 can be dynamically updated according to the measured INL. Thus, in some examples, the control logic includes a digital adder / subtractor circuit configured to adjust the raw PI code according to the measured INL and output a corresponding calibrated PI code, as described above.

[0067] Figure 6 is a flowchart of a method 600 for INL detection and calibration according to various embodiments. The method 600 can begin at block 605 by determining a phase of a PI output signal. In various examples, the PI can generate a phase-shifted input signal (e.g., a clock signal) based on a PI code. In the case of ideal PI, the phase of the input signal should shift by 1 LSB under each PI code. The phase of the signal that is shifted is the ideal PI phase. However, due to INL, this is not the case. Thus, the phase of the PI output signal (e.g., the phase of the PI) can be determined.

[0068] At block 610, the method 600 continues by measuring the INL of the PI under a given PI code. In various examples, the INL can be measured as a phase difference between the phase of the PI under the given PI code and the ideal PI phase under the PI code. As previously described, the raw PI code should generate a signal that is shifted by 1 LSB under each PI code, e.g., 90 degrees. Thus, in various embodiments, the INL can be measured as a difference between the phase of the PI under the PI code and the corresponding ideal PI phase in units of LSBs. As previously described, in some examples, the INL of the PI can be measured in steps of a time scale circuit. The steps of the time scale can then be converted to units of LSBs. In various examples, the time scale circuit includes an adjustable delay circuit. The time scale circuit can be configured to output a reference signal that has been delayed for a duration of the adjustable delay of the time scale circuit. In some examples, the phase of the PI under a given code can be compared to the reference signal that has been delayed (effectively phase shifted), as previously described. In some examples, the phase of the PI and the delayed reference phase can be compared via a phase detector circuit. In some examples, the phase detector circuit outputs a signal indicative of the position of the phase of the PI relative to the delayed reference phase.

[0069] Accordingly, in some examples, the time scale circuit can scan the phase of the reference signal (e.g., the phase of the reference signal is shifted over time) by adjusting the tunable delay. For example, the reference signal can be incrementally (and / or decrementally) delayed in steps until the output of the phase detector circuit transitions, indicating that the phase of the PI has been matched to the delayed reference phase. Accordingly, the phase difference from the ideal PI phase can be measured in steps of the time scale circuit. In some examples, the phase difference from the ideal PI phase can be determined based at least in part on the total number of steps of the time scale circuit for a full rotation of the PI (e.g., using a scaling factor as previously described). Accordingly, the delay of the reference signal at the point where the phase of the PI matches the delayed reference phase is measured in steps of the time scale circuit under each respective PI code. The delay can then be converted to LSB units using a scaling factor as previously described via control logic. In this way, the INL of the PI can be measured in LSBs. In some examples, the INL of the PI can be measured under each PI code. In other examples, the INL can be measured in intervals of every m number of PI codes.

[0070] At block 615, the method 600 continues by calibrating the PI codes according to the measured INL. As previously described, in some examples, each PI code can be adjusted based on the measured INL that results in a PI output signal having a phase closest to the ideal PI phase of a given PI code. Accordingly, in various examples, for purposes of differentiation, a PI code prior to calibration can be referred to as an “original” PI code, while a PI code after calibration can be referred to as a “calibrated” PI code. Accordingly, in some examples, each original PI code can be mapped to a calibrated PI code, where the calibrated PI code causes the PI to produce an output having a phase closest to the ideal PI phase of the original PI code. In some examples, the INL can be measured in LSBs. Accordingly, calibrating the PI codes can include adjusting each original PI code based on the INL measured in LSBs and according to a mapping scheme, as previously described. For example, in one example, if the PI has a measured INL of 0.67 LSBs for a given PI code, the original PI code can be decreased by 0.67 LSBs in some examples. Correspondingly, if the PI has a measured INL of -0.67 LSBs for a given PI code, the original PI code can be increased by 0.67 LSBs.

[0071] In some further examples, calibrating the PI code includes calibrating a current- controlled DAC of the PI based on the INL. As previously described, the PI can include DAC cells segmented into groups with different PI codes. In some examples, each segment of the DAC can be controlled by a respective PI code. Thus, the output of each respective DAC cell can be weighted according to the INL measurement of a given raw PI code (or each group m number of PI codes as previously described) to offset the effect of the measured INL.

[0072] At block 620, the method 600 further includes mapping the raw PI code to a calibrated PI code. As previously described, adjustment of the raw PI code by the INL can result in a PI code that has been adjusted by a fraction of a LSB unit. In such examples, the raw PI code can be mapped to the closest PI code as the calibrated PI code. In some examples, each raw PI code can be mapped to a respective calibrated PI code. In some examples, the mapping can be implemented via a lookup table stored in control logic. In further examples, the mapping can be implemented at least in part via a summer / subtractor circuit that can adjust the raw PI code based on the measured INL to generate the corresponding calibrated PI code.

[0073] The techniques and processes described above with respect to various embodiments can be performed by one or more systems 100, 200 and / or subsystems thereof and components thereof, such as the linear phase interpolator circuit 300 described above with respect to Figures 1-3 various embodiments described herein, and one or more systems 100, 200 and / or subsystems thereof and components thereof can perform methods provided by various other embodiments as described herein.

[0074] While some features and aspects have been described with respect to embodiments, those skilled in the art will recognize that many modifications are possible within the spirit and scope of the application. For example, the methods and processes described herein can be implemented using hardware components, custom integrated circuits (ICs), programmable logic, and / or any combination thereof. Further, although the various methods and processes described herein can be described with respect to particular structural and / or functional components for ease of description, methods provided by various embodiments are not limited to any particular structural and / or functional architecture but instead can be implemented in any suitable hardware configuration. Similarly, although some functionality is ascribed to specific

[0075] Also, although the procedures of the methods and processes described herein are described in a certain order for ease of description, unless the context dictates otherwise, various procedures can be reordered, added, and / or omitted according to various embodiments. Moreover, the procedures described with respect to one method or process can be incorporated in other described methods or processes; likewise, system components described according to a particular architectural layout and / or with respect to one system can be organized similarly in other architectures and / or in other systems. Hence, while the above describes various embodiments, it is not intended to limit the scope of the application, as one will appreciate the many modifications and variations within the scope of the present application.

Claims

1. A method comprising: determining a first phase of an output signal of a phase interpolator, wherein the output signal is generated by the phase interpolator based on a first code; adjusting a delay of a reference signal having a second phase via an adjustable delay circuit until the second phase matches the first phase, wherein the delay of the reference signal is adjustable in step size increments; measuring, via control logic, a total delay of the reference signal when the second phase matches the first phase, wherein the total delay is measured in steps; determining an integral nonlinearity of the phase interpolator for the first code based at least in part on the total delay; and The first code is calibrated, via the control logic, based at least in part on the integral nonlinearity.

2. The method of claim 1 , wherein determining the integral nonlinearity of the phase interpolator under the first code further comprises: The total delay is converted from a step size to a phase difference measured in the least significant bits of the first code via the control logic.

3. The method of claim 2, wherein calibrating the first code further comprises: generating, via the control logic, a second code, wherein the second code is generated by adjusting the first code based on the phase difference; and The first code is mapped to the second code via the control logic.

4. The method of claim 3, wherein the second code is a phase interpolator code that is closest to an adjusted phase interpolator code, wherein the adjusted phase interpolator code is the first code adjusted based on the phase difference.

5. The method of claim 2, wherein the phase interpolator comprises one or more digital-to-analog converter (DAC) units, each DAC unit corresponding to a respective code, wherein calibrating the first code further comprises: A weight of at least one DAC unit of the one or more DAC units is adjusted based on the phase difference.

6. The method according to claim 1, further comprising: Determining the integral nonlinearity of the phase interpolator at a first interval of a phase interpolator code, wherein determining the integral nonlinearity of the phase interpolator at the first interval further comprises: determining respective first phases of the output signals generated by the phase interpolator based on respective phase interpolator codes separated by the first interval; for each respective phase interpolator code, delaying the reference signal via the adjustable delay circuit until a respective second phase of the reference signal matches the corresponding respective first phase; and A respective delay of the reference signal is measured via the control logic when a respective second phase matches the corresponding first phase.

7. The method according to claim 6, further comprising: Each phase interpolator code of the phase interpolator is mapped, via the control logic, to a corresponding calibrated phase interpolator code based on the measured total delay.

8. The method according to claim 1, further comprising: determining, via a phase detector circuit, a state of the first phase relative to the second phase, wherein the state indicates whether the first phase leads or lags the second phase; Wherein measuring the total delay further comprises measuring the total delay when a transition occurs in the state of the first phase relative to the second phase, wherein the transition is a change in the state of the first phase relative to the second phase.

9. A circuit comprising: A phase detector circuit configured to: determining a first phase of an output signal of a phase interpolator, wherein the output signal is generated by the phase interpolator based on a first code; determining a second phase of the reference signal; determining a state of the first phase relative to the second phase, wherein the state indicates whether the first phase leads or lags the second phase; an adjustable delay circuit coupled to the phase detector circuit, the adjustable delay circuit configured to adjust a delay of the reference signal until the second phase matches the first phase, wherein the delay of the reference signal is adjustable in step increments; control logic coupled to the phase detector circuit and the adjustable delay circuit, the control logic configured to: measuring a total delay of the reference signal when the second phase matches the first phase, wherein the total delay is measured in steps; determining an integral nonlinearity of the phase interpolator at the first code based on the total delay; and The first code is calibrated based at least in part on the integral nonlinearity.

10. The circuit of claim 9, wherein the control logic is further configured to convert the total delay from a step size into a phase difference measured in least significant bits of the first code, wherein the integral nonlinearity of the phase interpolator is determined based on the phase difference.

11. The circuit of claim 10, wherein calibrating the first code further comprises generating a second code, wherein the second code is generated by adjusting the first code based on the phase difference, wherein the control logic is further configured to map the first code to the second code.

12. The circuit of claim 11, wherein the second code is a phase interpolator code that is closest to an adjusted phase interpolator code, wherein the adjusted phase interpolator code is the first code adjusted based on the phase difference.

13. The circuit of claim 10, wherein the control logic is further configured to adjust a weight of at least one digital-to-analog (DAC) unit of the phase interpolator based on the phase difference, wherein the phase interpolator comprises one or more DAC units, each DAC unit corresponding to a respective code.

14. The circuit of claim 9, wherein measuring the total delay further comprises measuring the total delay when a transition occurs in the state of the first phase relative to the second phase, wherein the transition is a change in the state of the first phase relative to the second phase.

15. An apparatus comprising: control logic coupled to the phase detector circuit and the adjustable delay circuit, the control logic configured to: obtaining, via the phase detector circuit, a state of a first phase of an output signal of a phase interpolator relative to a second phase of a reference signal, wherein the state indicates whether the first phase leads or lags the second phase, wherein the output signal is generated by the phase interpolator based on a first code; adjusting a delay of the reference signal via the adjustable delay circuit until the second phase matches the first phase, wherein the delay of the reference signal is adjustable in step size increments; measuring a total delay of the reference signal when the second phase matches the first phase, wherein the total delay is measured in steps; determining an integral nonlinearity of the phase interpolator at the first code based on the total delay; and The first code is calibrated based at least in part on the integral nonlinearity.

16. The apparatus of claim 15, wherein the control logic is further configured to convert the total delay from a step size to a phase difference measured in least significant bits of the first code, wherein the integral nonlinearity of the phase interpolator is determined based on the phase difference.

17. The apparatus of claim 16, wherein calibrating the first code further comprises generating a second code, wherein the second code is generated by adjusting the first code based on the phase difference, wherein the control logic is further configured to map the first code to the second code.

18. The apparatus of claim 17, wherein the second code is a phase interpolator code that is closest to an adjusted phase interpolator code, wherein the adjusted phase interpolator code is the first code adjusted based on the phase difference.

19. The apparatus of claim 16, wherein the control logic is further configured to adjust a weight of at least one digital-to-analog (DAC) unit of the phase interpolator based on the phase difference, wherein the phase interpolator comprises one or more DAC units, each DAC unit corresponding to a respective code.

20. The apparatus of claim 15, wherein measuring the total delay further comprises measuring the total delay when a transition occurs in the state of the first phase relative to the second phase, wherein the transition is a change in the state of the first phase relative to the second phase.

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